On 1.6.2017 05:11, Simon Glass wrote:
> On 29 May 2017 at 01:11, Michal Simek wrote:
>> Add support for calling poweroff in case of psci is wired.
>> Based on the same solution as is used for reset.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>>
On 05/31/2017 10:38 AM, Andes wrote:
> From: rick
>
> Support Andestech ftsdc010 SD/MMC device tree flow
> on AG101P/AE3XX platforms.
>
> Signed-off-by: rick
> ---
> board/AndesTech/adp-ae3xx/adp-ae3xx.c |4 +---
>
On 05/31/2017 10:37 AM, Andes wrote:
> From: rick
>
> Support Andestech ftsdc010 SD/MMC device tree flow
> on AG101P/AE3XX platforms.
>
> Signed-off-by: rick
Reviewed-by: Jaehoon Chung
> ---
> arch/nds32/dts/ae3xx.dts |8
Hi
On 05/13/2017 10:51 PM, Marek Vasut wrote:
> From: Kouei Abe
>
> Renesas SDHI SD/MMC driver has 16-bit width bus access to SD_BUF.
> This adds 64-bit width bus access to SD_BUF.
aarch64: + r8a7795_salvator-x
+board/renesas/salvator-x/salvator-x.c: In function
Hi Kever,
On 23 May 2017 at 20:35, Kever Yang wrote:
> Hi Simon,
>
>
>
> On 05/20/2017 10:29 AM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 16 May 2017 at 21:44, Kever Yang wrote:
>>>
>>> In rk3328, some function pin may have more than one
On 23 May 2017 at 13:18, Álvaro Fernández Rojas wrote:
> It's a Macronix (mx25l12805d) 16 MB SPI flash.
>
> Signed-off-by: Álvaro Fernández Rojas
> ---
> arch/mips/dts/comtrend,ar-5387un.dts| 12
> configs/comtrend_ar5387un_ram_defconfig |
On 06/01/2017 08:57 AM, Simon Glass wrote:
> This file does not report a few possible errors and one message is missing
> a newline. Fix these.
>
> Signed-off-by: Simon Glass
Reviewed-by: Jaehoon Chung
And CC'd correct Lukasz's mail account.
> ---
On 24 May 2017 at 09:04, Tom Rini wrote:
> We only want to apply files such as 'omap5-u-boot.dtsi', which resides
> in arch/arm/dts/ to other files in arch/arm/dts/ and not say
> test/overlay/. Rework the make logic to check for -u-boot.dtsi files in
> the same directory as
On 23 May 2017 at 13:18, Álvaro Fernández Rojas wrote:
> This driver manages the high speed SPI controller present on this SoC.
>
> Signed-off-by: Álvaro Fernández Rojas
> ---
> arch/mips/dts/brcm,bcm63268.dtsi | 21 +
> 1 file changed,
On 26 May 2017 at 07:55, Wadim Egorov wrote:
> Hello Simon,
>
>
> Am 24.05.2017 um 02:44 schrieb Simon Glass:
>> Hi Wadim,
>>
>> On 15 May 2017 at 08:19, Wadim Egorov wrote:
>>> The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
>>>
Hi,
On 29 May 2017 at 02:28, wrote:
> Hi,
>
> I was wondering if anyone is currently working on u-boot support for TPM2.0
> chips, especially the "native" spi versions.
> (i.e. direct access to the tpm via spi, not via something like the pch)
> Having support for
On 30 May 2017 at 07:05, Hannes Schmelzer
wrote:
> With this commit we can modify single values within an array of a dts
> property.
>
> This is useful if we have for example a pwm-backlight where we want to
> modifiy the pwm frequency per u-boot script.
>
>
On 29 May 2017 at 01:57, wrote:
> From: Patrice Chotard
>
> Add support of generic PHY framework support
>
> Signed-off-by: Patrice Chotard
> ---
> v4: _ none
> v3: _ use generic_phy_valid() method
> v2: _ none
On 31 May 2017 at 02:04, Bin Meng wrote:
> At present lpe/lpss-sio/scc FSP properties are all boolean, but in
> fact for "enable-lpe" it has 3 possible options. This adds macros
> for these options and change the property from a boolean type to
> an integer type, and change
On 29 May 2017 at 01:57, wrote:
> From: Patrice Chotard
>
> This allow to check if a PHY has been correctly
> initialised and avoid to get access to phy struct.
>
> Signed-off-by: Patrice Chotard
> ---
>
> v4: _ none
>
Hi,
On 25 May 2017 at 10:23, Pantelis Antoniou
wrote:
> The dtb blob section must always be present in the resulting image.
> Either if OF_EMBEDED is used or if unit tests include dtb blobs.
>
OF_EMBED (and below)
Reviewed-by: Simon Glass
>
On 31 May 2017 at 02:04, Bin Meng wrote:
> Introduce various meaningful macros for FSP settings and switch over
> to use them instead of magic numbers.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/baytrail/fsp_configs.c| 35
On 29 May 2017 at 01:57, wrote:
> From: Patrice Chotard
>
> DWC3 dual role mode is selected using DT "dr_mode"
> property. If not found, DWC3 controller is configured
> in HOST mode by default
>
> Signed-off-by: Patrice Chotard
On 23 May 2017 at 15:05, Jernej Skrabec wrote:
> This commit fixes the warning produced by gcc 7.1.
>
> Signed-off-by: Jernej Skrabec
> ---
>
> common/edid.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
On Tue, 2017-05-30 at 08:48 -0500, Dinh Nguyen wrote:
>
> On 05/28/2017 11:00 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This is the 6th version of patchset to adds support for Intel Arria
> > 10 SoC FPGA
> > driver. This version mainly
On 29 May 2017 at 01:57, wrote:
> From: Patrice Chotard
>
> phy->dev need to be set to NULL in case of generic_phy_get_by_index()
> fails. Then phy->dev can be used to check if the phy is valid
>
> Reported-by: Jean-Jacques Hiblot
On 29 May 2017 at 19:06, Jaehoon Chung wrote:
> Remove the COMPAT_DM_I2C_COMPAT config.
>
> Signed-off-by: Jaehoon Chung
> ---
> This patch is based on "Enable the CONFIG_DM_MMC for Exynos4 series"
>
> configs/odroid_defconfig | 2 +-
>
Hi Marcel,
On 29 May 2017 at 09:08, Marcel Ziswiler wrote:
> Hi Simon
>
> On Fri, 2017-05-19 at 08:31 -0600, Simon Glass wrote:
>> Change this board to use a live device tree after relocation.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>>
On 31 May 2017 at 02:04, Bin Meng wrote:
> The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per
> FSP default settings. 0 is not valid.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/baytrail/fsp_configs.c | 2 +-
>
Hi Peter,
On 29 May 2017 at 07:29, Peter Robinson wrote:
> On Mon, May 22, 2017 at 12:17 PM, Simon Glass wrote:
>> Most Chromebooks support chain-loading U-Boot but instructions are
>> somewhat scattered. Add a README to hold this information within the
On 29 May 2017 at 01:57, wrote:
> From: Patrice Chotard
>
> Add Driver Model support with use of generic DT
> compatible string "snps,dwc3"
>
> Signed-off-by: Patrice Chotard
> ---
> v4: _ none
> v3: _ none
> v2:
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> Extend ohci-generic driver with generic PHY framework
>
> Signed-off-by: Patrice Chotard
> ---
>
> v4: _ use generic_phy_valid() before generic_phy_exit()
On 29 May 2017 at 01:06, Michal Simek wrote:
> Add poweroff description to Kconfig to make it selectable
> via menuconfig.
>
> Signed-off-by: Michal Simek
> ---
>
> cmd/Kconfig | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> use array to save deasserted resets reference in order to
> assert them in case of error during probe() or during driver
> removal.
>
> Signed-off-by: Patrice Chotard
On 23 May 2017 at 03:57, wrote:
> From: Patrice Chotard
>
> This allow to check if a PHY has been correctly
> initialised and avoid to get access to phy struct.
>
> Signed-off-by: Patrice Chotard
> ---
>
On 30 May 2017 at 15:32, Philipp Tomsich
wrote:
> The Rockchip BootROM relies on init_size being aligned to 2KB
> (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html).
>
> This pads the image to 2KB both for SD card images and SPI images
> and
Hi Maxime,
On 30 May 2017 at 14:41, Maxime Ripard wrote:
> On Wed, May 24, 2017 at 05:34:52PM +0200, Jernej Škrabec wrote:
>> Hi,
>>
>> Dne torek, 23. maj 2017 ob 22:22:14 CEST je Maxime Ripard napisal(a):
>> > Hi Jernej,
>> >
>> > On Mon, May 22, 2017 at
On 31 May 2017 at 02:04, Bin Meng wrote:
> "serial-debug-port-address" and "serial-debug-port-type" settings
> are actually reserved in the FSP UPD data structure. Remove them.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/baytrail/fsp_configs.c
On 29 May 2017 at 01:11, Michal Simek wrote:
> Add support for calling poweroff in case of psci is wired.
> Based on the same solution as is used for reset.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/cpu/armv8/fwcall.c | 7 +++
>
On 30 May 2017 at 15:32, Philipp Tomsich
wrote:
> This change restores the earlier setting of init_boot_size to include
> the maximum area covered by the the boot ROM of each chip for resolve
> issues with back-to-bootrom functionality reported by Kever and
Hi Tom,
On 24 May 2017 at 06:56, Tom Rini wrote:
> On Wed, May 24, 2017 at 10:18:12AM +0200, Heiko Stuebner wrote:
>> Am Dienstag, 23. Mai 2017, 18:44:37 CEST schrieb Simon Glass:
>> > Hi,
>> >
>> > On 23 May 2017 at 16:18, Andreas Färber wrote:
>> > > Hi
On 25 May 2017 at 10:24, Pantelis Antoniou
wrote:
> Unit tests require mallinfo which in turn requires DEBUG on
> dlmalloc to be enabled.
>
> The dependancy on CONFIG_SANDBOX is wrong.
>
> Signed-off-by: Pantelis Antoniou
> ---
>
On 29 May 2017 at 18:03, Chris Packham wrote:
> There is some inconsistency between uses of CONFIG_RTC_DS13xx and
> CONFIG_SYS_RTC_DS13xx. Address this by dropping the "SYS" from
> these variables.
>
> Signed-off-by: Chris Packham
> ---
> README
Hi Daniel,
On 17 May 2017 at 13:27, Daniel Schwierzeck
wrote:
>
>
> Am 17.05.2017 um 16:22 schrieb Simon Glass:
>> Rather than including this arch-specific header file in common.h, include
>> it from within mips's u-boot.h header.
>>
>> Signed-off-by: Simon Glass
Hi Patrice,
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> Add clk_count() method to be able to get the number
> of clocks contained into a clock property. This will allow
> to allocate the right amount of memory in order to keep
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> Extend ehci-generic driver with generic PHY framework
>
> Signed-off-by: Patrice Chotard
> ---
>
> v4: _ use generic_phy_valid() before generic_phy_exit()
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> Use an array to save enabled clocks reference and deasserted resets
> in order to respectively disabled and asserted them in case of error
> during probe() or during driver removal.
>
>
On 24 May 2017 at 07:07, wrote:
> From: Patrice Chotard
>
> Add clk_disable_all() method which Request/Disable/Free an
> array of clocks that has been previously requested by
> clk_request/get_by_*()
>
> Signed-off-by: Patrice Chotard
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> Add reset_assert_all() method which Request/Assert/Free an
> array of resets signal that has been previously successfully
> requested by reset_get_by_*()
>
> Signed-off-by: Patrice
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> use array to save enabled clocks reference in order to
> disabled them in case of error during probe() or during
> driver removal.
>
> Signed-off-by: Patrice Chotard
Hi Patrice,
On 24 May 2017 at 07:01, wrote:
> From: Patrice Chotard
>
> Add reset_count() method to be able to get the number
> of resets contained into a resets property. This will allow
> to allocate the right amount of memory in order to keep
On 23 May 2017 at 13:18, Álvaro Fernández Rojas wrote:
> This driver manages the SPI controller present on this SoC.
>
> Signed-off-by: Álvaro Fernández Rojas
> ---
> arch/mips/dts/brcm,bcm6328.dtsi | 24
> 1 file changed, 24
Hi Alvaro,
On 23 May 2017 at 13:18, Álvaro Fernández Rojas wrote:
> This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c
>
> Signed-off-by: Álvaro Fernández Rojas
> ---
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile
Hi Tom,
Please pull the following patch from u-boot-nds32 into your tree.
Thanks!
The following changes since commit ccbbada0a59fead35495409d0c2c7bcb22a40278:
Merge branch 'master' of git://git.denx.de/u-boot-mmc (2017-05-30 14:07:23
-0400)
are available in the git repository at:
Rather than relying on common.h to provide this include, which is going
away at some point, include it explicitly in each file.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
---
Changes in v2:
- Drop #ifdef guard in arch/arm/lib/spl.c
This error needs to go to stderr otherwise it will not be reported by
buildman. Fix it.
Signed-off-by: Simon Glass
---
Makefile | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Makefile b/Makefile
index 89e0451a49..c13937c3a8 100644
---
Hi Philipp:
2017-05-31 18:58 GMT+08:00 Dr. Philipp Tomsich <
philipp.toms...@theobroma-systems.com>:
> Now that there are no remaining cases where (spl_boot0 == false), we can
> drop the spl_boot0 field from struct spl_info and also remove the if-check
> (leaving only the code-path for true in
On 05/31/2017 08:17 AM, Roy Pledge wrote:
> On 5/30/2017 12:40 PM, york sun wrote:
>> On 05/12/2017 01:30 PM, Roy Pledge wrote:
>>> From: Ahmed Mansour
>>>
>>> This patch adds changes necessary to move functionality present in
>>> PowerPC folders with ARM architectures that
Banana Pi BPI-M2 Ultra is a quad-core mini single board computer built with
Allwinner R40 SoC. It features 2GB of RAM and 8GB eMMC. Duncan Hare
714 931 7952
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
BPI-M64 is a 64-bit quad-core mini single board computer
using the Allwinner A64 SOC.
BPI-M64 features
- 1.2 Ghz Quad-Core ARM Cortex A53
- 2GB DDR3 SDRAM with 733MHz
- MicroSD/eMMC(8GB)
- 10/100/1000Mbps ethernet (Realtek RTL8211E/D)
- Wifi + BT
- IR receiver
- Audio In/Out
- Video In/Out
- 5V
The clock fix-up for tegra is still present in the code. It causes a
divide-by-zero bug after relocation when chain-loading U-Boot from
coreboot. Fix this by adding a check.
Signed-off-by: Simon Glass
Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks)
---
Add a sample .its file for booting U-Boot on a jerry Chromebook.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch containing a .its file for chromium
doc/chromium/chromebook_jerry.its | 42 +++
1 file changed, 42
Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 74
Add a debug() statement so we can see when something goes wrong with the
regulator.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Add a sample .its file for booting U-Boot on a nyan-big Chromebook.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch containing a .its file for chromium
doc/chromium/nyan-big.its | 42 ++
1 file changed, 42 insertions(+)
At present if the
Signed-off-by: Simon Glass
Fixes: 874ee59 (rockchip: pwm: implement pwm_set_invert())
---
Changes in v2: None
drivers/pwm/rk_pwm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index 59eae0956e..28de62d716
Add instructions for chromebook_jerry.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add instructions and patches for chain-loading into U-Boot on jerry
doc/README.chromium | 70 +
1 file changed, 70 insertions(+)
diff
Add remove() methods for EDP and VOP so that U-Boot can shut down the
video on exit. This avoids leaving DMA running while booting Linux which
can cause problems if Linux uses the frame buffer for something else.
It also makes it clear what is needed to shut down video.
While we are here, make
Most Chromebooks support chain-loading U-Boot but instructions are
somewhat scattered. Add a README to hold this information within the
U-Boot tree. Also add the standard developer keys to simplify the
instructions, since they are small.
For now this only supports nyan-big.
Signed-off-by: Simon
Show the U-Boot banner and board information on the video display during
boot.
Signed-off-by: Simon Glass
---
Changes in v2: None
include/configs/rockchip-common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/rockchip-common.h
At present CP15 init is disabled on tegra. Use the correct option so that
this init is performed on boot. This enables the instruction cache, for
example, which is critical to the machine running at full speed.
Signed-off-by: Simon Glass
---
Changes in v2: None
On reset the standby bit is clear, but if U-Boot is chain-loaded from
another boot loader it may be set. Clear it before starting up video so
that it works correctly.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/video/rockchip/rk_vop.c | 3 +++
1 file changed,
If U-Boot is the secondary boot loader, or has been run from itself, the
SOR may already be powered up. Powering it up again causes a hang, so
detect this situation and skip it.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/video/tegra124/sor.c | 9 +
1
If U-Boot is chain-loaded from a previous boot loader we must set up the
clocks the way U-Boot wants them. Add code for this. It will do nothing if
SPL has already done the job.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board.c | 35
Detect with a previous boot loader has already set up the clocks and set
them up again so that U-Boot gets what it expects.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/clk/rockchip/clk_rk3288.c | 25 +++--
1 file changed, 19 insertions(+),
If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does enable LPAE.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 9 +
1
At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
has an ARMv4T boot CPU. Add a check for the architecture version to allow
the code to be built. It will not actually be executed by the boot CPU,
but needs
This typo doesn't actually cause any problems, but is wrong. Fix it.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/dts/rk3288-veyron-jerry.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts
The display on jerry is so fast that this option is not needed. Drop it so
that the display scrolls more smoothly.
Signed-off-by: Simon Glass
---
Changes in v2: None
configs/chromebook_jerry_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git
For devices that need a delay between SPI transactions we seem to need an
additional delay before the first one if the CPU is running at full speed.
Add this, under control of the existing setting. At present it will only
be enabled with the Chrome OS EC.
Signed-off-by: Simon Glass
At present the interrupt does not work and the SPI bus runs much less
quickly than it should. Add settings to fix this.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git
This appears to be a typo. Fix it.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9bbcf5122..0f7020a315 100644
---
At present early clock init happens in SPL. If SPL did not run (because
for example U-Boot is chain-loaded from another boot loader) then the
clocks are not set as U-Boot expects.
Add a function to detect this and call the early clock init in U-Boot
proper.
Signed-off-by: Simon Glass
This file does not report a few possible errors and one message is missing
a newline. Fix these.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
Enable this so we can roughly measure CPU performance. Also enable the
cache command to allow for timing.
Signed-off-by: Simon Glass
---
Changes in v2: None
configs/nyan-big_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/nyan-big_defconfig
This option allows skipping the call to lowlevel() while still performing
CP15 init. Support this on ARM720T so it can be used with Tegra.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/arm720t/start.S | 6 --
1 file changed, 4 insertions(+), 2
At present the U-Boot banner is only displayed on the serial console. If
this is not visible to the user, the banner does not show. Some devices
have a video display which can usefully display this information.
Add a banner which is printed after relocation only on non-serial devices
if
Move the display options code into a separate function so that the U-Boot
banner can be obtained from other code. Adjust the 'version' command to
use it.
Signed-off-by: Simon Glass
---
Changes in v2: None
cmd/version.c | 4 +++-
include/display_options.h | 15
Every now and then someone wants to chain-load U-Boot on a Chromebook.
The procedure is not very complicated but there are some oddities.
This series updates a few things with allow U-Boot to start on nyan-big
in this way and adds documentation on how to do it. This provides a
central place where
From: Daniel Thompson
Currently these (board agnostic) commands cannot be selected using
menuconfig and friends. Fix this the obvious way. As part of this,
don't muddle the meaning of CONFIG_HASH_VERIFY to mean both 'hash -v'
and "we have a hashing command" as this
On Wed, May 31, 2017 at 12:13:45PM +, Jagan Teki wrote:
> From: Jagan Teki
>
> BPI-M64 is a 64-bit quad-core mini single board computer
> using the Allwinner A64 SOC.
>
> BPI-M64 features
> - 1.2 Ghz Quad-Core ARM Cortex A53
> - 2GB DDR3 SDRAM with 733MHz
> -
On Wed, May 31, 2017 at 08:27:33AM +0200, Jörg Krause wrote:
> Hi Maxime,
>
> On Tue, 2017-05-30 at 23:09 +0200, Maxime Ripard wrote:
> > Hi Jörg,
> >
> > On Tue, May 30, 2017 at 09:39:57AM +0200, Jörg Krause wrote:
> > > On Mon, 2017-02-27 at 18:22 +0100, Maxime Ripard wrote:
> > > >
Hi Tom,
please pull another update for Broadcom MIPS.
This contains new SoC's, new boards and new drivers and some bugfixes.
Travis CI: https://travis-ci.org/danielschwierzeck/u-boot/builds/237925917
The following changes since commit ccbbada0a59fead35495409d0c2c7bcb22a40278:
Merge branch
Hi Kevin,
On 31 May 2017 at 12:13, Kevin Hilman wrote:
> While trying to build v2017.05 for sun5i-r8-chip (CHIP_defconfig), I get
> the following build error. I'm not familiar with binman, so not sure
> what I should be looking for.
>
> $ CROSS_COMPILE=arm-linux-gnueabihf-
Hi Matthew,
On 31 May 2017 at 12:40, Matthew Gorski wrote:
>
>
> On Wed, May 31, 2017 at 2:28 PM, Matthew Gorski
> wrote:
>>
>>
>>
>> On Mon, May 22, 2017 at 7:17 AM, Simon Glass wrote:
>>>
>>> Every now and then someone wants to
On Wed, May 31, 2017 at 2:28 PM, Matthew Gorski
wrote:
>
>
> On Mon, May 22, 2017 at 7:17 AM, Simon Glass wrote:
>
>> Every now and then someone wants to chain-load U-Boot on a Chromebook.
>> The procedure is not very complicated but there are some
On Mon, May 22, 2017 at 7:17 AM, Simon Glass wrote:
> Every now and then someone wants to chain-load U-Boot on a Chromebook.
> The procedure is not very complicated but there are some oddities.
>
> This series updates a few things with allow U-Boot to start on nyan-big
> in
While trying to build v2017.05 for sun5i-r8-chip (CHIP_defconfig), I get
the following build error. I'm not familiar with binman, so not sure
what I should be looking for.
$ CROSS_COMPILE=arm-linux-gnueabihf- make
[...]
LD spl/drivers/serial/built-in.o
LD spl/drivers/built-in.o
LD
On 30 May 2017 at 21:47, Simon Glass wrote:
> Update the clk uclass to support a live device tree.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v4:
> - Update zynq clock driver to use the correct error number
>
> Changes in v3: None
> Changes in v2:
On 30 May 2017 at 21:47, Simon Glass wrote:
> Add support for requesting GPIOs with a live device tree.
>
> This involves adjusting the function signature for the legacy function
> gpio_request_by_name_nodev(), so fix up all callers.
>
> Signed-off-by: Simon Glass
Hi Tom,
Here it is again with the reported problems (zynq_zc702, stm disco) fixed.
The following changes since commit ccbbada0a59fead35495409d0c2c7bcb22a40278:
Merge branch 'master' of git://git.denx.de/u-boot-mmc (2017-05-30
14:07:23 -0400)
are available in the git repository at:
Refactor OMAP3/4/5 code so that we have only one get_device_type()
function for all platforms.
Details:
- Add ctrl variable for AM33xx and OMAP3 platforms (like it's done for
OMAP4/5), so we can obtain status register in common way
- For now ctrl structure for AM33xx/OMAP3 contains only
The RK3399-Q7 has a KSZ9031 GbE PHY. Enable support for it in defconfig.
Signed-off-by: Philipp Tomsich
---
Changes in v2: None
configs/puma-rk3399_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/puma-rk3399_defconfig
The RK3399-Q7 exposes I2C on its edge connector and uses it as one of
the interfaces towards the on-module STM32 (for the emulated RTC and
fan-controller).
Enable I2C and CMD_I2C support in the defconfig.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
With the merging of Andre's SPL_FIT support, the CONFIG_SPL_FIT option
is no longer required for the RK3399-Q7. Remove it from the defconfig.
Signed-off-by: Philipp Tomsich
---
Changes in v2: None
configs/puma-rk3399_defconfig | 1 -
1 file changed, 1
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