Re: [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver

Hi David, On 02/03/2018 02:56 PM, David Wu wrote: > Use this driver to fit all Rockchip SOCs and to support > the desired pinctrl configuration via DTS. > > Signed-off-by: David Wu Reviewed-by: Kever Yang Tested-by: Kever Yang

[U-Boot] About convert to LIVE DT

Hi Simon, Philipp, When I try to convert to live dt, I fount there are many APIs work in fdt are missing in live dt, do you have any suggestion to add these APIs in live dt quickly? I need: fdtdec_get_addr_size_auto_noparent fdt_alloc_phandle fdt_device_is_available fdt_for_each_subnode

Re: [U-Boot] Please pull u-boot-dm

On Sat, Feb 03, 2018 at 10:12:41AM -0700, Simon Glass wrote: > Hi Tom, > > On 26 January 2018 at 17:50, Tom Rini wrote: > > On Fri, Jan 26, 2018 at 02:45:29PM -0700, Simon Glass wrote: > > > >> Hi Tom, > >> > >> Here are some additions to logging and 64-bit sandbox support. >

[U-Boot] [PATCH 2/2] sandbox: Rename 'num-gpios' property to avoid dtc warning

At present dtc produces these warnings when compiling sandbox: arch/sandbox/dts/test.dtb: Warning (gpios_property): Could not get phandle node for /base-gpios:num-gpios(cell 0) arch/sandbox/dts/test.dtb: Warning (gpios_property): Missing property '#gpio-cells' in node /reset-ctl

[U-Boot] [PATCH 1/2] sandbox: Correct dtc warning in /chosen node

At present dtc produces these warnings when compiling sandbox: arch/sandbox/dts/test.dtb: Warning (reg_format): "reg" property in /chosen/chosen-test has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/sandbox/dts/test.dtb: Warning (avoid_default_addr_size): Relying on

Re: [U-Boot] Please pull u-boot-dm

Hi Tom, On 26 January 2018 at 17:50, Tom Rini wrote: > On Fri, Jan 26, 2018 at 02:45:29PM -0700, Simon Glass wrote: > >> Hi Tom, >> >> Here are some additions to logging and 64-bit sandbox support. >> >> >> The following changes since commit

Re: [U-Boot] [PATCH v2] spl: eMMC/SD: Provide one __weak spl_boot_mode() function

On Sat, Feb 3, 2018 at 5:29 AM, Lukasz Majewski wrote: > The goal of this patch is to clean up the code related to choosing SPL > MMC boot mode. > > The spl_boot_mode() now is called only in spl_mmc_load_image() function, > which is only compiled in if CONFIG_SPL_MMC_SUPPORT is

[U-Boot] [PATCH v2] mips: bmips: select OF_EMBED for all boards

Signed-off-by: Álvaro Fernández Rojas --- v2: add missing Huawei HG556a configs/comtrend_ar5315u_ram_defconfig | 1 + configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_ct5361_ram_defconfig| 1 + configs/comtrend_vr3032u_ram_defconfig | 1 +

[U-Boot] [PATCH 13/14] ARM: dts: rockchip: Enable gmac2phy feature for rk3328-evb

In fact, the rk3328-evb is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy. Signed-off-by: David Wu --- arch/arm/dts/rk3328-evb.dts | 10 ++ 1 file changed, 10 insertions(+)

[U-Boot] [PATCH 14/14] rockchip: defconfig: Enable CONFIG_RESET_ROCKCHIP for rk3329-evb and rk3328-evb

The integtated phy inside the rk3229 and rk3328 need the reset request for power up. Signed-off-by: David Wu --- configs/evb-rk3229_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/evb-rk3229_defconfig

[U-Boot] [PATCH 11/14] clk: rk3328: Implement the gmac2phy clock assignment

Implement the setting parent and rate for gmac2phy clock, and add internal pll div set for gmac2phy clk. Signed-off-by: David Wu --- drivers/clk/rockchip/clk_rk3328.c | 86 +++ 1 file changed, 86 insertions(+) diff --git

[U-Boot] [PATCH 10/14] ARM: dts: rockchip: Enable integrated phy support for rk3229-evb

In fact, the evb-rk3229 is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy. Signed-off-by: David Wu --- arch/arm/dts/rk3229-evb.dts | 22 ++ 1 file changed, 22

[U-Boot] [PATCH 12/14] ARM: dts: rockchip: Add gmac2phy dts node for rk3328

The gmac2phy is connected with integrated with phy, we can fix the phy node at dtsi level. Signed-off-by: David Wu --- arch/arm/dts/rk3328.dtsi | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/dts/rk3328.dtsi

[U-Boot] [PATCH 09/14] ARM: dts: rockchip: Add integrated phy reset and clock for rk322x

To support the integrated phy for rk322x, add their reset and clock property at dtsi level. Signed-off-by: David Wu --- arch/arm/dts/rk322x.dtsi | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk322x.dtsi

[U-Boot] [PATCH 07/14] clk: rockchip: Init CPLL 600M for rk322x

The gmac for integrated phy need 50M clock, it seems that only come from CPLL 600M, the GPLL is not suitable. Signed-off-by: David Wu --- arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 + drivers/clk/rockchip/clk_rk322x.c | 11 +++ 2 files

[U-Boot] [PATCH 08/14] clk: rockchip: Add SCLK_MAC_SRC clock rate setup

The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested by the integrated phy usuage. Signed-off-by: David Wu --- drivers/clk/rockchip/clk_rk322x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk322x.c

[U-Boot] [PATCH 06/14] clk: rockchip: fix the gmac selection of pll source for rk322x

There is a wrong selection for gmac pll source, fix it. Signed-off-by: David Wu --- drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index

[U-Boot] [PATCH 05/14] cllk: rockchip: Change the defined name for CONFIG_RESET_ROCKCHIP

It seems that the "CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)" always should not been active. Signed-off-by: David Wu --- drivers/clk/rockchip/clk_rk3036.c | 2 +- drivers/clk/rockchip/clk_rk322x.c | 4 ++-- drivers/clk/rockchip/clk_rk3288.c | 2 +-

[U-Boot] [PATCH 04/14] net: rockchip: Add integrated phy for rk3228 and rk3328

The rk3228 and rk3328 Socs both support integrated phy, implement their power up function to support it. Signed-off-by: David Wu --- drivers/net/gmac_rockchip.c | 122 1 file changed, 122 insertions(+) diff --git

[U-Boot] [PATCH 03/14] net: rockchip: Add integrated phy ops

Some rockchio Socs have integrated phy inside, to support it, add the integrated phy ops. Signed-off-by: David Wu --- drivers/net/gmac_rockchip.c | 29 + 1 file changed, 29 insertions(+) diff --git a/drivers/net/gmac_rockchip.c

[U-Boot] [PATCH 02/14] net: rockchip: Add rmii interface and rmii speed setup for rk3228 and rk3328

The rk3228 and rk3328 Socs both have rmii interface, that might be used, so add them for usage. Signed-off-by: David Wu --- drivers/net/gmac_rockchip.c | 115 1 file changed, 115 insertions(+) diff --git

[U-Boot] [PATCH 01/14] net: rockchip: Separate rmii and rgmii speed setup

Some Socs both have rgmii and rmii interface, so we need to separate their speed setting. Signed-off-by: David Wu --- drivers/net/gmac_rockchip.c | 62 +++-- 1 file changed, 43 insertions(+), 19 deletions(-) diff --git

[U-Boot] [PATCH 00/14] Add integrated phy support for rk322x and rk3328

To support the integrated phy, it is necessary that the gmac need to get 50M clock rate from internal PLL, the integrated phy can't generate 50M clock itself. David Wu (14): net: rockchip: Separate rmii and rgmii speed setup net: rockchip: Add rmii interface and rmii speed setup for rk3228

Re: [U-Boot] [U-Boot,v3,1/2] bcm283x: Add pinctrl driver

On Sat, Feb 03, 2018 at 09:02:25AM +0100, Alexander Graf wrote: > > > On 03.02.18 02:47, Jonathan Gray wrote: > > On Sun, Jan 28, 2018 at 01:54:25PM -0500, Tom Rini wrote: > >> On Tue, Jan 23, 2018 at 06:05:21PM +0100, Alexander Graf wrote: > >> > >>> The bcm283x family of SoCs have a GPIO

Re: [U-Boot] [PATCH] cmd: nvedit: env_get_f must check for env_get_char error codes

On 02/02/2018 21:04, York Sun wrote: > On 02/02/2018 10:51 AM, Maxime Ripard wrote: > > > > Simon, This patch looks correct. But it doesn't fix NOR flash. Do you have plan to add .get_char function to other drivers? Without that function, we cannot get env variables

Re: [U-Boot] [PATCH v3 12/15] env: Allow to build multiple environments in Kconfig

On 01.02.2018 20:47, Maxime Ripard wrote: > On Thu, Feb 01, 2018 at 11:06:14AM +0100, Simon Goldschmidt wrote: >> On 23.01.2018 21:17, Maxime Ripard wrote: >> > Now that we have everything in place in the code, let's allow to build >> > multiple environments backend through Kconfig. >> > >> >

[U-Boot] [PATCH v2 2/3] MIPS: add support for Broadcom MIPS BCM6362 SoC family

Signed-off-by: Álvaro Fernández Rojas --- v2: no changes arch/mips/dts/brcm,bcm6362.dtsi| 186 + arch/mips/mach-bmips/Kconfig | 12 ++ include/configs/bmips_bcm6362.h| 25 +++

[U-Boot] [PATCH v2 3/3] MIPS: add BMIPS Netgear DGND3700v2 board

Signed-off-by: Álvaro Fernández Rojas --- v2: Introduce changes suggested by Daniel Schwierzeck: - Use setbits_be32() arch/mips/dts/Makefile | 1 + arch/mips/dts/netgear,dgnd3700v2.dts | 121 +++

[U-Boot] [PATCH v2 0/3] mips: bmips: add BCM6362 SoC support

BCM6362 is a dual core BCM63xx SoC. v2: Introduce changes suggested by Daniel Schwierzeck: - Use setbits_be32() Álvaro Fernández Rojas (3): dm: cpu: bmips: add BCM6362 support MIPS: add support for Broadcom MIPS BCM6362 SoC family MIPS: add BMIPS Netgear DGND3700v2 board

Re: [U-Boot] [U-Boot,v3,1/2] bcm283x: Add pinctrl driver

On 03.02.18 02:47, Jonathan Gray wrote: > On Sun, Jan 28, 2018 at 01:54:25PM -0500, Tom Rini wrote: >> On Tue, Jan 23, 2018 at 06:05:21PM +0100, Alexander Graf wrote: >> >>> The bcm283x family of SoCs have a GPIO controller that also acts as >>> pinctrl controller. >>> >>> This patch introduces