Hi Tom,
Please pull the following patch from u-boot-riscv into your tree.
Thanks!
The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7:
add FIT data-position & data-offset property support (2018-05-26 18:19:19
-0400)
are available in the Git repository at:
git://
On 28.05.2018 13:39, Chris Packham wrote:
Add DM support for the Marvell RTC driver.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
On 28.05.2018 13:39, Chris Packham wrote:
Split the rtc_{get,set,reset} functions so that the bodies can be used
in a DM driver.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
htt
On 28.05.2018 12:35, Baruch Siach wrote:
From: Jon Nettleton
The a38x sata interfaces run in ahci mode and can
be accessed via the scsi command.
Signed-off-by: Jon Nettleton
[baruch: rebase on current upstream]
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Thanks,
Stefan
Hi Dennis,
On 26.05.2018 22:02, dgilm...@redhat.com wrote:
From: Dennis Gilmore
The helios4 is built on the SolidRun Armada 38x SOM.
Which specific SoM?
The port os based on the ClearFog board, using information from
https://github.com/helios-4/u-boot-marvell as well as dtb input
from http
On 28.05.2018 08:33, Baruch Siach wrote:
From: Jon Nettleton
Both ping_receive and arp_receive would transmit a received packet
back out using its original point. This causes problems with
certain network cards that add a custom header to the packet.
Specifically the mvneta driver for the Arma
On 28.05.2018 08:33, Baruch Siach wrote:
> From: Jon Nettleton
>
> This makes sure the DMA buffers are properly aligned for the
> hardware.
>
> Signed-off-by: Jon Nettleton
> Signed-off-by: Baruch Siach
> ---
> drivers/net/mvneta.c | 20 ++--
> 1 file changed, 14 insertions(
On 29.05.2018 06:45, Baruch Siach wrote:
Equivalent code that disables the hidden i2c0 slave already exists in
the Turris Omnia platform specific code. But this hidden i2c0 slave that
interferes the i2c bus is not board specific. Armada 38x SoCs and at
least some Kirkwood variants are affected as
Hi,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, May 29, 2018 10:22 AM
> To: Marek Vasut ; Siva Durga Prasad Paladugu
>
> Cc: U-Boot Mailing List ; Tom Rini
>
> Subject: Re: [U-Boot] [PATCH] sf: Enable FSR polling on N25Q256(A)
>
> + Siva
>
On 28.5.2018 10:12, Clement Laigle wrote:
> MiniZed is a single-core Zynq 7Z007S development board.
>
> More information on this board: http://zedboard.org/product/minized
>
> Signed-off-by: Clement Laigle
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/zynq-minized.dts | 61
>
On 29.05.2018 07:10, Chris Packham wrote:
On Tue, May 29, 2018 at 4:58 PM Baruch Siach wrote:
Hi Chris,
On Tue, May 29, 2018 at 10:53:38AM +1200, Chris Packham wrote:
On Tue, May 29, 2018 at 4:11 AM Baruch Siach wrote:
From: Jon Nettleton
This switches the clearfog boards to use DM
2018-05-26 11:06 GMT+09:00 Simon Glass :
> +Masahiro
>
> On 25 May 2018 at 02:50, Ley Foon Tan wrote:
>>
>> On Fri, May 25, 2018 at 11:33 AM, Simon Glass wrote:
>> > Hi,
>> >
>> > On 24 May 2018 at 21:24, Ley Foon Tan wrote:
>> >>
>> >> On Thu, May 24, 2018 at 12:33 AM, Simon Glass wrote:
>> >>
On Tue, May 29, 2018 at 4:58 PM Baruch Siach wrote:
> Hi Chris,
> On Tue, May 29, 2018 at 10:53:38AM +1200, Chris Packham wrote:
> > On Tue, May 29, 2018 at 4:11 AM Baruch Siach wrote:
> >
> > > From: Jon Nettleton
> >
> > > This switches the clearfog boards to use DM based gpio and i2c
> > >
On Mon, May 28, 2018 at 11:13 PM, Vasily Khoruzhick wrote:
> You need both patches in order for it to work.
>
> I tested these patches on Pinebook and Pine64 LTS, both were able to
> boot from eMMC. What board are you using?
Did you test BPI-M64? Here is the another board [1] where it failed
[1]
Hi Chris,
On Tue, May 29, 2018 at 10:53:38AM +1200, Chris Packham wrote:
> On Tue, May 29, 2018 at 4:11 AM Baruch Siach wrote:
>
> > From: Jon Nettleton
>
> > This switches the clearfog boards to use DM based gpio and i2c
> > drivers. The io expanders are configured via their device-tree
> >
+ Siva
On Fri, May 25, 2018 at 1:28 AM, Marek Vasut wrote:
> The N25Q256(A) datasheet clearly states that this device does have
> a Flag Status Register and does update FSR PEC bit 7 during Program
> and Erase cycles to indicate the cycle is in progress. Enable the
> FSR PEC bit polling on this d
Code that disables the i2c slave is now in the mvtwsi i2c driver.
Platform must enable DM_I2C to use that code. Add a comment in the code
as a reminder for the planned DM_I2C migration of Turris Omnia.
Reviewed-by: Heiko Schocher
Signed-off-by: Baruch Siach
---
v2: Add Reviewed-by from Heiko
---
Equivalent code that disables the hidden i2c0 slave already exists in
the Turris Omnia platform specific code. But this hidden i2c0 slave that
interferes the i2c bus is not board specific. Armada 38x SoCs and at
least some Kirkwood variants are affected as well. Add code to disable
this slave to th
On Wed, May 16, 2018 at 8:15 PM, Marek Vasut wrote:
> Add ID for the Winbond W25Q256 flash.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> ---
Applied to u-boot-spi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/
On Thu, May 17, 2018 at 6:19 PM, Marek Vasut wrote:
> Add ID for the Macronix MX25U25635F flash.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> ---
Applied to u-boot-spi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/list
Hello Chris,
Am 29.05.2018 um 05:49 schrieb Chris Packham:
On Tue, May 29, 2018 at 2:39 PM Baruch Siach wrote:
Hi Chris,
On Tue, May 29, 2018 at 10:32:47AM +1200, Chris Packham wrote:
Did you intend to omit the u-boot mailing list?
No, sorry. Thanks for noticing. I'll resend with the c
Hello Peng,
Am 28.05.2018 um 14:25 schrieb Peng Fan:
From: Ye Li
When doing "i2c dev 4; i2c probe" with ENET daughter card connected
on iMX8QXP MEK board, we met a i2c bus busy issue, that the BBF of
lpi2c always show busy, but the master is idle, and stop is detected
(SDF set).
This patch ad
On Tue, May 29, 2018 at 3:56 PM Baruch Siach wrote:
> Hi Chris,
> On Tue, May 29, 2018 at 03:49:44PM +1200, Chris Packham wrote:
> > On Tue, May 29, 2018 at 2:39 PM Baruch Siach wrote:
> > > On Tue, May 29, 2018 at 10:32:47AM +1200, Chris Packham wrote:
> > > > Did you intend to omit the u-boot
Hi Chris,
On Tue, May 29, 2018 at 03:49:44PM +1200, Chris Packham wrote:
> On Tue, May 29, 2018 at 2:39 PM Baruch Siach wrote:
> > On Tue, May 29, 2018 at 10:32:47AM +1200, Chris Packham wrote:
> > > Did you intend to omit the u-boot mailing list?
>
> > No, sorry. Thanks for noticing. I'll resen
Hello Peng,
Am 28.05.2018 um 14:25 schrieb Peng Fan:
From: Ye Li
In xfer function, both bus_i2c_read and bus_i2c_write will
send a STOP command. This causes a problem when reading register
data from i2c device.
Generally two operations comprise the register data reading:
1. Write the reg
Hello Peng,
Am 28.05.2018 um 14:25 schrieb Peng Fan:
From: Gao Pan
For LPI2C IP, NACK is detected by the rising edge of the ninth clock.
In current uboot driver, once NACK is detected, it will reset and then
disable LPI2C master. As a result, we can never see the falling edge
of the ninth cloc
On Tue, May 29, 2018 at 2:39 PM Baruch Siach wrote:
> Hi Chris,
> On Tue, May 29, 2018 at 10:32:47AM +1200, Chris Packham wrote:
> > Did you intend to omit the u-boot mailing list?
> No, sorry. Thanks for noticing. I'll resend with the change that Stefan
> suggested and keep your Tested-by.
>
Hello Peng,
Am 28.05.2018 um 14:25 schrieb Peng Fan:
From: Ye Li
Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory
to u-boot include directory as a common header file.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
Cc: Heiko Schocher
---
drivers/i2c/imx_lpi2c.c
Hello Tom,
please pull from u-boot-ubi.git master
The following changes since commit 624d2cae3401c2e4d43c571a9b81d1f650e7703d:
SPDX: Fixup SPDX tags in a few new files (2018-05-20 09:47:45 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-ubi.git master
for you to f
Hello Patrice,
Am 22.05.2018 um 10:10 schrieb Patrice Chotard:
Since 'commit f82290afc847 ("mtd: ubi: Fix worker handling")',
when booting from NAND, on a fresh NAND just after being flashed (and
only in this case), we got the following log:
ubi0: default fastmap pool size: 200
ubi0: default fa
Hi Chris,
On Tue, May 29, 2018 at 10:32:47AM +1200, Chris Packham wrote:
> Did you intend to omit the u-boot mailing list?
No, sorry. Thanks for noticing. I'll resend with the change that Stefan
suggested and keep your Tested-by.
> On Tue, May 29, 2018 at 3:11 AM Baruch Siach wrote:
> > Equiva
> -Original Message-
> From: Benoît Thébaudeau [mailto:benoit.thebaudeau@gmail.com]
> Sent: 2018年5月29日 6:32
> To: Peng Fan
> Cc: sba...@denx.de; Fabio Estevam ; U-Boot
> ; Bough Chen
> Subject: Re: [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock
> setting issue
>
>
On Sun, May 27, 2018 at 07:45:12PM -0600, Simon Glass wrote:
> +Tom
>
> Hi Angelo,
>
> On 27 May 2018 at 01:22, Angelo Dureghello wrote:
> > Hi Simon,
> >
> > On Sat, May 26, 2018 at 04:18:57PM -0600, Simon Glass wrote:
> >> Hi Angelo,
> >>
> >> On 3 May 2018 at 16:01, Angelo Dureghello wrote:
Hi, Bryan
Anson Huang
Best Regards!
> -Original Message-
> From: Bryan O'Donoghue [mailto:bryan.odonog...@linaro.org]
> Sent: Monday, May 28, 2018 4:59 PM
> To: Anson Huang ; sba...@denx.de; Fabio Estevam
> ; albert.u.b...@aribaud.net;
> christian.gmei...@gmail.com; Peng Fan ;
> patrick.
On Tue, May 29, 2018 at 11:12:22AM +1200, Chris Packham wrote:
> Hi Tom,
> On Tue, May 29, 2018 at 7:12 AM Tom Rini wrote:
>
> > On Wed, May 16, 2018 at 08:34:14PM +1200, Chris Packham wrote:
>
> > > Now that there are more boards defining this it can be removed from the
> > > whitelist.
> > >
>
This is initial support for the Pengpod 1000 tablet. The display is
not currently working but the UART works fine and allows access to the
u-boot console. Memory timing is fine and Linux boots from SD card
and runs OK.
Signed-off-by: Bob Ham
---
arch/arm/dts/Makefile | 1 +
>
>
>>
> I understand that this might fix an issue on a specific board (ClearFog
> in this case, correct?). But are you sure that its safe to force this
> link detection for all A38x boards?
>
We have tested on clearfog-pro / base and two other custom boards that we
have.
On long traces this fix m
On 05/28/2018 11:07 PM, Jorge Ramirez-Ortiz wrote:
Jorge, I just sent you a fix. can you test it and if it works I'll
push it upstream.
yes I can see the console now so that fix is good.
however there must be some other regression lurking because the system
wont boot a kernel from the SD card
2018-05-28 18:44 GMT+09:00 Ramon Fried :
> Add WARN_ONCE definition to allow single time notification
> of warnings to the user.
>
> Signed-off-by: Ramon Fried
> ---
> include/linux/bug.h | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/include/linux/bug.h b/include/li
Hi Tom,
On Tue, May 29, 2018 at 7:12 AM Tom Rini wrote:
> On Wed, May 16, 2018 at 08:34:14PM +1200, Chris Packham wrote:
> > Now that there are more boards defining this it can be removed from the
> > whitelist.
> >
> > Signed-off-by: Chris Packham
> > Reviewed-by: Simon Glass
> Applied to u-
On Tue, May 29, 2018 at 4:11 AM Baruch Siach wrote:
> From: Jon Nettleton
> This switches the clearfog boards to use DM based gpio and i2c
> drivers. The io expanders are configured via their device-tree
> entries.
> Signed-off-by: Jon Nettleton
> [baruch: add DT i2c aliases]
> Signed-off-by
On Tue, May 29, 2018, 12:11 AM Jorge Ramirez-Ortiz
wrote:
>
> On 05/28/2018 11:07 PM, Jorge Ramirez-Ortiz wrote:
>
> Jorge, I just sent you a fix. can you test it and if it works I'll
> push it upstream.
>
>
> yes I can see the console now so that fix is good.
>
> however there must be some other
The missing clock causes serial_msm driver probe to fail.
Added a dummy node so the probe succeeds, as the clock init
currently in db820c is empty.
Fixes: 11d59fe5374a ("serial: serial_msm: fail probe if settings clocks fails")
Signed-off-by: Ramon Fried
---
arch/arm/dts/dragonboard820c.dts | 1
On Tue, May 29, 2018 at 12:52 AM Stefan Roese wrote:
> (Added Mario and Chris)
> On 27.05.2018 17:34, Baruch Siach wrote:
> > From: Rabeeh Khoury
> >
> > Some QCA988x based modules presence is not detected by the SERDES lanes,
> > so force this detection which will trigger the LTSSM state machi
Dear Peng Fan,
On Mon, May 28, 2018 at 2:25 PM, Peng Fan wrote:
> From: Ye Li
>
> When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
> the actual clock rate is just half of the expected clock.
>
> This patch set the DDR_EN bit first for DDR mode, hardware divide
> the usdhc clock
On 05/28/2018 10:25 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 11:14 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 11:07 PM, Jorge Ramirez-Ortiz
wrote:
On 05/28/2018 10:01 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
wrote:
On 05/28/2018 09:48 PM, Ramon
Pool size must be increased to support new additionals
drivers.
Signed-off-by: Ramon Fried
---
v2: increase pool size to 0x200 as suggested by Tom.
arch/arm/mach-snapdragon/Kconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdrag
On Mon, May 28, 2018 at 10:35 PM, Tom Rini wrote:
> On Mon, May 28, 2018 at 10:28:51PM +0300, Ramon Fried wrote:
>> On Mon, May 28, 2018 at 10:26 PM, Tom Rini wrote:
>> > On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
>> >> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>> >>
On Mon, May 28, 2018 at 11:07 PM, Jorge Ramirez-Ortiz
wrote:
> On 05/28/2018 10:01 PM, Ramon Fried wrote:
>>
>> On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
>> wrote:
>>>
>>> On 05/28/2018 09:48 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 10:24 PM, Ramon Fried
wrote:
>
On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
wrote:
> On 05/28/2018 09:48 PM, Ramon Fried wrote:
>>
>> On Mon, May 28, 2018 at 10:24 PM, Ramon Fried
>> wrote:
>>>
>>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>>> wrote:
On 05/28/2018 09:12 PM, Tom Rini wrote:
>
On 05/28/2018 10:01 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
wrote:
On 05/28/2018 09:48 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 10:24 PM, Ramon Fried
wrote:
On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
wrote:
On 05/28/2018 09:12 PM, Tom R
On Mon, May 28, 2018 at 10:24 PM, Ramon Fried wrote:
> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
> wrote:
>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>
>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>
UART clock enabling flow was wrong.
Changed the flow
On 05/28/2018 09:48 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 10:24 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
wrote:
On 05/28/2018 09:12 PM, Tom Rini wrote:
On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
UART clock enabling flow was wro
On Mon, May 28, 2018 at 11:14 PM, Ramon Fried wrote:
> On Mon, May 28, 2018 at 11:07 PM, Jorge Ramirez-Ortiz
> wrote:
>> On 05/28/2018 10:01 PM, Ramon Fried wrote:
>>>
>>> On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
>>> wrote:
On 05/28/2018 09:48 PM, Ramon Fried wrote:
>
On Mon, May 28, 2018 at 10:28:51PM +0300, Ramon Fried wrote:
> On Mon, May 28, 2018 at 10:26 PM, Tom Rini wrote:
> > On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
> >> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
> >> wrote:
> >> > On 05/28/2018 09:12 PM, Tom Rini wrote:
>
On Mon, May 28, 2018 at 10:26 PM, Tom Rini wrote:
> On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>> wrote:
>> > On 05/28/2018 09:12 PM, Tom Rini wrote:
>> >>
>> >> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
On Thu, May 17, 2018 at 02:50:43PM +0200, Patrice Chotard wrote:
> Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and
> USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets.
> Sort defines by descendant order.
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Simon Glass
Applie
On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
> wrote:
> > On 05/28/2018 09:12 PM, Tom Rini wrote:
> >>
> >> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
> >>
> >>> UART clock enabling flow was wrong.
> >>> Chan
On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
wrote:
> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>
>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>
>>> UART clock enabling flow was wrong.
>>> Changed the flow according to downstream implementation in LK.
>>>
>>> Signed-off
On Thu, May 17, 2018 at 04:53:57PM +0200, Patrice Chotard wrote:
> SDMMC_CMD_CPSMEN bit is wrongly check and set in
> SDMMC_ARG register instead of SDMMC_CMD register.
>
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
__
On 05/28/2018 09:12 PM, Tom Rini wrote:
On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.
Signed-off-by: Ramon Fried
Applied to u-boot/master, thanks!
Ramon, did you re-test this
On Thu, May 17, 2018 at 02:50:45PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Add possibility to update the serial parity used.
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP sig
On Sat, May 19, 2018 at 06:21:37PM +0800, Kelvin Cheung wrote:
> Add FIT data-position & data-offset property support for bootm,
> which were already supported in SPL.
>
> Signed-off-by: Kelvin Cheung
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Sat, May 26, 2018 at 04:18:45PM -0600, Simon Glass wrote:
> Hi,
>
> On 15 May 2018 at 19:52, Simon Glass wrote:
> > This series ads a few more features to binman, principally the ability to
> > nest entries within other entries, to form hierarchical images.
> >
> > Also included are support fo
On Wed, May 16, 2018 at 12:13:41PM +0300, Ramon Fried wrote:
> Added TLMM pinctrl node for pin muxing & config.
> Additionally, added a serial node for uart.
>
> Signed-off-by: Ramon Fried
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Fri, May 18, 2018 at 06:03:12PM +0800, Ley Foon Tan wrote:
> Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use
> malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes
> to align with the requested alignment.
>
> The original memalign() function
On Wed, May 16, 2018 at 12:13:38PM +0300, Ramon Fried wrote:
> The uart is already initialized prior to relocation,
> reinitialization after relocation is unnecessary.
>
> Signed-off-by: Ramon Fried
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Descripti
On Thu, May 17, 2018 at 03:24:04PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> The register TAMP_BOOT_CONTEXT is already updated in
> get_bootmode() in cpu.c and no need to be done
> twice.
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrice Chotard
Applied to u-boot/
On Thu, May 17, 2018 at 02:50:46PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Add the needed information to enable the debug uart
> to have printf before the serial driver probe
> (so before probe for clock, pincontrol and reset drivers)
>
> To enable the debug on uart 4 (defaul
On Thu, May 17, 2018 at 03:24:05PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Add a MISC driver with read and write access to BSEC IP
> (Boot and Security and OTP control)
> - offset 0: shadowed values
> - offset 0x8000: OTP fuse box values (SAFMEM)
>
> Signed-off-by: Patric
On Mon, May 14, 2018 at 07:38:12PM +0300, Tuomas Tynkkynen wrote:
> All of the debug output from this file is squished to one line. Fix
> it.
>
> Signed-off-by: Tuomas Tynkkynen
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
___
On Mon, May 14, 2018 at 07:38:13PM +0300, Tuomas Tynkkynen wrote:
> Currently, if we happen to allocate an address requiring 64 bits to a
> device only supporting 32-bit BARs, the address eventually gets silently
> truncated to 32 bits. Avoid this by adding a new flag to
> pciauto_region_allocate(
On Thu, May 17, 2018 at 03:24:06PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Add support of fuse command (read/write/program/sense)
> on bank 0 to access to BSEC SAFMEM (4096 OTP bits).
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrice Chotard
Applied to u-boot/ma
On Thu, May 17, 2018 at 02:50:42PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Add support for early debug printf, before the availability of
> driver model and device tree support.
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrice Chotard
> Reviewed-by: Simon Glass
On Wed, May 16, 2018 at 12:13:40PM +0300, Ramon Fried wrote:
> This patch adds pinmux and pinctrl driver for TLMM
> subsystem in snapdragon chipsets.
> Currently, supporting only 8016, but implementation is
> generic and 8096 can be added easily.
>
> Driver is using the generic dt-bindings and do
On Wed, May 16, 2018 at 12:13:42PM +0300, Ramon Fried wrote:
> Serial port configuration was missing from previous implementation.
> It only worked because it was preconfigured by LK.
> This patch configures the uart for 115200 8N1.
> It also configures the pin mux for uart pins using DT bindings.
On Wed, May 16, 2018 at 12:13:36PM +0300, Ramon Fried wrote:
> The clock and serial nodes are needed before relocation.
> This patch ensures that the msm-serial driver will probe
> and provide uart output before relocation.
>
> Signed-off-by: Ramon Fried
> Reviewed-by: Simon Glass
Applied to u
On Wed, May 16, 2018 at 08:34:14PM +1200, Chris Packham wrote:
> Now that there are more boards defining this it can be removed from the
> whitelist.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signatur
On Thu, May 17, 2018 at 02:50:44PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Implements serial setparity ops to allow uart parity change.
> It allows to select ODD, EVEN or NONE parity.
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrice Chotard
Applied to u-boot/ma
On Thu, May 17, 2018 at 03:24:07PM +0200, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Use OTP57 and 58 for MAC address
> - OTP57 = MAC address bits [31:0]
> - OTP58 = MAC address bit [47:32] stored in OTP LSB's
>
> Use manufacture information in OTP13 to OTP15 to build unique
> chip
On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
> UART clock enabling flow was wrong.
> Changed the flow according to downstream implementation in LK.
>
> Signed-off-by: Ramon Fried
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
__
On Wed, May 16, 2018 at 05:27:11PM +0200, Radoslaw Pietrzyk wrote:
> - adds reading FMC swap setting from DTB to SDRAM driver
> - sets FMC swap for stm32f429-disco board
> - changes ram start address to 0x9000
>
> Signed-off-by: Radoslaw Pietrzyk
> Acked-by: Patrice Chotard
Applied to u-bo
On Mon, May 14, 2018 at 11:50:05PM +0300, Tuomas Tynkkynen wrote:
> Add a doc comment for pciauto_region_allocate().
>
> Signed-off-by: Tuomas Tynkkynen
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Wed, May 16, 2018 at 12:13:37PM +0300, Ramon Fried wrote:
> Failure to set the clocks will causes data abort exception when
> trying to write to AHB uart registers.
> This patch ensures that we don't touch these registers if clock
> setting failed.
>
> Signed-off-by: Ramon Fried
> Reviewed-by
On Mon, May 14, 2018 at 06:47:52PM +0300, Tuomas Tynkkynen wrote:
> Now that U-Boot works fine with highmem enabled, there is no need to
> tell users to disable highmem.
>
> Signed-off-by: Tuomas Tynkkynen
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
De
On Mon, May 14, 2018 at 06:47:50PM +0300, Tuomas Tynkkynen wrote:
> Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with
> the 'highmem=off' parameter passed to QEMU's virt machine. The reason is
> that when 'highmem' is not disabled, QEMU appends 64-bit a memory
> resource to the
On Mon, May 14, 2018 at 06:47:51PM +0300, Tuomas Tynkkynen wrote:
> Now that PCI devices work with highmem-enabled QEMU emulation, bump up
> the RAM size in the MMU tables to gain access to the full 255 GB of RAM
> potential instead of the puny 3 GB.
>
> Signed-off-by: Tuomas Tynkkynen
> Reviewe
You need both patches in order for it to work.
I tested these patches on Pinebook and Pine64 LTS, both were able to
boot from eMMC. What board are you using?
On Sun, May 27, 2018 at 11:43 AM, Jagan Teki wrote:
> On Mon, May 14, 2018 at 8:57 PM, Vasily Khoruzhick wrote:
>> That is necessary for
From: Jon Nettleton
This switches the clearfog boards to use DM based gpio and i2c
drivers. The io expanders are configured via their device-tree
entries.
Signed-off-by: Jon Nettleton
[baruch: add DT i2c aliases]
Signed-off-by: Baruch Siach
---
The context lines in this patch depend on the p
Android documentation defines the recommended image format for storing
DTB/DTBO files in a single dtbo.img image. This patch includes the
latest header file with the struct definitions for this format from
AOSP.
The header was adapted to U-Boot's coding style and the function
declarations were rem
On 28.05.2018 15:15, Mario Six wrote:
Hi Stefan,
On Mon, May 28, 2018 at 2:52 PM, Stefan Roese wrote:
(Added Mario and Chris)
On 27.05.2018 17:34, Baruch Siach wrote:
From: Rabeeh Khoury
Some QCA988x based modules presence is not detected by the SERDES lanes,
so force this detection whic
On 28.05.2018 16:16, Rabeeh Khoury wrote:
I understand that this might fix an issue on a specific board (ClearFog
in this case, correct?). But are you sure that its safe to force this
link detection for all A38x boards?
We have tested on clearfog-pro / base and two other custom bo
On Mon, May 28, 2018 at 12:02:31PM +0200, Alex Deymo wrote:
> Hi,
> I checked with our team and the include/dt_table.h import as BSD-3 here is
> fine with us. Would you like me to send a patch with just this header file
> or just Signed-off-by this whole patch?
> Thanks,
> deymo@
Thanks and pleas
On 26.05.2018 12:32, Chris Packham wrote:
This was being used by some Marvell boards to enable some file system
related features (many of which have already been moved to Kconfig).
Make the future migration of the final 2 or 3 config options easier by
expanding #define CONFIG_SYS_MVFS into the op
MiniZed is a single-core Zynq 7Z007S development board.
More information on this board: http://zedboard.org/product/minized
Signed-off-by: Clement Laigle
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-minized.dts | 61 ++
configs/zynq_mini
Hi Alex, Sam,
Sam have you tested Alex patches on your HW (as you asked earlier for
the repo to fetch the code)?
Could you add Tested-by: tag?
Are there any more comments on this series?
Best regards,
Łukasz
> This series merges the fastboot UDP support from AOSP into mainline
> U-Boot.
>
> C
Hi Stefan,
On Mon, May 28, 2018 at 2:52 PM, Stefan Roese wrote:
> (Added Mario and Chris)
>
>
> On 27.05.2018 17:34, Baruch Siach wrote:
>>
>> From: Rabeeh Khoury
>>
>> Some QCA988x based modules presence is not detected by the SERDES lanes,
>> so force this detection which will trigger the LTSS
Hi Simon,
On Fri, May 25, 2018 at 4:41 AM, Simon Glass wrote:
> +Marex
>
> Hi Mario,
>
> On 23 May 2018 at 08:07, Mario Six wrote:
>> The comments in misc.h are not in kernel-doc format. Correct the format.
>>
>> Signed-off-by: Mario Six
>>
>> ---
>>
>> v2 -> v3:
>> New in v3
>>
>> ---
>> incl
(Added Mario and Chris)
On 27.05.2018 17:34, Baruch Siach wrote:
From: Rabeeh Khoury
Some QCA988x based modules presence is not detected by the SERDES lanes,
so force this detection which will trigger the LTSSM state machine to
negotiate link.
An example of such a card is WLE900VX.
Signed-of
Just an FYI, earlier this month the team spent some time polishing and
publishing in source.android.com documentation about the flows the
bootloader goes through in Android, specially true for stock Android like
in Pixels phones or other devices based of recent AOSP versions.
Take a look at https:
1 - 100 of 233 matches
Mail list logo