Re: [U-Boot] [PATCH] arm: socfpga: Move Stratix 10 SDRAM driver to DM

[Ley Foon Tan]

On Thu, Mar 28, 2019 at 5:24 PM Simon Goldschmidt
 wrote:
>
> On Thu, Mar 28, 2019 at 3:06 AM Ley Foon Tan  wrote:
> >
> > On Wed, Mar 27, 2019 at 7:34 PM Simon Goldschmidt
> >  wrote:
> > >
> > > On Wed, Mar 27, 2019 at 10:15 AM Ley Foon Tan  
> > > wrote:
> > > >
> > > > Convert Stratix 10 SDRAM driver to device model.
> > >
> > > Nice to see that :-)
> > >
> > > >
> > > > Get rid of call to socfpga_per_reset() and use reset
> > > > framework.
> > > >
> > > > SPL is changed from calling function in SDRAM driver
> > > > directly to just probing UCLASS_RAM.
> > > >
> > > > Move sdram_s10.h from arch to driver/ddr/altera directory.
> > > >
> > > > Signed-off-by: Ley Foon Tan 
> > > > ---
> > > >  arch/arm/Kconfig  |   4 +-
> > > >  arch/arm/dts/socfpga_stratix10.dtsi   |  10 +
> > > >  arch/arm/dts/socfpga_stratix10_socdk.dts  |   4 +
> > > >  arch/arm/mach-socfpga/Kconfig |   1 +
> > > >  arch/arm/mach-socfpga/spl_s10.c   |   9 +-
> > > >  drivers/ddr/altera/Kconfig|   2 +-
> > > >  drivers/ddr/altera/sdram_s10.c| 246 --
> > > >  .../mach => drivers/ddr/altera}/sdram_s10.h   |   4 -
> > > >  include/configs/socfpga_stratix10_socdk.h |   5 -
> > > >  9 files changed, 195 insertions(+), 90 deletions(-)
> > > >  rename {arch/arm/mach-socfpga/include/mach => 
> > > > drivers/ddr/altera}/sdram_s10.h (97%)
> > > >
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index 77a534f81fd..a2d4f7f4c25 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -821,14 +821,14 @@ config ARCH_SOCFPGA
> > > > select DM_SERIAL
> > > > select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || 
> > > > TARGET_SOCFPGA_ARRIA10
> > > > select OF_CONTROL
> > > > -   select RAM if TARGET_SOCFPGA_GEN5
> > > > +   select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
> > > > select SPL_DM_RESET if DM_RESET
> > > > select SPL_DM_SERIAL
> > > > select SPL_LIBCOMMON_SUPPORT
> > > > select SPL_LIBGENERIC_SUPPORT
> > > > select SPL_NAND_SUPPORT if SPL_NAND_DENALI
> > > > select SPL_OF_CONTROL
> > > > -   select SPL_RAM if TARGET_SOCFPGA_GEN5
> > > > +   select SPL_RAM if TARGET_SOCFPGA_GEN5 || 
> > > > TARGET_SOCFPGA_STRATIX10
> > > > select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
> > > > select SPL_SERIAL_SUPPORT
> > > > select SPL_WATCHDOG_SUPPORT
> > > > diff --git a/arch/arm/dts/socfpga_stratix10.dtsi 
> > > > b/arch/arm/dts/socfpga_stratix10.dtsi
> > > > index ee93725d648..15d0f88f182 100644
> > > > --- a/arch/arm/dts/socfpga_stratix10.dtsi
> > > > +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> > > > @@ -245,6 +245,16 @@
> > > > u-boot,dm-pre-reloc;
> > > > };
> > > >
> > > > +   sdr: sdr@f8000400 {
> > > > +compatible = "altr,sdr-ctl-s10";
> > > > +reg = <0xf8000400 0x80>,
> > > > +  <0xf801 0x190>,
> > > > +  <0xf8011000 0x500>;
> > > > +resets = < DDRSCH_RESET>;
> > > > +u-boot,dm-pre-reloc;
> > > > +status = "disabled";
> > >
> > > Why is this optional? The SPL won't work without that any more by default,
> > > or would it? I would have thought it's enabled by default?
> > Customer can use either SDRAM controller in HPS or in FPGA.
> > We don't need this driver if SDRAM controller is in FPGA. All
> > initialization process will handled by HW.
> > I think we just need a very simple sdram driver for sdram controller
> > in FPGA, just to setup get_info().
>
> Fair enough. But how often will this be used? Would it make sense to use the
> internal SDRAM controller by default and let the customers with a controller
> in the FPGA override it or is this a common use case?
Yes, will make HPS SDRAM as default and customer needs to disable it
if they use FPGA SDRAM.

Thanks.

Regard
Ley Foon
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[U-Boot] [PATCH v5] arm: dts: Stratix10: Add QSPI node

[Ley Foon Tan]

Merge qspi dts node from Linux.
Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10)

Add -u-boot.dtsi files for non Linux dts properties and
update properties for Uboot.
- add u-boot,dm-pre-reloc
- add alias for spi0
- change compatible for flash
- support quad read and quad write
- change maximum frequency to 100MHz

Tested on Stratix 10 SoC devkit.
SOCFPGA_STRATIX10 # sf probe 0:0
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 
MiB

Signed-off-by: Ley Foon Tan 

---
v4->v5:
- Add -u-boot.dtsi
- Update commit message with Linux commit ID

v3->v4:
- Add qspi node to dtsi based on alphabetical order
- Add spi-tx-bus-width and spi-rx-bus-width

v2->v3:
- Change flash compatible to "jedec,spi-nor"
- Change spi-max-frequency to 100MHz
---
 arch/arm/dts/socfpga_stratix10.dtsi   | 13 +++
 .../dts/socfpga_stratix10_socdk-u-boot.dtsi   | 25 +
 arch/arm/dts/socfpga_stratix10_socdk.dts  | 35 +++
 3 files changed, 73 insertions(+)
 mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10.dtsi
 create mode 100755 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
 mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/socfpga_stratix10.dtsi 
b/arch/arm/dts/socfpga_stratix10.dtsi
old mode 100644
new mode 100755
index ee93725d648..d1ae2fabae0
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -237,6 +237,19 @@
reg = <0xffe0 0x10>;
};
 
+   qspi: spi@ff8d2000 {
+   compatible = "cdns,qspi-nor";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0xff8d2000 0x100>,
+ <0xff90 0x10>;
+   interrupts = <0 3 4>;
+   cdns,fifo-depth = <128>;
+   cdns,fifo-width = <4>;
+   cdns,trigger-address = <0x>;
+   status = "disabled";
+   };
+
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi 
b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
new file mode 100755
index 000..e1cfb522bfc
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+/{
+   aliases {
+   spi0 = 
+   };
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   compatible = "jedec,spi-nor";
+   spi-max-frequency = <1>;
+   spi-tx-bus-width = <4>;
+   spi-rx-bus-width = <4>;
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
b/arch/arm/dts/socfpga_stratix10_socdk.dts
old mode 100644
new mode 100755
index 6e8ddcd9f4c..09c8a174671
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -85,6 +85,41 @@
smplsel = <0>;
 };
 
+ {
+   flash0: flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "n25q00a";
+   reg = <0>;
+   spi-max-frequency = <5000>;
+
+   m25p,fast-read;
+   cdns,page-size = <256>;
+   cdns,block-size = <16>;
+   cdns,read-delay = <1>;
+   cdns,tshsl-ns = <50>;
+   cdns,tsd2d-ns = <50>;
+   cdns,tchsh-ns = <4>;
+   cdns,tslch-ns = <4>;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   qspi_boot: partition@0 {
+   label = "Boot and fpga data";
+   reg = <0x0 0x400>;
+   };
+
+   qspi_rootfs: partition@400 {
+   label = "Root Filesystem - JFFS2";
+   reg = <0x400 0x400>;
+   };
+   };
+   };
+};
+
  {
status = "okay";
 };
-- 
2.19.0

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Re: [U-Boot] [PATCH 07/13 v3] arm: at91: Enable watchdog support

[Stefan Roese]

Hi Eugen,

On 02.04.19 13:50, Stefan Roese wrote:




This breaks pm9261_defconfig

AS  arch/arm/mach-at91/arm926ejs/lowlevel_init.o
./arch/arm/include/asm/arch/at91_wdt.h: Assembler messages:
./arch/arm/include/asm/arch/at91_wdt.h:50: Error: bad instruction
`struct at91_wdt_priv {'
./arch/arm/include/asm/arch/at91_wdt.h:51: Error: bad instruction `void
__iomem*regs'
./arch/arm/include/asm/arch/at91_wdt.h:52: Error: bad instruction `u32
regval'
./arch/arm/include/asm/arch/at91_wdt.h:53: Error: bad instruction `u32
timeout'
./arch/arm/include/asm/arch/at91_wdt.h:54: Error: junk at end of line,
first unrecognized character is `}'
scripts/Makefile.build:314: recipe for target
'arch/arm/mach-at91/arm926ejs/lowlevel_init.o' failed


Sorry about these breakages. I'll fix this and will run the new
patches through Travis and will only send the next version once
this is compile clean.


I've sent out 2 new patch versions and this series now compiles
clean. Here the Travis build log:

https://travis-ci.org/stroese/u-boot/builds/514639947

Thanks,
Stefan
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[U-Boot] [PATCH 07/13 v4] arm: at91: Enable watchdog support

[Stefan Roese]

This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
v4:
- Move struct in header into location not compiled in assembler files
  to remove the compile breakage

v3:
- Move WDT struct and macros into arch header so that it can be used
  by the arch code to start the driver (timeout value)
- This change now enables the use of the "timeout-sec" DT property
  to specifiy a board specific WD timeout value

v2:
- Remove #ifdef to enable compilation also in SPL version

 arch/arm/mach-at91/clock.c | 48 ++
 arch/arm/mach-at91/include/mach/at91_wdt.h | 10 +
 drivers/watchdog/at91sam9_wdt.c| 10 -
 3 files changed, 58 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 64cbc3d1ed..1d3df2c09d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -5,12 +5,17 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 #define EN_UPLL_TIMEOUT500
 
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
+
 void at91_periph_clk_enable(int id)
 {
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -118,3 +123,46 @@ void at91_pllicpr_init(u32 icpr)
 
writel(icpr, >pllicpr);
 }
+
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+   static ulong next_reset;
+   ulong now;
+
+   if (!watchdog_dev)
+   return;
+
+   now = get_timer(0);
+
+   /* Do not reset the watchdog too often */
+   if (now > next_reset) {
+   next_reset = now + 1000;/* reset every 1000ms */
+   wdt_reset(watchdog_dev);
+   }
+}
+
+int arch_early_init_r(void)
+{
+   struct at91_wdt_priv *priv;
+
+   /* Init watchdog */
+   if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
+   debug("Watchdog: Not found by seq!\n");
+   if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
+   puts("Watchdog: Not found!\n");
+   return 0;
+   }
+   }
+
+   priv = dev_get_priv(watchdog_dev);
+   if (!priv) {
+   printf("Watchdog: priv not available!\n");
+   return 0;
+   }
+
+   wdt_start(watchdog_dev, priv->timeout * 1000, 0);
+   printf("Watchdog: Started\n");
+
+   return 0;
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h 
b/arch/arm/mach-at91/include/mach/at91_wdt.h
index cd2272367b..a8fc73b3d1 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -25,6 +25,12 @@ typedef struct at91_wdt {
u32 sr;
 } at91_wdt_t;
 
+struct at91_wdt_priv {
+   void __iomem *regs;
+   u32 regval;
+   u32 timeout;
+};
+
 #endif
 
 /* Watchdog Control Register */
@@ -43,4 +49,8 @@ typedef struct at91_wdt {
 #define AT91_WDT_MR_WDDBGHLT   0x1000
 #define AT91_WDT_MR_WDIDLEHLT  0x2000
 
+/* Hardware timeout in seconds */
+#define WDT_MAX_TIMEOUT16
+#define WDT_DEFAULT_TIMEOUT2
+
 #endif
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index a9fd547e2f..000769d46d 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -31,16 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define WDT_SEC2TICKS(s)   (((s) << 8) - 1)
 
-/* Hardware timeout in seconds */
-#define WDT_MAX_TIMEOUT16
-#define WDT_DEFAULT_TIMEOUT2
-
-struct at91_wdt_priv {
-   void __iomem *regs;
-   u32 regval;
-   u32 timeout;
-};
-
 /*
  * Set the watchdog time interval in 1/256Hz (write-once)
  * Counter is 12 bit.
-- 
2.21.0

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[U-Boot] [PATCH 06/13 v4] arm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUT

[Stefan Roese]

This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any
more. The WD timeout value can be provided via the "timeout-sec" DT
property. If not provided this way, the default value of 2 seconds will
be used.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
v4:
- Add CONFIG_IS_ENABLED(OF_CONTROL) to DT property read and provide
  default value for in the non-DT version
  
v3:
- New patch

 README  | 3 ---
 configs/smartweb_defconfig  | 1 -
 configs/taurus_defconfig| 1 -
 drivers/watchdog/Kconfig| 4 
 drivers/watchdog/at91sam9_wdt.c | 4 +++-
 5 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/README b/README
index c9a20db34f..a514f48cae 100644
--- a/README
+++ b/README
@@ -767,9 +767,6 @@ The following options need to be configured:
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
 
-   CONFIG_AT91_HW_WDT_TIMEOUT
-   specify the timeout in seconds. default 2 seconds.
-
 - Real-Time Clock:
 
When CONFIG_CMD_DATE is selected, the type of the RTC
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 7c7220afc8..807a569121 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -59,6 +59,5 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
-CONFIG_AT91_HW_WDT_TIMEOUT=y
 CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 022b0b6da1..d69f4895ef 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -62,5 +62,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
-CONFIG_AT91_HW_WDT_TIMEOUT=y
 CONFIG_USE_TINY_PRINTF=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 115fc4551f..34e78beb2a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -139,10 +139,6 @@ config WDT_AT91
   Select this to enable Microchip watchdog timer, which can be found on
   some AT91 devices.
 
-config AT91_HW_WDT_TIMEOUT
-   bool "AT91 watchdog timeout specified"
-   depends on WDT_AT91
-
 config WDT_MT7621
bool "MediaTek MT7621 watchdog timer support"
depends on WDT && ARCH_MT7620
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index b0a3b4ed58..a9fd547e2f 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -117,10 +117,12 @@ static int at91_wdt_probe(struct udevice *dev)
if (!priv->regs)
return -EINVAL;
 
-#ifdef CONFIG_AT91_HW_WDT_TIMEOUT
+#if CONFIG_IS_ENABLED(OF_CONTROL)
priv->timeout = dev_read_u32_default(dev, "timeout-sec",
 WDT_DEFAULT_TIMEOUT);
debug("%s: timeout %d", __func__, priv->timeout);
+#else
+   priv->timeout = WDT_DEFAULT_TIMEOUT;
 #endif
 
debug("%s: Probing wdt%u\n", __func__, dev->seq);
-- 
2.21.0

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Re: [U-Boot] burning eMMC from sdcard.img in U-Boot

[Jack Mitchell]

On 02/04/2019 21:59, Adam Ford wrote:
> I have a board with eMMC storage.  I've been trying to find an elegant
> solution to burning the sdcard image to eMMC.  I looked at using the
> USB mass storage gadget, but it's a bit slow.  I was hoping to avoid
> having to boot all the way into Linux to do it, but the sdcard.img
> file is larger than the memory I have available.

DFU could be worth a look, it has an mmc backend and may be more
efficient than the mass storage gadget.

> 
> Does anyone have any suggestions on how to burn the contents of a file
> to eMMC (or mmc/sd) from within U-Boot when the source file size may
> vary and it's larger than the available memory, so it needs to be done
> in blocks?
> 
> thanks
> 
> adam
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Re: [U-Boot] [PATCH] ARM: imx6q_logic: Correct phy fixup for broken ethernet

[Jagan Teki]

Hi Adam,

On Sun, Jan 13, 2019 at 5:02 AM Adam Ford  wrote:
>
> The Ethernet has been broken for some time.  This patch unifies
> this board with a few others that use a similar approach to
> enabling phy.  This fixes ar8031 Ethernet controller so it works.
>
> Signed-off-by: Adam Ford 
>
> diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
> index cda76a8084..eb4849117d 100644
> --- a/board/logicpd/imx6/imx6logic.c
> +++ b/board/logicpd/imx6/imx6logic.c
> @@ -60,57 +60,6 @@ static iomux_v3_cfg_t const uart3_pads[] = {
> MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
>  };
>
> -#ifndef CONFIG_SPL_BUILD
> -static void fixup_enet_clock(void)
> -{
> -   struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> -   struct gpio_desc nint;
> -   struct gpio_desc reset;
> -   int ret;
> -
> -   /* Set Ref Clock to 50 MHz */
> -   enable_fec_anatop_clock(0, ENET_50MHZ);

I just wonder why the fec working w/o ene_ref set rate to 50MHz, any idea?
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[U-Boot] [PATCH] riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure

[Andes]

From: Rick Chen 

It occurs since commit 27cb7300ffda
("Ensure device tree DTS is compiled").

More details can refer to
89c2b5c02049aea746b1edee0b4e1d8519dec2f4
ARM: fix arch/arm/dts/Makefile

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/dts/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b400def..f9cd606 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
-- 
2.7.4

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[U-Boot] [PATCH] usb: ehci-mx6: Use common code to extract dr_mode

[Adam Ford]

There exists code in drivers/common/common.c to read the dr_mode
from the device tree.  This patch converts this driver to use that
function to initialize the driver.

Signed-off-by: Adam Ford 

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 948394709f..e24f5ad14a 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ehci.h"
 
@@ -483,23 +484,24 @@ static int ehci_usb_phy_mode(struct udevice *dev)
 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
 {
struct usb_platdata *plat = dev_get_platdata(dev);
-   const char *mode;
+   enum usb_dr_mode dr_mode;
 
-   mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
-   if (mode) {
-   if (strcmp(mode, "peripheral") == 0)
-   plat->init_type = USB_INIT_DEVICE;
-   else if (strcmp(mode, "host") == 0)
-   plat->init_type = USB_INIT_HOST;
-   else if (strcmp(mode, "otg") == 0)
-   return ehci_usb_phy_mode(dev);
-   else
-   return -EINVAL;
+   dr_mode = usb_get_dr_mode(dev_of_offset(dev));
 
-   return 0;
-   }
+   switch (dr_mode) {
+   case USB_DR_MODE_HOST:
+   plat->init_type = USB_INIT_HOST;
+   break;
+   case USB_DR_MODE_UNKNOWN:
+   return -EINVAL;
+   case USB_DR_MODE_PERIPHERAL:
+   plat->init_type = USB_INIT_DEVICE;
+   break;
+   case USB_DR_MODE_OTG:
+   return ehci_usb_phy_mode(dev);
+   };
 
-   return ehci_usb_phy_mode(dev);
+   return 0;
 }
 
 static int ehci_usb_probe(struct udevice *dev)
-- 
2.17.1

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Re: [U-Boot] [PATCH 37/40] x86: Update device tree for TPL

[Simon Glass]

Hi Bin,

On Fri, 22 Feb 2019 at 00:20, Bin Meng  wrote:
>
> Hi Simon,
>
> On Wed, Jan 30, 2019 at 12:01 PM Simon Glass  wrote:
> >
> > Add TPL binaries to the device x86 binman desciption. When enabled, TPL
> > will start first, doing the 16-bit init, then jump to SPL and finally
> > U-Boot proper.
>
> I am confused by "TPL will start first". My understanding is that
> "SPL" starts before "TPL".

No, it is TPL -> SPL - > U-Boot.

Regards,
Simon
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Re: [U-Boot] [PATCH 28/40] x86: Add a sysreset driver for the Intel PCH

[Simon Glass]

Hi Bin,

On Fri, 22 Feb 2019 at 00:20, Bin Meng  wrote:
>
> Hi Simon,
>
> On Wed, Jan 30, 2019 at 12:00 PM Simon Glass  wrote:
> >
> > Intel SoCs support a fairly stardard reset mechanism which can support
> > powering off the device. Add support for this and enable it by default on
> > broadwell, which already has the necessary pm.h header file.
> >
> > This driver augments the standard x86 sysreset driver.
> >
>
> I think we need update the existing sysreset_x86 driver to support
> SYSRESET_POWER_OFF, instead of creating a new driver to do such.
>
> We can add a new PCH ioctl code to get the pmbase, and do the ACPI
> power off in the sysreset_x86 driver.

So are you saying that the registers are the same for all x86 chips?
From what I can tell, the offsets vary.

Regards,
Simon

>
> > Signed-off-by: Simon Glass 
> > ---
> >
> >  arch/x86/cpu/broadwell/Kconfig|   1 +
> >  drivers/sysreset/Kconfig  |   9 ++
> >  drivers/sysreset/Makefile |   1 +
> >  drivers/sysreset/sysreset_intel_pch.c | 125 ++
> >  4 files changed, 136 insertions(+)
> >  create mode 100644 drivers/sysreset/sysreset_intel_pch.c
> >
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 17/40] x86: broadwell: Allow SDRAM init from SPL

[Simon Glass]

Hi Bin,

On Fri, 22 Feb 2019 at 00:19, Bin Meng  wrote:
>
> Hi Simon,
>
> On Wed, Jan 30, 2019 at 12:00 PM Simon Glass  wrote:
> >
> > At present SDRAM is always set up in U-Boot proper. Allow this to be done
>
> I don't understand. I thought SDRAM was already set up in the U-Boot
> SPL in the 64-bit build. The U-Boot proper needs a MMU table which
> resides in RAM, so without RAM being initialized first there is no way
> for U-Boot proper to run. Am I missing anything?

I'll update this to make it clear it is just for broadwell, which
doesn't support 64-bit.

Regards,
Simon

>
> > in SPL instead so that U-Boot proper can be loaded into SDRAM and run
> > from there. This allows U-Boot to be compressed to reduce space, since
> > it is not necessary to run it directly from flash.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> >  arch/x86/cpu/broadwell/Makefile  |  2 +-
> >  arch/x86/cpu/broadwell/northbridge.c | 93 
> >  arch/x86/cpu/broadwell/sdram.c   | 93 
> >  3 files changed, 94 insertions(+), 94 deletions(-)
> >
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Rick Chen]

Hi Bin and Lukas

Rick Chen  於 2019年4月2日 週二 上午9:22寫道：
>
> Hi Bin
>
> Bin Meng  於 2019年4月1日 週一 下午5:01寫道：
> >
> > Hi Rick,
> >
> > On Mon, Apr 1, 2019 at 4:29 PM Andes  wrote:
> > >
> > > From: Rick Chen 
> > >
> > > Changes in v3:
> > > Patch 1
> > > - Rename plic_init() as enable_ipi()
> > > - Remove PLIC_BASE_GET() from enable_ipi()
> > > Patch 2
> > > - Add a space before (PLMT)
> > > Patch 6
> > > - Fix some mis-alignments
> > > - Recovery isa string of CPU1
> > >
> > > Changes in v2:
> > > - Drop patch1 and replace by simple-bus driver
> > > - Rename nds_plic as andes_plic
> > > - Move initialize plic to PLIC_BASE_GET() and called automatically
> > > - Rename nds_plmt as andes_plmt
> > > - Recovery dts isa string
> > >
> > > Rick Chen (7):
> > >   riscv: Add a SYSCON driver for Andestech's PLIC
> > >   riscv: Add a SYSCON driver for Andestech's PLMT
> > >   riscv: ae350: disable ATCPIT100 timer
> > >   riscv: ax25: Add platform-specific Kconfig options
> > >   riscv: ax25: Andes specific cache shall only support in M-mode
> > >   riscv: dts: ae350 support SMP
> > >   riscv: ae350: enable SMP
> > >
> >
> > Looks good to me. Are you going to send PR to Tom to include SMP
> > series in v2019.04?
> >
>
> Thanks for your review.
> But there seem have some suggestions from Lukas to be fixed.
> After that I will send PR to Tom ASAP.
>

I have send V4 and Lukas have reviewed it.
When I try to sync to master, I found that there seem
have CONFIG_DEFAULT_DEVICE_TREE failures issue in u-boot.git master.
Troy have reported it actually. But u-boot-riscv.git is fine.
So I am not sure if I shall sync to master now.
Or I shall wait until it has been fixed.

Rick

> Thanks
> Rick
> > Regards,
> > Bin
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Re: [U-Boot] [PATCH v4 0/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Kever Yang]

Hi Heinrich,


On 04/03/2019 01:19 AM, Heinrich Schuchardt wrote:
> The SPL image for the Tinker Board has to fit into 32 KiB. This includes
> up to 2 KiB for the file header.

32KB is the limit of SPL size, not SPL image size, does not include 2KB
header.
>
> A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
> the board specific limit.

There is already CONFIG_SPL_MAX_SIZE for the SPL size limit, isn't it?
I don't understand  why we need new variable.

Thanks,
- Kever
> A common Makefile function is used for this test and the test against
> CONFIG_BOARD_SIZE_LIMIT.
>
> Move the board size check from arch/arm/mach-imx/Makefile to Makefile.
>
> v4:
>   use a common function for all size checks in the Makefiles
>
> Heinrich Schuchardt (4):
>   Makefile: reusable function for BOARD_SIZE_CHECK
>   imx: move BOARD_SIZE_CHECK to main Makefile
>   configs: define CONFIG_SPL_SIZE_LIMIT
>   configs: rk3288: Tinker Board SPL file must fit into 32 KiB
>
>  Kconfig |  8 
>  Makefile| 33 +++--
>  arch/arm/mach-imx/Makefile  | 16 
>  configs/tinker-rk3288_defconfig |  1 +
>  4 files changed, 32 insertions(+), 26 deletions(-)
>
> --
> 2.20.1
>



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Re: [U-Boot] burning eMMC from sdcard.img in U-Boot

[Alex Kiernan]

On Tue, Apr 2, 2019 at 9:59 PM Adam Ford  wrote:
>
> I have a board with eMMC storage.  I've been trying to find an elegant
> solution to burning the sdcard image to eMMC.  I looked at using the
> USB mass storage gadget, but it's a bit slow.  I was hoping to avoid
> having to boot all the way into Linux to do it, but the sdcard.img
> file is larger than the memory I have available.
>
> Does anyone have any suggestions on how to burn the contents of a file
> to eMMC (or mmc/sd) from within U-Boot when the source file size may
> vary and it's larger than the available memory, so it needs to be done
> in blocks?
>

Convert to Android sparse format and use that? You still need the
sparse image to fit into memory though.

-- 
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[U-Boot] Does u-boot end itself after starting the kernel?

[U.Mutlu]

Hi,

the bootloader, here u-boot, starts the kernel.
Is u-boot still active (ie. in a running state)
after it starts the kernel?

platform: ARMv7-a

Thx

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Re: [U-Boot] [PATCH v4 2/6] riscv: Add a SYSCON driver for Andestech's PLMT

[Auer, Lukas]

On Tue, 2019-04-02 at 15:56 +0800, Andes wrote:
> From: Rick Chen 
> 
> The platform-Level Machine Timer (PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
> 
> This driver implements the riscv_get_time() which
> is required by the generic RISC-V timer driver.
> 
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> Reviewed-by: Bin Meng 
> ---
> Changes in v4:
> - Rename nds_plmt as andes_plmt
> 
>  arch/riscv/Kconfig   |  9 ++
>  arch/riscv/include/asm/global_data.h |  3 ++
>  arch/riscv/include/asm/syscon.h  |  1 +
>  arch/riscv/lib/Makefile  |  1 +
>  arch/riscv/lib/andes_plmt.c  | 53 
> 
>  5 files changed, 67 insertions(+)
>  create mode 100644 arch/riscv/lib/andes_plmt.c
> 

Reviewed-by: Lukas Auer 
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Re: [U-Boot] [PATCH v4 1/6] riscv: Add a SYSCON driver for Andestech's PLIC

[Auer, Lukas]

On Tue, 2019-04-02 at 15:56 +0800, Andes wrote:
> From: Rick Chen 
> 
> The Platform-Level Interrupt Controller (PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt. It is required
> for handling IPI.
> 
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> Reviewed-by: Bin Meng 
> ---
> Changes in V4:
> - Drop the empty comment line
> - Check return value after cpu_get_count()
> - Rename nds_plic as andes_plic
> - Fix checkpatch error issues
> 
>  arch/riscv/Kconfig   |   9 +++
>  arch/riscv/include/asm/global_data.h |   3 +
>  arch/riscv/include/asm/syscon.h  |   3 +-
>  arch/riscv/lib/Makefile  |   1 +
>  arch/riscv/lib/andes_plic.c  | 113 
> +++
>  5 files changed, 127 insertions(+), 2 deletions(-)
>  create mode 100644 arch/riscv/lib/andes_plic.c
> 

Looks good now, thanks!

Reviewed-by: Lukas Auer 
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Re: [U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

[Auer, Lukas]

Hi Rick,

On Tue, 2019-04-02 at 10:12 +0800, Rick Chen wrote:
> Hi Lukas
> 
> > Auer, Lukas  於 2019年4月1日 週一 下午5:08寫道：
> > 
> > Hi Rick,
> > 
> > On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > > From: Rick Chen 
> > > 
> > > The Platform-Level Interrupt Controller (PLIC)
> > > block holds memory-mapped claim and pending registers
> > > associated with software interrupt. It is required
> > > for handling IPI.
> > > 
> > > Signed-off-by: Rick Chen 
> > > Cc: Greentime Hu 
> > > ---
> > > V3:
> > >  - Rename plic_init() as enable_ipi().
> > >  - Declase as static.
> > >  - Remove PLIC_BASE_GET() from enable_ipi().
> > > 
> > 
> > Take a look at patman [1], it makes it really easy to handle different
> > versions of a patch series. :)
> 
> OK
> Thanks :)
> 
> > [1]: https://github.com/u-boot/u-boot/blob/master/tools/patman/README
> > 
> > >  arch/riscv/Kconfig   |   9 +++
> > >  arch/riscv/include/asm/global_data.h |   3 +
> > >  arch/riscv/include/asm/syscon.h  |   2 +-
> > >  arch/riscv/lib/Makefile  |   1 +
> > >  arch/riscv/lib/andes_plic.c  | 110 
> > > +++
> > >  5 files changed, 124 insertions(+), 1 deletion(-)
> > >  create mode 100644 arch/riscv/lib/andes_plic.c
> > > 
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index 3a4470d..511768b 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> > > The SiFive CLINT block holds memory-mapped control and status 
> > > registers
> > > associated with software and timer interrupts.
> > > 
> > > +config ANDES_PLIC
> > > + bool
> > > + depends on RISCV_MMODE
> > > + select REGMAP
> > > + select SYSCON
> > > + help
> > > +   The Andes PLIC block holds memory-mapped claim and pending 
> > > registers
> > > +   associated with software interrupt.
> > > +
> > >  config RISCV_RDTIME
> > >   bool
> > >   default y if RISCV_SMODE
> > > diff --git a/arch/riscv/include/asm/global_data.h 
> > > b/arch/riscv/include/asm/global_data.h
> > > index 80e3165..b867910 100644
> > > --- a/arch/riscv/include/asm/global_data.h
> > > +++ b/arch/riscv/include/asm/global_data.h
> > > @@ -18,6 +18,9 @@ struct arch_global_data {
> > >  #ifdef CONFIG_SIFIVE_CLINT
> > >   void __iomem *clint;/* clint base address */
> > >  #endif
> > > +#ifdef CONFIG_ANDES_PLIC
> > > + void __iomem *plic; /* plic base address */
> > > +#endif
> > >  #ifdef CONFIG_SMP
> > >   struct ipi_data ipi[CONFIG_NR_CPUS];
> > >  #endif
> > > diff --git a/arch/riscv/include/asm/syscon.h 
> > > b/arch/riscv/include/asm/syscon.h
> > > index d311ee6..c1b4b86 100644
> > > --- a/arch/riscv/include/asm/syscon.h
> > > +++ b/arch/riscv/include/asm/syscon.h
> > > @@ -9,11 +9,11 @@
> > >  /*
> > >   * System controllers in a RISC-V system
> > >   *
> > 
> > nit: can you also drop the empty comment line above?
> 
> OK
> 
> > > - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> > >   */
> > >  enum {
> > >   RISCV_NONE,
> > >   RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> > > + RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller 
> > > (PLIC) */
> > >  };
> > > 
> > >  #endif /* _ASM_SYSCON_H */
> > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > > index 35dbf64..1bf554b 100644
> > > --- a/arch/riscv/lib/Makefile
> > > +++ b/arch/riscv/lib/Makefile
> > > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> > >  obj-y+= cache.o
> > >  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > >  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > > +obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > >  obj-y+= interrupts.o
> > >  obj-y+= reset.o
> > >  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > > new file mode 100644
> > > index 000..67ab561
> > > --- /dev/null
> > > +++ b/arch/riscv/lib/andes_plic.c
> > > @@ -0,0 +1,110 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2019, Rick Chen 
> > > + *
> > > + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller 
> > > (PLIC).
> > > + * The PLIC block holds memory-mapped claim and pending registers
> > > + * associated with software interrupt.
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> > > +/* pending register */
> > > +#define PENDING_REG(base, hart)  ((ulong)(base) + 0x1000 + (hart) * 
> > > 8)
> > > +/* enable register */
> > > +#define ENABLE_REG(base, hart)   ((ulong)(base) + 0x2000 + (hart) * 
> > > 0x80)
> > > +/* claim register */
> > > +#define CLAIM_REG(base, hart)((ulong)(base) + 0x24 + (hart) 
> > > * 0x1000)
> > > +
> > > +#define ENABLE_HART_IPI (0x80808080)
> > > 

[U-Boot] burning eMMC from sdcard.img in U-Boot

[Adam Ford]

I have a board with eMMC storage.  I've been trying to find an elegant
solution to burning the sdcard image to eMMC.  I looked at using the
USB mass storage gadget, but it's a bit slow.  I was hoping to avoid
having to boot all the way into Linux to do it, but the sdcard.img
file is larger than the memory I have available.

Does anyone have any suggestions on how to burn the contents of a file
to eMMC (or mmc/sd) from within U-Boot when the source file size may
vary and it's larger than the available memory, so it needs to be done
in blocks?

thanks

adam
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Re: [U-Boot] Riscv: CONFIG_DEFAULT_DEVICE_TREE failures

[Troy Benjegerdes]

> On Mar 31, 2019, at 5:02 PM, Tom Rini  wrote:
> 
> On Fri, Mar 29, 2019 at 11:15:48PM -0700, Troy Benjegerdes wrote:
> 
>> I attempted to merge in the latest master branch into
>> https://github.com/sifive/u-boot/tree/sandbox and I got
>> the following error, which seems somewhat broken..
>> 
>> 
>> Device Tree Source is not correctly specified.
>> Please define 'CONFIG_DEFAULT_DEVICE_TREE'
>> or build with 'DEVICE_TREE=' argument
>> 
>> dts/Makefile:28: recipe for target 'arch/riscv/dts/fu540.dtb' failed
>> 
>> 
>> Does anyone have any idea what would have caused that?
>> 
>> Also any feedback or pointers on why the serial_sifive.c 
>> driver with CONFIG_DM_SERIAL would not work, but serial_hifive.c
>> without CONFIG_DM_SERIAL does seem to work might be appreciated.
> 
> You'll need to do something like
> 
> commit 89c2b5c02049aea746b1edee0b4e1d8519dec2f4
> Author: Masahiro Yamada 
> Date:   Thu Mar 14 14:58:33 2019 +0900
> 
>ARM: fix arch/arm/dts/Makefile
> 
>Since commit 27cb7300ffda ("Ensure device tree DTS is compiled"),
>build succeeds irrespective of the correctness of Makefile.
> 
>In fact, you can compile any defconfig without adding any entry in
>arch/*/dts/Makefile.
> 
>As a result, a lot of wrong code have been merged unnoticed.
> 
>I am going to revert that commit, and lots of hidden issues have
>come to light:
> 
>[1] Typos
> 
>  armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts
> 
>  use the extension ".dts" instead of ".dtb"
> 
>[2] DTB is associated to undefined CONFIG option
> 
>  For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but
>  associates its device tree to CONFIG_MX6SL, which is undefined.
> 
>[3] Lots of entries are missing
> 
>Signed-off-by: Masahiro Yamada 
>Reviewed-by: Chris Packham 
>[trini: add imx6ul pico dtbs]
>Signed-off-by: Tom Rini 
> 
> But to arch/riscv/dts/Makefile
> 
> -- 
> Tom


I ended up reverting that commit, and we now have 
https://github.com/sifive/u-boot/tree/sandbox booting to a prompt based on 
upstream master.

It still needs the macb driver ported over, and probably re-worked to do what 
Rockchip boards do to put the Denali memory init code in the device tree.
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Re: [U-Boot] [PATCH v4 0/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Heinrich Schuchardt]

On 4/2/19 7:47 PM, Tom Rini wrote:
> On Tue, Apr 02, 2019 at 07:33:42PM +0200, Heinrich Schuchardt wrote:
>> On 4/2/19 7:29 PM, Tom Rini wrote:
>>> On Tue, Apr 02, 2019 at 07:19:03PM +0200, Heinrich Schuchardt wrote:
>>>
 The SPL image for the Tinker Board has to fit into 32 KiB. This includes
 up to 2 KiB for the file header.

 A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
 the board specific limit.

 A common Makefile function is used for this test and the test against
 CONFIG_BOARD_SIZE_LIMIT.

 Move the board size check from arch/arm/mach-imx/Makefile to Makefile.
>>>
>>> I'm sorry you weren't Cc'd on Simon's thread where we're trying to
>>> improve the size check stuff to be generic enough to use everywhere.  We
>>> can't generically use a shell script as we need to know some processed
>>> values too.  I don't know if Simon got to the point of writing a C based
>>> helper to use or not.
>>>
>>
>> Hello Tom,
>>
>> could you, please, provide a link to the thread.
> 
> https://patchwork.ozlabs.org/patch/1050465/ (and no, I didn't apply it,
> I forgot to delete my email before I sent out that batch of applieds).
> 
>> Is the test prior to my patch incorrect? Or do you want to imply that
>> after my patch we get different results?
> 
> The problem is that I don't want to make wider use of the shell checking
> notion.  It's not as complete as we'd like and can't be used on as many
> platforms as need it either, due to needing cpp to actually determine
> values in some cases.
> 

Yes, the patch by Simon G. is similiar to my patch series. What his
patch does not address is the duplicate coding for checking *.imx files.
My idea has been to put all tests into the main Makefile to avoid
problems with variable substitutions.

It is unclear to me what you mean by: "It's not as complete as we'd
like" and where you see a need for "cpp to actually determine values".

I would not be able to provide a better patch without understanding your
view on the requirements.

Best regards

Heinrich



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Re: [U-Boot] [PATCH v4 0/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Simon Goldschmidt]

On 02.04.19 19:33, Heinrich Schuchardt wrote:

On 4/2/19 7:29 PM, Tom Rini wrote:

On Tue, Apr 02, 2019 at 07:19:03PM +0200, Heinrich Schuchardt wrote:


The SPL image for the Tinker Board has to fit into 32 KiB. This includes
up to 2 KiB for the file header.

A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
the board specific limit.

A common Makefile function is used for this test and the test against
CONFIG_BOARD_SIZE_LIMIT.

Move the board size check from arch/arm/mach-imx/Makefile to Makefile.


I'm sorry you weren't Cc'd on Simon's thread where we're trying to
improve the size check stuff to be generic enough to use everywhere.  We
can't generically use a shell script as we need to know some processed
values too.  I don't know if Simon got to the point of writing a C based
helper to use or not.


Right, I should have included you, Heinrich, sorry.

No, unfortunately, I haven't found the time to work on the C based 
approach, yet.


To sum it up, Heinrich, the issue was that for socfpga gen5, we're 
approaching the 64KiB total limit for SPL. That includes all regions we 
can check via CONFIG_SPL_MAX_FOOTPRINT (e.g. text, data, bss) plus 
devicetree, early malloc, global data and initial stack.


My approach would have been much like your check (which by the way is 
better than mine in that the check stays in main Makefile), but the size 
limit needs to include those items I've mentioned above. So while I 
could add a Kconfig based total size, I would need to subtract gd, 
malloc area and reserved stack size to get the SPL_SIZE_LIMIT value.


The problem I see here is that this is a different size limit to the one 
you want to check. I need "SRAM_SIZE - x - y - z" while you need 
"LOAD_LIMIT", which is constant.


Maybe we could start with your limit and then add bool config options 
like "SPL_SIZE_LIMIT_SUBTRACT_GD", "SPL_SIZE_LIMIT_SUBTRACT_MALLOC_F" 
and "SPL_SIZE_LIMIT_SUBTRACT_STACK_SIZE" that could then be used by a C 
program to help the size check.


Regards,
Simon





Hello Tom,

could you, please, provide a link to the thread.

Is the test prior to my patch incorrect? Or do you want to imply that
after my patch we get different results?

Best regards

Heinrich


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Re: [U-Boot] [U-Boot,v2] travis-ci: fix at91 missing boards

[Tom Rini]

On Mon, Apr 01, 2019 at 11:04:03AM +, eugen.hris...@microchip.com wrote:

> From: Eugen Hristev 
> 
> Fix missing at91 boards and split the at91 in two categories:
> at91 arm v7
> at91 arm926esj
> which are the two main cores for the at91 architecture.
> 
> Signed-off-by: Eugen Hristev 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH v2 1/3] rockchip: add common header boot0.h and gpio.h for soc

[Tom Rini]

On Tue, Apr 02, 2019 at 10:09:42AM +0800, Kever Yang wrote:

> boot0.h and gpio.h will be used by system and include by
> 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'.
> 
> Signed-off-by: Kever Yang 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PULL] u-boot-sh/master

[Tom Rini]

On Tue, Apr 02, 2019 at 03:16:36AM +0200, Marek Vasut wrote:

> Minor fixes for the Alt board and PHY use on Gen2.
> 
> The following changes since commit c3aef9339ce0592b06c8d44cf2eaf9e6f3713e4f:
> 
>   Merge branch '2019-03-29-master-imports' (2019-03-29 10:53:28 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-sh.git master
> 
> for you to fetch changes up to 0c78ec64bcc96c34642ebd29614c4c26132ad4b6:
> 
>   ARM: rmobile: alt: Fix I2C bus number (2019-03-30 08:28:25 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Dirk Behme]

On 02.04.19 17:40, Eugeniu Rosca wrote:

On Tue, Apr 02, 2019 at 05:28:43PM +0200, Marek Vasut wrote:

On 4/2/19 5:17 PM, Dirk Behme wrote:

On 02.04.19 15:34, Marek Vasut wrote:

On 4/2/19 3:18 PM, Eugeniu Rosca wrote:

With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:

-8<-
    LD  u-boot
drivers/gpio/built-in.o: In function `rcar_gpio_request':
drivers/gpio/gpio-rcar.c:128: undefined reference to
`sh_pfc_config_mux_for_gpio'
-8<-

Fix it in the least intrusive way and *avoid* ifdefs in the *.c code.

Some recent Linux commits sharing the same approach:
   -
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=23222f8f8dce

     ("acpi, nfit: Add function to look up nvdimm device and provide
SMBIOS handle")
   -
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f143af7501e

     ("spi: make OF helper available for others")
   -
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bccd06223f21

     ("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")

Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
Reported-by: Dirk Behme 
Signed-off-by: Eugeniu Rosca 


Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?



Why not? Main memory, boot device and UART are configured before U-Boot,
no?


It depends on what is running before U-Boot, so not necessarily.

And speaking of boot device, consider the case where the system runs
from eMMC and uses the HS200/HS400 modes, which need to switch bus mode
using the pinmux driver.

Is there a real-world use case where you would want to disable the
pinmux driver ? And what is the benefit of that, except that it would
cause all kinds of weird problems.


My H3ULCB-KF boots just fine [1] with CONFIG_PINCTRL_PFC=n, but I
personally don't have any use-case which I need to fulfill on a
Renesas reference design by disabling PFC.



What's about people needing to do products based on these reference 
designs which have boot time and by this size requirements?


And having functions which are build time encapsulated with CONFIG_* 
but not their callers I simply would consider as a bug which needs to 
be fixed. Like you have done here, citing several kernel examples for 
this :)


Best regards

Dirk


Rather, the motivation here is to ensure U-Boot builds fine with as
many randconfig results as possible, which is a standard practice in
Linux. I personally favor my solution, but I am also open minded if
the linker error is avoided by introducing a direct/reverse dependency
between PFC and another relevant R-Car3 Kconfig symbol.

[1] U-Boot 2019.04-rc4-00100-g03ece61db8 (Apr 02 2019 - 17:23:57 +0200)

CPU: Renesas Electronics R8A7795 rev 2.0
Model: Renesas H3ULCB board based on r8a7795 ES2.0+
DRAM:  3.9 GiB
MMC:   gpio@e6055000: set_value: error: gpio gpio@e60550001 not reserved
Can't set regulator : regulator-vccq-sdhi0 gpio to: 1
sd@ee10: 0, sd@ee14: 1
Loading Environment from MMC... OK
In:serial@e6e88000
Out:   serial@e6e88000
Err:   serial@e6e88000
Net:   gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
eth0: ethernet@e680
Hit any key to stop autoboot:  0


--
Best regards,
Marek Vasut


Best regards,
Eugeniu.



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[U-Boot] tpm2_nvread

[Tommaso Corda]

Hi all,

I'm trying to use the tpm2_nvread command on u-boot but it seems it is not 
implemented on tpm2.
Does anyone know how to make it work?

Thanks in advance.

BR.
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Re: [U-Boot] [PATCH v4 0/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Tom Rini]

On Tue, Apr 02, 2019 at 07:33:42PM +0200, Heinrich Schuchardt wrote:
> On 4/2/19 7:29 PM, Tom Rini wrote:
> > On Tue, Apr 02, 2019 at 07:19:03PM +0200, Heinrich Schuchardt wrote:
> > 
> >> The SPL image for the Tinker Board has to fit into 32 KiB. This includes
> >> up to 2 KiB for the file header.
> >>
> >> A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
> >> the board specific limit.
> >>
> >> A common Makefile function is used for this test and the test against
> >> CONFIG_BOARD_SIZE_LIMIT.
> >>
> >> Move the board size check from arch/arm/mach-imx/Makefile to Makefile.
> > 
> > I'm sorry you weren't Cc'd on Simon's thread where we're trying to
> > improve the size check stuff to be generic enough to use everywhere.  We
> > can't generically use a shell script as we need to know some processed
> > values too.  I don't know if Simon got to the point of writing a C based
> > helper to use or not.
> > 
> 
> Hello Tom,
> 
> could you, please, provide a link to the thread.

https://patchwork.ozlabs.org/patch/1050465/ (and no, I didn't apply it,
I forgot to delete my email before I sent out that batch of applieds).

> Is the test prior to my patch incorrect? Or do you want to imply that
> after my patch we get different results?

The problem is that I don't want to make wider use of the shell checking
notion.  It's not as complete as we'd like and can't be used on as many
platforms as need it either, due to needing cpp to actually determine
values in some cases.

-- 
Tom


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Re: [U-Boot] [PATCH v4 0/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Heinrich Schuchardt]

On 4/2/19 7:29 PM, Tom Rini wrote:
> On Tue, Apr 02, 2019 at 07:19:03PM +0200, Heinrich Schuchardt wrote:
> 
>> The SPL image for the Tinker Board has to fit into 32 KiB. This includes
>> up to 2 KiB for the file header.
>>
>> A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
>> the board specific limit.
>>
>> A common Makefile function is used for this test and the test against
>> CONFIG_BOARD_SIZE_LIMIT.
>>
>> Move the board size check from arch/arm/mach-imx/Makefile to Makefile.
> 
> I'm sorry you weren't Cc'd on Simon's thread where we're trying to
> improve the size check stuff to be generic enough to use everywhere.  We
> can't generically use a shell script as we need to know some processed
> values too.  I don't know if Simon got to the point of writing a C based
> helper to use or not.
> 

Hello Tom,

could you, please, provide a link to the thread.

Is the test prior to my patch incorrect? Or do you want to imply that
after my patch we get different results?

Best regards

Heinrich



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Re: [U-Boot] [PATCH v4 0/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Tom Rini]

On Tue, Apr 02, 2019 at 07:19:03PM +0200, Heinrich Schuchardt wrote:

> The SPL image for the Tinker Board has to fit into 32 KiB. This includes
> up to 2 KiB for the file header.
> 
> A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
> the board specific limit.
> 
> A common Makefile function is used for this test and the test against
> CONFIG_BOARD_SIZE_LIMIT.
> 
> Move the board size check from arch/arm/mach-imx/Makefile to Makefile.

I'm sorry you weren't Cc'd on Simon's thread where we're trying to
improve the size check stuff to be generic enough to use everywhere.  We
can't generically use a shell script as we need to know some processed
values too.  I don't know if Simon got to the point of writing a C based
helper to use or not.

-- 
Tom


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[U-Boot] [PATCH v4 3/4] configs: define CONFIG_SPL_SIZE_LIMIT

[Heinrich Schuchardt]

A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
the board specific maximum size for the SPL file.

Use Makefile function size_check() to implement the test.

Depending on the size of CONFIG_SPL_SIZE_LIMIT an error like the following
is thrown:

spl/u-boot-spl.bin exceeds file size limit:
  limit:  30720 bytes
  actual: 33426 bytes
  excess: 2706 bytes
make: *** [Makefile:1663: spl/u-boot-spl.bin] Error 1

Signed-off-by: Heinrich Schuchardt 
---
v4
use function size_check()
split off change in tinker-rk3288_defconfig
---
 Kconfig  | 8 
 Makefile | 8 
 2 files changed, 16 insertions(+)

diff --git a/Kconfig b/Kconfig
index 305b265ed7..69212bf58f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -172,6 +172,14 @@ config TPL_SYS_MALLOC_F_LEN
  particular needs this to operate, so that it can allocate the
  initial serial device and any others that are needed.

+config SPL_SIZE_LIMIT
+   int "Maximum size of SPL image"
+   depends on SPL
+   default 0
+   help
+ Specifies the maximum length of the U-Boot SPL image.
+ If this value is zero, it is ignored.
+
 menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
diff --git a/Makefile b/Makefile
index 6398117e64..073ef2b387 100644
--- a/Makefile
+++ b/Makefile
@@ -789,6 +789,12 @@ else
 BOARD_SIZE_CHECK =
 endif

+ifneq ($(CONFIG_SPL_SIZE_LIMIT),0)
+SPL_SIZE_CHECK = @$(call size_check,$@,$(CONFIG_SPL_SIZE_LIMIT))
+else
+SPL_SIZE_CHECK =
+endif
+
 # Statically apply RELA-style relocations (currently arm64 only)
 # This is useful for arm64 where static relocation needs to be performed on
 # the raw binary, but certain simulators only accept an ELF file (but don't
@@ -1654,6 +1660,8 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE

 spl/u-boot-spl.bin: spl/u-boot-spl
@:
+   $(SPL_SIZE_CHECK)
+
 spl/u-boot-spl: tools prepare \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
--
2.20.1

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[U-Boot] [PATCH v4 4/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Heinrich Schuchardt]

The SPL image for the Tinker Board has to fit into 32 KiB. This includes
up to 2 KiB for the file header.

Signed-off-by: Heinrich Schuchardt 
---
The error for the TinkerBoard is resolved by:
configs: tinker-rk3288 disable CONFIG_SPL_I2C_SUPPORT
https://lists.denx.de/pipermail/u-boot/2019-February/360367.html

v4
split of change in tinker-rk3288_defconfig
---
 configs/tinker-rk3288_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 85ef9dabbd..585fbf505c 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
+CONFIG_SPL_SIZE_LIMIT=30720
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_TINKER_RK3288=y
 CONFIG_DEBUG_UART_BASE=0xff69
--
2.20.1

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[U-Boot] [PATCH v4 1/4] Makefile: reusable function for BOARD_SIZE_CHECK

[Heinrich Schuchardt]

Carve out function size_check from macro BOARD_SIZE_CHECK. This will allow
us to reuse the function for other file size checks.

Depending on the value of CONFIG_BOARD_SIZE_LIMIT an error like the
following is thrown:

u-boot-dtb.img exceeds file size limit:
  limit:  409516 bytes
  actual: 444346 bytes
  excess: 34830 bytes
make: *** [Makefile:1212: u-boot-dtb.img] Error 1

Signed-off-by: Heinrich Schuchardt 
---
v4
new patch
---
 Makefile | 24 ++--
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/Makefile b/Makefile
index c1af9307b3..9878595a82 100644
--- a/Makefile
+++ b/Makefile
@@ -330,6 +330,19 @@ endif
 #  KBUILD_MODULES := 1
 #endif

+define size_check
+   actual=$$( wc -c $1 | awk '{print $$1}'); \
+   limit=$$( printf "%d" $2 ); \
+   if test $$actual -gt $$limit; then \
+   echo "$1 exceeds file size limit:" >&2; \
+   echo "  limit:  $$limit bytes" >&2; \
+   echo "  actual: $$actual bytes" >&2; \
+   echo "  excess: $$((actual - limit)) bytes" >&2; \
+   exit 1; \
+   fi
+endef
+export size_check
+
 export KBUILD_MODULES KBUILD_BUILTIN
 export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD

@@ -771,16 +784,7 @@ LDPPFLAGS += \
 #

 ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
-   @actual=`wc -c $@ | awk '{print $$1}'`; \
-   limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
-   if test $$actual -gt $$limit; then \
-   echo "$@ exceeds file size limit:" >&2 ; \
-   echo "  limit:  $$limit bytes" >&2 ; \
-   echo "  actual: $$actual bytes" >&2 ; \
-   echo "  excess: $$((actual - limit)) bytes" >&2; \
-   exit 1; \
-   fi
+BOARD_SIZE_CHECK= @ $(call size_check,$@,$(CONFIG_BOARD_SIZE_LIMIT))
 else
 BOARD_SIZE_CHECK =
 endif
--
2.20.1

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[U-Boot] [PATCH v4 2/4] imx: move BOARD_SIZE_CHECK to main Makefile

[Heinrich Schuchardt]

We currently have duplicate definitions for BOARD_SIZE_CHECK in Makefile
and arch/arm/mach-imx/Makefile.

Move the board size check from arch/arm/mach-imx/Makefile to Makefile.

Depending on the value of CONFIG_BOARD_SIZE_LIMIT an error like an error
like the following is thrown:

u-boot-dtb.imx exceeds file size limit:
  limit:  503696 bytes
  actual: 509720 bytes
  excess: 6024 bytes
make: *** [Makefile:1051: u-boot-dtb.imx] Error 1

Signed-off-by: Heinrich Schuchardt 
---
v4
new patch
---
 Makefile   |  1 +
 arch/arm/mach-imx/Makefile | 16 
 2 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/Makefile b/Makefile
index 9878595a82..6398117e64 100644
--- a/Makefile
+++ b/Makefile
@@ -1042,6 +1042,7 @@ endif

 %.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+   $(BOARD_SIZE_CHECK)

 %.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c3ed62aed6..7985afb154 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -61,21 +61,6 @@ obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
 obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
 endif

-ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
-@actual=`wc -c $@ | awk '{print $$1}'`; \
-limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
-if test $$actual -gt $$limit; then \
-echo "$@ exceeds file size limit:" >&2 ; \
-echo "  limit:  $$limit bytes" >&2 ; \
-echo "  actual: $$actual bytes" >&2 ; \
-echo "  excess: $$((actual - limit)) bytes" >&2; \
-exit 1; \
-fi
-else
-BOARD_SIZE_CHECK =
-endif
-
 PLUGIN = board/$(BOARDDIR)/plugin

 ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
@@ -124,7 +109,6 @@ u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log

 u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
-   $(BOARD_SIZE_CHECK)

 ifeq ($(CONFIG_OF_SEPARATE),y)
 MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
--
2.20.1

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[U-Boot] [PATCH v4 0/4] configs: rk3288: Tinker Board SPL file must fit into 32 KiB

[Heinrich Schuchardt]

The SPL image for the Tinker Board has to fit into 32 KiB. This includes
up to 2 KiB for the file header.

A new configuration variable CONFIG_SPL_SIZE_LIMIT is introduced to define
the board specific limit.

A common Makefile function is used for this test and the test against
CONFIG_BOARD_SIZE_LIMIT.

Move the board size check from arch/arm/mach-imx/Makefile to Makefile.

v4:
use a common function for all size checks in the Makefiles

Heinrich Schuchardt (4):
  Makefile: reusable function for BOARD_SIZE_CHECK
  imx: move BOARD_SIZE_CHECK to main Makefile
  configs: define CONFIG_SPL_SIZE_LIMIT
  configs: rk3288: Tinker Board SPL file must fit into 32 KiB

 Kconfig |  8 
 Makefile| 33 +++--
 arch/arm/mach-imx/Makefile  | 16 
 configs/tinker-rk3288_defconfig |  1 +
 4 files changed, 32 insertions(+), 26 deletions(-)

--
2.20.1

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Re: [U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Eugeniu Rosca]

On Tue, Apr 02, 2019 at 06:02:46PM +0200, Marek Vasut wrote:
> On 4/2/19 5:40 PM, Eugeniu Rosca wrote:
> > On Tue, Apr 02, 2019 at 05:28:43PM +0200, Marek Vasut wrote:
> >> On 4/2/19 5:17 PM, Dirk Behme wrote:
> >>> On 02.04.19 15:34, Marek Vasut wrote:
>  On 4/2/19 3:18 PM, Eugeniu Rosca wrote:
> > With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:
> >
> > -8<-
> >    LD  u-boot
> > drivers/gpio/built-in.o: In function `rcar_gpio_request':
> > drivers/gpio/gpio-rcar.c:128: undefined reference to
> > `sh_pfc_config_mux_for_gpio'
> > -8<-
[..]
>  Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?
> >>>
> >>> Why not? Main memory, boot device and UART are configured before U-Boot,
> >>> no?
> >>
> >> It depends on what is running before U-Boot, so not necessarily.
> >>
> >> And speaking of boot device, consider the case where the system runs
> >> from eMMC and uses the HS200/HS400 modes, which need to switch bus mode
> >> using the pinmux driver.
> >>
> >> Is there a real-world use case where you would want to disable the
> >> pinmux driver ? And what is the benefit of that, except that it would
> >> cause all kinds of weird problems.
> > 
> > My H3ULCB-KF boots just fine [1] with CONFIG_PINCTRL_PFC=n, but I
> > personally don't have any use-case which I need to fulfill on a
> > Renesas reference design by disabling PFC.
> 
> And the eMMC and SDHI both work fine too in HS400/SDR104 modes ?
> They cannot, since you cannot switch the pinmux properties of the bus.
> What about the errors in the log below, they don't look quite fine.
> 
> > Rather, the motivation here is to ensure U-Boot builds fine with as
> > many randconfig results as possible, which is a standard practice in
> > Linux. I personally favor my solution, but I am also open minded if
> > the linker error is avoided by introducing a direct/reverse dependency
> > between PFC and another relevant R-Car3 Kconfig symbol.
> 
> I am fine with fixing randconfig build errors. My question here is
> whether it makes sense to allow U-Boot build without PFC support,
> since that would cause all kinds of problems. I am banking toward
> playing it safe and not allowing such an option at all. Thoughts ?

It looks like in Linux, PINCTRL is a fundamental feature selected
(i.e. *cannot* be disabled by users) by ARCH_RENESAS since v4.5 commit
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=26a7e06dfee9
("arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support").

So, demanding a PFC-free U-Boot doesn't look reasonable to me.

Should PINCTRL be selected by CONFIG_RCAR_GEN3 as it is done in Linux?
One caveat is that PINCTRL currently depends on DM, so R-Car3 U-Boot
would become dependent on DM too, i.e. users won't have the option of
a legacy U-Boot anymore.

> > [1] U-Boot 2019.04-rc4-00100-g03ece61db8 (Apr 02 2019 - 17:23:57 +0200)
[..]

Best regards,
Eugeniu.
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Re: [U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Marek Vasut]

On 4/2/19 5:40 PM, Eugeniu Rosca wrote:
> On Tue, Apr 02, 2019 at 05:28:43PM +0200, Marek Vasut wrote:
>> On 4/2/19 5:17 PM, Dirk Behme wrote:
>>> On 02.04.19 15:34, Marek Vasut wrote:
 On 4/2/19 3:18 PM, Eugeniu Rosca wrote:
> With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:
>
> -8<-
>    LD  u-boot
> drivers/gpio/built-in.o: In function `rcar_gpio_request':
> drivers/gpio/gpio-rcar.c:128: undefined reference to
> `sh_pfc_config_mux_for_gpio'
> -8<-
>
> Fix it in the least intrusive way and *avoid* ifdefs in the *.c code.
>
> Some recent Linux commits sharing the same approach:
>   -
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=23222f8f8dce
>
>     ("acpi, nfit: Add function to look up nvdimm device and provide
> SMBIOS handle")
>   -
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f143af7501e
>
>     ("spi: make OF helper available for others")
>   -
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bccd06223f21
>
>     ("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")
>
> Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
> Reported-by: Dirk Behme 
> Signed-off-by: Eugeniu Rosca 

 Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?
>>>
>>>
>>> Why not? Main memory, boot device and UART are configured before U-Boot,
>>> no?
>>
>> It depends on what is running before U-Boot, so not necessarily.
>>
>> And speaking of boot device, consider the case where the system runs
>> from eMMC and uses the HS200/HS400 modes, which need to switch bus mode
>> using the pinmux driver.
>>
>> Is there a real-world use case where you would want to disable the
>> pinmux driver ? And what is the benefit of that, except that it would
>> cause all kinds of weird problems.
> 
> My H3ULCB-KF boots just fine [1] with CONFIG_PINCTRL_PFC=n, but I
> personally don't have any use-case which I need to fulfill on a
> Renesas reference design by disabling PFC.

And the eMMC and SDHI both work fine too in HS400/SDR104 modes ?
They cannot, since you cannot switch the pinmux properties of the bus.
What about the errors in the log below, they don't look quite fine.

> Rather, the motivation here is to ensure U-Boot builds fine with as
> many randconfig results as possible, which is a standard practice in
> Linux. I personally favor my solution, but I am also open minded if
> the linker error is avoided by introducing a direct/reverse dependency
> between PFC and another relevant R-Car3 Kconfig symbol.

I am fine with fixing randconfig build errors. My question here is
whether it makes sense to allow U-Boot build without PFC support,
since that would cause all kinds of problems. I am banking toward
playing it safe and not allowing such an option at all. Thoughts ?

> [1] U-Boot 2019.04-rc4-00100-g03ece61db8 (Apr 02 2019 - 17:23:57 +0200)
> 
> CPU: Renesas Electronics R8A7795 rev 2.0
> Model: Renesas H3ULCB board based on r8a7795 ES2.0+
> DRAM:  3.9 GiB
> MMC:   gpio@e6055000: set_value: error: gpio gpio@e60550001 not reserved
> Can't set regulator : regulator-vccq-sdhi0 gpio to: 1
> sd@ee10: 0, sd@ee14: 1
> Loading Environment from MMC... OK
> In:serial@e6e88000
> Out:   serial@e6e88000
> Err:   serial@e6e88000
> Net:   gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
> gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
> eth0: ethernet@e680
> Hit any key to stop autoboot:  0 
> 
>> -- 
>> Best regards,
>> Marek Vasut
> 
> Best regards,
> Eugeniu.
> 


-- 
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Marek Vasut
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Re: [U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Eugeniu Rosca]

On Tue, Apr 02, 2019 at 05:28:43PM +0200, Marek Vasut wrote:
> On 4/2/19 5:17 PM, Dirk Behme wrote:
> > On 02.04.19 15:34, Marek Vasut wrote:
> >> On 4/2/19 3:18 PM, Eugeniu Rosca wrote:
> >>> With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:
> >>>
> >>> -8<-
> >>>    LD  u-boot
> >>> drivers/gpio/built-in.o: In function `rcar_gpio_request':
> >>> drivers/gpio/gpio-rcar.c:128: undefined reference to
> >>> `sh_pfc_config_mux_for_gpio'
> >>> -8<-
> >>>
> >>> Fix it in the least intrusive way and *avoid* ifdefs in the *.c code.
> >>>
> >>> Some recent Linux commits sharing the same approach:
> >>>   -
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=23222f8f8dce
> >>>
> >>>     ("acpi, nfit: Add function to look up nvdimm device and provide
> >>> SMBIOS handle")
> >>>   -
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f143af7501e
> >>>
> >>>     ("spi: make OF helper available for others")
> >>>   -
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bccd06223f21
> >>>
> >>>     ("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")
> >>>
> >>> Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
> >>> Reported-by: Dirk Behme 
> >>> Signed-off-by: Eugeniu Rosca 
> >>
> >> Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?
> > 
> > 
> > Why not? Main memory, boot device and UART are configured before U-Boot,
> > no?
> 
> It depends on what is running before U-Boot, so not necessarily.
> 
> And speaking of boot device, consider the case where the system runs
> from eMMC and uses the HS200/HS400 modes, which need to switch bus mode
> using the pinmux driver.
> 
> Is there a real-world use case where you would want to disable the
> pinmux driver ? And what is the benefit of that, except that it would
> cause all kinds of weird problems.

My H3ULCB-KF boots just fine [1] with CONFIG_PINCTRL_PFC=n, but I
personally don't have any use-case which I need to fulfill on a
Renesas reference design by disabling PFC.

Rather, the motivation here is to ensure U-Boot builds fine with as
many randconfig results as possible, which is a standard practice in
Linux. I personally favor my solution, but I am also open minded if
the linker error is avoided by introducing a direct/reverse dependency
between PFC and another relevant R-Car3 Kconfig symbol.

[1] U-Boot 2019.04-rc4-00100-g03ece61db8 (Apr 02 2019 - 17:23:57 +0200)

CPU: Renesas Electronics R8A7795 rev 2.0
Model: Renesas H3ULCB board based on r8a7795 ES2.0+
DRAM:  3.9 GiB
MMC:   gpio@e6055000: set_value: error: gpio gpio@e60550001 not reserved
Can't set regulator : regulator-vccq-sdhi0 gpio to: 1
sd@ee10: 0, sd@ee14: 1
Loading Environment from MMC... OK
In:serial@e6e88000
Out:   serial@e6e88000
Err:   serial@e6e88000
Net:   gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved
eth0: ethernet@e680
Hit any key to stop autoboot:  0 

> -- 
> Best regards,
> Marek Vasut

Best regards,
Eugeniu.
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Re: [U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Marek Vasut]

On 4/2/19 5:17 PM, Dirk Behme wrote:
> On 02.04.19 15:34, Marek Vasut wrote:
>> On 4/2/19 3:18 PM, Eugeniu Rosca wrote:
>>> With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:
>>>
>>> -8<-
>>>    LD  u-boot
>>> drivers/gpio/built-in.o: In function `rcar_gpio_request':
>>> drivers/gpio/gpio-rcar.c:128: undefined reference to
>>> `sh_pfc_config_mux_for_gpio'
>>> -8<-
>>>
>>> Fix it in the least intrusive way and *avoid* ifdefs in the *.c code.
>>>
>>> Some recent Linux commits sharing the same approach:
>>>   -
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=23222f8f8dce
>>>
>>>     ("acpi, nfit: Add function to look up nvdimm device and provide
>>> SMBIOS handle")
>>>   -
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f143af7501e
>>>
>>>     ("spi: make OF helper available for others")
>>>   -
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bccd06223f21
>>>
>>>     ("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")
>>>
>>> Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
>>> Reported-by: Dirk Behme 
>>> Signed-off-by: Eugeniu Rosca 
>>
>> Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?
> 
> 
> Why not? Main memory, boot device and UART are configured before U-Boot,
> no?

It depends on what is running before U-Boot, so not necessarily.

And speaking of boot device, consider the case where the system runs
from eMMC and uses the HS200/HS400 modes, which need to switch bus mode
using the pinmux driver.

Is there a real-world use case where you would want to disable the
pinmux driver ? And what is the benefit of that, except that it would
cause all kinds of weird problems.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Dirk Behme]

On 02.04.19 15:34, Marek Vasut wrote:

On 4/2/19 3:18 PM, Eugeniu Rosca wrote:

With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:

-8<-
   LD  u-boot
drivers/gpio/built-in.o: In function `rcar_gpio_request':
drivers/gpio/gpio-rcar.c:128: undefined reference to 
`sh_pfc_config_mux_for_gpio'
-8<-

Fix it in the least intrusive way and *avoid* ifdefs in the *.c code.

Some recent Linux commits sharing the same approach:
  - 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=23222f8f8dce
("acpi, nfit: Add function to look up nvdimm device and provide SMBIOS 
handle")
  - 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f143af7501e
("spi: make OF helper available for others")
  - 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bccd06223f21
("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")

Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
Reported-by: Dirk Behme 
Signed-off-by: Eugeniu Rosca 


Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?



Why not? Main memory, boot device and UART are configured before 
U-Boot, no?


Best regards

Dirk



What is the usecase of CONFIG_PINCTRL_PFC=n ?

I suspect we should rather make sure CONFIG_PINCTRL_PFC=y .


---
  drivers/pinctrl/renesas/sh_pfc.h | 8 
  1 file changed, 8 insertions(+)

diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index b98c2f185d26..3d95d3c725cf 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -261,7 +261,15 @@ void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
  const struct pinmux_bias_reg *
  sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
   unsigned int *bit);
+#if IS_ENABLED(CONFIG_PINCTRL_PFC)
  int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
+#else
+static inline
+int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
+{
+   return -ENODEV;
+}
+#endif
  
  extern const struct sh_pfc_soc_info r8a7790_pinmux_info;

  extern const struct sh_pfc_soc_info r8a7791_pinmux_info;






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Re: [U-Boot] [PATCH v1 04/14] apalis/colibri_imx6/imx6ull: make sure loadaddr does not collide

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk 

On Fri, Mar 29, 2019 at 1:36 PM Marcel Ziswiler  wrote:
>
> From: Stefan Agner 
>
> Currently $loadaddr and $fdt_addr_r point to the same address. This
> might be not ideal for some distro boot scripts which make use of
> $loadaddr after loading the device tree.
>
> Make sure the two variables point to two different addresses. Moving
> $loadaddr is not entirly trivial since it is defined in mx6_common.h.
> Move $fdt_addr_r and $ramdisk_addr_r by 1MiB, which should be enough
> for scripts.
>
> Signed-off-by: Stefan Agner 
> Acked-by: Marcel Ziswiler 
>
> ---
>
>  include/configs/apalis_imx6.h | 4 ++--
>  include/configs/colibri-imx6ull.h | 4 ++--
>  include/configs/colibri_imx6.h| 4 ++--
>  3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
> index 95dd6f9362..02ca8bf361 100644
> --- a/include/configs/apalis_imx6.h
> +++ b/include/configs/apalis_imx6.h
> @@ -139,12 +139,12 @@
>
>  #define MEM_LAYOUT_ENV_SETTINGS \
> "bootm_size=0x2000\0" \
> -   "fdt_addr_r=0x1200\0" \
> +   "fdt_addr_r=0x1210\0" \
> "fdt_high=0x\0" \
> "initrd_high=0x\0" \
> "kernel_addr_r=0x1100\0" \
> "pxefile_addr_r=0x1710\0" \
> -   "ramdisk_addr_r=0x1210\0" \
> +   "ramdisk_addr_r=0x1220\0" \
> "scriptaddr=0x1700\0"
>
>  #define NFS_BOOTCMD \
> diff --git a/include/configs/colibri-imx6ull.h 
> b/include/configs/colibri-imx6ull.h
> index 7cf550cf9e..31248b14a1 100644
> --- a/include/configs/colibri-imx6ull.h
> +++ b/include/configs/colibri-imx6ull.h
> @@ -48,12 +48,12 @@
>
>  #define MEM_LAYOUT_ENV_SETTINGS \
> "bootm_size=0x1000\0" \
> -   "fdt_addr_r=0x8200\0" \
> +   "fdt_addr_r=0x8210\0" \
> "fdt_high=0x\0" \
> "initrd_high=0x\0" \
> "kernel_addr_r=0x8100\0" \
> "pxefile_addr_r=0x8710\0" \
> -   "ramdisk_addr_r=0x8210\0" \
> +   "ramdisk_addr_r=0x8220\0" \
> "scriptaddr=0x8700\0"
>
>  #define NFS_BOOTCMD \
> diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
> index d2f8a58e80..3b94078f82 100644
> --- a/include/configs/colibri_imx6.h
> +++ b/include/configs/colibri_imx6.h
> @@ -129,12 +129,12 @@
>
>  #define MEM_LAYOUT_ENV_SETTINGS \
> "bootm_size=0x1000\0" \
> -   "fdt_addr_r=0x1200\0" \
> +   "fdt_addr_r=0x1210\0" \
> "fdt_high=0x\0" \
> "initrd_high=0x\0" \
> "kernel_addr_r=0x1100\0" \
> "pxefile_addr_r=0x1710\0" \
> -   "ramdisk_addr_r=0x1210\0" \
> +   "ramdisk_addr_r=0x1220\0" \
> "scriptaddr=0x1700\0"
>
>  #define NFS_BOOTCMD \
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Marek Vasut]

On 4/2/19 3:18 PM, Eugeniu Rosca wrote:
> With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:
> 
> -8<-
>   LD  u-boot
> drivers/gpio/built-in.o: In function `rcar_gpio_request':
> drivers/gpio/gpio-rcar.c:128: undefined reference to 
> `sh_pfc_config_mux_for_gpio'
> -8<-
> 
> Fix it in the least intrusive way and *avoid* ifdefs in the *.c code.
> 
> Some recent Linux commits sharing the same approach:
>  - 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=23222f8f8dce
>("acpi, nfit: Add function to look up nvdimm device and provide SMBIOS 
> handle")
>  - 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f143af7501e
>("spi: make OF helper available for others")
>  - 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bccd06223f21
>("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")
> 
> Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
> Reported-by: Dirk Behme 
> Signed-off-by: Eugeniu Rosca 

Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?
What is the usecase of CONFIG_PINCTRL_PFC=n ?

I suspect we should rather make sure CONFIG_PINCTRL_PFC=y .

> ---
>  drivers/pinctrl/renesas/sh_pfc.h | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/pinctrl/renesas/sh_pfc.h 
> b/drivers/pinctrl/renesas/sh_pfc.h
> index b98c2f185d26..3d95d3c725cf 100644
> --- a/drivers/pinctrl/renesas/sh_pfc.h
> +++ b/drivers/pinctrl/renesas/sh_pfc.h
> @@ -261,7 +261,15 @@ void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
>  const struct pinmux_bias_reg *
>  sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
>  unsigned int *bit);
> +#if IS_ENABLED(CONFIG_PINCTRL_PFC)
>  int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
> +#else
> +static inline
> +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
> +{
> + return -ENODEV;
> +}
> +#endif
>  
>  extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
>  extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
> 


-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] pinctrl: renesas: Fix linker error when PINCTRL_PFC=n

[Eugeniu Rosca]

With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:

-8<-
  LD  u-boot
drivers/gpio/built-in.o: In function `rcar_gpio_request':
drivers/gpio/gpio-rcar.c:128: undefined reference to 
`sh_pfc_config_mux_for_gpio'
-8<-

Fix it in the least intrusive way and *avoid* ifdefs in the *.c code.

Some recent Linux commits sharing the same approach:
 - 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=23222f8f8dce
   ("acpi, nfit: Add function to look up nvdimm device and provide SMBIOS 
handle")
 - 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f143af7501e
   ("spi: make OF helper available for others")
 - 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bccd06223f21
   ("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")

Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
Reported-by: Dirk Behme 
Signed-off-by: Eugeniu Rosca 
---
 drivers/pinctrl/renesas/sh_pfc.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index b98c2f185d26..3d95d3c725cf 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -261,7 +261,15 @@ void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
 const struct pinmux_bias_reg *
 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
   unsigned int *bit);
+#if IS_ENABLED(CONFIG_PINCTRL_PFC)
 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
+#else
+static inline
+int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
+{
+   return -ENODEV;
+}
+#endif
 
 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
-- 
2.21.0

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Re: [U-Boot] [PATCH 1/2] Makefile: Add target to generate hex output for combined spl and dtb

[Dalon L Westergreen]

On Sat, 2019-03-30 at 15:18 -0600, Simon Glass wrote:
> Hi,
> On Fri, 22 Mar 2019 at 09:32, Dalon Westergreen<
> dalon.westergr...@linux.intel.com> wrote:
> > From: Dalon Westergreen 
> > Some architectures, Stratix10, require a hex formatted spl that combinesthe
> > spl image and dtb.  This adds a target to create said hex file withand
> > offset of SPL_TEXT_BASE.
> > Signed-off-by: Dalon Westergreen --- Makefile |
> > 9 + 1 file changed, 9 insertions(+)
> 
> Reviewed-by: Simon Glass 
> Please see below.
> > diff --git a/Makefile b/Makefileindex c52a33b403..ecba06ffce 100644---
> > a/Makefile+++ b/Makefile@@ -1074,6 +1074,11 @@ OBJCOPYFLAGS_u-boot-spl.hex =
> > $(OBJCOPYFLAGS_u-boot.hex) spl/u-boot-spl.hex: spl/u-boot-spl
> > FORCE$(call if_changed,objcopy)
> > +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-
> > address=$(CONFIG_SPL_TEXT_BASE)
> 
> Can we drop the -dtb part here? u-boot-spl includes the DTB anyway. Itis the
> -nodtb version which does not.

sure thing.

> 
> > +
> > +spl/u-boot-spl-dtb.hex: spl/u-boot-spl-dtb.bin FORCE
> > +   $(call if_changed,objcopy)
> > +
> >  binary_size_check: u-boot-nodtb.bin FORCE
> > @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
> > map_size=$(shell cat u-boot.map | \
> > @@ -1643,6 +1648,10 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
> > 
> >  spl/u-boot-spl.bin: spl/u-boot-spl
> > @:
> > +
> > +spl/u-boot-spl-dtb.bin: spl/u-boot-spl
> > +   @:
> > +
> >  spl/u-boot-spl: tools prepare \
> > $(if 
> > $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
> >  \
> > $(if 
> > $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
> > --
> > 2.20.1
> > 
> 
> Regards,
> Simon
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[U-Boot] [PATCH v6 07/11] sysreset: enable driver support in SPL/TPL

[Kever Yang]

SPL/TPL also need use sysreset for some feature like panic callback.

Signed-off-by: Kever Yang 
---

Changes in v6:
- update defconfig for stm32mp15_basic, am65x_evm_r5, mt7629_rfb,
  x86, sandbox... to enable SPL_SYSRESET.

 arch/Kconfig|  1 +
 arch/arm/Kconfig|  1 +
 configs/am65x_evm_a53_defconfig |  1 +
 configs/am65x_evm_r5_defconfig  |  1 +
 configs/mt7629_rfb_defconfig|  1 +
 configs/sandbox_spl_defconfig   |  1 +
 drivers/sysreset/Kconfig| 18 ++
 drivers/sysreset/Makefile   |  2 +-
 8 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index 2f3d07c13a..562f9ea692 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -158,6 +158,7 @@ config X86
imply DM_USB
imply DM_VIDEO
imply SYSRESET
+   imply SPL_SYSRESET
imply SYSRESET_X86
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 18e8d9355c..3f67d98755 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1433,6 +1433,7 @@ config ARCH_STM32MP
select SYSRESET
select SYS_THUMB_BUILD
imply CMD_DM
+   imply SPL_SYSRESET
help
  Support for STM32MP SoC family developed by STMicroelectronics,
  MPUs based on ARM cortex A core
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 8f6fd25531..23db645c24 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -68,4 +68,5 @@ CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 49498b13b6..0371189688 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -82,6 +82,7 @@ CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index 459c67827d..f9de4b26df 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -64,6 +64,7 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_MTK_QSPI=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 012f3342ac..784a2fe4bb 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -174,6 +174,7 @@ CONFIG_SANDBOX_SPI=y
 CONFIG_SPMI=y
 CONFIG_SPMI_SANDBOX=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_TIMER=y
 CONFIG_TIMER_EARLY=y
 CONFIG_SANDBOX_TIMER=y
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 8ce3e2e207..d456f0ce36 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -13,6 +13,24 @@ config SYSRESET
  to effect a reset. The uclass will try all available drivers when
  reset_walk() is called.
 
+config SPL_SYSRESET
+   bool "Enable support for system reset drivers in SPL mode"
+   depends on SYSRESET && SPL_DM
+   help
+ Enable system reset drivers which can be used to reset the CPU or
+ board. Each driver can provide a reset method which will be called
+ to effect a reset. The uclass will try all available drivers when
+ reset_walk() is called.
+
+config TPL_SYSRESET
+   bool "Enable support for system reset drivers in TPL mode"
+   depends on SYSRESET && TPL_DM
+   help
+ Enable system reset drivers which can be used to reset the CPU or
+ board. Each driver can provide a reset method which will be called
+ to effect a reset. The uclass will try all available drivers when
+ reset_walk() is called.
+
 if SYSRESET
 
 config SYSRESET_GPIO
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index b3728ac17f..8e1c845dfe 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -2,7 +2,7 @@
 #
 # (C) Copyright 2016 Cadence Design Systems Inc.
 
-obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
 obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
 obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
-- 
2.20.1

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[U-Boot] [PATCH v6 10/11] rockchip: evb-rk3229: add README file for OP-TEE support

[Kever Yang]

Detail of step by step to bring up the board with OP-TEE support.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 board/rockchip/evb_rk3229/README | 72 
 1 file changed, 72 insertions(+)
 create mode 100644 board/rockchip/evb_rk3229/README

diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README
new file mode 100644
index 00..93328c75b2
--- /dev/null
+++ b/board/rockchip/evb_rk3229/README
@@ -0,0 +1,72 @@
+Get the Source and prebuild binary
+==
+
+  > mkdir ~/evb_rk3229
+  > cd ~/evb_rk3229
+  > git clone git://git.denx.de/u-boot.git
+  > git clone https://github.com/OP-TEE/optee_os.git
+  > git clone https://github.com/rockchip-linux/rkbin.git
+  > git clone https://github.com/rockchip-linux/rkdeveloptool.git
+
+Compile the OP-TEE
+===
+
+  > cd optee_os
+  > make clean
+  > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x
+  Get tee.bin in this step, copy it to U-Boot root dir:
+  > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin
+
+Compile the U-Boot
+==
+
+  > cd ../u-boot
+  > export CROSS_COMPILE=arm-linux-gnueabihf-
+  > export ARCH=arm
+  > make evb-rk3229_defconfig
+  > make
+  > make u-boot.itb
+
+  Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
+
+Compile the rkdeveloptool
+===
+  Follow instructions in latest README
+  > cd ../rkflashtool
+  > autoreconf -i
+  > ./configure
+  > make
+  > sudo make install
+
+  Get rkdeveloptool in you Host in this step.
+
+Both origin binaries and Tool are ready now, choose either option 1 or
+option 2 to deploy U-Boot.
+
+Package the image
+=
+
+  > cd ../u-boot
+  > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img
+  > cat spl/u-boot-spl.bin >> idbloader.img
+
+  Get idbloader.img in this step.
+
+Flash the image to eMMC
+===
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > cd ..
+  > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
+  > rkdeveloptool wl 64 u-boot/idbloader.img
+  > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+  > rkdeveloptool rd
+
+Flash the image to SD card
+==
+  > dd if=u-boot/idbloader.img of=/dev/sdb seek=64
+  > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384
+
+You should be able to get U-Boot log message with OP-TEE boot info.
+
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
-- 
2.20.1

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[U-Boot] [PATCH v6 08/11] rockchip: rk322x: dts: enable uart2 for SPL/TPL

[Kever Yang]

When we use DM_SERIAL for serial driver, we need enable the
dts node for the debug console.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 arch/arm/dts/rk3229-evb.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index bfb367ac99..632cdc9bc3 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -82,6 +82,7 @@
 };
 
  {
+   u-boot,dm-pre-reloc;
status = "okay";
 };
 
-- 
2.20.1

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[U-Boot] [PATCH v6 11/11] rockchip: evb-rk322x: update defconfig with tpl and optee support

[Kever Yang]

Enable all the options for TPL/SPL and OPTEE.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 configs/evb-rk3229_defconfig | 25 +
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 14ff54af20..8ad48bad68 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -1,37 +1,51 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x6000
+CONFIG_SYS_TEXT_BASE=0x6100
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ROCKCHIP_RK322X=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
 CONFIG_TARGET_EVB_RK3229=y
 CONFIG_DEBUG_UART_BASE=0x1103
 CONFIG_DEBUG_UART_CLOCK=2400
-CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_SPL_STACK_R_ADDR=0x6060
 CONFIG_DEBUG_UART=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_OPTEE=y
+CONFIG_SPL_FIT_SOURCE="arch/arm/mach-rockchip/fit_spl_optee.its"
 CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_FASTBOOT_BUF_SIZE=0x0400
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
@@ -46,6 +60,7 @@ CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
@@ -57,3 +72,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_ERRNO_STR=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_USE_TINY_PRINTF=y
-- 
2.20.1

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[U-Boot] [PATCH v6 09/11] rockchip: evb-rk3229: remove unnecessary defines

[Kever Yang]

Prefer to use default setting like other SoCs.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 include/configs/evb_rk3229.h | 44 +---
 1 file changed, 1 insertion(+), 43 deletions(-)

diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h
index 369b0bc68a..6a91a82ceb 100644
--- a/include/configs/evb_rk3229.h
+++ b/include/configs/evb_rk3229.h
@@ -8,48 +8,6 @@
 
 #include 
 
-
-/* Store env in emmc */
-#define CONFIG_SYS_MMC_ENV_DEV  0
-#define CONFIG_SYS_MMC_ENV_PART 0
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#ifndef CONFIG_SPL_BUILD
-/* Enable gpt partition table */
-#undef PARTS_DEFAULT
-#define PARTS_DEFAULT \
-   "uuid_disk=${uuid_gpt_disk};" \
-   "name=loader_a,start=4M,size=4M,uuid=${uuid_gpt_loader};" \
-   "name=loader_b,size=4M,uuid=${uuid_gpt_reserved};" \
-   "name=trust_a,size=4M,uuid=${uuid_gpt_reserved};" \
-   "name=trust_b,size=4M,uuid=${uuid_gpt_reserved};" \
-   "name=misc,size=4M,uuid=${uuid_gpt_misc};" \
-   "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
-   "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \
-   "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \
-   "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \
-   "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \
-   "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \
-   "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \
-   "name=cache,size=100M,uuid=${uuid_gpt_cache};" \
-   "name=persist,size=4M,uuid=${uuid_gpt_persist};" \
-   "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \
-
-#define CONFIG_PREBOOT
-
-#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
-   "mmc read 0x6100 0x8000 0x5000;" \
-   "bootm 0x6100" \
-
-/* Enable atags */
-#define CONFIG_SYS_BOOTPARAMS_LEN  (64*1024)
-#define CONFIG_INITRD_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-
-#endif
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 #endif
-- 
2.20.1

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[U-Boot] [PATCH v6 04/11] rockchip: rk322x: add CLK_EMMC_SAMPLE clock support

[Kever Yang]

Signed-off-by: Kever Yang 
---

Changes in v6: None

 drivers/clk/rockchip/clk_rk322x.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk322x.c 
b/drivers/clk/rockchip/clk_rk322x.c
index 48ed14b2af..4b599fbb24 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -217,6 +217,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, 
uint clk_general_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
+   case SCLK_EMMC_SAMPLE:
con = readl(>cru_clksel_con[11]);
mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
con = readl(>cru_clksel_con[12]);
@@ -293,6 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, 
uint clk_general_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
+   case SCLK_EMMC_SAMPLE:
rk_clrsetreg(>cru_clksel_con[11],
 EMMC_PLL_MASK,
 mux << EMMC_PLL_SHIFT);
-- 
2.20.1

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[U-Boot] [PATCH v6 02/11] arm: add option for TPL support in arm 32bit

[Kever Yang]

Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY
and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 arch/arm/Kconfig | 29 +
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a5851aeeae..18e8d9355c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -338,6 +338,17 @@ config SPL_SYS_THUMB_BUILD
   density. For ARM architectures that support Thumb2 this flag will
   result in Thumb2 code generated by GCC.
 
+config TPL_SYS_THUMB_BUILD
+   bool "Build TPL using the Thumb instruction set"
+   default y if SYS_THUMB_BUILD
+   depends on TPL && !ARM64
+   help
+  Use this flag to build SPL using the Thumb instruction set for
+  ARM architectures. Thumb instruction set provides better code
+  density. For ARM architectures that support Thumb2 this flag will
+  result in Thumb2 code generated by GCC.
+
+
 config SYS_L2CACHE_OFF
bool "L2cache off"
help
@@ -373,6 +384,15 @@ config SPL_USE_ARCH_MEMCPY
  Such implementation may be faster under some conditions
  but may increase the binary size.
 
+config TPL_USE_ARCH_MEMCPY
+   bool "Use an assembly optimized implementation of memcpy for TPL"
+   default y if USE_ARCH_MEMCPY
+   depends on !ARM64
+   help
+ Enable the generation of an optimized version of memcpy.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
 config USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset"
default y
@@ -391,6 +411,15 @@ config SPL_USE_ARCH_MEMSET
  Such implementation may be faster under some conditions
  but may increase the binary size.
 
+config TPL_USE_ARCH_MEMSET
+   bool "Use an assembly optimized implementation of memset for TPL"
+   default y if USE_ARCH_MEMSET
+   depends on !ARM64
+   help
+ Enable the generation of an optimized version of memset.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
 config ARM64_SUPPORT_AARCH32
bool "ARM64 system support AArch32 execution state"
default y if ARM64 && !TARGET_THUNDERX_88XX
-- 
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[U-Boot] [PATCH v6 05/11] rockchip: clk: rk322x: fix assert clock value

[Kever Yang]

BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 drivers/clk/rockchip/clk_rk322x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk322x.c 
b/drivers/clk/rockchip/clk_rk322x.c
index 4b599fbb24..f09730c91b 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru)
assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
-   assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
+   assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
 
hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
-   assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
+   assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
 
rk_clrsetreg(>cru_clksel_con[0],
 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
-- 
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[U-Boot] [PATCH v6 06/11] rockchip: rk322x: add tpl support

[Kever Yang]

Move original spl to tpl, and add spl to load next stage firmware,
adapt all the address and option for them.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 arch/arm/mach-rockchip/Kconfig| 26 +++
 arch/arm/mach-rockchip/Makefile   |  3 +-
 arch/arm/mach-rockchip/rk322x-board-spl.c | 46 
 arch/arm/mach-rockchip/rk322x-board-tpl.c | 53 +++
 arch/arm/mach-rockchip/u-boot-tpl.lds | 12 +
 include/configs/rk322x_common.h   | 10 +++--
 6 files changed, 116 insertions(+), 34 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c
 create mode 100644 arch/arm/mach-rockchip/u-boot-tpl.lds

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 17b3b9372d..d0ed369f55 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -47,14 +47,40 @@ config ROCKCHIP_RK322X
bool "Support Rockchip RK3228/RK3229"
select CPU_V7A
select SUPPORT_SPL
+   select SUPPORT_TPL
select SPL
+   select SPL_DM
+   select SPL_OF_LIBFDT
+   select TPL
+   select TPL_DM
+   select TPL_OF_LIBFDT
+   select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
+   select TPL_NEEDS_SEPARATE_STACK if TPL
+   select SPL_DRIVERS_MISC_SUPPORT
+   imply SPL_SERIAL_SUPPORT
+   imply TPL_SERIAL_SUPPORT
select ROCKCHIP_BROM_HELPER
+   select TPL_LIBCOMMON_SUPPORT
+   select TPL_LIBGENERIC_SUPPORT
help
  The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
  including NEON and GPU, Mali-400 graphics, several DDR3 options
  and video codec support. Peripherals include Gigabit Ethernet,
  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
+if ROCKCHIP_RK322X
+
+config TPL_TEXT_BASE
+default 0x10081000
+
+config TPL_MAX_SIZE
+default 28672
+
+config TPL_STACK
+default 0x10088000
+
+endif
+
 config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7A
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 368302e1da..fd62a693fe 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,10 +11,11 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 
 obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
 
 obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c 
b/arch/arm/mach-rockchip/rk322x-board-spl.c
index 888310efbe..c9b41c62c0 100644
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -4,55 +4,43 @@
  */
 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
-#include 
 #include 
-#include 
 
 u32 spl_boot_device(void)
 {
return BOOT_DEVICE_MMC1;
 }
 
+u32 spl_boot_mode(const u32 boot_device)
+{
+   return MMCSD_MODE_RAW;
+}
+
 #define SGRF_DDR_CON0 0x1015
 void board_init_f(ulong dummy)
 {
-   struct udevice *dev;
int ret;
 
-#ifdef CONFIG_DEBUG_UART
-   /*
-* Debug UART can be used from here if required:
-*
-* debug_uart_init();
-* printch('a');
-* printhex8(0x1234);
-* printascii("string");
-*/
-   debug_uart_init();
-   printascii("SPL Init");
-#endif
ret = spl_early_init();
if (ret) {
-   debug("spl_early_init() failed: %d\n", ret);
+   printf("spl_early_init() failed: %d\n", ret);
hang();
}
-
-   rockchip_timer_init();
-   printf("timer init done\n");
-   ret = uclass_get_device(UCLASS_RAM, 0, );
-   if (ret) {
-   printf("DRAM init failed: %d\n", ret);
-   return;
-   }
+   preloader_console_init();
 
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && 
!defined(CONFIG_SPL_BOARD_INIT)
-   back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
 }
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   /* Just empty function now - can't decide what to choose */
+   debug("%s: %s\n", __func__, name);
+
+   return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c 
b/arch/arm/mach-rockchip/rk322x-board-tpl.c
new file mode 100644
index 00..92d40ee43a
--- 

[U-Boot] [PATCH v6 01/11] Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"

[Kever Yang]

This reverts commit f338cca1d2bce906b049722d2fdbf527a4963b61.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 drivers/ram/rockchip/sdram_rk322x.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk322x.c 
b/drivers/ram/rockchip/sdram_rk322x.c
index c596523d4f..e96ac54c39 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -49,7 +49,7 @@ struct rk322x_sdram_params {
struct regmap *map;
 };
 
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
 /*
  * [7:6]  bank(n:n bit bank)
  * [5:4]  row(13+n)
@@ -750,7 +750,7 @@ static int rk322x_dmc_ofdata_to_platdata(struct udevice 
*dev)
 
return 0;
 }
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_TPL_BUILD */
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 static int conv_of_platdata(struct udevice *dev)
@@ -778,7 +778,7 @@ static int conv_of_platdata(struct udevice *dev)
 
 static int rk322x_dmc_probe(struct udevice *dev)
 {
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
struct rk322x_sdram_params *plat = dev_get_platdata(dev);
int ret;
struct udevice *dev_clk;
@@ -786,7 +786,7 @@ static int rk322x_dmc_probe(struct udevice *dev)
struct dram_info *priv = dev_get_priv(dev);
 
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_platdata(dev);
if (ret)
@@ -842,12 +842,12 @@ U_BOOT_DRIVER(dmc_rk322x) = {
.id = UCLASS_RAM,
.of_match = rk322x_dmc_ids,
.ops = _dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
.ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata,
 #endif
.probe = rk322x_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
.platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params),
 #endif
 };
-- 
2.20.1

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[U-Boot] [PATCH v6 03/11] arm: add a separate stack for TPL

[Kever Yang]

TPL stack may different from SPL and sys stack, add support for
separate one when the board defines it.

Signed-off-by: Kever Yang 
---

Changes in v6: None

 arch/arm/lib/crt0.S | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index fe312db690..30fba20e1b 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -67,7 +67,9 @@ ENTRY(_main)
  * Set up initial C runtime environment and call board_init_f(0).
  */
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
+   ldr r0, =(CONFIG_TPL_STACK)
+#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
 #else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
-- 
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[U-Boot] [PATCH v6 00/11] rockchip: add tpl and OPTEE support for rk3229

[Kever Yang]

Add some generic options for TPL support for arm 32bit, and then
and TPL support for rk3229(cortex-A7), and then add OPTEE support
in SPL.

Version 5 rebase on master branch with 'SYS_SOC name correct' patch
set, remove the patches for OP-TEE which has been mergerd.

Version 6 fix travis build error cause by sysreset update.
https://travis-ci.org/keveryang/u-boot/builds/514475183

Changes in v6:
- update defconfig for stm32mp15_basic, am65x_evm_r5, mt7629_rfb,
  x86, sandbox... to enable SPL_SYSRESET.

Kever Yang (11):
  Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"
  arm: add option for TPL support in arm 32bit
  arm: add a separate stack for TPL
  rockchip: rk322x: add CLK_EMMC_SAMPLE clock support
  rockchip: clk: rk322x: fix assert clock value
  rockchip: rk322x: add tpl support
  sysreset: enable driver support in SPL/TPL
  rockchip: rk322x: dts: enable uart2 for SPL/TPL
  rockchip: evb-rk3229: remove unnecessary defines
  rockchip: evb-rk3229: add README file for OP-TEE support
  rockchip: evb-rk322x: update defconfig with tpl and optee support

 arch/Kconfig  |  1 +
 arch/arm/Kconfig  | 30 ++
 arch/arm/dts/rk3229-evb.dts   |  1 +
 arch/arm/lib/crt0.S   |  4 +-
 arch/arm/mach-rockchip/Kconfig| 26 
 arch/arm/mach-rockchip/Makefile   |  3 +-
 arch/arm/mach-rockchip/rk322x-board-spl.c | 46 ++-
 arch/arm/mach-rockchip/rk322x-board-tpl.c | 53 +
 arch/arm/mach-rockchip/u-boot-tpl.lds | 12 
 board/rockchip/evb_rk3229/README  | 72 +++
 configs/am65x_evm_a53_defconfig   |  1 +
 configs/am65x_evm_r5_defconfig|  1 +
 configs/evb-rk3229_defconfig  | 25 ++--
 configs/mt7629_rfb_defconfig  |  1 +
 configs/sandbox_spl_defconfig |  1 +
 drivers/clk/rockchip/clk_rk322x.c |  6 +-
 drivers/ram/rockchip/sdram_rk322x.c   | 12 ++--
 drivers/sysreset/Kconfig  | 18 ++
 drivers/sysreset/Makefile |  2 +-
 include/configs/evb_rk3229.h  | 44 +-
 include/configs/rk322x_common.h   | 10 ++--
 21 files changed, 278 insertions(+), 91 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c
 create mode 100644 arch/arm/mach-rockchip/u-boot-tpl.lds
 create mode 100644 board/rockchip/evb_rk3229/README

-- 
2.20.1

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Re: [U-Boot] [PATCH] net: macb: Add small delay after link establishment

[Eugen.Hristev]

On 29.03.2019 17:24, Stefan Roese wrote:

> 
> On 29.03.19 15:59, eugen.hris...@microchip.com wrote:
>>
>>
>> On 29.03.2019 16:52, Stefan Roese wrote:
>>
>>> Hi Eugen,
>>>
>>> On 29.03.19 15:40, eugen.hris...@microchip.com wrote:
> I've noticed that the first ethernet packet after PHY link 
> establishment
> is not tranferred correctly most of the time on my AT91SAM9G25 board.
> Here I usually see a timeout of a few seconds, which is quite
> annoying.
>
> Adding a small delay (10ms in this case) after the link establishment
> helps to solve this problem. With this patch applied, this timeout
> on the first packet is not seen any more.

 Hi Stefan,

 I find this a bit odd... maybe someone with a different board having
 this Ethernet controller can confirm or infirm this ?
>>>
>>> I've seen such issues of timeouts with the first ethernet packet
>>> after link negotiation on other platforms / controllers a few
>>> times before in U-Boot. Using a short delay after link-up always
>>> did help here.
>>>
>>> I'm not saying that this is the perfect solution, but its one that
>>> works and removes these timeouts, which really annoy me.
>>>
 Linux driver for macb has a similar issue ?
>>>
>>> Not that I am aware of. There might be some delay in the link
>>> establishment hidden as well. I did not check yet.
>>>
 Adding a delay just for the sake of it might hide another issue that we
 are missing at this point: why exactly transfer fails right away... it
 is likely that we want to send packets but link in fact is not ready ?
>>>
>>> Yes, something like this.
>>
>> I see there is a small udelay below your code, you add a delay 100 times
>> bigger... maybe that small delay is related ?
> 
> The udelay(100) below is for the timeout handling of the link autoneg
> loop. This should be probably moved to some loop using get_timer() so
> that this udelay can be removed completely.
> 
> Coming back to your question, if these delays are related. No, they
> are not. The one that I insert is explicitly added *after* the link
> was established. I could experiment if a smaller value also works, but
> I found that 100ms was working in all my test cases. Possibly 10ms
> or even 1ms also works. Not sure.

Hi Joe,

If you agree with this change I will take it through my tree. Or any 
feedback appreciated from you or someone familiar with the macb / 
network devices.

Thanks !
Eugen

> 
> Thanks,
> Stefan
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Re: [U-Boot] [PATCH 07/13 v3] arm: at91: Enable watchdog support

[Stefan Roese]

On 02.04.19 13:26, eugen.hris...@microchip.com wrote:



On 02.04.2019 11:57, Stefan Roese wrote:



This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
v3:
- Move WDT struct and macros into arch header so that it can be used
by the arch code to start the driver (timeout value)
- This change now enables the use of the "timeout-sec" DT property
to specifiy a board specific WD timeout value



Hi Stefan,

This breaks pm9261_defconfig

   AS  arch/arm/mach-at91/arm926ejs/lowlevel_init.o
./arch/arm/include/asm/arch/at91_wdt.h: Assembler messages:
./arch/arm/include/asm/arch/at91_wdt.h:50: Error: bad instruction
`struct at91_wdt_priv {'
./arch/arm/include/asm/arch/at91_wdt.h:51: Error: bad instruction `void
__iomem*regs'
./arch/arm/include/asm/arch/at91_wdt.h:52: Error: bad instruction `u32
regval'
./arch/arm/include/asm/arch/at91_wdt.h:53: Error: bad instruction `u32
timeout'
./arch/arm/include/asm/arch/at91_wdt.h:54: Error: junk at end of line,
first unrecognized character is `}'
scripts/Makefile.build:314: recipe for target
'arch/arm/mach-at91/arm926ejs/lowlevel_init.o' failed


Sorry about these breakages. I'll fix this and will run the new
patches through Travis and will only send the next version once
this is compile clean.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)

[Stefano Babic]

On 02/04/19 13:22, Fabio Estevam wrote:
> Hi Lukasz,
> 
> On Mon, Apr 1, 2019 at 5:49 PM Lukasz Majewski  wrote:
> 
>>> We should probably use the same approach as in the kernel to avoid
>>> regressions with old dtbs.
>>>
>>> In the kernel the GPIO polarity passed in the 'phy-reset-gpios'
>>> property is ignored and it is assumed to be active low, unless
>>> 'phy-reset-active-high' is passed.
>>
>> This may be a good solution.
>>
>> However, I do hope that this fix will be accepted to v2019.04 as it is
>> necessary to have ETH working (and it is the only convenient way to
>> update u-boot on this board).
> 
> Yes, agreed.
> 

+1

It is just a small fix, I pick it up.

Stefano

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[U-Boot] [PATCH v2 10/10] ARM: imx6: Enable CLK for Engicam i.MX6UL boards

[Jagan Teki]

Now, clock driver available for i.MX6UL so enable the CLK
in SPL and U-Boot proper for Engicam i.MX6UL boards.

Signed-off-by: Jagan Teki 
---
 arch/arm/mach-imx/mx6/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index e782859b1e..851cabc6fa 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -361,6 +361,7 @@ config TARGET_MX6UL_14X14_EVK
 config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
select BOARD_LATE_INIT
+   select CLK
select DM
select DM_ETH
select DM_GPIO
@@ -369,6 +370,7 @@ config TARGET_MX6UL_ENGICAM
select DM_THERMAL
select MX6UL
select OF_CONTROL
+   select SPL_CLK if SPL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
select SPL_PINCTRL if SPL
-- 
2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH v2 07/10] ARM: dts: i.MX6QDL: Add u-boot, dm-spl for clks

[Jagan Teki]

Add clks node available for SPL in imx6qdl SoC.

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6qdl-u-boot.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi
index 0aa29e38b8..912cb4281c 100644
--- a/arch/arm/dts/imx6qdl-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-u-boot.dtsi
@@ -24,6 +24,10 @@
u-boot,dm-spl;
 };
 
+ {
+   u-boot,dm-spl;
+};
+
  {
u-boot,dm-spl;
 };
-- 
2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH v2 08/10] ARM: dts: i.MX6UL: Add u-boot, dm-spl for clks

[Jagan Teki]

Add clks node available for SPL in imx6ul SoC.

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6ul-u-boot.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imx6ul-u-boot.dtsi b/arch/arm/dts/imx6ul-u-boot.dtsi
index eb190cf8c8..b25f77cb44 100644
--- a/arch/arm/dts/imx6ul-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-u-boot.dtsi
@@ -21,6 +21,10 @@
u-boot,dm-spl;
 };
 
+ {
+   u-boot,dm-spl;
+};
+
  {
u-boot,dm-spl;
 };
-- 
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[U-Boot] [PATCH v2 09/10] configs: icore_mipi: Enable CLK

[Jagan Teki]

Now, clock driver available for i.MX6Q so enable the CLK
in SPL and U-Boot proper for Engicam i.CoreM6 MIPI boards.

Signed-off-by: Jagan Teki 
---
 configs/imx6qdl_icore_mipi_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/imx6qdl_icore_mipi_defconfig 
b/configs/imx6qdl_icore_mipi_defconfig
index 7a0e5169b6..bb5e0d3abd 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
+CONFIG_SPL_CLK=y
 CONFIG_DEBUG_UART_BASE=0x021f
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -44,6 +45,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
 CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_I2C_MXC=y
+CONFIG_CLK=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
-- 
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[U-Boot] [PATCH v2 06/10] clk: imx6: Add imx6ul clock tree support

[Jagan Teki]

i.MX6 clock control module comprise of parent clocks, gates, multiplexers,
dividers, PODF, PLL, fixed rate and etc.

So, the U-Boot implementation of ccm has divided into gates and tree.

1) gate clocks are generic clock configuration of enable/disable bit management
   which can be handle via imx6_clock_gate.
2) tree clocks are handle via tree clock management where it link the clocks
   based on the parent clock which usually required to get and set the
   clock rates.

This patch add tree clock management for imx6ul USDHC clocks, so the mmc driver
from imx6 can eventually use this so getting the USDHC clock rates.

Unlike Linux, U-Boot implementation may not require to maintain exact clock tree
due to various constrains and use cases. So here is how the clock tree differs
between them.

usdhc clock tree in Linux:
-
USDHC1 => USDHC1_PODF => USDHC1_SEL => PLL2_PFD2 => PLL2_BUS => PLL2_BYPASS => 
PLL2 => OSC

usdhc clock tree in U-Boot:
---
USDHC1 => USDHC1_PODF => USDHC1_SEL => PLL2_PFD2 => PLL2_BUS => OSC

Signed-off-by: Jagan Teki 
---
 drivers/clk/imx/clk-imx6ul.c | 48 
 1 file changed, 48 insertions(+)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index f5250e8b72..8528176eec 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -10,6 +10,53 @@
 #include 
 #include 
 
+static const unsigned long pll2_bus[] = {
+   IMX6UL_CLK_OSC,
+};
+
+static const unsigned long pfd_352m[] = {
+   IMX6UL_CLK_PLL2_BUS,
+};
+
+static const unsigned long usdhc_sel[] = {
+   IMX6UL_CLK_PLL2_PFD2,
+   IMX6UL_CLK_PLL2_PFD0,
+};
+
+static const unsigned long usdhc1_podf[] = {
+   IMX6UL_CLK_USDHC1_SEL,
+};
+
+static const unsigned long usdhc2_podf[] = {
+   IMX6UL_CLK_USDHC2_SEL,
+};
+
+static const unsigned long usdhc1[] = {
+   IMX6UL_CLK_USDHC1_PODF,
+};
+
+static const unsigned long usdhc2[] = {
+   IMX6UL_CLK_USDHC2_PODF,
+};
+
+static const struct imx6_clk_tree imx6ul_tree[] = {
+   [IMX6UL_CLK_OSC]= FIXED(OSC_24M_ULL),
+
+   [IMX6UL_CLK_PLL2_BUS]   = PLL_DIV(pll2_bus, 0x30, 13, 1),
+
+   [IMX6UL_CLK_PLL2_PFD0]  = PLL_PFD(pfd_352m, 0x100, 6, 0),
+   [IMX6UL_CLK_PLL2_PFD2]  = PLL_PFD(pfd_352m, 0x100, 6, 2),
+
+   [IMX6UL_CLK_USDHC2_SEL] = MUX(usdhc_sel, 0x01c, 17, 1),
+   [IMX6UL_CLK_USDHC1_SEL] = MUX(usdhc_sel, 0x01c, 16, 1),
+
+   [IMX6UL_CLK_USDHC2_PODF]= DIV(usdhc2_podf, 0x024, 16, 3),
+   [IMX6UL_CLK_USDHC1_PODF]= DIV(usdhc1_podf, 0x024, 11, 3),
+
+   [IMX6UL_CLK_USDHC2] = SIMPLE(usdhc2),
+   [IMX6UL_CLK_USDHC1] = SIMPLE(usdhc1),
+};
+
 static const struct imx6_clk_gate imx6ul_gates[] = {
[IMX6UL_CLK_USDHC1] = GATE(0x080, GENMASK(3, 2)),
[IMX6UL_CLK_USDHC2] = GATE(0x080, GENMASK(5, 4)),
@@ -17,6 +64,7 @@ static const struct imx6_clk_gate imx6ul_gates[] = {
 
 static const struct imx6_clk_desc imx6ul_clk_desc = {
.gates = imx6ul_gates,
+   .tree = imx6ul_tree,
 };
 
 static const struct udevice_id clk_imx6ul_ids[] = {
-- 
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[U-Boot] [PATCH v2 03/10] clk: imx: Add i.MX6UL clock driver

[Jagan Teki]

i.MX6 clock control module comprise of parent clocks, gates, multiplexers,
dividers, PODF, PLL, fixed rate and etc.

This patch add i.MX6UL USDHC clocks via gate clock which would eventually
handle enable/disable operations via imx6_clock_gate.

Signed-off-by: Jagan Teki 
---
 drivers/clk/imx/Kconfig  |  7 +++
 drivers/clk/imx/Makefile |  1 +
 drivers/clk/imx/clk-imx6ul.c | 37 
 3 files changed, 45 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imx6ul.c

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index f81903dcf4..952cec8bff 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -15,6 +15,13 @@ config CLK_IMX6Q
  This enables common clock driver support for platforms based
  on i.MX6 QDL SoC.
 
+config CLK_IMX6UL
+   bool "Clock driver for i.MX6UL"
+   default MX6UL
+   help
+This enables common clock driver support for platforms based
+on i.MX6 UL SoC.
+
 config CLK_IMX8
bool "Clock support for i.MX8"
default ARCH_IMX8
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index a4cb2bbf3b..999de1dd6f 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -7,4 +7,5 @@ obj-$(CONFIG_CLK_IMX) += clk-imx6-common.o
 endif
 
 obj-$(CONFIG_CLK_IMX6Q) += clk-imx6q.o
+obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
 obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
new file mode 100644
index 00..f5250e8b72
--- /dev/null
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Amarula Solutions.
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct imx6_clk_gate imx6ul_gates[] = {
+   [IMX6UL_CLK_USDHC1] = GATE(0x080, GENMASK(3, 2)),
+   [IMX6UL_CLK_USDHC2] = GATE(0x080, GENMASK(5, 4)),
+};
+
+static const struct imx6_clk_desc imx6ul_clk_desc = {
+   .gates = imx6ul_gates,
+};
+
+static const struct udevice_id clk_imx6ul_ids[] = {
+   {
+ .compatible = "fsl,imx6ul-ccm",
+ .data = (ulong)_clk_desc
+   },
+   { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_imx6ul) = {
+   .name   = "clk_imx6ul",
+   .id = UCLASS_CLK,
+   .of_match   = clk_imx6ul_ids,
+   .priv_auto_alloc_size   = sizeof(struct imx6_clk_priv),
+   .ops= _clk_ops,
+   .probe  = imx6_clk_probe,
+};
-- 
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[U-Boot] [PATCH v2 05/10] clk: imx: Add imx6q clock tree support

[Jagan Teki]

i.MX6 clock control module comprise of parent clocks, gates, multiplexers,
dividers, PODF, PLL, fixed rate and etc.

So, the U-Boot implementation of ccm has divided into gates and tree.

1) gate clocks are generic clock configuration of enable/disable bit management
   which can be handle via imx6_clock_gate.
2) tree clocks are handle via tree clock management where it link the clocks
   based on the parent clock which usually required to get and set the
   clock rates.

This patch add tree clock management for imx6q USDHC clocks, so the mmc driver
from imx6 can eventually use this so getting the USDHC clock rates.

Unlike Linux, U-Boot implementation may not require to maintain exact clock tree
due to various constrains and use cases. So here is how the clock tree differs
between them.

usdhc clock tree in Linux:
-
USDHC1 => USDHC1_PODF => USDHC1_SEL => PLL2_PFD2 => PLL2_BUS => PLL2_BYPASS => 
PLL2 => OSC

usdhc clock tree in U-Boot:
---
USDHC1 => USDHC1_PODF => USDHC1_SEL => PLL2_PFD2 => PLL2_BUS => OSC

Signed-off-by: Jagan Teki 
---
 arch/arm/include/asm/arch-mx6/clock.h |  65 
 drivers/clk/imx/clk-imx6-common.c | 103 ++
 drivers/clk/imx/clk-imx6q.c   |  70 +
 3 files changed, 238 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index fa921a9f08..424231c691 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -21,6 +21,67 @@
 #define MXC_CLK32  32768
 #endif
 
+#define OSC_24M_ULL2400ULL
+
+enum imx6_clk_type {
+   IMX6_CLK_TYPE_SIMPLE= 0,
+   IMX6_CLK_TYPE_FIXED,
+   IMX6_CLK_TYPE_DIV,
+   IMX6_CLK_TYPE_MUX,
+   IMX6_CLK_TYPE_PLL_PFD,
+   IMX6_CLK_TYPE_PLL_DIV,
+};
+
+/**
+ * struct imx6_clk_tree - imx6 ccm clock tree
+ *
+ * @parent:parent clock tree
+ * @type:  clock type
+ * @off:   register offset of the specified clock
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @idx:   index of the specified clock
+ * @fixed_rate:fixed clock rate
+ */
+struct imx6_clk_tree {
+   const unsigned long *parent;
+   enum imx6_clk_type type;
+   u16 off;
+
+   u8 shift;
+   u8 width;
+   u8 idx;
+   ulong fixed_rate;
+};
+
+#define TREE(_parent, _type, _off, _shift, _width, _idx, _fixed_rate) {
\
+   .parent = _parent,  \
+   .type = _type,  \
+   .off = _off,\
+   .shift = _shift,\
+   .width = _width,\
+   .idx = _idx,\
+   .fixed_rate = _fixed_rate,  \
+}
+
+#define SIMPLE(_parent)
\
+   TREE(_parent, IMX6_CLK_TYPE_SIMPLE, 0, 0, 0, 0, 0)
+
+#define FIXED(_fixed_rate) \
+   TREE(NULL, IMX6_CLK_TYPE_FIXED, 0, 0, 0, 0, _fixed_rate)
+
+#define DIV(_parent, _off, _shift, _width) \
+   TREE(_parent, IMX6_CLK_TYPE_DIV, _off, _shift, _width, 0, 0)
+
+#define MUX(_parent, _off, _shift, _width) \
+   TREE(_parent, IMX6_CLK_TYPE_MUX, _off, _shift, _width, 0, 0)
+
+#define PLL_PFD(_parent, _off, _width, _idx)   \
+   TREE(_parent, IMX6_CLK_TYPE_PLL_PFD, _off, 0, _width, _idx, 0)
+
+#define PLL_DIV(_parent, _off, _shift, _width) \
+   TREE(_parent, IMX6_CLK_TYPE_PLL_DIV, _off, _shift, _width, 0, 0)
+
 /**
  * struct imx6_clk_gate - imx6 ccm clock gate
  *
@@ -41,19 +102,23 @@ struct imx6_clk_gate {
  * struct imx6_clk_desc - imx6 clock control module descriptor
  *
  * @gates: ccm clock gates
+ * @tree:  ccm clock tree
  */
 struct imx6_clk_desc {
const struct imx6_clk_gate *gates;
+   const struct imx6_clk_tree *tree;
 };
 
 /**
  * struct imx6_clk_priv - imx6 clock control module
  *
  * @base:  ccm base address
+ * @anatop:anatop base address
  * @desc:  ccm descriptor
  */
 struct imx6_clk_priv {
void *base;
+   void *anatop;
const struct imx6_clk_desc *desc;
 };
 
diff --git a/drivers/clk/imx/clk-imx6-common.c 
b/drivers/clk/imx/clk-imx6-common.c
index 1d38f51f7e..d21facf2e5 100644
--- a/drivers/clk/imx/clk-imx6-common.c
+++ b/drivers/clk/imx/clk-imx6-common.c
@@ -6,18 +6,117 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
+#include 
+
 static const struct imx6_clk_gate *priv_to_gate(struct imx6_clk_priv *priv,
   

[U-Boot] [PATCH v2 04/10] clk: Add clk_div_mask helper

[Jagan Teki]

Add clock helper to compute the clock divider mask when use invoke
with clock width.

Signed-off-by: Jagan Teki 
---
 include/clk-uclass.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index e76d98e2f6..15ac8867a7 100644
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -100,4 +100,6 @@ struct clk_ops {
int (*disable)(struct clk *clk);
 };
 
+#define clk_div_mask(width)((1 << (width)) - 1)
+
 #endif
-- 
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[U-Boot] [PATCH v2 02/10] clk: imx: Add i.MX6Q clock driver

[Jagan Teki]

i.MX6 clock control module comprise of parent clocks, gates, multiplexers,
dividers, PODF, PLL, fixed rate and etc.

This patch add i.MX6Q USDHC clocks via gate clock which would eventually
handle enable/disable operations via imx6_clock_gate.

Signed-off-by: Jagan Teki 
---
 arch/arm/include/asm/arch-mx6/clock.h | 44 +
 drivers/clk/imx/Kconfig   |  9 +++-
 drivers/clk/imx/Makefile  |  5 ++
 drivers/clk/imx/clk-imx6-common.c | 69 +++
 drivers/clk/imx/clk-imx6q.c   | 39 +++
 5 files changed, 165 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/imx/clk-imx6-common.c
 create mode 100644 drivers/clk/imx/clk-imx6q.c

diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index a9481a5fea..fa921a9f08 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -21,6 +21,50 @@
 #define MXC_CLK32  32768
 #endif
 
+/**
+ * struct imx6_clk_gate - imx6 ccm clock gate
+ *
+ * @off:   ccm gate offset
+ * @bit:   ccm gate bit
+ */
+struct imx6_clk_gate {
+   u16 off;
+   u32 bit;
+};
+
+#define GATE(_off, _bit) { \
+   .off = _off,\
+   .bit = _bit,\
+}
+
+/**
+ * struct imx6_clk_desc - imx6 clock control module descriptor
+ *
+ * @gates: ccm clock gates
+ */
+struct imx6_clk_desc {
+   const struct imx6_clk_gate *gates;
+};
+
+/**
+ * struct imx6_clk_priv - imx6 clock control module
+ *
+ * @base:  ccm base address
+ * @desc:  ccm descriptor
+ */
+struct imx6_clk_priv {
+   void *base;
+   const struct imx6_clk_desc *desc;
+};
+
+/**
+ * imx6_clk_probe - common imx6 clock probe
+ * @dev:   clock device
+ */
+int imx6_clk_probe(struct udevice *dev);
+
+extern struct clk_ops imx6_clk_ops;
+
 enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_PER_CLK,
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index a125c23a19..f81903dcf4 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -1,6 +1,6 @@
 config CLK_IMX
bool "Clock support for i.MX SoCs"
-   depends on CLK && ARCH_IMX8
+   depends on CLK && (ARCH_MX6 || ARCH_IMX8)
default y
help
  This enables support for common clock driver API on i.MX
@@ -8,6 +8,13 @@ config CLK_IMX
 
 if CLK_IMX
 
+config CLK_IMX6Q
+   bool "Clock driver for i.MX6QDL"
+   default MX6QDL
+   help
+ This enables common clock driver support for platforms based
+ on i.MX6 QDL SoC.
+
 config CLK_IMX8
bool "Clock support for i.MX8"
default ARCH_IMX8
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 5505ae52e2..a4cb2bbf3b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -2,4 +2,9 @@
 #
 # SPDX-License-Identifier: GPL-2.0
 
+ifdef CONFIG_ARCH_MX6
+obj-$(CONFIG_CLK_IMX) += clk-imx6-common.o
+endif
+
+obj-$(CONFIG_CLK_IMX6Q) += clk-imx6q.o
 obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
diff --git a/drivers/clk/imx/clk-imx6-common.c 
b/drivers/clk/imx/clk-imx6-common.c
new file mode 100644
index 00..1d38f51f7e
--- /dev/null
+++ b/drivers/clk/imx/clk-imx6-common.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Amarula Solutions.
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct imx6_clk_gate *priv_to_gate(struct imx6_clk_priv *priv,
+   unsigned long id)
+{
+   return >desc->gates[id];
+}
+
+static int imx6_set_gate(struct clk *clk, bool on)
+{
+   struct imx6_clk_priv *priv = dev_get_priv(clk->dev);
+   const struct imx6_clk_gate *gate = priv_to_gate(priv, clk->id);
+   u32 reg;
+
+   debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
+ clk->id, gate->off, ilog2(gate->bit));
+
+   reg = readl(priv->base + gate->off);
+   if (on)
+   reg |= gate->bit;
+   else
+   reg &= ~gate->bit;
+
+   writel(reg, priv->base + gate->off);
+
+   return 0;
+}
+
+static int imx6_clk_enable(struct clk *clk)
+{
+   return imx6_set_gate(clk, true);
+}
+
+static int imx6_clk_disable(struct clk *clk)
+{
+   return imx6_set_gate(clk, false);
+}
+
+struct clk_ops imx6_clk_ops = {
+   .enable = imx6_clk_enable,
+   .disable = imx6_clk_disable,
+};
+
+int imx6_clk_probe(struct udevice *dev)
+{
+   struct imx6_clk_priv *priv = dev_get_priv(dev);
+
+   priv->base = dev_read_addr_ptr(dev);
+   if (!priv->base)
+   return -ENOMEM;
+
+   priv->desc = (const struct imx6_clk_desc *)dev_get_driver_data(dev);
+   if (!priv->desc)
+   return -EINVAL;
+
+   return 0;
+}
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
new file mode 100644
index 00..8ec713298d

[U-Boot] [PATCH v2 01/10] clk: imx: Kconfig: Make CONFIG_CLK available for selection

[Jagan Teki]

Adjust the Kconfig to hide architecture and other internal configs
so-that generic CONFIG_CLK is available for selection.

This would make easy for configuration selections between SoC
families with in the same SoC and even more readable.

Cc: Peng Fan 
Signed-off-by: Jagan Teki 
---
 configs/imx8qxp_mek_defconfig |  2 +-
 drivers/clk/imx/Kconfig   | 15 +--
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index a94998b8b5..8ad7ef4c04 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -40,7 +40,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_IMX8=y
+CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_GPIO=y
 CONFIG_MXC_GPIO=y
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index a6fb58d6cf..a125c23a19 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -1,6 +1,17 @@
+config CLK_IMX
+   bool "Clock support for i.MX SoCs"
+   depends on CLK && ARCH_IMX8
+   default y
+   help
+ This enables support for common clock driver API on i.MX
+ SoCs.
+
+if CLK_IMX
+
 config CLK_IMX8
bool "Clock support for i.MX8"
-   depends on ARCH_IMX8
-   select CLK
+   default ARCH_IMX8
help
  This enables support clock driver for i.MX8 platforms.
+
+endif # CLK_IMX
-- 
2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH v2 00/10] clk: imx: Add i.MX6 CLK support

[Jagan Teki]

This is revised version of previous i.MX6 clock management [1]. 

The main difference between previous version is
- Group the i.MX6 ccm clocks into gates and tree instead of handling the 
  clocks in simple way using case statement.
- use gate clocks for enable/disable management.
- use tree clocks for get/set rate or parent traverse management.
- parent clock handling via clock type.
- traverse the parent clock using recursive functionlaity.

The main motive behind this tree framework is to make the clock tree 
management simple and useful for U-Boot requirements instead of garbing 
Linux clock management code.

We are trying to manage the Allwinner clocks with similar kind, so having 
this would really help i.MX6 as well.

Added simple names for clock macros, but will update it in future
version.

I have skipped ENET clocks from previous series, will add it in future
patches.

Changes for v2:
- changed framework patches.
- add support for imx6qdl and imx6ul boards
- add clock gates, tree.

[1] https://patchwork.ozlabs.org/cover/950964/

Any inputs?
Jagan.

Jagan Teki (10):
  clk: imx: Kconfig: Make CONFIG_CLK available for selection
  clk: imx: Add i.MX6Q clock driver
  clk: imx: Add i.MX6UL clock driver
  clk: Add clk_div_mask helper
  clk: imx: Add imx6q clock tree support
  clk: imx6: Add imx6ul clock tree support
  ARM: dts: i.MX6QDL: Add u-boot,dm-spl for clks
  ARM: dts: i.MX6UL: Add u-boot,dm-spl for clks
  configs: icore_mipi: Enable CLK
  ARM: imx6: Enable CLK for Engicam i.MX6UL boards

 arch/arm/dts/imx6qdl-u-boot.dtsi  |   4 +
 arch/arm/dts/imx6ul-u-boot.dtsi   |   4 +
 arch/arm/include/asm/arch-mx6/clock.h | 109 
 arch/arm/mach-imx/mx6/Kconfig |   2 +
 configs/imx6qdl_icore_mipi_defconfig  |   2 +
 configs/imx8qxp_mek_defconfig |   2 +-
 drivers/clk/imx/Kconfig   |  29 -
 drivers/clk/imx/Makefile  |   6 +
 drivers/clk/imx/clk-imx6-common.c | 172 ++
 drivers/clk/imx/clk-imx6q.c   | 109 
 drivers/clk/imx/clk-imx6ul.c  |  85 +
 include/clk-uclass.h  |   2 +
 12 files changed, 523 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/imx/clk-imx6-common.c
 create mode 100644 drivers/clk/imx/clk-imx6q.c
 create mode 100644 drivers/clk/imx/clk-imx6ul.c

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Re: [U-Boot] [PATCH 07/13 v3] arm: at91: Enable watchdog support

[Eugen.Hristev]

On 02.04.2019 11:57, Stefan Roese wrote:

> 
> This patch enables and starts the watchdog on the AT91 platform if
> configured. The WD timeout value is read in the AT91 WD device driver
> from the DT, using the "timeout-sec" DT property. If not provided in
> the DT, the default value of 2 seconds is used.
> 
> Signed-off-by: Stefan Roese 
> Cc: Heiko Schocher 
> Cc: Andreas Bießmann 
> Cc: Eugen Hristev 
> ---
> v3:
> - Move WDT struct and macros into arch header so that it can be used
>by the arch code to start the driver (timeout value)
> - This change now enables the use of the "timeout-sec" DT property
>to specifiy a board specific WD timeout value


Hi Stefan,

This breaks pm9261_defconfig

  AS  arch/arm/mach-at91/arm926ejs/lowlevel_init.o
./arch/arm/include/asm/arch/at91_wdt.h: Assembler messages:
./arch/arm/include/asm/arch/at91_wdt.h:50: Error: bad instruction 
`struct at91_wdt_priv {'
./arch/arm/include/asm/arch/at91_wdt.h:51: Error: bad instruction `void 
__iomem*regs'
./arch/arm/include/asm/arch/at91_wdt.h:52: Error: bad instruction `u32 
regval'
./arch/arm/include/asm/arch/at91_wdt.h:53: Error: bad instruction `u32 
timeout'
./arch/arm/include/asm/arch/at91_wdt.h:54: Error: junk at end of line, 
first unrecognized character is `}'
scripts/Makefile.build:314: recipe for target 
'arch/arm/mach-at91/arm926ejs/lowlevel_init.o' failed


> 
> v2:
> - Remove #ifdef to enable compilation also in SPL version
> 
>   arch/arm/mach-at91/clock.c | 48 ++
>   arch/arm/mach-at91/include/mach/at91_wdt.h | 10 +
>   drivers/watchdog/at91sam9_wdt.c| 10 -
>   3 files changed, 58 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
> index 64cbc3d1ed..1d3df2c09d 100644
> --- a/arch/arm/mach-at91/clock.c
> +++ b/arch/arm/mach-at91/clock.c
> @@ -5,12 +5,17 @@
>*/
>   
>   #include 
> +#include 
> +#include 
>   #include 
>   #include 
>   #include 
> +#include 
>   
>   #define EN_UPLL_TIMEOUT 500
>   
> +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
> +
>   void at91_periph_clk_enable(int id)
>   {
>   struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> @@ -118,3 +123,46 @@ void at91_pllicpr_init(u32 icpr)
>   
>   writel(icpr, >pllicpr);
>   }
> +
> +/* Called by macro WATCHDOG_RESET */
> +void watchdog_reset(void)
> +{
> + static ulong next_reset;
> + ulong now;
> +
> + if (!watchdog_dev)
> + return;
> +
> + now = get_timer(0);
> +
> + /* Do not reset the watchdog too often */
> + if (now > next_reset) {
> + next_reset = now + 1000;/* reset every 1000ms */
> + wdt_reset(watchdog_dev);
> + }
> +}
> +
> +int arch_early_init_r(void)
> +{
> + struct at91_wdt_priv *priv;
> +
> + /* Init watchdog */
> + if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
> + debug("Watchdog: Not found by seq!\n");
> + if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
> + puts("Watchdog: Not found!\n");
> + return 0;
> + }
> + }
> +
> + priv = dev_get_priv(watchdog_dev);
> + if (!priv) {
> + printf("Watchdog: priv not available!\n");
> + return 0;
> + }
> +
> + wdt_start(watchdog_dev, priv->timeout * 1000, 0);
> + printf("Watchdog: Started\n");
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h 
> b/arch/arm/mach-at91/include/mach/at91_wdt.h
> index cd2272367b..c977b090c8 100644
> --- a/arch/arm/mach-at91/include/mach/at91_wdt.h
> +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
> @@ -43,4 +43,14 @@ typedef struct at91_wdt {
>   #define AT91_WDT_MR_WDDBGHLT0x1000
>   #define AT91_WDT_MR_WDIDLEHLT   0x2000
>   
> +/* Hardware timeout in seconds */
> +#define WDT_MAX_TIMEOUT  16
> +#define WDT_DEFAULT_TIMEOUT  2
> +
> +struct at91_wdt_priv {
> + void __iomem *regs;
> + u32 regval;
> + u32 timeout;
> +};
> +
>   #endif
> diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
> index 1c71778bdc..793425c8d2 100644
> --- a/drivers/watchdog/at91sam9_wdt.c
> +++ b/drivers/watchdog/at91sam9_wdt.c
> @@ -31,16 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
>*/
>   #define WDT_SEC2TICKS(s)(((s) << 8) - 1)
>   
> -/* Hardware timeout in seconds */
> -#define WDT_MAX_TIMEOUT  16
> -#define WDT_DEFAULT_TIMEOUT  2
> -
> -struct at91_wdt_priv {
> - void __iomem *regs;
> - u32 regval;
> - u32 timeout;
> -};
> -
>   /*
>* Set the watchdog time interval in 1/256Hz (write-once)
>* Counter is 12 bit.
> 
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Re: [U-Boot] [PATCH] DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)

[Fabio Estevam]

Hi Lukasz,

On Mon, Apr 1, 2019 at 5:49 PM Lukasz Majewski  wrote:

> > We should probably use the same approach as in the kernel to avoid
> > regressions with old dtbs.
> >
> > In the kernel the GPIO polarity passed in the 'phy-reset-gpios'
> > property is ignored and it is assumed to be active low, unless
> > 'phy-reset-active-high' is passed.
>
> This may be a good solution.
>
> However, I do hope that this fix will be accepted to v2019.04 as it is
> necessary to have ETH working (and it is the only convenient way to
> update u-boot on this board).

Yes, agreed.
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[U-Boot] [PATCH 3/13 v4] serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL

[Stefan Roese]

This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.

Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.

This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
a different value if needed.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
v4:
- Restrict SPL_UART_CLOCK on SPL && !SPL_CLK
- Provide default value for non AT91 platforms to not break the
  build
- Fix typo in Kconfig text

v3:
- Depend fixed clock atmel_serial_enable_clk() function also on
  !CONFIG_SPL_CLK so that board with full clocj support in SPL
  can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead
  of the hardcoded value

v2:
- Reword patch subject and commit text to make it more clear, that
  this change only affects ports with SPL and DM_SERIAL enabled
  
 drivers/serial/Kconfig   | 10 ++
 drivers/serial/atmel_usart.c | 12 
 2 files changed, 22 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 887cd687c0..79fb397cf9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -508,6 +508,16 @@ config ATMEL_USART
  configured in the device tree, and input clock frequency can
  be got from the clk node.
 
+config SPL_UART_CLOCK
+   int "SPL fixed UART input clock"
+   depends on SPL && !SPL_CLK
+   default 132096000 if ARCH_AT91
+   default 0
+   help
+ Provide a fixed clock value as input to the UART controller. This
+ might be needed on platforms which can't enable CONFIG_SPL_CLK
+ because of SPL image size restrictions.
+
 config BCM283X_MU_SERIAL
bool "Support for BCM283x Mini-UART"
depends on DM_SERIAL && ARCH_BCM283X
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index aa8cdff840..c450a4e08a 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = {
.setbrg = atmel_serial_setbrg,
 };
 
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
+static int atmel_serial_enable_clk(struct udevice *dev)
+{
+   struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+   /* Use fixed clock value in SPL */
+   priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
+
+   return 0;
+}
+#else
 static int atmel_serial_enable_clk(struct udevice *dev)
 {
struct atmel_serial_priv *priv = dev_get_priv(dev);
@@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
 
return 0;
 }
+#endif
 
 static int atmel_serial_probe(struct udevice *dev)
 {
-- 
2.21.0

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Re: [U-Boot] [PATCH 06/13 v3] arm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUT

[Eugen.Hristev]

On 02.04.2019 11:57, Stefan Roese wrote:
> External E-Mail
> 
> 
> This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any
> more. The WD timeout value can be provided via the "timeout-sec" DT
> property. If not provided this way, the default value of 2 seconds will
> be used.
> 
> Signed-off-by: Stefan Roese 
> Cc: Heiko Schocher 
> Cc: Andreas Bießmann 
> Cc: Eugen Hristev 
> ---
> v3:
> - New patch
> 
>   README  | 3 ---
>   configs/smartweb_defconfig  | 1 -
>   configs/taurus_defconfig| 1 -
>   drivers/watchdog/Kconfig| 4 
>   drivers/watchdog/at91sam9_wdt.c | 2 --
>   5 files changed, 11 deletions(-)
> 
> diff --git a/README b/README
> index c9a20db34f..a514f48cae 100644
> --- a/README
> +++ b/README
> @@ -767,9 +767,6 @@ The following options need to be configured:
>   SoC, then define this variable and provide board
>   specific code for the "hw_watchdog_reset" function.
>   
> - CONFIG_AT91_HW_WDT_TIMEOUT
> - specify the timeout in seconds. default 2 seconds.
> -
>   - Real-Time Clock:
>   
>   When CONFIG_CMD_DATE is selected, the type of the RTC
> diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
> index 7c7220afc8..807a569121 100644
> --- a/configs/smartweb_defconfig
> +++ b/configs/smartweb_defconfig
> @@ -59,6 +59,5 @@ CONFIG_USB_ETHER_ASIX=y
>   CONFIG_USB_ETHER_MCS7830=y
>   CONFIG_WDT=y
>   CONFIG_WDT_AT91=y
> -CONFIG_AT91_HW_WDT_TIMEOUT=y
>   CONFIG_SPL_TINY_MEMSET=y
>   # CONFIG_EFI_LOADER is not set
> diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
> index 022b0b6da1..d69f4895ef 100644
> --- a/configs/taurus_defconfig
> +++ b/configs/taurus_defconfig
> @@ -62,5 +62,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
>   CONFIG_USB_GADGET_DOWNLOAD=y
>   CONFIG_WDT=y
>   CONFIG_WDT_AT91=y
> -CONFIG_AT91_HW_WDT_TIMEOUT=y
>   CONFIG_USE_TINY_PRINTF=y
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 115fc4551f..34e78beb2a 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -139,10 +139,6 @@ config WDT_AT91
>  Select this to enable Microchip watchdog timer, which can be found on
>  some AT91 devices.
>   
> -config AT91_HW_WDT_TIMEOUT
> - bool "AT91 watchdog timeout specified"
> - depends on WDT_AT91
> -
>   config WDT_MT7621
>   bool "MediaTek MT7621 watchdog timer support"
>   depends on WDT && ARCH_MT7620
> diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
> index b0a3b4ed58..1c71778bdc 100644
> --- a/drivers/watchdog/at91sam9_wdt.c
> +++ b/drivers/watchdog/at91sam9_wdt.c
> @@ -117,11 +117,9 @@ static int at91_wdt_probe(struct udevice *dev)
>   if (!priv->regs)
>   return -EINVAL;
>   
> -#ifdef CONFIG_AT91_HW_WDT_TIMEOUT
>   priv->timeout = dev_read_u32_default(dev, "timeout-sec",
>WDT_DEFAULT_TIMEOUT);
>   debug("%s: timeout %d", __func__, priv->timeout);
> -#endif
>   
>   debug("%s: Probing wdt%u\n", __func__, dev->seq);
>   
> 

Hi Stefan,

This breaks picosam9g45_defconfig

include/dm/read.h:535: undefined reference to `ofnode_read_u32_default'
arm-linux-gnueabihf-ld.bfd: BFD (Linaro_Binutils-2018.05) 
2.28.2.20170706 assertion fail 
/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-linux-gnueabihf/snapshots/binutils-gdb.git~users~linaro~binutils-2_28-branch/bfd/elf32-arm.c:9514
Makefile:1497: recipe for target 'u-boot' failed

gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision 
d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)

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Re: [U-Boot] [PATCH] doc: Fix outdated ohci board hook documentation

[Marek Vasut]

On 4/2/19 9:32 AM, Krzysztof Kozlowski wrote:
> The ohci driver calls board_usb_init(), not usb_board_init().
> 
> Signed-off-by: Krzysztof Kozlowski 
> ---
>  doc/README.generic_usb_ohci | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci
> index 61300c35758a..65b0896c7fd2 100644
> --- a/doc/README.generic_usb_ohci
> +++ b/doc/README.generic_usb_ohci
> @@ -13,7 +13,7 @@ Configuration options
>  
>   CONFIG_SYS_USB_OHCI_BOARD_INIT: call the board dependant hooks:
>  
> -   - extern int usb_board_init(void);
> +   - extern int board_usb_init(void);
> - extern int usb_board_stop(void);
> - extern int usb_cpu_init_fail(void);
>  
> 
Applied to usb/master, thanks.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 03/13 v3] serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL

[Eugen.Hristev]

On 02.04.2019 13:40, Stefan Roese wrote:
> External E-Mail
> 
> 
> Hi Eugen,
> 
> On 02.04.19 12:12, eugen.hris...@microchip.com wrote:
>>
>>
>> On 02.04.2019 11:57, Stefan Roese wrote:
>>
>>> This patch adds an alterative SPL version of atmel_serial_enable_clk().
>>> This enables the usage of this driver without full clock support (in
>>> drivers and DT nodes). This saves some space in the SPL image.
>>>
>>> Please note that this fixed clock support is only added to the SPL code
>>> in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
>>> should not be affected.
>>>
>>> This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
>>> input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
>>> a different value if needed.
>>>
>>> Signed-off-by: Stefan Roese 
>>> Cc: Heiko Schocher 
>>> Cc: Andreas Bießmann 
>>> Cc: Eugen Hristev 
>>> Reviewed-by: Heiko Schocher 
>>> Tested on the taurus board:
>>> Tested-by: Heiko Schocher 
>>> ---
>>> v3:
>>> - Depend fixed clock atmel_serial_enable_clk() function also on
>>>     !CONFIG_SPL_CLK so that board with full clocj support in SPL
>>>     can still use the normal function here
>>> - Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead
>>>     of the hardcoded value
>>>
>>> v2:
>>> - Reword patch subject and commit text to make it more clear, that
>>>     this change only affects ports with SPL and DM_SERIAL enabled
>>>    drivers/serial/Kconfig   |  9 +
>>>    drivers/serial/atmel_usart.c | 12 
>>>    2 files changed, 21 insertions(+)
>>>
>>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>>> index 887cd687c0..d6bf8309d3 100644
>>> --- a/drivers/serial/Kconfig
>>> +++ b/drivers/serial/Kconfig
>>> @@ -508,6 +508,15 @@ config ATMEL_USART
>>>  configured in the device tree, and input clock frequency can
>>>  be got from the clk node.
>>> +config SPL_UART_CLOCK
>>> +    int "SPL fixed UART input clock"
>>> +    depends on SPL
>>> +    default 132096000 if ARCH_AT91
>>
>> Hi Stefan,
>>
>> This doesn't look good. This has to be unset for the platforms that do
>> not specifically set it.
>>
>> For example, when I build the sama5d2_xplained_mmc_defconfig, I look in
>> .config and :
>>
>> CONFIG_SPL_UART_CLOCK=132096000
>>
>> This may be unused, but it's confusing
> 
> Okay, I agree.
> 
>> Can you make this default unset and then specifically set it in the
>> boards that need it ? ( the specific defconfig )
>>
>> And if you have a mutual exclusion with CONFIG_SPL_CLK can we make it
>> somehow ? (in a menu or choice..., either old behavior or fixed uart 
>> clock)
> 
> How about this version?
> 
> config SPL_UART_CLOCK
>  int "SPL fixed UART input clock"
>  depends on SPL && !SPL_CLK
>  help
>    Provide a fixed clock value as input to the UART controller. This
>    might be needed on platforms which can't enable CONFIG_SPL_CLK
>    because of SPL image size restirctions.

Looks much better. Typo on restrictirions

Can also add some default then, to not break build in case someone 
disables SPL_CLK but does not set SPL_UART_CLOCK ?

Thanks !

> 
> Thanks,
> Stefan
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Re: [U-Boot] [PATCH] watchdog: Move watchdog_dev to data section (BSS may not be cleared)

[Stefan Roese]

On 02.04.19 12:30, Michal Simek wrote:

On 02. 04. 19 11:57, Stefan Roese wrote:

This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Tom Rini 
Cc: Michal Simek 
Cc: "Marek Behún" 
Cc: Daniel Schwierzeck 
---
  arch/mips/mach-mt7620/cpu.c  | 2 +-
  board/CZ.NIC/turris_mox/turris_mox.c | 2 +-
  board/CZ.NIC/turris_omnia/turris_omnia.c | 2 +-
  board/xilinx/microblaze-generic/microblaze-generic.c | 2 +-
  board/xilinx/zynq/board.c| 2 +-
  board/xilinx/zynqmp/zynqmp.c | 2 +-
  6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c
index 9e0ca716f7..fe74f26a54 100644
--- a/arch/mips/mach-mt7620/cpu.c
+++ b/arch/mips/mach-mt7620/cpu.c
@@ -70,7 +70,7 @@ int print_cpuinfo(void)
  }
  
  #ifdef CONFIG_WATCHDOG

-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
  
  /* Called by macro WATCHDOG_RESET */

  void watchdog_reset(void)
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c 
b/board/CZ.NIC/turris_mox/turris_mox.c
index 65d50a92dd..96cb9c7e5c 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -120,7 +120,7 @@ int board_fix_fdt(void *blob)
  #endif
  
  #ifdef CONFIG_WDT_ARMADA_37XX

-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
  
  void watchdog_reset(void)

  {
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c 
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 1f7650cb36..c7f6479a0c 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -365,7 +365,7 @@ static bool disable_mcu_watchdog(void)
  #endif
  
  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)

-static struct udevice *watchdog_dev = NULL;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
  #endif
  
  int board_init(void)

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c 
b/board/xilinx/microblaze-generic/microblaze-generic.c
index c946ec3208..28c9efa3a2 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -25,7 +25,7 @@
  DECLARE_GLOBAL_DATA_PTR;
  
  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)

-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
  #endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
  
  ulong ram_base;

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index b4b84df576..7c8c32a1c7 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -19,7 +19,7 @@
  DECLARE_GLOBAL_DATA_PTR;
  
  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)

-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
  #endif
  
  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 5e1d2116bc..1c2aa99b97 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -25,7 +25,7 @@
  DECLARE_GLOBAL_DATA_PTR;
  
  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)

-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
  #endif
  
  #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \




If you want to do it for all then please remove the same from this file

http://git.denx.de/?p=u-boot.git;a=commitdiff;h=4490e013ee4f2a4b9b6ca9224221fed2788b6940

+#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
+   /* bss is not cleared at time when watchdog_reset() is called */
+   watchdog_dev = NULL;
+#endif


And also from zynq file.
board/xilinx/zynq/board.c


Thanks for spotting. I'll remove it in v2.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 03/13 v3] serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL

[Stefan Roese]

Hi Eugen,

On 02.04.19 12:12, eugen.hris...@microchip.com wrote:



On 02.04.2019 11:57, Stefan Roese wrote:


This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.

Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.

This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
a different value if needed.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on
!CONFIG_SPL_CLK so that board with full clocj support in SPL
can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead
of the hardcoded value

v2:
- Reword patch subject and commit text to make it more clear, that
this change only affects ports with SPL and DM_SERIAL enabled

   drivers/serial/Kconfig   |  9 +

   drivers/serial/atmel_usart.c | 12 
   2 files changed, 21 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 887cd687c0..d6bf8309d3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -508,6 +508,15 @@ config ATMEL_USART
  configured in the device tree, and input clock frequency can
  be got from the clk node.
   
+config SPL_UART_CLOCK

+   int "SPL fixed UART input clock"
+   depends on SPL
+   default 132096000 if ARCH_AT91


Hi Stefan,

This doesn't look good. This has to be unset for the platforms that do
not specifically set it.

For example, when I build the sama5d2_xplained_mmc_defconfig, I look in
.config and :

CONFIG_SPL_UART_CLOCK=132096000

This may be unused, but it's confusing


Okay, I agree.
 

Can you make this default unset and then specifically set it in the
boards that need it ? ( the specific defconfig )

And if you have a mutual exclusion with CONFIG_SPL_CLK can we make it
somehow ? (in a menu or choice..., either old behavior or fixed uart clock)


How about this version?

config SPL_UART_CLOCK
int "SPL fixed UART input clock"
depends on SPL && !SPL_CLK
help
  Provide a fixed clock value as input to the UART controller. This
  might be needed on platforms which can't enable CONFIG_SPL_CLK
  because of SPL image size restirctions.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] watchdog: Move watchdog_dev to data section (BSS may not be cleared)

[Michal Simek]

On 02. 04. 19 11:57, Stefan Roese wrote:
> This patch moves all instances of static "watchdog_dev" declarations to
> the "data" section. This may be needed, as the BSS may not be cleared
> in the early U-Boot phase, where watchdog_reset() is already beeing
> called. This may result in incorrect pointer access, as the check to
> "!watchdog_dev" in watchdog_reset() may not be true and the function
> may continue to run.
> 
> Signed-off-by: Stefan Roese 
> Cc: Heiko Schocher 
> Cc: Tom Rini 
> Cc: Michal Simek 
> Cc: "Marek Behún" 
> Cc: Daniel Schwierzeck 
> ---
>  arch/mips/mach-mt7620/cpu.c  | 2 +-
>  board/CZ.NIC/turris_mox/turris_mox.c | 2 +-
>  board/CZ.NIC/turris_omnia/turris_omnia.c | 2 +-
>  board/xilinx/microblaze-generic/microblaze-generic.c | 2 +-
>  board/xilinx/zynq/board.c| 2 +-
>  board/xilinx/zynqmp/zynqmp.c | 2 +-
>  6 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c
> index 9e0ca716f7..fe74f26a54 100644
> --- a/arch/mips/mach-mt7620/cpu.c
> +++ b/arch/mips/mach-mt7620/cpu.c
> @@ -70,7 +70,7 @@ int print_cpuinfo(void)
>  }
>  
>  #ifdef CONFIG_WATCHDOG
> -static struct udevice *watchdog_dev;
> +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
>  
>  /* Called by macro WATCHDOG_RESET */
>  void watchdog_reset(void)
> diff --git a/board/CZ.NIC/turris_mox/turris_mox.c 
> b/board/CZ.NIC/turris_mox/turris_mox.c
> index 65d50a92dd..96cb9c7e5c 100644
> --- a/board/CZ.NIC/turris_mox/turris_mox.c
> +++ b/board/CZ.NIC/turris_mox/turris_mox.c
> @@ -120,7 +120,7 @@ int board_fix_fdt(void *blob)
>  #endif
>  
>  #ifdef CONFIG_WDT_ARMADA_37XX
> -static struct udevice *watchdog_dev;
> +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
>  
>  void watchdog_reset(void)
>  {
> diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c 
> b/board/CZ.NIC/turris_omnia/turris_omnia.c
> index 1f7650cb36..c7f6479a0c 100644
> --- a/board/CZ.NIC/turris_omnia/turris_omnia.c
> +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
> @@ -365,7 +365,7 @@ static bool disable_mcu_watchdog(void)
>  #endif
>  
>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
> -static struct udevice *watchdog_dev = NULL;
> +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
>  #endif
>  
>  int board_init(void)
> diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c 
> b/board/xilinx/microblaze-generic/microblaze-generic.c
> index c946ec3208..28c9efa3a2 100644
> --- a/board/xilinx/microblaze-generic/microblaze-generic.c
> +++ b/board/xilinx/microblaze-generic/microblaze-generic.c
> @@ -25,7 +25,7 @@
>  DECLARE_GLOBAL_DATA_PTR;
>  
>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
> -static struct udevice *watchdog_dev;
> +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
>  #endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
>  
>  ulong ram_base;
> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
> index b4b84df576..7c8c32a1c7 100644
> --- a/board/xilinx/zynq/board.c
> +++ b/board/xilinx/zynq/board.c
> @@ -19,7 +19,7 @@
>  DECLARE_GLOBAL_DATA_PTR;
>  
>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
> -static struct udevice *watchdog_dev;
> +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
>  #endif
>  
>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index 5e1d2116bc..1c2aa99b97 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -25,7 +25,7 @@
>  DECLARE_GLOBAL_DATA_PTR;
>  
>  #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
> -static struct udevice *watchdog_dev;
> +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
>  #endif
>  
>  #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
> 

If you want to do it for all then please remove the same from this file

http://git.denx.de/?p=u-boot.git;a=commitdiff;h=4490e013ee4f2a4b9b6ca9224221fed2788b6940

+#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
+   /* bss is not cleared at time when watchdog_reset() is called */
+   watchdog_dev = NULL;
+#endif


And also from zynq file.
board/xilinx/zynq/board.c

Thanks,
Michal
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Re: [U-Boot] [PATCH 03/13 v3] serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL

[Eugen.Hristev]

On 02.04.2019 11:57, Stefan Roese wrote:

> This patch adds an alterative SPL version of atmel_serial_enable_clk().
> This enables the usage of this driver without full clock support (in
> drivers and DT nodes). This saves some space in the SPL image.
> 
> Please note that this fixed clock support is only added to the SPL code
> in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
> should not be affected.
> 
> This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
> input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
> a different value if needed.
> 
> Signed-off-by: Stefan Roese 
> Cc: Heiko Schocher 
> Cc: Andreas Bießmann 
> Cc: Eugen Hristev 
> Reviewed-by: Heiko Schocher 
> Tested on the taurus board:
> Tested-by: Heiko Schocher 
> ---
> v3:
> - Depend fixed clock atmel_serial_enable_clk() function also on
>!CONFIG_SPL_CLK so that board with full clocj support in SPL
>can still use the normal function here
> - Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead
>of the hardcoded value
> 
> v2:
> - Reword patch subject and commit text to make it more clear, that
>this change only affects ports with SPL and DM_SERIAL enabled
>
>   drivers/serial/Kconfig   |  9 +
>   drivers/serial/atmel_usart.c | 12 
>   2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 887cd687c0..d6bf8309d3 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -508,6 +508,15 @@ config ATMEL_USART
> configured in the device tree, and input clock frequency can
> be got from the clk node.
>   
> +config SPL_UART_CLOCK
> + int "SPL fixed UART input clock"
> + depends on SPL
> + default 132096000 if ARCH_AT91

Hi Stefan,

This doesn't look good. This has to be unset for the platforms that do 
not specifically set it.

For example, when I build the sama5d2_xplained_mmc_defconfig, I look in 
.config and :

CONFIG_SPL_UART_CLOCK=132096000

This may be unused, but it's confusing

Can you make this default unset and then specifically set it in the 
boards that need it ? ( the specific defconfig )

And if you have a mutual exclusion with CONFIG_SPL_CLK can we make it 
somehow ? (in a menu or choice..., either old behavior or fixed uart clock)

Does this make sense?

Thanks

> + help
> +   Provide a fixed clock value as input to the UART controller. This
> +   might be needed on platforms which can't enable CONFIG_SPL_CLK
> +   because of SPL image size restirctions.
> +
>   config BCM283X_MU_SERIAL
>   bool "Support for BCM283x Mini-UART"
>   depends on DM_SERIAL && ARCH_BCM283X
> diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
> index aa8cdff840..c450a4e08a 100644
> --- a/drivers/serial/atmel_usart.c
> +++ b/drivers/serial/atmel_usart.c
> @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = {
>   .setbrg = atmel_serial_setbrg,
>   };
>   
> +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
> +static int atmel_serial_enable_clk(struct udevice *dev)
> +{
> + struct atmel_serial_priv *priv = dev_get_priv(dev);
> +
> + /* Use fixed clock value in SPL */
> + priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
> +
> + return 0;
> +}
> +#else
>   static int atmel_serial_enable_clk(struct udevice *dev)
>   {
>   struct atmel_serial_priv *priv = dev_get_priv(dev);
> @@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
>   
>   return 0;
>   }
> +#endif
>   
>   static int atmel_serial_probe(struct udevice *dev)
>   {
> 
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[U-Boot] [PATCH] watchdog: Move watchdog_dev to data section (BSS may not be cleared)

[Stefan Roese]

This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Tom Rini 
Cc: Michal Simek 
Cc: "Marek Behún" 
Cc: Daniel Schwierzeck 
---
 arch/mips/mach-mt7620/cpu.c  | 2 +-
 board/CZ.NIC/turris_mox/turris_mox.c | 2 +-
 board/CZ.NIC/turris_omnia/turris_omnia.c | 2 +-
 board/xilinx/microblaze-generic/microblaze-generic.c | 2 +-
 board/xilinx/zynq/board.c| 2 +-
 board/xilinx/zynqmp/zynqmp.c | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c
index 9e0ca716f7..fe74f26a54 100644
--- a/arch/mips/mach-mt7620/cpu.c
+++ b/arch/mips/mach-mt7620/cpu.c
@@ -70,7 +70,7 @@ int print_cpuinfo(void)
 }
 
 #ifdef CONFIG_WATCHDOG
-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
 
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c 
b/board/CZ.NIC/turris_mox/turris_mox.c
index 65d50a92dd..96cb9c7e5c 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -120,7 +120,7 @@ int board_fix_fdt(void *blob)
 #endif
 
 #ifdef CONFIG_WDT_ARMADA_37XX
-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
 
 void watchdog_reset(void)
 {
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c 
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 1f7650cb36..c7f6479a0c 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -365,7 +365,7 @@ static bool disable_mcu_watchdog(void)
 #endif
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
-static struct udevice *watchdog_dev = NULL;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
 #endif
 
 int board_init(void)
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c 
b/board/xilinx/microblaze-generic/microblaze-generic.c
index c946ec3208..28c9efa3a2 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -25,7 +25,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
 #endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
 
 ulong ram_base;
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index b4b84df576..7c8c32a1c7 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -19,7 +19,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
 #endif
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 5e1d2116bc..1c2aa99b97 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -25,7 +25,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
-static struct udevice *watchdog_dev;
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
 #endif
 
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-- 
2.21.0

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[U-Boot] [PATCH 07/13 v3] arm: at91: Enable watchdog support

[Stefan Roese]

This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
v3:
- Move WDT struct and macros into arch header so that it can be used
  by the arch code to start the driver (timeout value)
- This change now enables the use of the "timeout-sec" DT property
  to specifiy a board specific WD timeout value

v2:
- Remove #ifdef to enable compilation also in SPL version

 arch/arm/mach-at91/clock.c | 48 ++
 arch/arm/mach-at91/include/mach/at91_wdt.h | 10 +
 drivers/watchdog/at91sam9_wdt.c| 10 -
 3 files changed, 58 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 64cbc3d1ed..1d3df2c09d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -5,12 +5,17 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 #define EN_UPLL_TIMEOUT500
 
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
+
 void at91_periph_clk_enable(int id)
 {
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -118,3 +123,46 @@ void at91_pllicpr_init(u32 icpr)
 
writel(icpr, >pllicpr);
 }
+
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+   static ulong next_reset;
+   ulong now;
+
+   if (!watchdog_dev)
+   return;
+
+   now = get_timer(0);
+
+   /* Do not reset the watchdog too often */
+   if (now > next_reset) {
+   next_reset = now + 1000;/* reset every 1000ms */
+   wdt_reset(watchdog_dev);
+   }
+}
+
+int arch_early_init_r(void)
+{
+   struct at91_wdt_priv *priv;
+
+   /* Init watchdog */
+   if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
+   debug("Watchdog: Not found by seq!\n");
+   if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
+   puts("Watchdog: Not found!\n");
+   return 0;
+   }
+   }
+
+   priv = dev_get_priv(watchdog_dev);
+   if (!priv) {
+   printf("Watchdog: priv not available!\n");
+   return 0;
+   }
+
+   wdt_start(watchdog_dev, priv->timeout * 1000, 0);
+   printf("Watchdog: Started\n");
+
+   return 0;
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h 
b/arch/arm/mach-at91/include/mach/at91_wdt.h
index cd2272367b..c977b090c8 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -43,4 +43,14 @@ typedef struct at91_wdt {
 #define AT91_WDT_MR_WDDBGHLT   0x1000
 #define AT91_WDT_MR_WDIDLEHLT  0x2000
 
+/* Hardware timeout in seconds */
+#define WDT_MAX_TIMEOUT16
+#define WDT_DEFAULT_TIMEOUT2
+
+struct at91_wdt_priv {
+   void __iomem *regs;
+   u32 regval;
+   u32 timeout;
+};
+
 #endif
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 1c71778bdc..793425c8d2 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -31,16 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define WDT_SEC2TICKS(s)   (((s) << 8) - 1)
 
-/* Hardware timeout in seconds */
-#define WDT_MAX_TIMEOUT16
-#define WDT_DEFAULT_TIMEOUT2
-
-struct at91_wdt_priv {
-   void __iomem *regs;
-   u32 regval;
-   u32 timeout;
-};
-
 /*
  * Set the watchdog time interval in 1/256Hz (write-once)
  * Counter is 12 bit.
-- 
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[U-Boot] [PATCH 12/13 v3] arm: at91: at91sam9x5.dtsi: Add watchdog handle

[Stefan Roese]

This makes it possible to reference the watchdog DT node via ""
from board dts files.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
---
v3:
- No change

v2:
- New patch

 arch/arm/dts/at91sam9x5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi
index ea319cc18b..bd4abe00d6 100644
--- a/arch/arm/dts/at91sam9x5.dtsi
+++ b/arch/arm/dts/at91sam9x5.dtsi
@@ -1180,7 +1180,7 @@
};
};
 
-   watchdog@fe40 {
+   watchdog: watchdog@fe40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
-- 
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[U-Boot] [PATCH 06/13 v3] arm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUT

[Stefan Roese]

This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any
more. The WD timeout value can be provided via the "timeout-sec" DT
property. If not provided this way, the default value of 2 seconds will
be used.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
---
v3:
- New patch

 README  | 3 ---
 configs/smartweb_defconfig  | 1 -
 configs/taurus_defconfig| 1 -
 drivers/watchdog/Kconfig| 4 
 drivers/watchdog/at91sam9_wdt.c | 2 --
 5 files changed, 11 deletions(-)

diff --git a/README b/README
index c9a20db34f..a514f48cae 100644
--- a/README
+++ b/README
@@ -767,9 +767,6 @@ The following options need to be configured:
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
 
-   CONFIG_AT91_HW_WDT_TIMEOUT
-   specify the timeout in seconds. default 2 seconds.
-
 - Real-Time Clock:
 
When CONFIG_CMD_DATE is selected, the type of the RTC
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 7c7220afc8..807a569121 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -59,6 +59,5 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
-CONFIG_AT91_HW_WDT_TIMEOUT=y
 CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 022b0b6da1..d69f4895ef 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -62,5 +62,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
-CONFIG_AT91_HW_WDT_TIMEOUT=y
 CONFIG_USE_TINY_PRINTF=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 115fc4551f..34e78beb2a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -139,10 +139,6 @@ config WDT_AT91
   Select this to enable Microchip watchdog timer, which can be found on
   some AT91 devices.
 
-config AT91_HW_WDT_TIMEOUT
-   bool "AT91 watchdog timeout specified"
-   depends on WDT_AT91
-
 config WDT_MT7621
bool "MediaTek MT7621 watchdog timer support"
depends on WDT && ARCH_MT7620
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index b0a3b4ed58..1c71778bdc 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -117,11 +117,9 @@ static int at91_wdt_probe(struct udevice *dev)
if (!priv->regs)
return -EINVAL;
 
-#ifdef CONFIG_AT91_HW_WDT_TIMEOUT
priv->timeout = dev_read_u32_default(dev, "timeout-sec",
 WDT_DEFAULT_TIMEOUT);
debug("%s: timeout %d", __func__, priv->timeout);
-#endif
 
debug("%s: Probing wdt%u\n", __func__, dev->seq);
 
-- 
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[U-Boot] [PATCH 09/13 v3] Makefile.spl: Move generated AT91SAM NAND image boot.bin to spl directory

[Stefan Roese]

This patch moves the AT91SAM NAND booting SPL image "boot.bin" which
includes the ECC values from the root directory into the spl directory,
where all SPL related images are located.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 scripts/Makefile.spl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 54b160d72b..56dbbe127b 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -179,10 +179,10 @@ MKIMAGEFLAGS_boot.bin = -T atmelimage
 ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y)
 MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params)
 
-boot.bin: $(obj)/../tools/atmel_pmecc_params
+$(obj)/boot.bin: $(obj)/../tools/atmel_pmecc_params
 endif
 
-boot.bin: $(obj)/u-boot-spl.bin FORCE
+$(obj)/boot.bin: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
 else
 ifdef CONFIG_ARCH_ZYNQ
@@ -225,7 +225,7 @@ endif
 endif
 
 ifeq ($(CONFIG_SYS_SOC),"at91")
-ALL-y  += boot.bin
+ALL-y  += $(obj)/boot.bin
 endif
 
 ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin
-- 
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[U-Boot] [PATCH 03/13 v3] serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL

[Stefan Roese]

This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.

Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.

This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
a different value if needed.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on
  !CONFIG_SPL_CLK so that board with full clocj support in SPL
  can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead
  of the hardcoded value

v2:
- Reword patch subject and commit text to make it more clear, that
  this change only affects ports with SPL and DM_SERIAL enabled
  
 drivers/serial/Kconfig   |  9 +
 drivers/serial/atmel_usart.c | 12 
 2 files changed, 21 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 887cd687c0..d6bf8309d3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -508,6 +508,15 @@ config ATMEL_USART
  configured in the device tree, and input clock frequency can
  be got from the clk node.
 
+config SPL_UART_CLOCK
+   int "SPL fixed UART input clock"
+   depends on SPL
+   default 132096000 if ARCH_AT91
+   help
+ Provide a fixed clock value as input to the UART controller. This
+ might be needed on platforms which can't enable CONFIG_SPL_CLK
+ because of SPL image size restirctions.
+
 config BCM283X_MU_SERIAL
bool "Support for BCM283x Mini-UART"
depends on DM_SERIAL && ARCH_BCM283X
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index aa8cdff840..c450a4e08a 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = {
.setbrg = atmel_serial_setbrg,
 };
 
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
+static int atmel_serial_enable_clk(struct udevice *dev)
+{
+   struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+   /* Use fixed clock value in SPL */
+   priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
+
+   return 0;
+}
+#else
 static int atmel_serial_enable_clk(struct udevice *dev)
 {
struct atmel_serial_priv *priv = dev_get_priv(dev);
@@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
 
return 0;
 }
+#endif
 
 static int atmel_serial_probe(struct udevice *dev)
 {
-- 
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[U-Boot] [PATCH 05/13 v3] watchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start()

[Stefan Roese]

This patch fixes the timer register setup in at91_wdt_start() to
correctly configure the register again. The input timeout value is
now in milli-seconds instead of seconds with the new watchdog API.
Make sure to take this into account and only use a max timeout
value of 16 seconds as appropriate for this SoC.

Also the check against a lower timeout value than 0 is removed. This
check makes no sense, as the timeout value is unsigned.

Signed-off-by: Stefan Roese 
Reported-by: Heiko Schocher 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 drivers/watchdog/at91sam9_wdt.c | 26 ++
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 13f8772e41..b0a3b4ed58 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -31,27 +32,30 @@ DECLARE_GLOBAL_DATA_PTR;
 #define WDT_SEC2TICKS(s)   (((s) << 8) - 1)
 
 /* Hardware timeout in seconds */
-#define WDT_MAX_TIMEOUT 16
-#define WDT_MIN_TIMEOUT 0
-#define WDT_DEFAULT_TIMEOUT 2
+#define WDT_MAX_TIMEOUT16
+#define WDT_DEFAULT_TIMEOUT2
 
 struct at91_wdt_priv {
void __iomem *regs;
-   u32 regval;
-   u32 timeout;
+   u32 regval;
+   u32 timeout;
 };
 
 /*
  * Set the watchdog time interval in 1/256Hz (write-once)
  * Counter is 12 bit.
  */
-static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags)
+static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
 {
struct at91_wdt_priv *priv = dev_get_priv(dev);
-   u32 timeout = WDT_SEC2TICKS(timeout_s);
+   u64 timeout;
+   u32 ticks;
 
-   if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT)
-   timeout = priv->timeout;
+   /* Calculate timeout in seconds and the resulting ticks */
+   timeout = timeout_ms;
+   do_div(timeout, 1000);
+   timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT);
+   ticks = WDT_SEC2TICKS(timeout);
 
/* Check if disabled */
if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) {
@@ -65,12 +69,10 @@ static int at91_wdt_start(struct udevice *dev, u64 
timeout_s, ulong flags)
 * Since WDV is a 12-bit counter, the maximum period is
 * 4096 / 256 = 16 seconds.
 */
-
priv->regval = AT91_WDT_MR_WDRSTEN  /* causes watchdog reset */
| AT91_WDT_MR_WDDBGHLT  /* disabled in debug mode */
| AT91_WDT_MR_WDD(0xfff)/* restart at any time */
-   | AT91_WDT_MR_WDV(timeout); /* timer value */
-
+   | AT91_WDT_MR_WDV(ticks);   /* timer value */
writel(priv->regval, priv->regs + AT91_WDT_MR);
 
return 0;
-- 
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[U-Boot] [PATCH 10/13 v3] Makefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binary

[Stefan Roese]

This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that
shall be used to generate the combined SPL + U-Boot image. The default
value is the current value "spl/u-boot-spl.bin".

This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets
which use SPL NAND support (boot from NAND). For these build targets the
combined image "u-boot-with-spl.bin" is now automatically generated and
can be programmed into NAND as one single image (vs. SPL image and U-Boot
as 2 separate images).

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 Kconfig  | 10 ++
 Makefile |  4 +++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index 305b265ed7..7c2b86f1f3 100644
--- a/Kconfig
+++ b/Kconfig
@@ -224,6 +224,15 @@ config BUILD_ROM
  which are not shipped in the U-Boot source tree.
  Please, see doc/README.x86 for details.
 
+config SPL_IMAGE
+   string "SPL image filename that is generated"
+   default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
+   default "spl/u-boot-spl.bin"
+   help
+ The SPL image filename that is generated by the build process.
+ This image might be used to generated a combined image with
+ SPL and main U-Boot proper as well.
+
 config BUILD_TARGET
string "Build target special images"
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
@@ -232,6 +241,7 @@ config BUILD_TARGET
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
default "u-boot.kwb" if KIRKWOOD
+   default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
  Some SoCs need special image types (e.g. U-Boot binary
  with a special header) as build targets. By defining
diff --git a/Makefile b/Makefile
index c1af9307b3..077bb6634e 100644
--- a/Makefile
+++ b/Makefile
@@ -1225,9 +1225,11 @@ else
 SPL_PAYLOAD := u-boot.bin
 endif
 
+SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%)
+
 OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \
   --pad-to=$(CONFIG_SPL_PAD_TO)
-u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE
+u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE
$(call if_changed,pad_cat)
 
 ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
-- 
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[U-Boot] [PATCH 02/13 v3] arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled

[Stefan Roese]

This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 arch/arm/mach-at91/spl_at91.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index 23ebaa99b1..1065f090e0 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -75,6 +75,16 @@ void __weak spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+   int ret;
+
+   ret = spl_early_init();
+   if (ret) {
+   debug("spl_early_init() failed: %d\n", ret);
+   hang();
+   }
+#endif
+
lowlevel_clock_init();
 #if !defined(CONFIG_WDT_AT91)
at91_disable_wdt();
-- 
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[U-Boot] [PATCH 13/13 v3] arm: at91: Add gardena-gateway-at91sam support

[Stefan Roese]

The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
---
v3:
- Add "timeout-sec" DT property

v2:
- Add dtb build target in dts Makefile
- Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot
  specific DT properties
- at91sam9x5ek.dtsi is not included in the dts file any more as this
  did enable too much unused devices

 arch/arm/dts/Makefile |   3 +
 ...1sam9g25-gardena-smart-gateway-u-boot.dtsi |   5 +
 .../dts/at91sam9g25-gardena-smart-gateway.dts | 120 
 arch/arm/mach-at91/Kconfig|   8 ++
 board/gardena/smart-gateway-at91sam/Kconfig   |  12 ++
 .../gardena/smart-gateway-at91sam/MAINTAINERS |   7 +
 board/gardena/smart-gateway-at91sam/Makefile  |   7 +
 board/gardena/smart-gateway-at91sam/board.c   |  59 
 board/gardena/smart-gateway-at91sam/spl.c | 135 ++
 .../gardena-smart-gateway-at91sam_defconfig   |  83 +++
 .../configs/gardena-smart-gateway-at91sam.h   |  88 
 11 files changed, 527 insertions(+)
 create mode 100644 arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi
 create mode 100644 arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
 create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig
 create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS
 create mode 100644 board/gardena/smart-gateway-at91sam/Makefile
 create mode 100644 board/gardena/smart-gateway-at91sam/board.c
 create mode 100644 board/gardena/smart-gateway-at91sam/spl.c
 create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig
 create mode 100644 include/configs/gardena-smart-gateway-at91sam.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0e2ffdb87f..ff2212ed47 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -607,6 +607,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
 
 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
 
+dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
+   at91sam9g25-gardena-smart-gateway.dtb
+
 dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
 
 dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb
diff --git a/arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi 
b/arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi
new file mode 100644
index 00..732dee6c0e
--- /dev/null
+++ b/arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts 
b/arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
new file mode 100644
index 00..e2f8d8047e
--- /dev/null
+++ b/arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the GARDENA smart Gateway (AT91SAM)
+ *
+ *  Copyright (C) 2012 Atmel,
+ *2012 Nicolas Ferre 
+ */
+
+/dts-v1/;
+
+#include "at91sam9g25.dtsi"
+
+/ {
+   model = "GARDENA smart Gateway (AT91SAM)";
+   compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory {
+   reg = <0x2000 0x800>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   power_blue {
+   label = "smartgw:power:blue";
+   gpios = < 21 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   power_green {
+   label = "smartgw:power:green";
+   gpios = < 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   power_red {
+   label = "smartgw:power:red";
+   gpios = < 19 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   radio_blue {
+   label = "smartgw:radio:blue";
+   gpios = < 18 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   radio_green {
+   label = "smartgw:radio:green";
+   gpios = < 17 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   radio_red 

[U-Boot] [PATCH 11/13 v3] arm: at91: siemens: Add support to generate combined SPL+U-Boot image

[Stefan Roese]

This patch adds the necessary defines to the Siemens AT91SAM based
boards (smartweb, corvus and taurus) to generate the combined binary
image with SPL and main U-Boot image combined (u-boot-with-spl.bin).

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 include/configs/corvus.h   | 3 +++
 include/configs/smartweb.h | 4 
 include/configs/taurus.h   | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 5dd5c28e08..749a67d4b0 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -139,4 +139,7 @@
 #define CONFIG_SYS_MCKR0x1301
 #define CONFIG_SYS_MCKR_CSS0x1302
 
+#define CONFIG_SPL_PAD_TO  CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+
 #endif
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 28af575bf2..f95b29480d 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -221,4 +221,8 @@
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF
 #endif
+
+#define CONFIG_SPL_PAD_TO  CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 1d24577993..3582eb2edf 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -173,4 +173,7 @@
 #define CONFIG_SYS_MCKR_CSS(0x02 | CONFIG_SYS_MCKR)
 #define CONFIG_SYS_AT91_PLLB   0x10193F05
 
+#define CONFIG_SPL_PAD_TO  CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+
 #endif
-- 
2.21.0

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[U-Boot] [PATCH 01/13 v3] arm: at91: Makefile: Compile lowlevel_init only when really necessary

[Stefan Roese]

Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 arch/arm/mach-at91/arm926ejs/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/arm926ejs/Makefile 
b/arch/arm/mach-at91/arm926ejs/Makefile
index 0639d7ea1e..6b0b28957a 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -24,8 +24,10 @@ obj-y+= timer.o
 endif
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 obj-y  += lowlevel_init.o
 endif
+endif
 
 ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
 ifndef CONFIG_HAS_THUMB2
-- 
2.21.0

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[U-Boot] [PATCH 04/13 v3] watchdog: Handle SPL build with watchdog disabled

[Stefan Roese]

This patch adds some checks, so that the watchdog can be enabled in main
U-Boot proper but can be disabled in SPL.

This will be used by some AT91SAM based boards, which might enable the
watchdog in the main U-Boot proper and not in SPL. It will be enabled in
SPL by default there, so no need to configure it there. This approach
saves some space in SPL.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
Tested on the taurus board:
Tested-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 include/watchdog.h | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/watchdog.h b/include/watchdog.h
index 14073cfdd2..3a357de903 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -51,9 +51,15 @@ int init_func_watchdog_reset(void);
#if defined(__ASSEMBLY__)
#define WATCHDOG_RESET bl watchdog_reset
#else
-   extern void watchdog_reset(void);
+   /* Don't require the watchdog to be enabled in SPL */
+   #if defined(CONFIG_SPL_BUILD) &&\
+   !defined(CONFIG_SPL_WATCHDOG_SUPPORT)
+   #define WATCHDOG_RESET() {}
+   #else
+   extern void watchdog_reset(void);
 
-   #define WATCHDOG_RESET watchdog_reset
+   #define WATCHDOG_RESET watchdog_reset
+   #endif
#endif
#else
/*
-- 
2.21.0

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[U-Boot] [PATCH 08/13 v3] arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds

[Stefan Roese]

This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.

Signed-off-by: Stefan Roese 
Cc: Heiko Schocher 
Cc: Andreas Bießmann 
Cc: Eugen Hristev 
Reviewed-by: Heiko Schocher 
---
v3:
- No change

v2:
- No change

 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds 
b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
index f18b17dc93..3955bea23a 100644
--- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -39,6 +39,8 @@ SECTIONS
*(.__end)
} >.sram
 
+   _image_binary_end = .;
+
.bss :
{
. = ALIGN(4);
-- 
2.21.0

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Re: [U-Boot] [PATCH] spl: fit: handle mmc read to sram case in rockchip SoCs

[Kever Yang]

Hi Philipp,


On 03/30/2019 06:16 PM, Philipp Tomsich wrote:
> Kever,
>
>> On 30.03.2019, at 02:43, Kever Yang > > wrote:
>>
>> Hi Simon,
>>
>>
>> On 03/29/2019 11:33 PM, Simon Goldschmidt wrote:
>>>
>>>
>>> On 29.03.19 15:09, Kever Yang wrote:
 Rockchip fit image with atf may have firmware for sram,
 so the fit driver need to read data from mmc to sram,
 but Rockchip mmc controller does not support this data
 path, we have to read into ddr first and then copy it
 to sram.

 Signed-off-by: Kever Yang >>> >
 ---

   common/spl/spl_fit.c | 10 ++
   1 file changed, 10 insertions(+)

 diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
 index c9bfe0cc8a..5c5b58f69d 100644
 --- a/common/spl/spl_fit.c
 +++ b/common/spl/spl_fit.c
 @@ -9,6 +9,7 @@
   #include 
   #include 
   #include 
 +#include 
   #include 
     #ifndef CONFIG_SYS_BOOTM_LEN
 @@ -215,6 +216,15 @@ static int spl_load_fit_image(struct
 spl_load_info *info, ulong sector,
   return -ENOENT;
     load_ptr = (load_addr + align_len) & ~align_len;
 +#if  defined(CONFIG_ROCKCHIP_RK3399) ||
 defined(CONFIG_ROCKCHIP_RK3368)
>>>
>>> This looks hacky. I don't think we should clutter platform independent
>>> code with platform dependent ifdefs. You're totally violating code
>>> abstraction here.
>>>
>>
>> Thanks for your comment, I know this looks hacky, could you share you
>> idea about how to implement this better?
>> We do need this to make things work.
>
> A more appropriate way would be to leverage the bounce buffers in the
> SD/MMC
> drivers and to make sure that the 0x memory region is not
> allocated as a
> DMA-able target address via bounce buffers.

Bounce buffer is a good idea, I have implement it and send to patch to
the list, thanks
very much.

This patch can be drop.

Thanks,
- Kever
>
> Note that this is the same issue that I had highlighted about a year
> and a half ago
> and that we ended up working around by loading the PMU firmware into DRAM,
> pass the info about the loadables to ATF as part of the FDT, and
> finally have ATF
> relocate the loadables to INTMEM.
>
>> Thanks,
>> - Kever
>>> Regards,
>>> Simon
>>>
 +    /*
 + * Rockchip SOC's mmc controller does not support read data
 + * from mmc to sram, we have to read to sdram first, and then
 + * copy to sram.
 + */
 +    if ((load_ptr & 0x) != CONFIG_SYS_SDRAM_BASE)
 +    load_ptr = (ulong)memalign(ARCH_DMA_MINALIGN, len);
 +#endif
   length = len;
     overhead = get_aligned_image_overhead(info, offset);

>>>
>>
>>
>>
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>

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[U-Boot] [PATCH 3/3] common: bouncebuf: handle address in sram for rockchip platform

[Kever Yang]

Rockchip SOC's mmc controller does not support read data
from mmc to sram, we need a bounce buffer(in sdram), and then
copy to sram.

Signed-off-by: Kever Yang 
---

 common/bouncebuf.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/common/bouncebuf.c b/common/bouncebuf.c
index a7098e2caf..364fb17c96 100644
--- a/common/bouncebuf.c
+++ b/common/bouncebuf.c
@@ -26,6 +26,18 @@ static int addr_aligned(struct bounce_buffer *state)
return 0;
}
 
+#ifdef CONFIG_ARCH_ROCKCHIP
+   /*
+* Rockchip SOC's mmc controller does not support read data
+* from mmc to sram, we need a bounce buffer(in sdram), and then
+* copy to sram.
+*/
+   if (((ulong)state->user_buffer & 0xfff8) ==
+   CONFIG_ROCKCHIP_IRAM_BASE) {
+   debug("Unsupport IRAM space %p\n", state->user_buffer);
+   return 0;
+   }
+#endif
/* Aligned */
return 1;
 }
-- 
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[U-Boot] [PATCH 2/3] rockchip: introduce ROCKCHIP_IRAM_BASE

[Kever Yang]

Rockchip SoCs have internal sram for bootrom data area and for
sdram init program space. Introduce the base address in case
we need to use it.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/Kconfig| 5 +
 arch/arm/mach-rockchip/rk3036/Kconfig | 3 +++
 arch/arm/mach-rockchip/rk3128/Kconfig | 3 +++
 arch/arm/mach-rockchip/rk3188/Kconfig | 3 +++
 arch/arm/mach-rockchip/rk322x/Kconfig | 3 +++
 arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++
 arch/arm/mach-rockchip/rk3328/Kconfig | 3 +++
 arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++
 arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++
 arch/arm/mach-rockchip/rv1108/Kconfig | 3 +++
 10 files changed, 32 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 50add08338..462b3ea6e0 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -250,6 +250,11 @@ config ROCKCHIP_BOOT_MODE_REG
  The Soc will enter to different boot mode(defined in 
asm/arch-rockchip/boot_mode.h)
  according to the value from this register.
 
+config ROCKCHIP_IRAM_BASE
+   hex "Rockchip Internal sRAM base address"
+   help
+ Rockchip SoCs has internal sram, U-Boot may need to use it.
+
 config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig 
b/arch/arm/mach-rockchip/rk3036/Kconfig
index 0f6b5c4629..ffc0944c95 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -13,6 +13,9 @@ config TARGET_KYLIN_RK3036
 
 endchoice
 
+config ROCKCHIP_IRAM_BASE
+   default 0x1008
+
 config SYS_SOC
default "rk3036"
 
diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig 
b/arch/arm/mach-rockchip/rk3128/Kconfig
index a82b7dc063..51ed091053 100644
--- a/arch/arm/mach-rockchip/rk3128/Kconfig
+++ b/arch/arm/mach-rockchip/rk3128/Kconfig
@@ -13,6 +13,9 @@ config TARGET_EVB_RK3128
 
 endchoice
 
+config ROCKCHIP_IRAM_BASE
+   default 0x1008
+
 config SYS_SOC
default "rk3128"
 
diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig 
b/arch/arm/mach-rockchip/rk3188/Kconfig
index a6fc691fb6..2e597bb65f 100644
--- a/arch/arm/mach-rockchip/rk3188/Kconfig
+++ b/arch/arm/mach-rockchip/rk3188/Kconfig
@@ -9,6 +9,9 @@ config TARGET_ROCK
  Expansion connectors provide access to display pins, I2C, SPI,
  UART and GPIOs.
 
+config ROCKCHIP_IRAM_BASE
+   default 0x1008
+
 config SYS_SOC
default "rk3188"
 
diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig 
b/arch/arm/mach-rockchip/rk322x/Kconfig
index 8a1f95f785..15fd4a9acf 100644
--- a/arch/arm/mach-rockchip/rk322x/Kconfig
+++ b/arch/arm/mach-rockchip/rk322x/Kconfig
@@ -4,6 +4,9 @@ config TARGET_EVB_RK3229
bool "EVB_RK3229"
select BOARD_LATE_INIT
 
+config ROCKCHIP_IRAM_BASE
+   default 0x1008
+
 config SYS_SOC
default "rk322x"
 
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index 59e403b7df..9aaae60363 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -152,6 +152,9 @@ config ROCKCHIP_FAST_SPL
  voltage. This option is only available on boards which support it
  and have the required PMIC code.
 
+config ROCKCHIP_IRAM_BASE
+   default 0xff70
+
 config SYS_SOC
default "rk3288"
 
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig 
b/arch/arm/mach-rockchip/rk3328/Kconfig
index 6c5c4303a3..d9155ebc0a 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -12,6 +12,9 @@ config TARGET_EVB_RK3328
 
 endchoice
 
+config ROCKCHIP_IRAM_BASE
+   default 0xff09
+
 config SYS_SOC
default "rk3328"
 
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig 
b/arch/arm/mach-rockchip/rk3368/Kconfig
index 325572a7e4..0502a0e30d 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -42,6 +42,9 @@ config TARGET_EVB_PX5
  sensor STK3410.
 endchoice
 
+config ROCKCHIP_IRAM_BASE
+   default 0xff8c
+
 config SYS_SOC
default "rk3368"
 
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig 
b/arch/arm/mach-rockchip/rk3399/Kconfig
index 2c5c93c0b8..9b0924033b 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -64,6 +64,9 @@ config TARGET_CHROMEBOOK_BOB
 
 endchoice
 
+config ROCKCHIP_IRAM_BASE
+   default 0xff8c
+
 config SYS_SOC
default "rk3399"
 
diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig 
b/arch/arm/mach-rockchip/rv1108/Kconfig
index c5402ab1bd..0cbf71bf58 100644
--- a/arch/arm/mach-rockchip/rv1108/Kconfig
+++ b/arch/arm/mach-rockchip/rv1108/Kconfig
@@ -27,6 +27,9 @@ config TARGET_ELGIN_RV1108
 
 endchoice
 
+config ROCKCHIP_IRAM_BASE
+   default 0x1008
+
 config SYS_SOC
default "rv1108"
 
-- 
2.20.1

[U-Boot] [PATCH 1/3] rockchip: fixup board choice in Kconfig

[Kever Yang]

Kconfig for board target select is choice option, fixup for
rk3036, rk3288 and rv1108.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3036/Kconfig | 5 +
 arch/arm/mach-rockchip/rk3288/Kconfig | 5 +
 arch/arm/mach-rockchip/rv1108/Kconfig | 5 +
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig 
b/arch/arm/mach-rockchip/rk3036/Kconfig
index 5e04d20448..0f6b5c4629 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -1,5 +1,8 @@
 if ROCKCHIP_RK3036
 
+choice
+   prompt "RK3036 board select"
+
 config TARGET_EVB_RK3036
bool "EVB_RK3036"
select BOARD_LATE_INIT
@@ -8,6 +11,8 @@ config TARGET_KYLIN_RK3036
bool "KYLIN_RK3036"
select BOARD_LATE_INIT
 
+endchoice
+
 config SYS_SOC
default "rk3036"
 
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index 50680ce606..59e403b7df 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -1,5 +1,8 @@
 if ROCKCHIP_RK3288
 
+choice
+   prompt "RK3288 board select"
+
 config TARGET_CHROMEBOOK_JERRY
bool "Google/Rockchip Veyron-Jerry Chromebook"
select BOARD_LATE_INIT
@@ -138,6 +141,8 @@ config TARGET_TINKER_RK3288
  8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
  I2C, SPI, UART, GPIOs.
 
+endchoice
+
 config ROCKCHIP_FAST_SPL
bool "Change the CPU to full speed in SPL"
depends on TARGET_CHROMEBOOK_JERRY
diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig 
b/arch/arm/mach-rockchip/rv1108/Kconfig
index e3a63b80e1..c5402ab1bd 100644
--- a/arch/arm/mach-rockchip/rv1108/Kconfig
+++ b/arch/arm/mach-rockchip/rv1108/Kconfig
@@ -1,5 +1,8 @@
 if ROCKCHIP_RV1108
 
+choice
+   prompt "RV1108 board select"
+
 config TARGET_EVB_RV1108
bool "EVB_RV1108"
help
@@ -22,6 +25,8 @@ config TARGET_ELGIN_RV1108
help
  RV1108 ELGIN is a board based on the Rockchip RV1108.
 
+endchoice
+
 config SYS_SOC
default "rv1108"
 
-- 
2.20.1

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[U-Boot] [U-Boot, 2/3] imx8mq_evk: README: Fix a typo in the destination path

[sbabic]

> The DDR firmware binaries should be copied to '$(srctree)', so fix
> a typo.
> Signed-off-by: Fabio Estevam 

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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