[PATCH 1/1] common: remove duplicate typedef for uchar
With commit 37db55b7e9db ("linux/types.h: fix typo unchar") we have a
duplicate typedef for uchar. As linux/types.h is included in common.h we
don't need another typedef for uchar there.
Fixes: 37db55b7e9db ("linux/types.h: fix typo unchar")
Signed-off-by: Heinrich Schuchardt
---
include/common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/common.h b/include/common.h
index 8b37b58747..52c02185f4 100644
--- a/include/common.h
+++ b/include/common.h
@@ -15,7 +15,6 @@
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
-typedef unsigned char uchar;
typedef volatile unsigned long vu_long;
typedef volatile unsigned short vu_short;
typedef volatile unsigned char vu_char;
--
2.24.0
Re: Wandboard - I2C error when booting with HDMI cable
Hello Fabio,
Hope you are fine?
Am 10.12.2019 um 01:33 schrieb Fabio Estevam:
Hi Anatolij and Heiko,
When booting a wandboard with a HDMI cable connected I get the
following I2C messages:
U-Boot 2020.01-rc4-00151-g8dc20b6ae3-dirty (Dec 09 2019 - 21:07:48 -0300)
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: WDOG
DRAM: 2 GiB
force_idle_bus: sda=0 scl=1 sda.gp=0x6d scl.gp=0x6c
force_idle_bus: failed to clear bus, sda=0 scl=1
force_idle_bus: sda=0 scl=1 sda.gp=0x6d scl.gp=0x6c
force_idle_bus: failed to clear bus, sda=0 scl=1
Hmm... seems to come from "arch/arm/mach-imx/i2c-mxv7.c" ...
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 2, FSL_SDHC: 1, FSL_SDHC: 0
Loading Environment from MMC... OK
auto-detected panel HDMI
Display: HDMI (1024x768)
The Wandboard logo is properly displayed via HDMI, but I am wondering
what can we do to get rid of these I2C messages?
If the board is booted without the HDMI cable connected such messages
do not appear.
Any ideas?
Hmm.. I have only a DL based wandboard ... but I try to find time
to boot it with a hdmi cable attached ... ok, bootline:
> force_idle_bus: sda=0 scl=1 sda.gp=0x6d scl.gp=0x6c
-> sda pin is 0x6d = 109 = gpio4_13
in arch/arm/dts/imx6dl-pinfunc.h:
#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1
#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0
Ok, so i2c bus 2. from imx6qdl-wandboard.dtsi:
85 {
86 clock-frequency = <10>;
87 pinctrl-names = "default";
88 pinctrl-0 = <_i2c2>;
89 status = "okay";
90
91 codec: sgtl5000@a {
ok, there is this sgtl5000 chip ... audio codec ... I do not see how
this has something to do with hdmi cable ... a very fast look into
wiring diagrams, shows only, that i2c2 _sda/scl goes also to camera1
(FP124-334M4) connector (wb-edm-imx6-rev-c1.pdf C1 schematics). Should
have nothing to do with hdmi ...
May it is worth to check error codes in arch/arm/mach-imx/i2c-mxv7.c ?
22 gpio_direction_input(p->sda.gp);
23 gpio_direction_input(p->scl.gp);
24
25 imx_iomux_v3_setup_pad(p->sda.gpio_mode);
26 imx_iomux_v3_setup_pad(p->scl.gpio_mode);
27
28 sda = gpio_get_value(p->sda.gp);
29 scl = gpio_get_value(p->scl.gp);
especially the imx_iomux_v3_setup_pad calls are interesting ... is
gpio_mode set correctly ?
May the pinmux is not setup to gpio mode, and so deblocking does
not work and or wrong vaules
Oh, I see in board code:
450 int board_init(void)
451 {
452 /* address of boot parameters */
453 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
454
455 #if defined(CONFIG_VIDEO_IPUV3)
456 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, _i2c2_pad_info);
457 if (is_mx6dq() || is_mx6dqp()) {
458 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, _i2c2_pad_info);
459 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, _i2c3_pad_info);
460 } else {
461 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, _i2c2_pad_info);
462 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, _i2c3_pad_info);
463 }
464
465 setup_display();
466 #endif
467
468 return 0;
469 }
So forget my speculation above ... :-(
The only possibility is, that the hdmi cable blocks i2c bus 2 ...
Or timeout until it gets unblocked is too low!
May you increase timeout in "arch/arm/mach-imx/i2c-mxv7.c"
49 elapsed = get_timer(start_time);
50 if (elapsed > (CONFIG_SYS_HZ / 5)) {/* .2 seconds */
51 ret = -EBUSY;
?
Currently no more ideas ... sorry.
bye,
Heiko
--
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Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [U-Boot] Pull request: u-boot-riscv/master
On Tue, Dec 10, 2019 at 09:05:59AM +0800, ub...@andestech.com wrote: > Hi Tom, > > Please pull some riscv updates: > > - Increase stack size to avoid a stack overflow during distro boot. > - Add hifive-unleashed-a00.dts for SIFIVE FU540. > - Add OF_SEPARATE support for SIFIVE FU540. > - Add SPL support for Andes AX25 AE350. > - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V. > > https://travis-ci.org/rickchen36/u-boot-riscv/builds/622462488 > > Thanks > Rick > > > The following changes since commit 0c5c3f293554614416a188d16a8c05e0a6c5bfbb: > > arm: -march=armv5t for ARM11 (2019-12-09 10:36:00 -0500) > > are available in the Git repository at: > > g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 0e1233ce9069a87a84a4385de456665d2bc9229d: > > spl: opensbi: wait for ack from secondary harts before entering OpenSBI > (2019-12-10 08:23:10 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Pull request: u-boot-net.git master
On Mon, Dec 09, 2019 at 09:51:32AM -0600, Joe Hershberger wrote: > Hi Tom, > > Between dropping the superceeded atheros series and applying your nfs trim > patch, things appear to be all good. > > Passed testing at https://travis-ci.org/jhershbe/u-boot/builds/622465407 > > The following changes since commit b38c3a641fc01fcd4eda5fa107ae3c247baa0196: > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2019-12-08 > 10:51:00 -0500) > > are available in the git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-net.git master > > for you to fetch changes up to 2c4e067d493d031d1267eea1c635d1eab93ce8f7: > > cmd: pxe: Increase maximum path length (2019-12-09 09:49:48 -0600) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: i.MX8MM-EVK Boot failure
Hi Adam, On Sat, Dec 7, 2019 at 11:42 AM Adam Ford wrote: > > I am trying to run the latest master > > 4b19b89ca4a866b7baa642533e6dbd67cd832d27 > with the clock patches applied for 8mm, but I am getting a boot > failure when I follow the instructions in the README, which are also a > bit wrong. (the firmware versions don't match, and the ./firmware > command is missing the trailing '.bin', but it's trivial.) > > What comes out of the kit with DEBUG enabled is: > > (bunch of stuff deleted) > > [PMU Major message = 0x00fe] > [PMU Major message = 0x0007] > Training PASS > DDRINFO: ddrphy config done > DDRINFO:ddrphy calibration done > DDRINFO: ddrmix config done > >>SPL: board_init_r() > using memory lx-lx for malloc() > spl_init > Normal Boot > Trying to boot from MMC1 > common/dlmalloc.c:792: do_check_inuse_chunk: Assertion `inuse(p)' failed. > resetting ... > > The above sequence repeats again and again. I didn't put all the junk > into the log because it looked like everything seemed OK until the > dlmalloc failure at the end. If someone has any suggestions, I'd like > to try the 8mm-evk with a modern U-Boot. Same here on a imx8mq-evk: https://lists.denx.de/pipermail/u-boot/2019-November/391705.html I haven't had a chance to look at it deeper, but hopefully we can get this fixed in time for the 2020.01 release.
[U-Boot] Pull request: u-boot-riscv/master
Hi Tom, Please pull some riscv updates: - Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V. https://travis-ci.org/rickchen36/u-boot-riscv/builds/622462488 Thanks Rick The following changes since commit 0c5c3f293554614416a188d16a8c05e0a6c5bfbb: arm: -march=armv5t for ARM11 (2019-12-09 10:36:00 -0500) are available in the Git repository at: g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 0e1233ce9069a87a84a4385de456665d2bc9229d: spl: opensbi: wait for ack from secondary harts before entering OpenSBI (2019-12-10 08:23:10 +0800) Jagan Teki (1): riscv: dts: Add hifive-unleashed-a00 dts from Linux Lukas Auer (5): riscv: increase stack size to avoid a stack overflow during distro boot spl: opensbi: specify main hart as preferred boot hart riscv: add functions for reading the IPI status riscv: add option to wait for ack from secondary harts in smp functions spl: opensbi: wait for ack from secondary harts before entering OpenSBI Rick Chen (11): Use dts support from U-Boot via OF_SEPARATE instead of depending from opensbi. riscv: ax25: add SPL support riscv: ax25-ae350: add SPL configuration riscv: ax25-ae350: Use generic memory size setup riscv: andes_plic: Fix some wrong configurations riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL spl: cache: Allow cache drivers in SPL riscv: Fix clear bss loop in the start-up code riscv: dts: Support four cores SMP riscv: dts: Add #address-cells and #size-cells in nor node doc: update AX25-AE350 RISC-V documentation arch/riscv/Kconfig | 2 +- arch/riscv/cpu/ax25/Kconfig | 4 ++- arch/riscv/cpu/ax25/cache.c | 60 ++--- arch/riscv/cpu/start.S | 6 +++-- arch/riscv/cpu/u-boot-spl.lds | 2 +- arch/riscv/cpu/u-boot.lds | 2 +- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/ae350_32.dts | 61 +++--- arch/riscv/dts/ae350_64.dts | 61 +++--- arch/riscv/dts/fu540-c000.dtsi | 251 + arch/riscv/dts/hifive-unleashed-a00.dts | 96 arch/riscv/include/asm/smp.h| 3 ++- arch/riscv/lib/andes_plic.c | 22 ++--- arch/riscv/lib/bootm.c | 2 +- arch/riscv/lib/sbi_ipi.c| 11 + arch/riscv/lib/sifive_clint.c | 9 +++ arch/riscv/lib/smp.c| 43 ++--- arch/riscv/lib/spl.c| 2 +- board/AndesTech/ax25-ae350/Kconfig | 9 +++ board/AndesTech/ax25-ae350/MAINTAINERS | 4 +++ board/AndesTech/ax25-ae350/ax25-ae350.c | 48 +--- common/spl/Kconfig | 7 ++ common/spl/spl_opensbi.c| 13 +- configs/ae350_rv32_spl_defconfig| 38 + configs/ae350_rv32_spl_xip_defconfig| 40 ++ configs/ae350_rv64_spl_defconfig| 39 ++ configs/ae350_rv64_spl_xip_defconfig| 41 +++ configs/sifive_fu540_defconfig | 3 ++- doc/board/AndesTech/ax25-ae350.rst | 209 ++--- doc/board/sifive/fu540.rst | 5 +--- drivers/Makefile| 1 + include/configs/ax25-ae350.h| 17 + include/opensbi.h | 18 +- 33 files changed, 1057 insertions(+), 73 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts create mode 100644 configs/ae350_rv32_spl_defconfig create mode 100644 configs/ae350_rv32_spl_xip_defconfig create mode 100644 configs/ae350_rv64_spl_defconfig create mode 100644 configs/ae350_rv64_spl_xip_defconfig
Wandboard - I2C error when booting with HDMI cable
Hi Anatolij and Heiko, When booting a wandboard with a HDMI cable connected I get the following I2C messages: U-Boot 2020.01-rc4-00151-g8dc20b6ae3-dirty (Dec 09 2019 - 21:07:48 -0300) CPU: Freescale i.MX6QP rev1.0 at 792 MHz Reset cause: WDOG DRAM: 2 GiB force_idle_bus: sda=0 scl=1 sda.gp=0x6d scl.gp=0x6c force_idle_bus: failed to clear bus, sda=0 scl=1 force_idle_bus: sda=0 scl=1 sda.gp=0x6d scl.gp=0x6c force_idle_bus: failed to clear bus, sda=0 scl=1 PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 2, FSL_SDHC: 1, FSL_SDHC: 0 Loading Environment from MMC... OK auto-detected panel HDMI Display: HDMI (1024x768) The Wandboard logo is properly displayed via HDMI, but I am wondering what can we do to get rid of these I2C messages? If the board is booted without the HDMI cable connected such messages do not appear. Any ideas? Thanks, Fabio Estevam
[PATCH v2 1/3] wandboard: Fix the DM_PMIC conversion
Commit ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
caused the following pmic_get() error:
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
PMIC: pmic_get() ret -19
...
and since the PMIC presence is used to determine the board D1 revision,
the following error is seen when booting a board rev D1:
WARNING: Could not determine dtb to use
and the kernel does not boot at all.
Fix the regression by passing "pfuze100@8" as the correct parameter
to the pmic_get() function in the DM case.
Fixes: ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Remove a double 'the' in the Subject
board/wandboard/wandboard.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 6c1e4ef27d..b2f961a7f0 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -363,7 +363,7 @@ int power_init_board(void)
puts("PMIC: ");
- ret = pmic_get("pfuze100", );
+ ret = pmic_get("pfuze100@8", );
if (ret < 0) {
printf("pmic_get() ret %d\n", ret);
return 0;
--
2.17.1
[PATCH v2 3/3] wandboard: Remove repeated PMIC string
After the conversion to DM_PMIC the following output is seen:
PMIC: PMIC: PFUZE100 ID=0x10
Remove the unnecessary PMIC string from the board file to
avoid the repetead string.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Make it part of a patch series
board/wandboard/wandboard.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 7209cc8211..e386ad2cc1 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -361,8 +361,6 @@ int power_init_board(void)
struct udevice *dev;
int reg, ret;
- puts("PMIC: ");
-
ret = pmic_get("pfuze100@8", );
if (ret < 0) {
printf("pmic_get() ret %d\n", ret);
--
2.17.1
[PATCH v2 2/3] wandboard: Propagate the error on PMIC function failure
When pmic_get() or pmic_reg_read() fail, the error code should
be propagated instead of returning success.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- None
board/wandboard/wandboard.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index b2f961a7f0..7209cc8211 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -366,13 +366,13 @@ int power_init_board(void)
ret = pmic_get("pfuze100@8", );
if (ret < 0) {
printf("pmic_get() ret %d\n", ret);
- return 0;
+ return ret;
}
reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
if (reg < 0) {
printf("pmic_reg_read() ret %d\n", reg);
- return 0;
+ return ret;
}
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
with_pmic = true;
--
2.17.1
[PATCH] wandboard: Remove repeated PMIC string
After the conversion to DM_PMIC the following output is seen:
PMIC: PMIC: PFUZE100 ID=0x10
Remove the unnecessary PMIC string from the board file to
avoid the repetead string.
Signed-off-by: Fabio Estevam
---
Hi Stefano,
This one depends on these two patches:
[PATCH 1/2] wandboard: Fix the the DM_PMIC conversion
[PATCH 2/2] wandboard: Propagate the error on PMIC function failure
board/wandboard/wandboard.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 7209cc8211..e386ad2cc1 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -361,8 +361,6 @@ int power_init_board(void)
struct udevice *dev;
int reg, ret;
- puts("PMIC: ");
-
ret = pmic_get("pfuze100@8", );
if (ret < 0) {
printf("pmic_get() ret %d\n", ret);
--
2.17.1
Re: Pull request: u-boot-net.git master
On Mon, Dec 09, 2019 at 11:15:39PM +, Joe Hershberger wrote: > Hi Tom, > > On Mon, Dec 9, 2019 at 4:49 PM Tom Rini wrote: > > > > On Mon, Dec 09, 2019 at 09:51:32AM -0600, Joe Hershberger wrote: > > > > > Hi Tom, > > > > > > Between dropping the superceeded atheros series and applying your nfs > > > trim patch, things appear to be all good. > > > > > > Passed testing at https://travis-ci.org/jhershbe/u-boot/builds/622465407 > > > > > > The following changes since commit > > > b38c3a641fc01fcd4eda5fa107ae3c247baa0196: > > > > > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2019-12-08 > > > 10:51:00 -0500) > > > > > > are available in the git repository at: > > > > > > https://gitlab.denx.de/u-boot/custodians/u-boot-net.git master > > > > > > for you to fetch changes up to 2c4e067d493d031d1267eea1c635d1eab93ce8f7: > > > > > > cmd: pxe: Increase maximum path length (2019-12-09 09:49:48 -0600) > > > > > > > > > Alex Marginean (18): > > > include: phy: define XFI and USXGMII interface types > > > include: phy: add data field for private driver data > > > drivers: net: aquantia: use XFI, USXGMII interface types > > > drivers: net: aquantia: add PHY generation information > > > drivers: net: aquantia: set up SI protocol based on interface type > > > drivers: net: aquantia: set MDI reversal based on DT property > > > drivers: net: aquantia: set SMBus addr based on DT property > > > drivers: net: aquantia: check system interface too when checking > > > for link up > > > doc: bindings: add bindings document for PHY nodes > > > doc: bindings: Aquantia PHY node binding > > > drivers: net: fsl_enetc: use XFI, USXGMII interface type macros > > > net: mdio-uclass: rename arguments of dm_mdio_phy_connect for > > > clarity > > > net: mdio-uclass: add dm_eth_phy_connect helper function > > > drivers: net: fsl_enetc: use the new MDIO DM helper functions > > > drivers: net: fsl_enetc: Add 2.5Gbps to supported link speeds > > > drivers: net: fsl_enetc: move PCS and PHY config to probe > > > drivers: net: fsl_enetc_mdio: return with time-out if HW is stuck > > > drivers: net: fsl_enetc: register internal MDIO bus > > > > > > Anatolij Gustschin (5): > > > net: phy: mv88e61xx: rework to enable detection of 88E6071 devices > > > net: phy: mv88e61xx: add CPU port parameter init for 88E6071 > > > net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 > > > net: phy: mv88e61xx: register phy_driver struct for 88E6071 > > > net: phy: fix switch vendor name > > > > > > Andre Przywara (1): > > > net: tftp: Fix too small block size > > > > > > Ben Wolsieffer (1): > > > cmd: pxe: Increase maximum path length > > > > > > Bin Meng (1): > > > net: tftp: Fix tftp store address check in store_block() > > > > > > Cédric Le Goater (1): > > > net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGN > > > > > > Florin Chiculita (1): > > > net: phy: aquantia: wait for phy init sequence to finish > > > > > > Grygorii Strashko (8): > > > net: phy: ti: rename ti.c to dp83867.c > > > net: phy: dp83867: move static initialization to .probe() > > > dt-bindings: phy: dp83867: Add documentation for disabling clock > > > output > > > net: phy: dp83867: Add ability to disable output clock > > > net: phy: dp83867: rework delay rgmii delay handling > > > net: phy: dp83867: io impedance is not dependent on RGMII delay > > > net: phy: dp83867: refactor rgmii configuration > > > arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode > > > to rgmii-rxid > > > > > > Grzegorz Jaszczyk (1): > > > net: mvpp2: mark phy as invalid in case of missing appropriate > > > driver > > > > > > Heinrich Schuchardt (1): > > > net: avoid address-of-packed-member error > > > > > > Joe Hershberger (3): > > > net: Always build the string_to_enetaddr() helper > > > net: Improve documentation for string_to_ip() > > > lib: Always build support for formatting MAC and IP address > > > > > > Josef Holzmayr (2): > > > net: macb: explicitly pass phy_adr to mdio read and write > > > net: macb: let miiphy_read/_write pass arbitrary addresses > > > > > > Michael Walle (1): > > > net: eth-uclass: ignore unavailable devices > > > > > > Nevo Hed (3): > > > arm: dts: armada-cp110-*dtsi: add xmdio nodes > > > net: mvpp2: use new MVMDIO driver > > > net: mvpp2: MVPP2 now needs MVMDIO > > > > > > Nicolas Ferre (1): > > > net: phy: micrel: make sure the factory test bit is cleared > > > > > > Priyanka Jain (1): > > > net/phy: Fix phy_connect() for phy addr 0 > > > > > > Ramon Fried (1): > > > cmd: mdio/mii: add Kconfig help and allow break dependency > > > > > > Stefan Chulski (1): > > >
Re: [PATCH 09/20] clk: imx: pllv3: add support for PLLV3_AV type
On Mon, 9 Dec 2019 18:13:04 +0100
Giulio Benetti wrote:
> Hi Lukasz,
>
> On 12/8/19 4:05 PM, Lukasz Majewski wrote:
> > On Wed, 4 Dec 2019 18:44:28 +0100
> > Giulio Benetti wrote:
> >
> >> Add support for PLLV3 AV type.
> >>
> >> Signed-off-by: Giulio Benetti
> >> ---
> >> drivers/clk/imx/clk-pllv3.c | 76
> >> + 1 file changed, 76
> >> insertions(+)
> >>
> >> diff --git a/drivers/clk/imx/clk-pllv3.c
> >> b/drivers/clk/imx/clk-pllv3.c index d5087a104e..fc16416d5f 100644
> >> --- a/drivers/clk/imx/clk-pllv3.c
> >> +++ b/drivers/clk/imx/clk-pllv3.c
> >> @@ -6,6 +6,7 @@
> >>
> >> #include
> >> #include
> >> +#include
> >> #include
> >> #include
> >> #include
> >> @@ -16,6 +17,10 @@
> >> #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC
> >> "imx_clk_pllv3_generic" #define UBOOT_DM_CLK_IMX_PLLV3_SYS
> >> "imx_clk_pllv3_sys" #define UBOOT_DM_CLK_IMX_PLLV3_USB
> >> "imx_clk_pllv3_usb" +#define UBOOT_DM_CLK_IMX_PLLV3_AV
> >> "imx_clk_pllv3_av" +
> >> +#define PLL_NUM_OFFSET0x10
> >> +#define PLL_DENOM_OFFSET 0x20
> >>
> >> #define BM_PLL_POWER (0x1 << 12)
> >> #define BM_PLL_LOCK (0x1 << 31)
> >> @@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops
> >> = { .set_rate = clk_pllv3_sys_set_rate,
> >> };
> >>
> >> +static ulong clk_pllv3_av_get_rate(struct clk *clk)
> >> +{
> >> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> >> + unsigned long parent_rate = clk_get_parent_rate(clk);
> >> + u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
> >> + u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
> >> + u32 div = readl(pll->base) & pll->div_mask;
> >> + u64 temp64 = (u64)parent_rate;
> >> +
> >> + temp64 *= mfn;
> >> + do_div(temp64, mfd);
> >> +
> >> + return parent_rate * div + (unsigned long)temp64;
> >> +}
> >> +
> >> +static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
> >> +{
> >> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> >> + unsigned long parent_rate = clk_get_parent_rate(clk);
> >> + unsigned long min_rate = parent_rate * 27;
> >> + unsigned long max_rate = parent_rate * 54;
> >> + u32 val, div;
> >> + u32 mfn, mfd = 100;
> >> + u32 max_mfd = 0x3FFF;
> >> + u64 temp64;
> >> +
> >> + if (rate < min_rate || rate > max_rate)
> >> + return -EINVAL;
> >> +
> >> + if (parent_rate <= max_mfd)
> >> + mfd = parent_rate;
> >> +
> >> + div = rate / parent_rate;
> >> + temp64 = (u64)(rate - div * parent_rate);
> >> + temp64 *= mfd;
> >> + do_div(temp64, parent_rate);
> >> + mfn = temp64;
> >> +
> >> + val = readl(pll->base);
> >> + val &= ~pll->div_mask;
> >> + val |= div;
> >> + writel(val, pll->base);
> >> + writel(mfn, pll->base + PLL_NUM_OFFSET);
> >> + writel(mfd, pll->base + PLL_DENOM_OFFSET);
> >> +
> >> + /* Wait for PLL to lock */
> >> + while (!(readl(pll->base) & BM_PLL_LOCK))
> >> + ;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static const struct clk_ops clk_pllv3_av_ops = {
> >> + .enable = clk_pllv3_generic_enable,
> >> + .disable= clk_pllv3_generic_disable,
> >> + .get_rate = clk_pllv3_av_get_rate,
> >> + .set_rate = clk_pllv3_av_set_rate,
> >> +};
> >> +
> >> struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char
> >> *name, const char *parent_name, void __iomem
> >> *base, u32 div_mask)
> >> @@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> >> type, const char *name, pll->div_shift = 1;
> >>pll->powerup_set = true;
> >>break;
> >> + case IMX_PLLV3_AV:
> >> + drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
> >> + pll->div_shift = 0;
> >> + pll->powerup_set = false;
> >> + break;
> >>default:
> >>kfree(pll);
> >>return ERR_PTR(-ENOTSUPP);
> >> @@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = {
> >>.ops= _pllv3_generic_ops,
> >>.flags = DM_FLAG_PRE_RELOC,
> >> };
> >> +
> >> +U_BOOT_DRIVER(clk_pllv3_av) = {
> >> + .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
> >> + .id = UCLASS_CLK,
> >> + .ops= _pllv3_av_ops,
> >> + .flags = DM_FLAG_PRE_RELOC,
> >> +};
> >
> > I don't mind about adding this new functionality, but I'm a bit
> > concerned about increase if the size of SPL binary (as it sets the
> > DM_FLAG_PRE_RELOC).
> >
> > Do you have any data about increase of the final binary size?
>
> Yes, following what you've pointed me below(using board kp_imx6q_tpc
> with buildman) these are the results(from patch 1 to 7):
> 01: clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different
> clocks 07: clk: imx: pllv3: add support for PLLV3_AV type
> arm: (for 1/1 boards) all +963.0 data +136.0 rodata +99.0
> spl/u-boot-spl:all +831.0 spl/u-boot-spl:data +136.0
> spl/u-boot-spl:rodata +99.0 spl/u-boot-spl:text +596.0 text +728.0
>
> So for SPL, as I understand, latest text increment of +728 should be
> taken because it's the sum of
[PATCH 1/2] wandboard: Fix the the DM_PMIC conversion
Commit ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
caused the following pmic_get() error:
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
PMIC: pmic_get() ret -19
...
and since the PMIC presence is used to determine the board D1 revision,
the following error is seen when booting a board rev D1:
WARNING: Could not determine dtb to use
and the kernel does not boot at all.
Fix the regression by passing "pfuze100@8" as the correct parameter
to the pmic_get() function in the DM case.
Fixes: ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
Signed-off-by: Fabio Estevam
---
board/wandboard/wandboard.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 6c1e4ef27d..b2f961a7f0 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -363,7 +363,7 @@ int power_init_board(void)
puts("PMIC: ");
- ret = pmic_get("pfuze100", );
+ ret = pmic_get("pfuze100@8", );
if (ret < 0) {
printf("pmic_get() ret %d\n", ret);
return 0;
--
2.17.1
[PATCH 2/2] wandboard: Propagate the error on PMIC function failure
When pmic_get() or pmic_reg_read() fail, the error code should
be propagated instead of returning success.
Signed-off-by: Fabio Estevam
---
board/wandboard/wandboard.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index b2f961a7f0..7209cc8211 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -366,13 +366,13 @@ int power_init_board(void)
ret = pmic_get("pfuze100@8", );
if (ret < 0) {
printf("pmic_get() ret %d\n", ret);
- return 0;
+ return ret;
}
reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
if (reg < 0) {
printf("pmic_reg_read() ret %d\n", reg);
- return 0;
+ return ret;
}
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
with_pmic = true;
--
2.17.1
RE: [PATCH 1/4] serial: n16550: Support run-time configuration
Hi Bin/Simon,
Thanks for adding me in this review thread. I like this approach very much. Let
me make a patch for Slim Bootloader to follow up this dynamic ns16550 and send
it for review. Thanks.
> -Original Message-
> From: Bin Meng
> Sent: Sunday, December 8, 2019 3:31 AM
> To: Simon Glass ; Park, Aiden
> Cc: U-Boot Mailing List
> Subject: Re: [PATCH 1/4] serial: n16550: Support run-time configuration
>
> +Aiden
>
> Hi Simon,
>
> On Fri, Dec 6, 2019 at 7:04 AM Simon Glass wrote:
> >
> > At present this driver uses an assortment of CONFIG options to control
> > how it accesses the hardware. This is painful for platforms that are
> > supposed to be controlled by a device tree or a previous-stage bootloader.
> >
> > Add a new CONFIG option to enable fully dynamic configuration. This
> > controls register spacing, size, offset and endianness.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > drivers/serial/Kconfig | 20 ++
> > drivers/serial/ns16550.c | 57 ++-
> -
> > include/ns16550.h| 13 +
> > 3 files changed, 82 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index
> > d36a0108ea..50710ab998 100644
> > --- a/drivers/serial/Kconfig
> > +++ b/drivers/serial/Kconfig
> > @@ -598,6 +598,26 @@ config SYS_NS16550
> > be used. It can be a constant or a function to get clock, eg,
> > get_serial_clock().
> >
> > +config NS16550_DYNAMIC
> > + bool "Allow NS16550 to be configured at runtime"
>
> nits: run-time
>
> > + default y if SYS_COREBOOT
>
> I believe we should also turn it on for slimbootloader.
>
> > + help
> > + Enable this option to allow device-tree control of the driver.
> > +
> > + Normally this driver is controlled by the following options:
> > +
> > + CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is
> used for
> > +access. If not enabled, then the UART is memory-mapped.
> > + CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that
> 32-bit
> > +access should be used (instead of 8-bit)
> > + CONFIG_SYS_NS16550_REG_SIZE - indicates endianness. If
> > + positive,
>
> This is not for endianness, but for the register width.
>
> > +big-endian access is used. If negative, little-endian is used.
> > +
> > + It is not good practive for a driver to be statically
> > + configured,
>
> not a good practice
>
> > + since it prevents the same driver being used for different types
> > of
> > + UARTs in a system. This option avoids this problem at the cost of
> > a
> > + slightly increased code size.
> > +
> > config INTEL_MID_SERIAL
> > bool "Intel MID platform UART support"
> > depends on DM_SERIAL && OF_CONTROL diff --git
> > a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index
> > 754b6e9921..96c4471efd 100644
> > --- a/drivers/serial/ns16550.c
> > +++ b/drivers/serial/ns16550.c
> > @@ -92,19 +92,57 @@ static inline int serial_in_shift(void *addr, int
> > shift) #define CONFIG_SYS_NS16550_CLK 0 #endif
> >
> > +static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
> > + int value) {
> > + if (plat->flags & NS16550_FLAG_BE) {
> > + if (plat->reg_width == 1)
> > + writeb(value, addr + (1 << plat->reg_shift) - 1);
> > + else if (plat->flags & NS16550_FLAG_IO)
> > + out_be32(addr, value);
> > + else
> > + writel(value, addr);
> > + } else {
> > + if (plat->reg_width == 1)
> > + writeb(value, addr);
> > + else if (plat->flags & NS16550_FLAG_IO)
> > + out_le32(addr, value);
> > + else
> > + writel(value, addr);
> > + }
> > +}
> > +
> > +static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
> > +{
> > + if (plat->flags & NS16550_FLAG_BE) {
> > + if (plat->reg_width == 1)
> > + return readb(addr + (1 << plat->reg_shift) - 1);
> > + else if (plat->flags & NS16550_FLAG_IO)
> > + return in_be32(addr);
> > + else
> > + return readl(addr);
> > + } else {
> > + if (plat->reg_width == 1)
> > + return readb(addr);
> > + else if (plat->flags & NS16550_FLAG_IO)
> > + return in_le32(addr);
> > + else
> > + return readl(addr);
> > + }
> > +}
> > +
> > static void ns16550_writeb(NS16550_t port, int offset, int value) {
> > struct ns16550_platdata *plat = port->plat;
> > unsigned char *addr;
> >
> > offset *= 1 << plat->reg_shift;
> > - addr =
Re: [PATCH 14/20] serial_lpuart: add clock enable if CONFIG_CLK is defined
On Mon, 9 Dec 2019 16:20:10 +0100
Giulio Benetti wrote:
> Hi Lukasz,
>
> On 12/8/19 3:52 PM, Lukasz Majewski wrote:
> > On Wed, 4 Dec 2019 18:44:33 +0100
> > Giulio Benetti wrote:
> >
> >> This driver assumes that lpuart clock is already enabled before
> >> probing but using DM only lpuart won't be automatically enabled so
> >> add clk_enable() when probing if CONFIG_CLK is defined.
> >>
> >> Signed-off-by: Giulio Benetti
> >> ---
> >> drivers/serial/serial_lpuart.c | 13 +
> >> 1 file changed, 13 insertions(+)
> >>
> >> diff --git a/drivers/serial/serial_lpuart.c
> >> b/drivers/serial/serial_lpuart.c index 4b0a964d1b..52bd2baf7d
> >> 100644 --- a/drivers/serial/serial_lpuart.c
> >> +++ b/drivers/serial/serial_lpuart.c
> >> @@ -483,6 +483,19 @@ static int lpuart_serial_pending(struct
> >> udevice *dev, bool input)
> >> static int lpuart_serial_probe(struct udevice *dev)
> >> {
> >> +#if CONFIG_IS_ENABLED(CLK)
> >> + struct clk per_clk;
> >> + int ret;
> >> +
> >> + ret = clk_get_by_name(dev, "per", _clk);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to get per clk: %d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + clk_enable(_clk);
> >> +#endif
> >> +
> >
> > I think that this change will _silently_ break all boards which do
> > have CONFIG_CLK enabled (for some clocks/drivers), but did not yet
> > provided CCF definition for lpuart clock.
>
> Oops, yes, you're totally right.
> Would it be correct if I try to retrieve clock and otherwise I
> fallback sending warnings like following?:
>
> `
> static int lpuart_serial_probe(struct udevice *dev)
> {
> #if CONFIG_IS_ENABLED(CLK)
> struct clk per_clk;
> int ret;
>
> ret = clk_get_by_name(dev, "per", _clk);
> if (!ret) {
> ret = clk_enable(_clk);
> if (ret) {
> dev_err(dev, "Failed to get per clk: %d\n",
> ret);
> return;
> }
> } else {
> dev_warn(dev, "Failed to get per clk: %d\n",
>ret);
> }
> #endif
>
Yes, warning is OK.
>
>
> `
>
> Best regards
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgpR6Mxx2Dtvc.pgp
Description: OpenPGP digital signature
Re: [PATCH 12/20] pinctrl: add i.MXRT driver
On Mon, 9 Dec 2019 12:54:33 +0100 Giulio Benetti wrote: > Hi Lukasz, Stefano, Fabio, all, > > On 12/8/19 3:45 PM, Lukasz Majewski wrote: > > On Wed, 4 Dec 2019 18:44:31 +0100 > > Giulio Benetti wrote: > > > >> Add i.MXRT pinctrl driver. > >> > >> Signed-off-by: Giulio Benetti > >> --- > >> drivers/pinctrl/nxp/Kconfig | 14 ++ > >> drivers/pinctrl/nxp/Makefile| 1 + > >> drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 > >> + 3 files changed, 55 insertions(+) > >> create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c > >> > >> diff --git a/drivers/pinctrl/nxp/Kconfig > >> b/drivers/pinctrl/nxp/Kconfig index f2e67ca231..ec55351e61 100644 > >> --- a/drivers/pinctrl/nxp/Kconfig > >> +++ b/drivers/pinctrl/nxp/Kconfig > >> @@ -99,6 +99,20 @@ config PINCTRL_MXS > >> familiy, e.g. i.MX28. This feature depends on device > >> tree configuration. > >> > >> +config PINCTRL_IMXRT > >> + bool "IMXRT pinctrl driver" > >> + depends on ARCH_IMXRT && PINCTRL_FULL > >> + select DEVRES > >> + select PINCTRL_IMX > >> + help > >> +Say Y here to enable the imxrt pinctrl driver > >> + > >> +This provides a simple pinctrl driver for i.MXRT SoC > >> familiy. > >> +This feature depends on device tree configuration. This > >> driver > >> +is different from the linux one, this is a simple > >> implementation, > > > > Could you add proper documentation entry (in ./doc/*) in which you > > would point out the differences between the full blown Linux driver > > and this U-Boot driver (I do guess that "only parsing 'fsl,pins'" > > is not the only difference - more details are welcome). > > Sure, but isn't maybe something to be done in the document below?... +1 > > > And a bit more generic request - it is also nice to add some kind of > > ./doc/README.* documentation in which one can put some hints (or > > usage patterns) for in-uboot boards (like during development > > discovered HW issues, etc.). Such information is priceless when > > other community member wants to use this code/board (and NXP is > > very often silence about them :-) ). > > Sure, I'm going to provide a > ./doc/device-tree-bindings/pinctrl/fsl,imx-pinctrl.txt unique for > every imx at this point, ok? I think that it would be ok, to first focus on iMXRT. > > And what do you think to provide defines in > ./include/dt-bindings/pinctrl/pinctrl-imxrt1050.h for every setting > in PAD? Or better, in a pinctrl-imxrt.h to be included in > pinctrl-imxrt1050.h(since they are the same) > I mean for pull-up/down, drive strength etc. I would prefer to have the same files as are (or would be) in the Linux kernel. Moreover, there are already added ./include/dt-bindings/pinctrl/pads-imx8q* files in this directory. Maybe you could provide similar structure ? > > Because, even for me that I'm developing, I see it very difficult to > recognize every setting from hexadecimal in dts file, and I loose the > overview. I've already used IMX_PAD_SION to set pad as input. User readable defines DO HELP a lot. IMX6Q uses for example: fsl,pins = < MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 >; which is in sync with Linux kernel. > > Then I would be happy, to add all definitions for every imx and > modify every dts file, but I'd need everyone to re-test its board. > What about this? Let's keep things in sync with Linux kernel as much as possible. This is one of U-Boot's recent goals to: 1. Reduce maintenance effort 2. Ease porting of Linux drivers. What we do need to focus on (in U-Boot) to trim those drivers to keep U-Boot's footprint _really_ small or at least as small as it was before DTS was introduced (in SPL for e.g. i.MX). > > Best regards Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de pgpi7m8GWz6sN.pgp Description: OpenPGP digital signature
Re: [PATCH 11/20] clk: imx: add i.IMXRT1050 clk driver
On Mon, 9 Dec 2019 11:53:05 +0100
Giulio Benetti wrote:
> Forgotten to ask you...
>
> On 12/9/19 11:49 AM, Giulio Benetti wrote:
> > Hi Lukasz,
> >
> > On 12/8/19 3:40 PM, Lukasz Majewski wrote:
> >> On Wed, 4 Dec 2019 18:44:30 +0100
> >> Giulio Benetti wrote:
> >>
> >>> Add i.MXRT1050 clk driver support.
> >>>
> >>> Signed-off-by: Giulio Benetti
> >>> ---
> >>>drivers/clk/imx/Kconfig | 16 ++
> >>>drivers/clk/imx/Makefile| 2 +
> >>>drivers/clk/imx/clk-imxrt1050.c | 292
> >>> include/dt-bindings/clock/imxrt1050-clock.h |
> >>> 65 + 4 files changed, 375 insertions(+)
> >>>create mode 100644 drivers/clk/imx/clk-imxrt1050.c
> >>>create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h
> >>>
> >>> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> >>> index 0ba8bc9f63..d5738b5211 100644
> >>> --- a/drivers/clk/imx/Kconfig
> >>> +++ b/drivers/clk/imx/Kconfig
> >>> @@ -52,3 +52,19 @@ config CLK_IMX8MN
> >>> select CLK_CCF
> >>> help
> >>> This enables support clock driver for i.MX8MN
> >>> platforms. +
> >>> +config SPL_CLK_IMXRT1050
> >>> + bool "SPL clock support for i.MXRT1050"
> >>> + depends on ARCH_IMXRT && SPL
> >>> + select SPL_CLK
> >>> + select SPL_CLK_CCF
> >>> + help
> >>> + This enables SPL DM/DTS support for clock driver in
> >>> i.MXRT1050 +
> >>> +config CLK_IMXRT1050
> >>> + bool "Clock support for i.MXRT1050"
> >>> + depends on ARCH_IMXRT
> >>> + select CLK
> >>> + select CLK_CCF
> >>> + help
> >>> + This enables support clock driver for i.MXRT1050
> >>> platforms. diff --git a/drivers/clk/imx/Makefile
> >>> b/drivers/clk/imx/Makefile index 222c5a4e08..166cb7bb44 100644
> >>> --- a/drivers/clk/imx/Makefile
> >>> +++ b/drivers/clk/imx/Makefile
> >>> @@ -14,3 +14,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) +=
> >>> clk-imx8mm.o clk-pll14xx.o \ clk-composite-8m.o
> >>>obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
> >>> clk-pll14xx.o \ clk-composite-8m.o
> >>> +
> >>> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
> >>> diff --git a/drivers/clk/imx/clk-imxrt1050.c
> >>> b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644
> >>> index 00..44ca52c013
> >>> --- /dev/null
> >>> +++ b/drivers/clk/imx/clk-imxrt1050.c
> >>> @@ -0,0 +1,292 @@
> >>> +// SPDX-License-Identifier: GPL-2.0+
> >>> +/*
> >>> + * Copyright(C) 2019
> >>> + * Author(s): Giulio Benetti
> >>>
> >>> + */
> >>> +
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +
> >>> +#include "clk.h"
> >>> +
> >>> +static ulong imxrt1050_clk_get_rate(struct clk *clk)
> >>> +{
> >>> + struct clk *c;
> >>> + int ret;
> >>> +
> >>> + debug("%s(#%lu)\n", __func__, clk->id);
> >>> +
> >>> + ret = clk_get_by_id(clk->id, );
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + return clk_get_rate(c);
> >>> +}
> >>> +
> >>> +static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
> >>> +{
> >>> + struct clk *c;
> >>> + int ret;
> >>> +
> >>> + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
> >>> +
> >>> + ret = clk_get_by_id(clk->id, );
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + return clk_set_rate(c, rate);
> >>> +}
> >>> +
> >>> +static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
> >>> +{
> >>> + struct clk *c;
> >>> + int ret;
> >>> +
> >>> + debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
> >>> +
> >>> + ret = clk_get_by_id(clk->id, );
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + if (enable)
> >>> + ret = clk_enable(c);
> >>> + else
> >>> + ret = clk_disable(c);
> >>> +
> >>> + return ret;
> >>> +}
> >>> +
> >>> +static int imxrt1050_clk_disable(struct clk *clk)
> >>> +{
> >>> + return __imxrt1050_clk_enable(clk, 0);
> >>> +}
> >>> +
> >>> +static int imxrt1050_clk_enable(struct clk *clk)
> >>> +{
> >>> + return __imxrt1050_clk_enable(clk, 1);
> >>> +}
> >>> +
> >>> +static struct clk_ops imxrt1050_clk_ops = {
> >>> + .set_rate = imxrt1050_clk_set_rate,
> >>> + .get_rate = imxrt1050_clk_get_rate,
> >>> + .enable = imxrt1050_clk_enable,
> >>> + .disable = imxrt1050_clk_disable,
> >>> +};
> >>> +
> >>> +static const char * const pll_ref_sels[] = {"osc", "dummy", };
> >>> +static const char * const pll1_bypass_sels[] = {"pll1_arm",
> >>> "pll1_arm_ref_sel", }; +static const char * const
> >>> pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; +static
> >>> const char * const pll3_bypass_sels[] = {"pll3_usb_otg",
> >>> "pll3_usb_otg_ref_sel", }; +static const char * const
> >>> pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", }; +
> >>> +static const char *const pre_periph_sels[] = { "pll2_sys",
> >>> "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", }; +static const
> >>> char *const periph_sels[] = { "pre_periph_sel", "todo", };
> >>> +static const char *const usdhc_sels[] = {
Re: Pull request: u-boot-net.git master
Hi Tom, On Mon, Dec 9, 2019 at 4:49 PM Tom Rini wrote: > > On Mon, Dec 09, 2019 at 09:51:32AM -0600, Joe Hershberger wrote: > > > Hi Tom, > > > > Between dropping the superceeded atheros series and applying your nfs trim > > patch, things appear to be all good. > > > > Passed testing at https://travis-ci.org/jhershbe/u-boot/builds/622465407 > > > > The following changes since commit b38c3a641fc01fcd4eda5fa107ae3c247baa0196: > > > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2019-12-08 > > 10:51:00 -0500) > > > > are available in the git repository at: > > > > https://gitlab.denx.de/u-boot/custodians/u-boot-net.git master > > > > for you to fetch changes up to 2c4e067d493d031d1267eea1c635d1eab93ce8f7: > > > > cmd: pxe: Increase maximum path length (2019-12-09 09:49:48 -0600) > > > > > > Alex Marginean (18): > > include: phy: define XFI and USXGMII interface types > > include: phy: add data field for private driver data > > drivers: net: aquantia: use XFI, USXGMII interface types > > drivers: net: aquantia: add PHY generation information > > drivers: net: aquantia: set up SI protocol based on interface type > > drivers: net: aquantia: set MDI reversal based on DT property > > drivers: net: aquantia: set SMBus addr based on DT property > > drivers: net: aquantia: check system interface too when checking for > > link up > > doc: bindings: add bindings document for PHY nodes > > doc: bindings: Aquantia PHY node binding > > drivers: net: fsl_enetc: use XFI, USXGMII interface type macros > > net: mdio-uclass: rename arguments of dm_mdio_phy_connect for clarity > > net: mdio-uclass: add dm_eth_phy_connect helper function > > drivers: net: fsl_enetc: use the new MDIO DM helper functions > > drivers: net: fsl_enetc: Add 2.5Gbps to supported link speeds > > drivers: net: fsl_enetc: move PCS and PHY config to probe > > drivers: net: fsl_enetc_mdio: return with time-out if HW is stuck > > drivers: net: fsl_enetc: register internal MDIO bus > > > > Anatolij Gustschin (5): > > net: phy: mv88e61xx: rework to enable detection of 88E6071 devices > > net: phy: mv88e61xx: add CPU port parameter init for 88E6071 > > net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 > > net: phy: mv88e61xx: register phy_driver struct for 88E6071 > > net: phy: fix switch vendor name > > > > Andre Przywara (1): > > net: tftp: Fix too small block size > > > > Ben Wolsieffer (1): > > cmd: pxe: Increase maximum path length > > > > Bin Meng (1): > > net: tftp: Fix tftp store address check in store_block() > > > > Cédric Le Goater (1): > > net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGN > > > > Florin Chiculita (1): > > net: phy: aquantia: wait for phy init sequence to finish > > > > Grygorii Strashko (8): > > net: phy: ti: rename ti.c to dp83867.c > > net: phy: dp83867: move static initialization to .probe() > > dt-bindings: phy: dp83867: Add documentation for disabling clock > > output > > net: phy: dp83867: Add ability to disable output clock > > net: phy: dp83867: rework delay rgmii delay handling > > net: phy: dp83867: io impedance is not dependent on RGMII delay > > net: phy: dp83867: refactor rgmii configuration > > arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to > > rgmii-rxid > > > > Grzegorz Jaszczyk (1): > > net: mvpp2: mark phy as invalid in case of missing appropriate driver > > > > Heinrich Schuchardt (1): > > net: avoid address-of-packed-member error > > > > Joe Hershberger (3): > > net: Always build the string_to_enetaddr() helper > > net: Improve documentation for string_to_ip() > > lib: Always build support for formatting MAC and IP address > > > > Josef Holzmayr (2): > > net: macb: explicitly pass phy_adr to mdio read and write > > net: macb: let miiphy_read/_write pass arbitrary addresses > > > > Michael Walle (1): > > net: eth-uclass: ignore unavailable devices > > > > Nevo Hed (3): > > arm: dts: armada-cp110-*dtsi: add xmdio nodes > > net: mvpp2: use new MVMDIO driver > > net: mvpp2: MVPP2 now needs MVMDIO > > > > Nicolas Ferre (1): > > net: phy: micrel: make sure the factory test bit is cleared > > > > Priyanka Jain (1): > > net/phy: Fix phy_connect() for phy addr 0 > > > > Ramon Fried (1): > > cmd: mdio/mii: add Kconfig help and allow break dependency > > > > Stefan Chulski (1): > > net: mvpp2x: fix traffic stuck after PHY start error > > > > Stefan Roese (1): > > net: phy: Increase link up delay in genphy_update_link() > > > > Thierry Reding (1): > > net: rtl8169: Support RTL-8168c/8111c > > > > Tom Rini (1): > > net: nfs: Only link in NFS code outside of SPL builds > > > >
Re: Pull request: u-boot-net.git master
On Mon, Dec 09, 2019 at 09:51:32AM -0600, Joe Hershberger wrote: > Hi Tom, > > Between dropping the superceeded atheros series and applying your nfs trim > patch, things appear to be all good. > > Passed testing at https://travis-ci.org/jhershbe/u-boot/builds/622465407 > > The following changes since commit b38c3a641fc01fcd4eda5fa107ae3c247baa0196: > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2019-12-08 > 10:51:00 -0500) > > are available in the git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-net.git master > > for you to fetch changes up to 2c4e067d493d031d1267eea1c635d1eab93ce8f7: > > cmd: pxe: Increase maximum path length (2019-12-09 09:49:48 -0600) > > > Alex Marginean (18): > include: phy: define XFI and USXGMII interface types > include: phy: add data field for private driver data > drivers: net: aquantia: use XFI, USXGMII interface types > drivers: net: aquantia: add PHY generation information > drivers: net: aquantia: set up SI protocol based on interface type > drivers: net: aquantia: set MDI reversal based on DT property > drivers: net: aquantia: set SMBus addr based on DT property > drivers: net: aquantia: check system interface too when checking for > link up > doc: bindings: add bindings document for PHY nodes > doc: bindings: Aquantia PHY node binding > drivers: net: fsl_enetc: use XFI, USXGMII interface type macros > net: mdio-uclass: rename arguments of dm_mdio_phy_connect for clarity > net: mdio-uclass: add dm_eth_phy_connect helper function > drivers: net: fsl_enetc: use the new MDIO DM helper functions > drivers: net: fsl_enetc: Add 2.5Gbps to supported link speeds > drivers: net: fsl_enetc: move PCS and PHY config to probe > drivers: net: fsl_enetc_mdio: return with time-out if HW is stuck > drivers: net: fsl_enetc: register internal MDIO bus > > Anatolij Gustschin (5): > net: phy: mv88e61xx: rework to enable detection of 88E6071 devices > net: phy: mv88e61xx: add CPU port parameter init for 88E6071 > net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 > net: phy: mv88e61xx: register phy_driver struct for 88E6071 > net: phy: fix switch vendor name > > Andre Przywara (1): > net: tftp: Fix too small block size > > Ben Wolsieffer (1): > cmd: pxe: Increase maximum path length > > Bin Meng (1): > net: tftp: Fix tftp store address check in store_block() > > Cédric Le Goater (1): > net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGN > > Florin Chiculita (1): > net: phy: aquantia: wait for phy init sequence to finish > > Grygorii Strashko (8): > net: phy: ti: rename ti.c to dp83867.c > net: phy: dp83867: move static initialization to .probe() > dt-bindings: phy: dp83867: Add documentation for disabling clock output > net: phy: dp83867: Add ability to disable output clock > net: phy: dp83867: rework delay rgmii delay handling > net: phy: dp83867: io impedance is not dependent on RGMII delay > net: phy: dp83867: refactor rgmii configuration > arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to > rgmii-rxid > > Grzegorz Jaszczyk (1): > net: mvpp2: mark phy as invalid in case of missing appropriate driver > > Heinrich Schuchardt (1): > net: avoid address-of-packed-member error > > Joe Hershberger (3): > net: Always build the string_to_enetaddr() helper > net: Improve documentation for string_to_ip() > lib: Always build support for formatting MAC and IP address > > Josef Holzmayr (2): > net: macb: explicitly pass phy_adr to mdio read and write > net: macb: let miiphy_read/_write pass arbitrary addresses > > Michael Walle (1): > net: eth-uclass: ignore unavailable devices > > Nevo Hed (3): > arm: dts: armada-cp110-*dtsi: add xmdio nodes > net: mvpp2: use new MVMDIO driver > net: mvpp2: MVPP2 now needs MVMDIO > > Nicolas Ferre (1): > net: phy: micrel: make sure the factory test bit is cleared > > Priyanka Jain (1): > net/phy: Fix phy_connect() for phy addr 0 > > Ramon Fried (1): > cmd: mdio/mii: add Kconfig help and allow break dependency > > Stefan Chulski (1): > net: mvpp2x: fix traffic stuck after PHY start error > > Stefan Roese (1): > net: phy: Increase link up delay in genphy_update_link() > > Thierry Reding (1): > net: rtl8169: Support RTL-8168c/8111c > > Tom Rini (1): > net: nfs: Only link in NFS code outside of SPL builds > > Vignesh Raghavendra (6): > dma: Introduce dma_get_cfg() interface > dma: ti: k3-udma: Implement dma_get_cfg() interface > net: ti: am65-cpsw-nuss: Rework RX flow ID handling > net: ti: am65-cpsw-nuss: Add new compatible for J721e > arm: dts:
Re: [PATCH] cros_ec: use uint instead of uint8_t for cmd param
On Mon, 9 Dec 2019 at 13:27, Michael Auchter wrote: > > Chromium EC commands can be up to 16-bits, so using a uint8_t here can > cause truncation. Update to use a uint instead. > > It looks like this should likely have been done as a part of > 9fea76f5d30264dc08ac591a7a89427b8441555b, but this function was skipped > for some reason. > > Signed-off-by: Michael Auchter > Cc: Simon Glass > --- > drivers/misc/cros_ec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH v2 1/4] serial: ns16550: Support run-time configuration
Am 09.12.2019 um 17:59 schrieb Simon Glass:
At present this driver uses an assortment of CONFIG options to control
how it accesses the hardware. This is painful for platforms that are
supposed to be controlled by a device tree or a previous-stage bootloader.
Add a new CONFIG option to enable fully dynamic configuration. This
controls register spacing, size, offset and endianness.
Signed-off-by: Simon Glass
---
Changes in v2:
- runtime -> run-time
- Enable run-time config for slimbootloader too
- Improve Kconfig help based on Bin's comments
- Use ns16550 in patch subject
drivers/serial/Kconfig | 21 +++
drivers/serial/ns16550.c | 57 ++--
include/ns16550.h| 13 +
3 files changed, 83 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ece7d87d4c..472a9f0929 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -598,6 +598,27 @@ config SYS_NS16550
be used. It can be a constant or a function to get clock, eg,
get_serial_clock().
+config NS16550_DYNAMIC
+ bool "Allow NS16550 to be configured at runtime"
+ default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER
+ help
+ Enable this option to allow device-tree control of the driver.
+
+ Normally this driver is controlled by the following options:
+
+ CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for
+access. If not enabled, then the UART is memory-mapped.
+ CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit
+access should be used (instead of 8-bit)
+ CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also
+endianness. If positive, big-endian access is used. If negative,
+little-endian is used.
+
+ It is not a good practice for a driver to be statically configured,
+ since it prevents the same driver being used for different types of
+ UARTs in a system. This option avoids this problem at the cost of a
+ slightly increased code size.
+
config INTEL_MID_SERIAL
bool "Intel MID platform UART support"
depends on DM_SERIAL && OF_CONTROL
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 754b6e9921..96c4471efd 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -92,19 +92,57 @@ static inline int serial_in_shift(void *addr, int shift)
#define CONFIG_SYS_NS16550_CLK 0
#endif
+static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
+ int value)
+{
+ if (plat->flags & NS16550_FLAG_BE) {
+ if (plat->reg_width == 1)
+ writeb(value, addr + (1 << plat->reg_shift) - 1);
+ else if (plat->flags & NS16550_FLAG_IO)
+ out_be32(addr, value);
+ else
+ writel(value, addr);
+ } else {
+ if (plat->reg_width == 1)
+ writeb(value, addr);
+ else if (plat->flags & NS16550_FLAG_IO)
+ out_le32(addr, value);
+ else
+ writel(value, addr);
+ }
+}
+
+static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
+{
+ if (plat->flags & NS16550_FLAG_BE) {
+ if (plat->reg_width == 1)
+ return readb(addr + (1 << plat->reg_shift) - 1);
+ else if (plat->flags & NS16550_FLAG_IO)
+ return in_be32(addr);
+ else
+ return readl(addr);
+ } else {
+ if (plat->reg_width == 1)
+ return readb(addr);
+ else if (plat->flags & NS16550_FLAG_IO)
+ return in_le32(addr);
+ else
+ return readl(addr);
+ }
+}
+
static void ns16550_writeb(NS16550_t port, int offset, int value)
{
struct ns16550_platdata *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = (unsigned char *)plat->base + offset;
+ addr = (unsigned char *)plat->base + offset + plat->reg_offset;
- /*
-* As far as we know it doesn't make sense to support selection of
-* these options at run-time, so use the existing CONFIG options.
-*/
- serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value);
+ if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
+ serial_out_dynamic(plat, addr, value);
+ else
+ serial_out_shift(addr, plat->reg_shift, value);
}
static int ns16550_readb(NS16550_t port, int offset)
@@ -113,9 +151,12 @@ static int ns16550_readb(NS16550_t port, int offset)
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = (unsigned char *)plat->base + offset;
+ addr = (unsigned
[PATCH] cros_ec: use uint instead of uint8_t for cmd param
Chromium EC commands can be up to 16-bits, so using a uint8_t here can
cause truncation. Update to use a uint instead.
It looks like this should likely have been done as a part of
9fea76f5d30264dc08ac591a7a89427b8441555b, but this function was skipped
for some reason.
Signed-off-by: Michael Auchter
Cc: Simon Glass
---
drivers/misc/cros_ec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 3b6370a6d5..3332c1c8a5 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -316,7 +316,7 @@ static int send_command(struct cros_ec_dev *dev, uint cmd,
int cmd_version,
* @param din_len Maximum size of response in bytes
* @return number of bytes in response, or -ve on error
*/
-static int ec_command_inptr(struct udevice *dev, uint8_t cmd,
+static int ec_command_inptr(struct udevice *dev, uint cmd,
int cmd_version, const void *dout, int dout_len,
uint8_t **dinp, int din_len)
{
--
2.23.0
Re: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions
On Mon, Dec 09, 2019 at 01:46:32PM -0600, Joe Hershberger wrote: > Hi Tom, > > On Mon, Dec 9, 2019 at 12:47 PM Tom Rini wrote: > > > > On Mon, Dec 09, 2019 at 07:42:00PM +0100, Michael Walle wrote: > > > Hi Tom, Hi Joe, > > > > > > Am 2019-12-06 00:58, schrieb Tom Rini: > > > > On Fri, Dec 06, 2019 at 12:27:39AM +0100, Michael Walle wrote: > > > > > Hi Joe, Hi Tom, > > > > > > > > > > Am 2019-12-05 16:55, schrieb Joe Hershberger: > > > > > > Hi Michael, > > > > > > > > > > > > On Fri, Oct 25, 2019 at 7:28 PM Michael Walle > > > > > > wrote: > > > > > > > > > > > > > > Provide functions to read and write the Atheros debug registers. > > > > > > > > > > > > > > Signed-off-by: Michael Walle > > > > > > > > > > > > This series is adding too much size to several of the boards' SPL it > > > > > > seems. > > > > > > > > > > > > https://travis-ci.org/jhershbe/u-boot/builds/620804934 > > > > > > > > > > > > Please address this and resend. > > > > > > > > > > So first of all, this was the old series. There was a v2 series, but > > > > > unfortunately, I've forgot to add the mailing to the recipients, so it > > > > > never ended up in the patchwork system. sorry :( > > > > > > > > > > I've resend the v2 series here: > > > > > https://patchwork.ozlabs.org/project/uboot/list/?series=146771 > > > > > > > > > > Now coming to the real problem here. The sizes, or like some boards > > > > > handle > > > > > the SPL stuff. Btw. I could not reproduce it on the > > > > > am335x_boneblack_vboot > > > > > board with a gcc-8. I've seen the travis ci job uses the gcc-7 so > > > > > this also > > > > > depends on the gcc. gcc-8 seems to produce smaller code, because on > > > > > the > > > > > am335x_evm the overflow was only by some 100 bytes. > > > > > > > > > > So taking the am335x_evm board for example. It has the following > > > > > options > > > > > set: > > > > > CONFIG_DM_ETH=y > > > > > CONFIG_SPL_NET_SUPPORT=y > > > > > CONFIG_PHY_ATHEROS=y (this one is set in the config.h!) > > > > > > > > > > So adding a new binding for the phy obviously increases the code > > > > > size. But > > > > > the hard question is, how could that be fixed. IMHO the board has > > > > > wrong > > > > > settings. I really don't know how that could be "fixed" other than not > > > > > applying this series. Well, we could make the additions conditional > > > > > and > > > > > introduce a new Kconfig setting, but that is a relly ugly hack and > > > > > won't > > > > > last long, would it? Doh! > > > > > > > > So, the gcc-7 from kernel.org is the min required and must work > > > > toolchain. Maybe once gcc-9 is mature enough for people to have made > > > > stand-alone toolchains for it we'll move up to that but gcc-8 for > > > > everyone ends up being too hard. For the boneblack_vboot config, we > > > > could just drop SPL networking, it's not super critical to that > > > > particular example. But am335x_evm is the kitchen-sink EVM and it is > > > > used and supported there. > > > > > > > > That said, looking over the u-boot-spl.map, it looks like nfs stuff > > > > doesn't get discarded for some reason, I'm going to look in to that. > > > > > > So do I need to do something now? I guess removing the NFS stuff will > > > make enough room to fit this. But how do we make sure, it will be applied > > > with this series? > > > > In this case, Joe has it in the -net PR right now. Thanks! > > It's actually excluded from the PR. I need to go back and review the > rest of the v2 series. Sorry I meant the NFS patch to reduce size. -- Tom signature.asc Description: PGP signature
Re: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions
Hi Tom, On Mon, Dec 9, 2019 at 12:47 PM Tom Rini wrote: > > On Mon, Dec 09, 2019 at 07:42:00PM +0100, Michael Walle wrote: > > Hi Tom, Hi Joe, > > > > Am 2019-12-06 00:58, schrieb Tom Rini: > > > On Fri, Dec 06, 2019 at 12:27:39AM +0100, Michael Walle wrote: > > > > Hi Joe, Hi Tom, > > > > > > > > Am 2019-12-05 16:55, schrieb Joe Hershberger: > > > > > Hi Michael, > > > > > > > > > > On Fri, Oct 25, 2019 at 7:28 PM Michael Walle > > > > > wrote: > > > > > > > > > > > > Provide functions to read and write the Atheros debug registers. > > > > > > > > > > > > Signed-off-by: Michael Walle > > > > > > > > > > This series is adding too much size to several of the boards' SPL it > > > > > seems. > > > > > > > > > > https://travis-ci.org/jhershbe/u-boot/builds/620804934 > > > > > > > > > > Please address this and resend. > > > > > > > > So first of all, this was the old series. There was a v2 series, but > > > > unfortunately, I've forgot to add the mailing to the recipients, so it > > > > never ended up in the patchwork system. sorry :( > > > > > > > > I've resend the v2 series here: > > > > https://patchwork.ozlabs.org/project/uboot/list/?series=146771 > > > > > > > > Now coming to the real problem here. The sizes, or like some boards > > > > handle > > > > the SPL stuff. Btw. I could not reproduce it on the > > > > am335x_boneblack_vboot > > > > board with a gcc-8. I've seen the travis ci job uses the gcc-7 so > > > > this also > > > > depends on the gcc. gcc-8 seems to produce smaller code, because on > > > > the > > > > am335x_evm the overflow was only by some 100 bytes. > > > > > > > > So taking the am335x_evm board for example. It has the following > > > > options > > > > set: > > > > CONFIG_DM_ETH=y > > > > CONFIG_SPL_NET_SUPPORT=y > > > > CONFIG_PHY_ATHEROS=y (this one is set in the config.h!) > > > > > > > > So adding a new binding for the phy obviously increases the code > > > > size. But > > > > the hard question is, how could that be fixed. IMHO the board has > > > > wrong > > > > settings. I really don't know how that could be "fixed" other than not > > > > applying this series. Well, we could make the additions conditional > > > > and > > > > introduce a new Kconfig setting, but that is a relly ugly hack and > > > > won't > > > > last long, would it? Doh! > > > > > > So, the gcc-7 from kernel.org is the min required and must work > > > toolchain. Maybe once gcc-9 is mature enough for people to have made > > > stand-alone toolchains for it we'll move up to that but gcc-8 for > > > everyone ends up being too hard. For the boneblack_vboot config, we > > > could just drop SPL networking, it's not super critical to that > > > particular example. But am335x_evm is the kitchen-sink EVM and it is > > > used and supported there. > > > > > > That said, looking over the u-boot-spl.map, it looks like nfs stuff > > > doesn't get discarded for some reason, I'm going to look in to that. > > > > So do I need to do something now? I guess removing the NFS stuff will > > make enough room to fit this. But how do we make sure, it will be applied > > with this series? > > In this case, Joe has it in the -net PR right now. Thanks! It's actually excluded from the PR. I need to go back and review the rest of the v2 series. Cheers, -Joe
Re: [PATCH 1/1] arm: -march=armv5t for ARM11
On Sat, Dec 07, 2019 at 09:14:50AM +0100, Heinrich Schuchardt wrote:
> In GCC 9 support for the Armv5 and Armv5E architectures (which have no
> known implementations) has been removed, cf.
> https://gcc.gnu.org/gcc-9/changes.html
>
> Commit 16540d07fd62 ("arm: fix -march for ARM11") changed the value of the
> compiler flag from -march=armv5 and -march=armv5t into -march=armv6 for
> ARM11.
>
> The values prior to this patch were:
>
> arch-$(CONFIG_CPU_ARM1136) =-march=armv5
> arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
>
> The change lead to a regression with the Raspberry Pi Zero W not booting
> anymore.
>
> Use -march=armv5t both for ARM1136 and ARM1176.
>
> Fixes: 16540d07fd62 ("arm: fix -march for ARM11")
> Signed-off-by: Heinrich Schuchardt
> Tested-by: Joris Offouga
Applied to u-boot/master, thanks!
--
Tom
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Re: [GIT PULL] Pull request: u-boot-imx u-boot-imx-20191209
On Mon, Dec 09, 2019 at 12:28:43PM +0100, Stefano Babic wrote: > Hi Tom, > > some fixes for 2020.01, please pull from u-boot-imx, thanks ! > > Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/621583741 > > u-boot-imx-20191209: > > Fixes for 2020.01 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] linux/types.h: fix typo unchar
On Sun, Dec 08, 2019 at 12:22:01AM +0100, Heinrich Schuchardt wrote: > unsigned char should be called uchar and not unchar. > > This fixes a build error in lib/crypto/x509_cert_parser.c. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions
On Mon, Dec 09, 2019 at 07:42:00PM +0100, Michael Walle wrote: > Hi Tom, Hi Joe, > > Am 2019-12-06 00:58, schrieb Tom Rini: > > On Fri, Dec 06, 2019 at 12:27:39AM +0100, Michael Walle wrote: > > > Hi Joe, Hi Tom, > > > > > > Am 2019-12-05 16:55, schrieb Joe Hershberger: > > > > Hi Michael, > > > > > > > > On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote: > > > > > > > > > > Provide functions to read and write the Atheros debug registers. > > > > > > > > > > Signed-off-by: Michael Walle > > > > > > > > This series is adding too much size to several of the boards' SPL it > > > > seems. > > > > > > > > https://travis-ci.org/jhershbe/u-boot/builds/620804934 > > > > > > > > Please address this and resend. > > > > > > So first of all, this was the old series. There was a v2 series, but > > > unfortunately, I've forgot to add the mailing to the recipients, so it > > > never ended up in the patchwork system. sorry :( > > > > > > I've resend the v2 series here: > > > https://patchwork.ozlabs.org/project/uboot/list/?series=146771 > > > > > > Now coming to the real problem here. The sizes, or like some boards > > > handle > > > the SPL stuff. Btw. I could not reproduce it on the > > > am335x_boneblack_vboot > > > board with a gcc-8. I've seen the travis ci job uses the gcc-7 so > > > this also > > > depends on the gcc. gcc-8 seems to produce smaller code, because on > > > the > > > am335x_evm the overflow was only by some 100 bytes. > > > > > > So taking the am335x_evm board for example. It has the following > > > options > > > set: > > > CONFIG_DM_ETH=y > > > CONFIG_SPL_NET_SUPPORT=y > > > CONFIG_PHY_ATHEROS=y (this one is set in the config.h!) > > > > > > So adding a new binding for the phy obviously increases the code > > > size. But > > > the hard question is, how could that be fixed. IMHO the board has > > > wrong > > > settings. I really don't know how that could be "fixed" other than not > > > applying this series. Well, we could make the additions conditional > > > and > > > introduce a new Kconfig setting, but that is a relly ugly hack and > > > won't > > > last long, would it? Doh! > > > > So, the gcc-7 from kernel.org is the min required and must work > > toolchain. Maybe once gcc-9 is mature enough for people to have made > > stand-alone toolchains for it we'll move up to that but gcc-8 for > > everyone ends up being too hard. For the boneblack_vboot config, we > > could just drop SPL networking, it's not super critical to that > > particular example. But am335x_evm is the kitchen-sink EVM and it is > > used and supported there. > > > > That said, looking over the u-boot-spl.map, it looks like nfs stuff > > doesn't get discarded for some reason, I'm going to look in to that. > > So do I need to do something now? I guess removing the NFS stuff will > make enough room to fit this. But how do we make sure, it will be applied > with this series? In this case, Joe has it in the -net PR right now. Thanks! -- Tom signature.asc Description: PGP signature
Re: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions
Hi Tom, Hi Joe, Am 2019-12-06 00:58, schrieb Tom Rini: On Fri, Dec 06, 2019 at 12:27:39AM +0100, Michael Walle wrote: Hi Joe, Hi Tom, Am 2019-12-05 16:55, schrieb Joe Hershberger: > Hi Michael, > > On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote: > > > > Provide functions to read and write the Atheros debug registers. > > > > Signed-off-by: Michael Walle > > This series is adding too much size to several of the boards' SPL it > seems. > > https://travis-ci.org/jhershbe/u-boot/builds/620804934 > > Please address this and resend. So first of all, this was the old series. There was a v2 series, but unfortunately, I've forgot to add the mailing to the recipients, so it never ended up in the patchwork system. sorry :( I've resend the v2 series here: https://patchwork.ozlabs.org/project/uboot/list/?series=146771 Now coming to the real problem here. The sizes, or like some boards handle the SPL stuff. Btw. I could not reproduce it on the am335x_boneblack_vboot board with a gcc-8. I've seen the travis ci job uses the gcc-7 so this also depends on the gcc. gcc-8 seems to produce smaller code, because on the am335x_evm the overflow was only by some 100 bytes. So taking the am335x_evm board for example. It has the following options set: CONFIG_DM_ETH=y CONFIG_SPL_NET_SUPPORT=y CONFIG_PHY_ATHEROS=y (this one is set in the config.h!) So adding a new binding for the phy obviously increases the code size. But the hard question is, how could that be fixed. IMHO the board has wrong settings. I really don't know how that could be "fixed" other than not applying this series. Well, we could make the additions conditional and introduce a new Kconfig setting, but that is a relly ugly hack and won't last long, would it? Doh! So, the gcc-7 from kernel.org is the min required and must work toolchain. Maybe once gcc-9 is mature enough for people to have made stand-alone toolchains for it we'll move up to that but gcc-8 for everyone ends up being too hard. For the boneblack_vboot config, we could just drop SPL networking, it's not super critical to that particular example. But am335x_evm is the kitchen-sink EVM and it is used and supported there. That said, looking over the u-boot-spl.map, it looks like nfs stuff doesn't get discarded for some reason, I'm going to look in to that. So do I need to do something now? I guess removing the NFS stuff will make enough room to fit this. But how do we make sure, it will be applied with this series? -michael
[PATCH] i2c: i2c_cdns: fix write timeout on fifo boundary
This fixes an issue that would cause I2C writes to timeout when the
number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).
Within the transfer loop, after writing the data register with a new
byte to transfer, if the transfer size equals the FIFO depth, the loop
pauses until the INTERRUPT_COMP bit asserts to indicate data has been
sent. This same check is performed after the loop as well to ensure data
has been transferred prior to returning.
In the case where the amount of data to be written is a multiple of the
FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
assert after writing the final byte, and then wait for this bit to
assert once more. However, since the transfer has finished at this
point, no new data has been written to the data register, and hence
INTERRUPT_COMP will never assert.
Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
there's still data to be written.
Signed-off-by: Michael Auchter
---
drivers/i2c/i2c-cdns.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 2c0301ad08..ff3956d8c2 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -265,7 +265,7 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus
*i2c_bus, u32 addr, u8 *data,
while (len-- && !is_arbitration_lost(regs)) {
writel(*(cur_data++), >data);
- if (readl(>transfer_size) == CDNS_I2C_FIFO_DEPTH) {
+ if (len && readl(>transfer_size) == CDNS_I2C_FIFO_DEPTH) {
ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
CDNS_I2C_INTERRUPT_ARBLOST);
if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
--
2.23.0
Re: [U-Boot] [PATCH 0/2] Add support for booting EFI FIT images
On 12/9/19 9:59 AM, Cristian Ciocaltea wrote:
On Sun, Dec 08, 2019 at 01:25:27AM +0100, Heinrich Schuchardt wrote:
On 11/28/19 8:20 AM, Heinrich Schuchardt wrote:
On 11/27/19 8:45 PM, Cristian Ciocaltea wrote:
On Tue, Nov 26, 2019 at 07:31:39PM +0100, Heinrich Schuchardt wrote:
On 11/24/19 9:11 PM, Cristian Ciocaltea wrote:
Currently the only way to run an EFI binary like GRUB2 is via the
'bootefi' command, which cannot be used in a verified boot scenario.
The obvious solution to this limitation is to add support for
booting FIT images containing those EFI binaries.
The implementation relies on a new image type - IH_OS_EFI - which
can be created by using 'os = "efi"' inside an ITS file:
/ {
#address-cells = <1>;
images {
efi-grub {
description = "GRUB EFI";
data = /incbin/("EFI/BOOT/bootarm.efi");
type = "kernel_noload";
arch = "arm";
os = "efi";
compression = "none";
load = <0x0>;
entry = <0x0>;
hash-1 {
algo = "sha256";
};
};
};
configurations {
default = "config-grub";
config-grub {
kernel = "efi-grub";
signature-1 {
algo = "sha256,rsa2048";
sign-images = "kernel";
};
};
};
};
The bootm command has been extended to handle the IH_OS_EFI images.
To enable this feature, a new configuration option has been added:
BOOTM_EFI
I tested the solution using the 'qemu_arm' board:
=> load scsi 0:1 ${kernel_addr_r} efi-image.fit
=> bootm ${kernel_addr_r}#config-grub
Thanks a lot for the patch series which makes good sense to me.
I think we should pass addresses and not strings to cmd/bootefi.c. This
will need a bit of refactoring as already addressed in a comment to
patch 2/2.
Additionally the documentation in doc/uefi/u-boot_on_efi.rst and
doc/uImage.FIT/howto.txt should be updated.
I cc the contributors given by
scripts/get_maintainer.pl -f common/bootm_os.c
Best regards
Heinrich
Thanks for the feedback, Heinrich!
Instead of creating new function(s), I think we could simply extend
int do_bootefi_image(const char *image_opt)
with a new parameter to hold the fdt address and move here the call
to 'efi_install_fdt()', which is now performed by 'do_bootefi()'.
efi_install_fdt() has to be called for the 'bootefi bootmgr' command too
so the refactoring is a bit more complicated. I have started on that.
The first step is to change efi_install_fdt() to expect the argument as
address instead of a string.
https://github.com/xypron/u-boot-patches/blob/efi-next/0001-efi_loader-pass-address-to-efi_install_fdt.patch
fdt_addr==NULL indicates no device tree supplied by user.
Best regards
Heinrich
However, I'm not sure about changing the data types, i.e. from
'char *' to ulong, for the following reasons:
1. image_opt may have a different meaning in addition to efi address
2. fdt address may not be provided, so we need somehow to detect an >> invalid
value
Kind regards,
Cristian
Hello Christian,
patch series
efi_loader: prepare for FIT images
https://lists.denx.de/pipermail/u-boot/2019-December/393192.html
is now available. It offers these functions:
/* Install device tree */
efi_status_t efi_install_fdt(uintptr_t fdt_addr);
/* Run loaded UEFI image */
efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size);
Could you, please, rebase your patches on this patch series.
Please, call efi_install_fdt with EFI_FDT_USE_INTERNAL if no device tree
is supplied by the FIT image.
The patch series is also available in branch efi-2020-04 at
https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
Best regards
Heinrich
Hello Heinrich,
Thanks for the patch series!
I will send the updated patches by latest tomorrow EOD.
You also mentioned updating the documentation in
doc/uefi/u-boot_on_efi.rst and doc/uImage.FIT/howto.txt.
I've checked those documents and their content is quite generic,
not particularly related to this work. The former describes
how to build and run u-boot as an EFI application/payload, while
the later shows how to build and use FIT images.
If you agree, I could instead add a new ITS file in uImage.FIT folder
and describe there the new functionality.
Having an example in uImage.Fit will be very helpful. But I still think
the capability to start UEFI binaries via FIT images should be mentioned
in the documentation. Just add a section after "Executing a UEFI binary"
in doc/uefi/uefi.rst, e.g.
Launching a UEFI binary from a FIT image
A signed FIT image can be used to securely boot a UEFI image via the
bootm command. A sample configuration is provided as file
doc/uImage.FIT/uefi.its. See doc/uImage.FIT/howto.txt for an
introduction to FIT images.
Best regards
Heinrich
Kind
Re: [PATCH 09/20] clk: imx: pllv3: add support for PLLV3_AV type
Hi Lukasz,
On 12/8/19 4:05 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:28 +0100
Giulio Benetti wrote:
Add support for PLLV3 AV type.
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-pllv3.c | 76
+ 1 file changed, 76 insertions(+)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index d5087a104e..fc16416d5f 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
#include
#include
@@ -16,6 +17,10 @@
#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC"imx_clk_pllv3_generic"
#define UBOOT_DM_CLK_IMX_PLLV3_SYS"imx_clk_pllv3_sys"
#define UBOOT_DM_CLK_IMX_PLLV3_USB"imx_clk_pllv3_usb"
+#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
+
+#define PLL_NUM_OFFSET 0x10
+#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
#define BM_PLL_LOCK (0x1 << 31)
@@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = {
.set_rate = clk_pllv3_sys_set_rate,
};
+static ulong clk_pllv3_av_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
+ u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
+ u32 div = readl(pll->base) & pll->div_mask;
+ u64 temp64 = (u64)parent_rate;
+
+ temp64 *= mfn;
+ do_div(temp64, mfd);
+
+ return parent_rate * div + (unsigned long)temp64;
+}
+
+static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ unsigned long min_rate = parent_rate * 27;
+ unsigned long max_rate = parent_rate * 54;
+ u32 val, div;
+ u32 mfn, mfd = 100;
+ u32 max_mfd = 0x3FFF;
+ u64 temp64;
+
+ if (rate < min_rate || rate > max_rate)
+ return -EINVAL;
+
+ if (parent_rate <= max_mfd)
+ mfd = parent_rate;
+
+ div = rate / parent_rate;
+ temp64 = (u64)(rate - div * parent_rate);
+ temp64 *= mfd;
+ do_div(temp64, parent_rate);
+ mfn = temp64;
+
+ val = readl(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel(val, pll->base);
+ writel(mfn, pll->base + PLL_NUM_OFFSET);
+ writel(mfd, pll->base + PLL_DENOM_OFFSET);
+
+ /* Wait for PLL to lock */
+ while (!(readl(pll->base) & BM_PLL_LOCK))
+ ;
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_av_ops = {
+ .enable = clk_pllv3_generic_enable,
+ .disable= clk_pllv3_generic_disable,
+ .get_rate = clk_pllv3_av_get_rate,
+ .set_rate = clk_pllv3_av_set_rate,
+};
+
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem
*base, u32 div_mask)
@@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
type, const char *name, pll->div_shift = 1;
pll->powerup_set = true;
break;
+ case IMX_PLLV3_AV:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ break;
default:
kfree(pll);
return ERR_PTR(-ENOTSUPP);
@@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = {
.ops= _pllv3_generic_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER(clk_pllv3_av) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
+ .id = UCLASS_CLK,
+ .ops= _pllv3_av_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
I don't mind about adding this new functionality, but I'm a bit
concerned about increase if the size of SPL binary (as it sets the
DM_FLAG_PRE_RELOC).
Do you have any data about increase of the final binary size?
Yes, following what you've pointed me below(using board kp_imx6q_tpc
with buildman) these are the results(from patch 1 to 7):
01: clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks
07: clk: imx: pllv3: add support for PLLV3_AV type
arm: (for 1/1 boards) all +963.0 data +136.0 rodata +99.0
spl/u-boot-spl:all +831.0 spl/u-boot-spl:data +136.0
spl/u-boot-spl:rodata +99.0 spl/u-boot-spl:text +596.0 text +728.0
So for SPL, as I understand, latest text increment of +728 should be
taken because it's the sum of text(596)+data(136) then padded, right?
So SPL increased not few.
The buildman script has options to check the difference of the final
binary (i.e. SPL) size (as provided by Tom Rini):
./tools/buildman/$ export SOURCE_DATE_EPOCH=`date +%s`
$ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master..
--force-build -CveE
$ ./tools/buildman/buildman -o /tmp/test --step 0 -b
[PATCH v2 4/4] x86: Move coreboot over to use the coreboot UART
Use this UART to improve the compatibility of U-Boot when used as a
coreboot payload.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/dts/coreboot.dts | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index a88da6eafd..38ddaafa19 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -8,7 +8,6 @@
/dts-v1/;
/include/ "skeleton.dtsi"
-/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
@@ -40,6 +39,11 @@
u-boot,dm-pre-reloc;
};
+ serial: serial {
+ u-boot,dm-pre-reloc;
+ compatible = "coreboot-serial";
+ };
+
coreboot-fb {
compatible = "coreboot-fb";
};
--
2.24.0.393.g34dc348eaf-goog
[PATCH v2 3/4] x86: serial: Add a coreboot serial driver
Coreboot can provide information about the serial device in use on a
platform. Add a driver that uses this information to produce a working
UART.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
drivers/serial/Kconfig | 11
drivers/serial/Makefile | 1 +
drivers/serial/serial_coreboot.c | 46
3 files changed, 58 insertions(+)
create mode 100644 drivers/serial/serial_coreboot.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 472a9f0929..c403c2fc25 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -539,6 +539,17 @@ config BCM6345_SERIAL
help
Select this to enable UART on BCM6345 SoCs.
+config COREBOOT_SERIAL
+ bool "Coreboot UART support"
+ depends on DM_SERIAL
+ default y if SYS_COREBOOT
+ select SYS_NS16550
+ help
+ Select this to enable a ns16550-style UART where the platform data
+ comes from the coreboot 'sysinfo' tables. This allows U-Boot to have
+ a serial console on any platform without needing to change the
+ device tree, etc.
+
config FSL_LINFLEXUART
bool "Freescale Linflex UART support"
depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 06ee30697d..76b1811510 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
+obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c
new file mode 100644
index 00..ccab347514
--- /dev/null
+++ b/drivers/serial/serial_coreboot.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UART support for U-Boot when launched from Coreboot
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static int coreboot_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+ struct cb_serial *cb_info = lib_sysinfo.serial;
+
+ plat->base = cb_info->baseaddr;
+ plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
+ plat->reg_width = cb_info->regwidth;
+ plat->clock = cb_info->input_hertz;
+ plat->fcr = UART_FCR_DEFVAL;
+ plat->flags = 0;
+ if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
+ plat->flags |= NS16550_FLAG_IO;
+
+ return 0;
+}
+
+static const struct udevice_id coreboot_serial_ids[] = {
+ { .compatible = "coreboot-serial" },
+ { },
+};
+
+U_BOOT_DRIVER(coreboot_uart) = {
+ .name = "coreboot_uart",
+ .id = UCLASS_SERIAL,
+ .of_match = coreboot_serial_ids,
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .ofdata_to_platdata = coreboot_ofdata_to_platdata,
+ .probe = ns16550_serial_probe,
+ .ops= _serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.24.0.393.g34dc348eaf-goog
[PATCH v2 1/4] serial: ns16550: Support run-time configuration
At present this driver uses an assortment of CONFIG options to control
how it accesses the hardware. This is painful for platforms that are
supposed to be controlled by a device tree or a previous-stage bootloader.
Add a new CONFIG option to enable fully dynamic configuration. This
controls register spacing, size, offset and endianness.
Signed-off-by: Simon Glass
---
Changes in v2:
- runtime -> run-time
- Enable run-time config for slimbootloader too
- Improve Kconfig help based on Bin's comments
- Use ns16550 in patch subject
drivers/serial/Kconfig | 21 +++
drivers/serial/ns16550.c | 57 ++--
include/ns16550.h| 13 +
3 files changed, 83 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ece7d87d4c..472a9f0929 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -598,6 +598,27 @@ config SYS_NS16550
be used. It can be a constant or a function to get clock, eg,
get_serial_clock().
+config NS16550_DYNAMIC
+ bool "Allow NS16550 to be configured at runtime"
+ default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER
+ help
+ Enable this option to allow device-tree control of the driver.
+
+ Normally this driver is controlled by the following options:
+
+ CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for
+access. If not enabled, then the UART is memory-mapped.
+ CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit
+access should be used (instead of 8-bit)
+ CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also
+endianness. If positive, big-endian access is used. If negative,
+little-endian is used.
+
+ It is not a good practice for a driver to be statically configured,
+ since it prevents the same driver being used for different types of
+ UARTs in a system. This option avoids this problem at the cost of a
+ slightly increased code size.
+
config INTEL_MID_SERIAL
bool "Intel MID platform UART support"
depends on DM_SERIAL && OF_CONTROL
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 754b6e9921..96c4471efd 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -92,19 +92,57 @@ static inline int serial_in_shift(void *addr, int shift)
#define CONFIG_SYS_NS16550_CLK 0
#endif
+static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
+ int value)
+{
+ if (plat->flags & NS16550_FLAG_BE) {
+ if (plat->reg_width == 1)
+ writeb(value, addr + (1 << plat->reg_shift) - 1);
+ else if (plat->flags & NS16550_FLAG_IO)
+ out_be32(addr, value);
+ else
+ writel(value, addr);
+ } else {
+ if (plat->reg_width == 1)
+ writeb(value, addr);
+ else if (plat->flags & NS16550_FLAG_IO)
+ out_le32(addr, value);
+ else
+ writel(value, addr);
+ }
+}
+
+static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
+{
+ if (plat->flags & NS16550_FLAG_BE) {
+ if (plat->reg_width == 1)
+ return readb(addr + (1 << plat->reg_shift) - 1);
+ else if (plat->flags & NS16550_FLAG_IO)
+ return in_be32(addr);
+ else
+ return readl(addr);
+ } else {
+ if (plat->reg_width == 1)
+ return readb(addr);
+ else if (plat->flags & NS16550_FLAG_IO)
+ return in_le32(addr);
+ else
+ return readl(addr);
+ }
+}
+
static void ns16550_writeb(NS16550_t port, int offset, int value)
{
struct ns16550_platdata *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = (unsigned char *)plat->base + offset;
+ addr = (unsigned char *)plat->base + offset + plat->reg_offset;
- /*
-* As far as we know it doesn't make sense to support selection of
-* these options at run-time, so use the existing CONFIG options.
-*/
- serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value);
+ if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
+ serial_out_dynamic(plat, addr, value);
+ else
+ serial_out_shift(addr, plat->reg_shift, value);
}
static int ns16550_readb(NS16550_t port, int offset)
@@ -113,9 +151,12 @@ static int ns16550_readb(NS16550_t port, int offset)
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = (unsigned char *)plat->base + offset;
+ addr = (unsigned char *)plat->base + offset + plat->reg_offset;
-
[PATCH v2 2/4] x86: Update coreboot serial table struct
Since mid 2016, coreboot has additional fields in the serial struct that
it passes down to U-Boot. Add these so we are in sync.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/include/asm/coreboot_tables.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/x86/include/asm/coreboot_tables.h
b/arch/x86/include/asm/coreboot_tables.h
index 2c54e24e02..61de0077d7 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -97,6 +97,25 @@ struct cb_serial {
u32 type;
u32 baseaddr;
u32 baud;
+ u32 regwidth;
+
+ /*
+* Crystal or input frequency to the chip containing the UART.
+* Provide the board specific details to allow the payload to
+* initialize the chip containing the UART and make independent
+* decisions as to which dividers to select and their values
+* to eventually arrive at the desired console baud-rate.
+*/
+ u32 input_hertz;
+
+ /*
+* UART PCI address: bus, device, function
+* 1 << 31 - Valid bit, PCI UART in use
+* Bus << 20
+* Device << 15
+* Function << 12
+*/
+ u32 uart_pci_addr;
};
#define CB_TAG_CONSOLE 0x0010
--
2.24.0.393.g34dc348eaf-goog
Re: [U-Boot] [PATCH] phy: atheros: add some debug output
Hi Michael, On Sun, Oct 27, 2019 at 3:38 PM Michael Walle wrote: > > The network driver has to set the PHY node correctly. If that is not the > case, ar803x_of_init() will fail. Add some debugging output. > > If the device tree binding is not working for you have a look at the > ar803x_of_init: found PHY node: phy@0 > output. In the case above "phy@0" is the phy node in the device tree. If > instead the node of your network device is displayed, you have to set > the phydev->node property in your network device driver. For example, > the following patch adds it to the fsl_enetc driver: > https://patchwork.ozlabs.org/patch/1184523/ > > Signed-off-by: Michael Walle This doesn't apply so I assume it's either superseded or not needed any more. If those are not the case, please rebase and resend on top of u-boot-net/master Thanks, -Joe
Re: [PATCH v2] arm64: zynqmp: Add support for u-boot.itb generation with ATF
On Mon, Dec 09, 2019 at 03:21:02PM +0100, Michal Simek wrote: > On 05. 12. 19 15:33, Tom Rini wrote: > > On Thu, Dec 05, 2019 at 09:46:57AM +0100, Michal Simek wrote: > >> Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which > >> includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for > >> quite a long time but with using out of tree solution. The patch is filling > >> this gap. > >> > >> Tested on zcu102, zcu104 and zcu100/Ultra96. > >> > >> zcu100/Ultra96 v2.2 ATF build by: > >> make DEBUG=0 ZYNQMP_CONSOLE=cadence1 RESET_TO_BL31=1 PLAT=zynqmp bl31 > >> > >> Signed-off-by: Michal Simek > >> --- > >> > >> Changes in v2: > >> - Exchange u-boot/atf in config section > >> - Use default ATF baseaddr from mainline > >> - Update commit message > >> > >> Kconfig | 3 +- > >> arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 99 + > > > > My only complaint here is adding and N'th version of mkimage_fit_atf.sh > > that varies seemingly only in addresses. Can we not abstract this > > enough to make it for everyone to use and pass in the needed values? > > First of all I will be sending v3 because of other things I found. > > Adding more folks to this. > > I have went through all versions and here is sort of stat: > > board/sunxi/mksunxi_fit_atf.sh - firmware is uboot, atf loadables (not > standard) > > board/theobroma-systems/puma_rk3399/fit_spl_atf.sh - license present > atf, uboot, pmufw (only present here) > > arch/arm/mach-rockchip/make_fit_atf.py - python (only one) and read > addresses from elfs > > arch/arm/mach-rockchip/fit_spl_optee.sh - firmware is tee(no ATF) > > arch/riscv/lib/mkimage_fit_opensbi.sh - reads stuff from .config and > also handles non DT case > > arch/arm/mach-imx/mkimage_fit_atf.sh - optee, atf, incorrect dt nodes names > > And of course this one. Thanks for looking more here. > --- > > I think the key point here is to start talk about how this should be done. > Language? One is python others are shell scripts. I don't have a hard preference here. I think the reason we have one in Python is for ease of working with ELF. Restrictions / issues like that probably mean it would be best to make sure we pick a language that allows for peeking at ELFs but I have not confirmed if we could easily re-do the rockchip python tool in shell by using a standard tool (objdump or similar from binutils, so we'll certainly have it). > Should it stop when ATF/TEE is not found? For CI it must non-fatally complete, but should also be verbose in that the resulting binary is non-functional. > What file to read to get information from u-boot? .config or > include/generated/autoconf.h? Honestly? I'd like to start looking at something better if we can here as these are not really user-configurable values, but system values. Some property under a -u-boot.dtsi file? > Read information about locations from ELFs? > > Should we handle non DT case? Yes? Sorry, non-DT case in this instance meaning what? We're talking about FIT and FIT uses a DT. > Move just DT generation to common location and keep VARs, file checking > in board/arch scripts? High level, this sounds right. Thanks! -- Tom signature.asc Description: PGP signature
[PATCH 0/2] arm64: zynqmp: Cleanup defconfigs
Hi, over years a lot of new Xilinx ZynqMP board have been added to U-Boot with corresponding defconfigs. Also a lot of drivers have been moved to DM that we can make one generic configuration with one defconfig. Nand still needs to be validated that's why dc2/dc3 are not moved yet. Boards can be build like this: export DEVICE_TREE="avnet-ultra96-rev1" make xilinx_zynqmp_virt_defconfig make -j Series depends on patches sent before that's why here is full tree: https://github.com/michalsimek/u-boot/tree/20191209-mainline Thanks, Michal Michal Simek (2): arm64: zynqmp: Add missing Kconfig options to zynqmp_virt platform arm64: zynqmp: Use zynqmp_virt platform configs/avnet_ultra96_rev1_defconfig | 90 -- configs/xilinx_zynqmp_a2197_revA_defconfig| 113 -- .../xilinx_zynqmp_e_a2197_00_revA_defconfig | 111 - .../xilinx_zynqmp_g_a2197_00_revA_defconfig | 111 - .../xilinx_zynqmp_m_a2197_01_revA_defconfig | 111 - .../xilinx_zynqmp_m_a2197_02_revA_defconfig | 111 - .../xilinx_zynqmp_m_a2197_03_revA_defconfig | 111 - .../xilinx_zynqmp_p_a2197_00_revA_defconfig | 111 - configs/xilinx_zynqmp_virt_defconfig | 28 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 50 configs/xilinx_zynqmp_zc1254_revA_defconfig | 50 .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 95 --- .../xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 68 --- .../xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 61 -- configs/xilinx_zynqmp_zcu100_revC_defconfig | 87 -- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 112 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 112 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 111 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 92 -- configs/xilinx_zynqmp_zcu104_revC_defconfig | 96 --- configs/xilinx_zynqmp_zcu106_revA_defconfig | 105 configs/xilinx_zynqmp_zcu111_revA_defconfig | 94 --- configs/xilinx_zynqmp_zcu1275_revA_defconfig | 50 configs/xilinx_zynqmp_zcu1275_revB_defconfig | 59 - configs/xilinx_zynqmp_zcu216_revA_defconfig | 95 --- 25 files changed, 26 insertions(+), 2208 deletions(-) delete mode 100644 configs/avnet_ultra96_rev1_defconfig delete mode 100644 configs/xilinx_zynqmp_a2197_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_e_a2197_00_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_g_a2197_00_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_m_a2197_01_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_m_a2197_02_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_m_a2197_03_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_p_a2197_00_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zc1232_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zc1254_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig delete mode 100644 configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig delete mode 100644 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu100_revC_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu102_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu102_revB_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu104_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu104_revC_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu106_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu111_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu1275_revA_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu1275_revB_defconfig delete mode 100644 configs/xilinx_zynqmp_zcu216_revA_defconfig -- 2.24.0
Re: [PATCH 14/20] serial_lpuart: add clock enable if CONFIG_CLK is defined
Hi Lukasz,
On 12/8/19 3:52 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:33 +0100
Giulio Benetti wrote:
This driver assumes that lpuart clock is already enabled before
probing but using DM only lpuart won't be automatically enabled so add
clk_enable() when probing if CONFIG_CLK is defined.
Signed-off-by: Giulio Benetti
---
drivers/serial/serial_lpuart.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/serial/serial_lpuart.c
b/drivers/serial/serial_lpuart.c index 4b0a964d1b..52bd2baf7d 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -483,6 +483,19 @@ static int lpuart_serial_pending(struct udevice
*dev, bool input)
static int lpuart_serial_probe(struct udevice *dev)
{
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk per_clk;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", _clk);
+ if (ret) {
+ dev_err(dev, "Failed to get per clk: %d\n", ret);
+ return ret;
+ }
+
+ clk_enable(_clk);
+#endif
+
I think that this change will _silently_ break all boards which do have
CONFIG_CLK enabled (for some clocks/drivers), but did not yet provided
CCF definition for lpuart clock.
Oops, yes, you're totally right.
Would it be correct if I try to retrieve clock and otherwise I fallback
sending warnings like following?:
`
static int lpuart_serial_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(CLK)
struct clk per_clk;
int ret;
ret = clk_get_by_name(dev, "per", _clk);
if (!ret) {
ret = clk_enable(_clk);
if (ret) {
dev_err(dev, "Failed to get per clk: %d\n",
ret);
return;
}
} else {
dev_warn(dev, "Failed to get per clk: %d\n",
ret);
}
#endif
`
Best regards
--
Giulio Benetti
Benetti Engineering sas
Was this series checked with travis-ci?
For example:
https://travis-ci.org/lmajewski/u-boot-dfu/jobs/66547
if (is_lpuart32(dev))
return _lpuart32_serial_init(dev);
else
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
[PATCH 2/2] arm64: zynqmp: Use zynqmp_virt platform
Decrease amount of the similar defconfigs and use generic one instead.
The change was declared by commit 4b37c13dc353
("arm64: zynqmp: Introduce virtual defconfig") and this patch removes
configs for the most of the boards.
Utra96/zcu100/zcu102/zcu102 and ZynqMP based System controllers *a2197*.
have been also boot tested to make sure that funcionality
remains the same.
Signed-off-by: Michal Simek
---
configs/avnet_ultra96_rev1_defconfig | 90 --
configs/xilinx_zynqmp_a2197_revA_defconfig| 113 --
.../xilinx_zynqmp_e_a2197_00_revA_defconfig | 111 -
.../xilinx_zynqmp_g_a2197_00_revA_defconfig | 111 -
.../xilinx_zynqmp_m_a2197_01_revA_defconfig | 111 -
.../xilinx_zynqmp_m_a2197_02_revA_defconfig | 111 -
.../xilinx_zynqmp_m_a2197_03_revA_defconfig | 111 -
.../xilinx_zynqmp_p_a2197_00_revA_defconfig | 111 -
configs/xilinx_zynqmp_virt_defconfig | 1 +
configs/xilinx_zynqmp_zc1232_revA_defconfig | 50
configs/xilinx_zynqmp_zc1254_revA_defconfig | 50
.../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 95 ---
.../xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 68 ---
.../xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 61 --
configs/xilinx_zynqmp_zcu100_revC_defconfig | 87 --
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 112 -
configs/xilinx_zynqmp_zcu102_revA_defconfig | 112 -
configs/xilinx_zynqmp_zcu102_revB_defconfig | 111 -
configs/xilinx_zynqmp_zcu104_revA_defconfig | 92 --
configs/xilinx_zynqmp_zcu104_revC_defconfig | 96 ---
configs/xilinx_zynqmp_zcu106_revA_defconfig | 105
configs/xilinx_zynqmp_zcu111_revA_defconfig | 94 ---
configs/xilinx_zynqmp_zcu1275_revA_defconfig | 50
configs/xilinx_zynqmp_zcu1275_revB_defconfig | 59 -
configs/xilinx_zynqmp_zcu216_revA_defconfig | 95 ---
25 files changed, 1 insertion(+), 2206 deletions(-)
delete mode 100644 configs/avnet_ultra96_rev1_defconfig
delete mode 100644 configs/xilinx_zynqmp_a2197_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_e_a2197_00_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_g_a2197_00_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_m_a2197_01_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_m_a2197_02_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_m_a2197_03_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zc1232_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zc1254_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
delete mode 100644 configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
delete mode 100644 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu100_revC_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu102_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu102_revB_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu104_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu104_revC_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu106_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu111_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu1275_revA_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu1275_revB_defconfig
delete mode 100644 configs/xilinx_zynqmp_zcu216_revA_defconfig
diff --git a/configs/avnet_ultra96_rev1_defconfig
b/configs/avnet_ultra96_rev1_defconfig
deleted file mode 100644
index 43aacf322ba3..
--- a/configs/avnet_ultra96_rev1_defconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x800
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff01
-CONFIG_DEBUG_UART_CLOCK=1
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=1500
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_BOOTMENU=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_BIND=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
[PATCH 1/2] arm64: zynqmp: Add missing Kconfig options to zynqmp_virt platform
These options are taken from zcu102/104 platforms. Also use OF_SEPARATE instead of OF_BOARD. Maybe at some point this option will be taken back but as of now board detection is not ready. export DEVICE_TREE="zynqmp-zcu102-revA" make xilinx_zynqmp_virt_defconfig make -j Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 27 +-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index c7e365d009ab..90e8c75d29c2 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -16,10 +16,13 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y +CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y @@ -29,14 +32,16 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_BOARD=y CONFIG_ENV_IS_IN_FAT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y @@ -53,7 +58,9 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y @@ -65,29 +72,37 @@ CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_MARVELL=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y +CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -101,4 +116,12 @@ CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_FUNCTION_THOR=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_WDT=y +CONFIG_WDT_CDNS=y +CONFIG_SPL_GZIP=y +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -- 2.24.0
Re: [RESEND PATCH v1] colibri_imx6: fix broken fsl_esdhc_imx conversion
On Mon, Dec 09, 2019 at 03:03:48PM +, Oliver Graute wrote:
> On 06/12/19, Tom Rini wrote:
> > On Fri, Dec 06, 2019 at 06:23:09PM +0100, Lukasz Majewski wrote:
> > > Hi Igor,
> > >
> > > > Hi Stefano
> > > >
> > > > On Fri, Dec 6, 2019 at 6:24 PM Igor Opaniuk
> > > > wrote:
> > > > >
> > > > > From: Igor Opaniuk
> > > > >
> > > > > Not all CONFIG_FSL_ESDHC defines were properly replaced with
> > > > > CONFIG_FSL_ESDHC_IMX, which broke U-boot proper booting on
> > > > > Colibri iMX6 SoMs.
> > > > >
> > > > > U-boot is stuck after this message:
> > > > > Commercial temperature grade DDR3 timings, 64bit bus width.
> > > > > Trying to boot from MMC1
> > > > >
> > > > > Fixes: e37ac717d7("Convert to use fsl_esdhc_imx for i.MX platforms")
> > > > > Signed-off-by: Igor Opaniuk
> > > > > ---
> > > > >
> > > > > board/toradex/colibri_imx6/colibri_imx6.c | 4 ++--
> > > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
> > > > > b/board/toradex/colibri_imx6/colibri_imx6.c index
> > > > > ad40b589c1..44173dde1f 100644 ---
> > > > > a/board/toradex/colibri_imx6/colibri_imx6.c +++
> > > > > b/board/toradex/colibri_imx6/colibri_imx6.c @@ -83,7 +83,7 @@
> > > > > iomux_v3_cfg_t const uart1_pads[] = {
> > > > > MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), };
> > > > >
> > > > > -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
> > > > > +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
> > > > > /* Colibri MMC */
> > > > > iomux_v3_cfg_t const usdhc1_pads[] = {
> > > > > MX6_PAD_SD1_CLK__SD1_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > @@ -304,7 +304,7 @@ int board_ehci_hcd_init(int port)
> > > > > }
> > > > > #endif
> > > > >
> > > > > -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
> > > > > +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
> > > > > /* use the following sequence: eMMC, MMC */
> > > > > struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
> > > > > {USDHC3_BASE_ADDR},
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > > I've just found the same fix [1] but from Ricardo with Awaiting
> > > > upstream status in patchwork (I thought that he has fixed just Apalis
> > > > iMX6), but seems the patch was
> > > > lost somewhere, as I can not find it nor in u-boot-imx/next neither
> > > > in u-boot-imx/master branches.
> > >
> > > Thanks for providing the fix (at least for the Toradex boards)
> > >
> > > And I do guess that more i.MX6 boards are affected ...
> >
> > I think there's just one other. The imx8qm_rom7720_a1 references
> > CONFIG_FSL_ESDHC still, but I don't see any other i.MX8 platforms doing
> > anything with the symbol to compare with.
>
> thx for that hint, so I must replace CONFIG_FSL_ESDHC with
> CONFIG_FSL_ESDHC_IMX in board/advantech/imx8qm_rom7720_a1/spl.c ?
Yes, and confirm that everything works as expected for the appropriate
use cases. Thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [U-Boot] amlogic a96 mini
On Mon, Dec 09, 2019 at 08:47:07AM +0100, Belisko Marek wrote: > Hi Tom, > > On Wed, Dec 4, 2019 at 11:26 PM Tom Rini wrote: > > > > On Fri, Nov 29, 2019 at 12:06:33PM +0100, Belisko Marek wrote: > > > > > Hi, > > > > > > I'm trying to run mainline u-boot on amlogic a96mini device but before > > > I try to flash it does anybody have an idea if it will work on > > > mainline. As I have limited number of devices and I know that after > > > flashing I can brick the board so would like to ask if anybody have > > > experience with this device and running mainline. Thanks and BR, > > > > I would strongly recommend making > > https://github.com/superna/linux/wiki/Amlogic-HDMI-Boot-Dongle as a > > back-up. While I have before managed to interrupt a re-flash cycle such > > that the DTB on-board is still there and so the binary portions of the > > firmware are happy it will then load U-Boot from SD card. I did not > > play with mainline however. > OK thanks for hint. IIRC this hdmi thingy tells FW from which media to > boot and then I can compile u-boot and have boot it from SDcard? Correct. The previous stages will check and then if it sees the magic continue to boot process from other media. This will prevent you from bricking the hardware :) -- Tom signature.asc Description: PGP signature
Re: [RESEND PATCH v1] colibri_imx6: fix broken fsl_esdhc_imx conversion
On 06/12/19, Tom Rini wrote:
> On Fri, Dec 06, 2019 at 06:23:09PM +0100, Lukasz Majewski wrote:
> > Hi Igor,
> >
> > > Hi Stefano
> > >
> > > On Fri, Dec 6, 2019 at 6:24 PM Igor Opaniuk
> > > wrote:
> > > >
> > > > From: Igor Opaniuk
> > > >
> > > > Not all CONFIG_FSL_ESDHC defines were properly replaced with
> > > > CONFIG_FSL_ESDHC_IMX, which broke U-boot proper booting on
> > > > Colibri iMX6 SoMs.
> > > >
> > > > U-boot is stuck after this message:
> > > > Commercial temperature grade DDR3 timings, 64bit bus width.
> > > > Trying to boot from MMC1
> > > >
> > > > Fixes: e37ac717d7("Convert to use fsl_esdhc_imx for i.MX platforms")
> > > > Signed-off-by: Igor Opaniuk
> > > > ---
> > > >
> > > > board/toradex/colibri_imx6/colibri_imx6.c | 4 ++--
> > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
> > > > b/board/toradex/colibri_imx6/colibri_imx6.c index
> > > > ad40b589c1..44173dde1f 100644 ---
> > > > a/board/toradex/colibri_imx6/colibri_imx6.c +++
> > > > b/board/toradex/colibri_imx6/colibri_imx6.c @@ -83,7 +83,7 @@
> > > > iomux_v3_cfg_t const uart1_pads[] = {
> > > > MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), };
> > > >
> > > > -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
> > > > +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
> > > > /* Colibri MMC */
> > > > iomux_v3_cfg_t const usdhc1_pads[] = {
> > > > MX6_PAD_SD1_CLK__SD1_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > @@ -304,7 +304,7 @@ int board_ehci_hcd_init(int port)
> > > > }
> > > > #endif
> > > >
> > > > -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
> > > > +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
> > > > /* use the following sequence: eMMC, MMC */
> > > > struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
> > > > {USDHC3_BASE_ADDR},
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > I've just found the same fix [1] but from Ricardo with Awaiting
> > > upstream status in patchwork (I thought that he has fixed just Apalis
> > > iMX6), but seems the patch was
> > > lost somewhere, as I can not find it nor in u-boot-imx/next neither
> > > in u-boot-imx/master branches.
> >
> > Thanks for providing the fix (at least for the Toradex boards)
> >
> > And I do guess that more i.MX6 boards are affected ...
>
> I think there's just one other. The imx8qm_rom7720_a1 references
> CONFIG_FSL_ESDHC still, but I don't see any other i.MX8 platforms doing
> anything with the symbol to compare with.
thx for that hint, so I must replace CONFIG_FSL_ESDHC with
CONFIG_FSL_ESDHC_IMX in board/advantech/imx8qm_rom7720_a1/spl.c ?
Best regards,
Oliver
Re: [PATCH 2/2] video: make BPP and ANSI configs optional
On Thu, 2019-12-05 at 19:32 +0100, Anatolij Gustschin wrote: > On Thu, 5 Dec 2019 18:15:49 +0100 > Anatolij Gustschin ag...@denx.de wrote: > > > Many boards do not use all selected framebuffer depth > > configurations, for such boards there is some unused > > code in video and console uclass routines. Make depth > > specific code optional to avoid dead code and slightly > > reduce binary size. Also make ANSI code optional for > > the same reason. When i.e. using only VIDEO_BPP16 the > > code size shrinks (below values when using gcc-7.3.0): > > > > $ ./tools/buildman/buildman -b video-wip -sS wandboard > > ... > > 01: Merge git://git.denx.de/u-boot-sh > > 02: video: add guards around 16bpp/32bbp code > > 03: video: make BPP and ANSI configs optional > > arm: (for 1/1 boards) all -776.0 bss -8.0 text -768.0 > > > > Also adjust defconfigs of DM_VIDEO enabled boards to select > > actually used BPP values. > > Forgot to CC board maintainers. Maybe you could review or test these > two patches [1],[2] on your board to confirm that these don't break > frame buffer support. > > > Thanks, > Anatolij Tested on mx53cx9020 Tested-by: Steffen Dirkwinkel Beckhoff Automation GmbH & Co. KG | Managing Director: Dipl. Phys. Hans Beckhoff Registered office: Verl, Germany | Register court: Guetersloh HRA 7075
[PATCH] arm: xilinx: Use device tree which can be passed on cmd line
DEVICE_TREE variable has been added by commit 6ab6b2afa091
("dts: re-write dts/Makefile more simply with Kbuild")
where DT can be specified on command line. If it is not then
CONFIG_DEFAULT_DEVICE_TREE is used to ensure backward compatibility.
Signed-off-by: Michal Simek
---
board/xilinx/zynq/Makefile | 2 +-
board/xilinx/zynqmp/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 8d3301543959..6a2acee108fa 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -14,7 +14,7 @@ spl/board/xilinx/zynq/ps_init_gpl.o
board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F
endif
ifeq ($(init-objs),)
-hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
init-objs := $(if $(wildcard
$(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
$(hw-platform-y)/ps7_init_gpl.o)
endif
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 5ace6cc1b478..174f4ed24be3 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -14,7 +14,7 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o
board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN
endif
ifeq ($(init-objs),)
-hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
init-objs := $(if $(wildcard
$(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
$(hw-platform-y)/psu_init_gpl.o)
endif
--
2.24.0
[PATCH] arm64: zynqmp: Fix return value of board_fit_config_name_match
Empty implementation should not return 0 (success) because that mean that
passed name matches the board configuration.
Signed-off-by: Michal Simek
---
arch/arm/mach-zynqmp/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 37f690d9b958..76bafcdd2a38 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -139,6 +139,6 @@ int board_fit_config_name_match(const char *name)
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
- return 0;
+ return -1;
}
#endif
--
2.24.0
[PATCH] arm64: zynqmp: Fix symlinks to SC psu_init* files
Names have to match device tree file names. Also add missing one.
Fixes: 50d92833477e ("arm64: zynqmp: Sync names for SC with Versal")
Signed-off-by: Michal Simek
---
.../zynqmp/{zynqmp-a2197-g-revA => zynqmp-g-a2197-00-revA} | 0
.../zynqmp/{zynqmp-a2197-m-revA => zynqmp-m-a2197-01-revA} | 0
.../zynqmp/{zynqmp-a2197-p-revA => zynqmp-m-a2197-02-revA} | 0
board/xilinx/zynqmp/zynqmp-m-a2197-03-revA | 1 +
board/xilinx/zynqmp/zynqmp-p-a2197-00-revA | 1 +
5 files changed, 2 insertions(+)
rename board/xilinx/zynqmp/{zynqmp-a2197-g-revA => zynqmp-g-a2197-00-revA}
(100%)
rename board/xilinx/zynqmp/{zynqmp-a2197-m-revA => zynqmp-m-a2197-01-revA}
(100%)
rename board/xilinx/zynqmp/{zynqmp-a2197-p-revA => zynqmp-m-a2197-02-revA}
(100%)
create mode 12 board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
create mode 12 board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-g-revA
b/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
similarity index 100%
rename from board/xilinx/zynqmp/zynqmp-a2197-g-revA
rename to board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-m-revA
b/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
similarity index 100%
rename from board/xilinx/zynqmp/zynqmp-a2197-m-revA
rename to board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-p-revA
b/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
similarity index 100%
rename from board/xilinx/zynqmp/zynqmp-a2197-p-revA
rename to board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
diff --git a/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
new file mode 12
index ..a64c140b860a
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
new file mode 12
index ..a64c140b860a
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
--
2.24.0
[PATCH] arm64: zynqmp: Add board_boot_order for MMC boot extension
In past SPL_ZYNQMP_TWO_SDHCI symbol was introduced to handle boards with
two sdhci controllers. The problem was that U-Boot is registering
controllers based on aliases in DT but bootmode targets specific controller
ID. That's why on boards with one "second" sdhci controller bootmode was
pointing to second controller(MMC2) but alias was setup to mmc0 (the first
controller). And SPL requires to point to mmc0 in this case.
Long time ago commit f101e4bd3703
("spl: add support for alternative boot device") added support for handling
multiple bootmodes in SPL. Use this functionality and setup second sdhci
controller as backup boot device.
Below is table with behavior:
HW/bootmode bootorder
sd0/sd0 mmc0/mmc1 (mmc1 never called)
sd1/sd1 mmc1/mmc0 (mmc0 fails and mmc1 is called)
sd0+sd1/sd0 mmc0/mmc1 (mmc1 never called)
sd0+sd1/sd1 mmc1/mmc0 (mmc0 never called)
All other bootmodes are not affected but order can be extended to cover
advance boot flows.
Signed-off-by: Michal Simek
---
arch/arm/mach-zynqmp/Kconfig | 11 ---
arch/arm/mach-zynqmp/spl.c | 14 ++
...ltrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 -
configs/xilinx_zynqmp_p_a2197_00_revA_defconfig| 1 -
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 -
5 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 6cf17eb94e11..d82a737a699e 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -117,17 +117,6 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
config ZYNQ_SDHCI_MAX_FREQ
default 2
-config SPL_ZYNQMP_TWO_SDHCI
- bool "Enable booting from both SDHCIs"
- depends on SPL
- help
- This option reflects that board has two SDHCI controllers which
- platform can use as boot device. This option ensures that SPL will
- setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for
- SDHCI0 controller. Platforms which have only one SDHCI controller
- shouldn't enable this option because it for software SDHCI0 or SDHCI1
- are both covered by BOOT_DEVICE_MMC1.
-
config SPL_ZYNQMP_ALT_BOOTMODE
hex
default 0x0 if JTAG_MODE
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 8bb1cdf69e1b..37f690d9b958 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -65,6 +65,16 @@ void spl_board_init(void)
}
#endif
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = spl_boot_device();
+
+ if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
+ spl_boot_list[1] = BOOT_DEVICE_MMC2;
+ if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
u32 spl_boot_device(void)
{
u32 reg = 0;
@@ -88,11 +98,7 @@ u32 spl_boot_device(void)
#ifdef CONFIG_SPL_MMC_SUPPORT
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
-/* if both controllers enabled, then these two are the second controller */
-#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
return BOOT_DEVICE_MMC2;
-/* else, fall through, the one SDHCI controller that is enabled is number 1 */
-#endif
case SD_MODE:
case EMMC_MODE:
return BOOT_DEVICE_MMC1;
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
index 177558db4198..280983d187a1 100644
--- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
+++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff00
CONFIG_DEBUG_UART_CLOCK=1
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
diff --git a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
index ba2cbaba58e9..f206be8a3145 100644
--- a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
+++ b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
@@ -9,7 +9,6 @@ CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ZYNQMP_USB=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 65ce1ff2d337..c7524f630788 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff00
CONFIG_DEBUG_UART_CLOCK=1
CONFIG_PMUFW_INIT_FILE="/mnt/disk/u-boot-bins/zynqmp/zynqmp-zc1751-xm015-dc1/pmufw.bin"
CONFIG_ZYNQMP_USB=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
--
Re: [U-Boot-Board-Maintainers] Raspberry pi 4 - u-boot - genet / scb
Hello Amit, no problem. Is there some git feature branch, to have a look ? Thank you Sascha Am Mo., 9. Dez. 2019 um 12:12 Uhr schrieb Amit Tomer : > > Hello Sascha, > > > > Am 07.12.19 um 07:23 schrieb Sascha Dewald: > > > > Hello, > > > > > > > > is there any progress yet ? > > Sorry for being late on this. > > We have made some progress, ping from RPI to host is working now. > Also, managed to received short files(< 63KB) via TFTP. > but haven't managed to get proper handshaking going(that would enable > us to receive bigger files too). > > Working on it and keep you posted about the progress. > > Thanks > -Amit
Re: [PATCH v2] arm64: zynqmp: Add support for u-boot.itb generation with ATF
On 05. 12. 19 15:33, Tom Rini wrote: > On Thu, Dec 05, 2019 at 09:46:57AM +0100, Michal Simek wrote: >> Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which >> includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for >> quite a long time but with using out of tree solution. The patch is filling >> this gap. >> >> Tested on zcu102, zcu104 and zcu100/Ultra96. >> >> zcu100/Ultra96 v2.2 ATF build by: >> make DEBUG=0 ZYNQMP_CONSOLE=cadence1 RESET_TO_BL31=1 PLAT=zynqmp bl31 >> >> Signed-off-by: Michal Simek >> --- >> >> Changes in v2: >> - Exchange u-boot/atf in config section >> - Use default ATF baseaddr from mainline >> - Update commit message >> >> Kconfig | 3 +- >> arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 99 + > > My only complaint here is adding and N'th version of mkimage_fit_atf.sh > that varies seemingly only in addresses. Can we not abstract this > enough to make it for everyone to use and pass in the needed values? First of all I will be sending v3 because of other things I found. Adding more folks to this. I have went through all versions and here is sort of stat: board/sunxi/mksunxi_fit_atf.sh - firmware is uboot, atf loadables (not standard) board/theobroma-systems/puma_rk3399/fit_spl_atf.sh - license present atf, uboot, pmufw (only present here) arch/arm/mach-rockchip/make_fit_atf.py - python (only one) and read addresses from elfs arch/arm/mach-rockchip/fit_spl_optee.sh - firmware is tee(no ATF) arch/riscv/lib/mkimage_fit_opensbi.sh - reads stuff from .config and also handles non DT case arch/arm/mach-imx/mkimage_fit_atf.sh - optee, atf, incorrect dt nodes names And of course this one. --- I think the key point here is to start talk about how this should be done. Language? One is python others are shell scripts. Should it stop when ATF/TEE is not found? What file to read to get information from u-boot? .config or include/generated/autoconf.h? Read information about locations from ELFs? Should we handle non DT case? Yes? Move just DT generation to common location and keep VARs, file checking in board/arch scripts? Thanks, Michal
[PATCH v5] mx7ulp: Add support for Embedded Artists COM board
The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam
---
Changes since v4:
- Lower the DDR frequency in DCD so that memtester can pass
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/imx7ulp-com.dts | 90
arch/arm/mach-imx/mx7ulp/Kconfig | 6 ++
board/ea/mx7ulp_com/Kconfig | 12 +++
board/ea/mx7ulp_com/MAINTAINERS | 6 ++
board/ea/mx7ulp_com/Makefile | 6 ++
board/ea/mx7ulp_com/imximage.cfg | 137 +++
board/ea/mx7ulp_com/mx7ulp_com.c | 48 +++
configs/mx7ulp_com_defconfig | 60 ++
include/configs/mx7ulp_com.h | 103 +++
10 files changed, 470 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx7ulp-com.dts
create mode 100644 board/ea/mx7ulp_com/Kconfig
create mode 100644 board/ea/mx7ulp_com/MAINTAINERS
create mode 100644 board/ea/mx7ulp_com/Makefile
create mode 100644 board/ea/mx7ulp_com/imximage.cfg
create mode 100644 board/ea/mx7ulp_com/mx7ulp_com.c
create mode 100644 configs/mx7ulp_com_defconfig
create mode 100644 include/configs/mx7ulp_com.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8846df1bd..9a92de71eb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -657,7 +657,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-pico-hobbit.dtb
-dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
diff --git a/arch/arm/dts/imx7ulp-com.dts b/arch/arm/dts/imx7ulp-com.dts
new file mode 100644
index 00..c01e03dd06
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-com.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2019 NXP
+// Author: Fabio Estevam
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+ model = "Embedded Artists i.MX7ULP COM";
+ compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
+
+ chosen {
+ stdout-path =
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x6000 0x800>;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart4>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_usbotg1_id>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+ {
+ fsl,tx-d-cal = <88>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc0>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_1>;
+
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC1__PTC1 0x2
+ >;
+ };
+
+ pinctrl_lpuart4: lpuart4grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX0x3
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
+ IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
+ IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
+ IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTD11__SDHC0_DQS0x42
+ >;
+ };
+
+ pinctrl_usbotg1_id: otg1idgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
+ >;
+ };
+};
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 138c58363f..6680f856c5 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -15,6 +15,11 @@ choice
prompt "MX7ULP board select"
optional
+config TARGET_MX7ULP_COM
+ bool "Support MX7ULP COM board"
+ select MX7ULP
+ select SYS_ARCH_TIMER
+
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
@@ -22,6 +27,7 @@ config TARGET_MX7ULP_EVK
endchoice
+source "board/ea/mx7ulp_com/Kconfig"
source "board/freescale/mx7ulp_evk/Kconfig"
endif
diff --git a/board/ea/mx7ulp_com/Kconfig b/board/ea/mx7ulp_com/Kconfig
new file mode 100644
index 00..90883aced4
---
Re: Pull request: socfpga-next
On Mon, Dec 9, 2019 at 1:57 PM Marek Vasut wrote: > > On 12/9/19 9:09 AM, Simon Goldschmidt wrote: > > The following changes since commit b38c3a641fc01fcd4eda5fa107ae3c247baa0196: > > > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 > > (2019-12-08 10:51:00 -0500) > > > > are available in the git repository at: > > > > https://github.com/goldsimon/u-boot.git socfpga-next > > Applied, thanks Hmm, I hadn't expected this, but travis says stratix10 and agilex now fail due to the MTD "cleanup" Tom recently pushed. I've pushed a fix for the 2nd last commit, travis is running. Sorry for the mess. Regards, Simon
[PATCH v2 1/4] apalis-tk1: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
Create an proper tegra image:
$ cbootimage -s tegra124 apalis-tk1.img.cfg apalis-tk1.img
Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot
Signed-off-by: Igor Opaniuk
---
include/configs/apalis-tk1.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 4127f2d6c6..8ca571b9b7 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -46,6 +46,14 @@
"zImage fat 0 1 mmcpart 0; " \
"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=0\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+
#define EMMC_BOOTCMD \
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
"ro rootfstype=ext4 rootwait\0" \
@@ -104,6 +112,7 @@
"fdt_module=" FDT_MODULE "\0" \
NFS_BOOTCMD \
SD_BOOTCMD \
+ UBOOT_UPDATE \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
--
2.17.1
[PATCH v2 3/4] colibri_t20: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage(NAND).
Create an proper tegra image:
$ cbootimage -s tegra20 colibri_t20-512-v12-nand.img.cfg colibri_t20.img
Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot
Signed-off-by: Igor Opaniuk
---
include/configs/colibri_t20.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 122294de6f..94e17bbb7c 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -27,10 +27,14 @@
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway
*/
+#define UBOOT_UPDATE \
+ "update_uboot=nand erase.part u-boot && " \
+ "nand write ${loadaddr} u-boot ${filesize}\0" \
+/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway
*/
#define BOARD_EXTRA_ENV_SETTINGS \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ UBOOT_UPDATE
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
--
2.17.1
[PATCH v2 4/4] colibri_t30: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
Create an proper tegra image:
$ cbootimage -s tegra30 colibri_t30.img.cfg colibri_t30.img
Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot
Signed-off-by: Igor Opaniuk
---
include/configs/colibri_t30.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 5aecf14393..4e5e89b547 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -39,6 +39,17 @@
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=0\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ UBOOT_UPDATE
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
--
2.17.1
[PATCH v2 2/4] apalis_t30: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
Create an proper tegra image:
$ cbootimage -s tegra30 apalis_t30.img.cfg apalis_t30.img
Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot
Signed-off-by: Igor Opaniuk
---
include/configs/apalis_t30.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 821162a2be..701b34aa84 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -40,6 +40,17 @@
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=0\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ UBOOT_UPDATE
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
--
2.17.1
[PATCH v2 0/4] toradex: tegra: add update_uboot wrapper
This patch series introduces universtal update_uboot
wrapper that helps to update U-Boot image on internal storage (eMMC/NAND).
Example of usage:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot
Igor Opaniuk (4):
apalis-tk1: add update_uboot wrapper
apalis_t30: add update_uboot wrapper
colibri_t20: add update_uboot wrapper
colibri_t30: add update_uboot wrapper
include/configs/apalis-tk1.h | 9 +
include/configs/apalis_t30.h | 11 +++
include/configs/colibri_t20.h | 8 ++--
include/configs/colibri_t30.h | 11 +++
4 files changed, 37 insertions(+), 2 deletions(-)
--
2.17.1
Re: Pull request: socfpga-next
On 12/9/19 9:09 AM, Simon Goldschmidt wrote: > The following changes since commit b38c3a641fc01fcd4eda5fa107ae3c247baa0196: > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 > (2019-12-08 10:51:00 -0500) > > are available in the git repository at: > > https://github.com/goldsimon/u-boot.git socfpga-next Applied, thanks
Re: [PATCH 15/20] serial_lpuart: add support for i.MXRT
Hi Lukasz,
On 12/8/19 3:58 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:34 +0100
Giulio Benetti wrote:
Add i.MXRT compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.
Also according to RM, the Receive RX FIFO Enable (RXFE) field in
LPUART FIFO register is bit 3, so this definition should change to
0x08 as done for i.MX8. It needs also to set baudrate the same way as
i.MX8 does.
Signed-off-by: Giulio Benetti
---
drivers/serial/serial_lpuart.c | 15 +++
include/fsl_lpuart.h | 3 ++-
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c
b/drivers/serial/serial_lpuart.c index 52bd2baf7d..2ac4c6d56a 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -49,7 +49,7 @@
#define FIFO_RXSIZE_MASK 0x7
#define FIFO_RXSIZE_OFF 0
#define FIFO_TXFE 0x80
-#ifdef CONFIG_ARCH_IMX8
+#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
#define FIFO_RXFE 0x08
#else
#define FIFO_RXFE 0x40
@@ -67,7 +67,8 @@ enum lpuart_devtype {
DEV_VF610 = 1,
DEV_LS1021A,
DEV_MX7ULP,
- DEV_IMX8
+ DEV_IMX8,
+ DEV_IMXRT,
};
struct lpuart_serial_platdata {
@@ -409,7 +410,8 @@ static int _lpuart32_serial_init(struct udevice
*dev)
lpuart_write32(plat->flags, >match, 0);
- if (plat->devtype == DEV_MX7ULP || plat->devtype ==
DEV_IMX8) {
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8
||
+ plat->devtype == DEV_IMXRT) {
_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
@@ -426,7 +428,8 @@ static int lpuart_serial_setbrg(struct udevice
*dev, int baudrate) struct lpuart_serial_platdata *plat =
dev_get_platdata(dev);
if (is_lpuart32(dev)) {
- if (plat->devtype == DEV_MX7ULP || plat->devtype ==
DEV_IMX8)
+ if (plat->devtype == DEV_MX7ULP || plat->devtype ==
DEV_IMX8 ||
+ plat->devtype == DEV_IMXRT)
_lpuart32_serial_setbrg_7ulp(dev, baudrate);
else
_lpuart32_serial_setbrg(dev, baudrate);
@@ -527,6 +530,8 @@ static int
lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype =
DEV_VF610; else if (!fdt_node_check_compatible(blob, node,
"fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8;
+ else if (!fdt_node_check_compatible(blob, node,
"fsl,imxrt-lpuart"))
+ plat->devtype = DEV_IMXRT;
return 0;
}
@@ -546,6 +551,8 @@ static const struct udevice_id
lpuart_serial_ids[] = { { .compatible = "fsl,vf610-lpuart"},
{ .compatible = "fsl,imx8qm-lpuart",
.data = LPUART_FLAG_REGMAP_32BIT_REG },
+ { .compatible = "fsl,imxrt-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ }
};
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index fc517d4b7f..511fb84367 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -4,7 +4,8 @@
*
*/
-#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
+#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
+ defined(CONFIG_ARCH_IMXRT)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
Please also used buildman to check if this patch series is bisectable
(i.e. if it can be build without errors for each separate commit).
For example:
./tools/buildman/buildman.py --branch=HEAD odroid edison trats trats2
--show_errors --force-build --count=4 --output-dir=../BUILD/
And indeed patch[19/20] is not bisectable and need rework.
Thanks for pointing me buildman, very cool script!
Best regards
--
Giulio Benetti
Benetti Engineering sas
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
[PATCH v4] mx7ulp: Add support for Embedded Artists COM board
The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam
---
Changes since v3:
- Rebased against the latest u-boot-imx tree.
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/imx7ulp-com.dts | 90 ++
arch/arm/mach-imx/mx7ulp/Kconfig | 6 ++
board/ea/mx7ulp_com/Kconfig | 12 +++
board/ea/mx7ulp_com/MAINTAINERS | 6 ++
board/ea/mx7ulp_com/Makefile | 6 ++
board/ea/mx7ulp_com/imximage.cfg | 128 +++
board/ea/mx7ulp_com/mx7ulp_com.c | 48
configs/mx7ulp_com_defconfig | 61 +++
include/configs/mx7ulp_com.h | 103 +
10 files changed, 462 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx7ulp-com.dts
create mode 100644 board/ea/mx7ulp_com/Kconfig
create mode 100644 board/ea/mx7ulp_com/MAINTAINERS
create mode 100644 board/ea/mx7ulp_com/Makefile
create mode 100644 board/ea/mx7ulp_com/imximage.cfg
create mode 100644 board/ea/mx7ulp_com/mx7ulp_com.c
create mode 100644 configs/mx7ulp_com_defconfig
create mode 100644 include/configs/mx7ulp_com.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8846df1bd..9a92de71eb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -657,7 +657,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-pico-hobbit.dtb
-dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
diff --git a/arch/arm/dts/imx7ulp-com.dts b/arch/arm/dts/imx7ulp-com.dts
new file mode 100644
index 00..c01e03dd06
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-com.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2019 NXP
+// Author: Fabio Estevam
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+ model = "Embedded Artists i.MX7ULP COM";
+ compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
+
+ chosen {
+ stdout-path =
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x6000 0x800>;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart4>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_usbotg1_id>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+ {
+ fsl,tx-d-cal = <88>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc0>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_1>;
+
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC1__PTC1 0x2
+ >;
+ };
+
+ pinctrl_lpuart4: lpuart4grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX0x3
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
+ IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
+ IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
+ IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTD11__SDHC0_DQS0x42
+ >;
+ };
+
+ pinctrl_usbotg1_id: otg1idgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
+ >;
+ };
+};
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 138c58363f..6680f856c5 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -15,6 +15,11 @@ choice
prompt "MX7ULP board select"
optional
+config TARGET_MX7ULP_COM
+ bool "Support MX7ULP COM board"
+ select MX7ULP
+ select SYS_ARCH_TIMER
+
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
@@ -22,6 +27,7 @@ config TARGET_MX7ULP_EVK
endchoice
+source "board/ea/mx7ulp_com/Kconfig"
source "board/freescale/mx7ulp_evk/Kconfig"
endif
diff --git a/board/ea/mx7ulp_com/Kconfig b/board/ea/mx7ulp_com/Kconfig
new file mode 100644
index 00..90883aced4
--- /dev/null
Re: [PATCH 12/20] pinctrl: add i.MXRT driver
Hi Lukasz, Stefano, Fabio, all,
On 12/8/19 3:45 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:31 +0100
Giulio Benetti wrote:
Add i.MXRT pinctrl driver.
Signed-off-by: Giulio Benetti
---
drivers/pinctrl/nxp/Kconfig | 14 ++
drivers/pinctrl/nxp/Makefile| 1 +
drivers/pinctrl/nxp/pinctrl-imxrt.c | 40
+ 3 files changed, 55 insertions(+)
create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index f2e67ca231..ec55351e61 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -99,6 +99,20 @@ config PINCTRL_MXS
familiy, e.g. i.MX28. This feature depends on device tree
configuration.
+config PINCTRL_IMXRT
+ bool "IMXRT pinctrl driver"
+ depends on ARCH_IMXRT && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imxrt pinctrl driver
+
+ This provides a simple pinctrl driver for i.MXRT SoC
familiy.
+ This feature depends on device tree configuration. This
driver
+ is different from the linux one, this is a simple
implementation,
Could you add proper documentation entry (in ./doc/*) in which you
would point out the differences between the full blown Linux driver and
this U-Boot driver (I do guess that "only parsing 'fsl,pins'" is not
the only difference - more details are welcome).
Sure, but isn't maybe something to be done in the document below?...
And a bit more generic request - it is also nice to add some kind of
./doc/README.* documentation in which one can put some hints (or usage
patterns) for in-uboot boards (like during development discovered HW
issues, etc.). Such information is priceless when other community
member wants to use this code/board (and NXP is very often silence
about them :-) ).
Sure, I'm going to provide a
./doc/device-tree-bindings/pinctrl/fsl,imx-pinctrl.txt unique for every
imx at this point, ok?
And what do you think to provide defines in
./include/dt-bindings/pinctrl/pinctrl-imxrt1050.h for every setting in
PAD? Or better, in a pinctrl-imxrt.h to be included in
pinctrl-imxrt1050.h(since they are the same)
I mean for pull-up/down, drive strength etc.
Because, even for me that I'm developing, I see it very difficult to
recognize every setting from hexadecimal in dts file, and I loose the
overview. I've already used IMX_PAD_SION to set pad as input.
Then I would be happy, to add all definitions for every imx and modify
every dts file, but I'd need everyone to re-test its board.
What about this?
Best regards
--
Giulio Benetti
Benetti Engineering sas
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile
b/drivers/pinctrl/nxp/Makefile index b86448aac9..066ca75b65 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_IMX8) +=
pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M) +=
pinctrl-imx8m.o obj-$(CONFIG_PINCTRL_MXS) +=
pinctrl-mxs.o obj-$(CONFIG_PINCTRL_VYBRID) +=
pinctrl-vf610.o +obj-$(CONFIG_PINCTRL_IMXRT)+=
pinctrl-imxrt.o diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c
b/drivers/pinctrl/nxp/pinctrl-imxrt.c new file mode 100644
index 00..4a93941927
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti
+ */
+
+#include
+#include
+#include
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
+ .flags = ZERO_OFFSET_VALID,
+};
+
+static int imxrt_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info
*)dev_get_driver_data(dev); +
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imxrt_pinctrl_match[] = {
+ { .compatible = "fsl,imxrt-iomuxc",
+ .data = (ulong)_pinctrl_soc_info },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imxrt_pinctrl) = {
+ .name = "imxrt-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imxrt_pinctrl_match),
+ .probe = imxrt_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .ops = _pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
[GIT PULL] Pull request: u-boot-imx u-boot-imx-20191209
Hi Tom, some fixes for 2020.01, please pull from u-boot-imx, thanks ! Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/621583741 u-boot-imx-20191209: Fixes for 2020.01 - - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support The following changes since commit 1297989804d66c8db92efbf9fa2e6cc76965a943: Prepare v2020.01-rc4 (2019-12-02 22:09:27 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20191209 for you to fetch changes up to 6a4b07e08605ad171823021aa158b6b9bebfc6e6: imx8m: fix rom version check to unbreak some B0 chips (2019-12-09 11:52:06 +0100) Fixes for 2020.01 - - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support Anatolij Gustschin (1): imx: imx8qxp_mek: increase buffer sizes and args number Fabio Estevam (8): mx7ulp: Print the LDO mode status mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitions mx7ulp: scg: Remove unnused scg_a7_apll_init() mx7ulp: Sync the device tree related files mx6cuboxi: Add Baruch as maintainer mx6: Allow configuring the NoC registers on i.MX6QP warp7: Fix U-Boot corruption after saving the environment Frieder Schrempf (1): clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[] Igor Opaniuk (2): common: fdt_support: add support for setting usable memory board: colibri_imx7: reserve DDR memory for Cortex-M4 Marek Vasut (7): ARM: mx6: pmu: Expose PMU LDO configuration interface ARM: imx: vining2000: Convert to SPL framework ARM: imx: vining2000: Enable DDR DRAM calibration ARM: imx: vining2000: Convert to ethernet DM ARM: imx: vining2000: Enable fitImage support ARM: imx: vining2000: Repair PCIe support ARM: imx: vining2000: Align SOC and ARM LDO voltages Patrick Wildt (1): imx8m: fix rom version check to unbreak some B0 chips Tom Rini (1): tbs2910: Disable VxWorks image booting support arch/arm/dts/imx6sx-softing-vining-2000.dts | 17 ++ arch/arm/dts/imx7ulp-evk.dts| 157 +--- arch/arm/dts/imx7ulp-pinfunc.h | 1748 +++-- arch/arm/dts/imx7ulp.dtsi | 28 +- arch/arm/include/asm/arch-mx6/sys_proto.h |8 + arch/arm/include/asm/arch-mx7ulp/scg.h |1 - arch/arm/include/asm/mach-imx/sys_proto.h |2 + arch/arm/mach-imx/imx8m/soc.c |1 + arch/arm/mach-imx/mx6/Kconfig |1 + arch/arm/mach-imx/mx6/soc.c | 43 +++- arch/arm/mach-imx/mx7ulp/Kconfig|5 + arch/arm/mach-imx/mx7ulp/scg.c | 61 - arch/arm/mach-imx/mx7ulp/soc.c | 78 ++ board/softing/vining_2000/vining_2000.c | 256 --- board/solidrun/mx6cuboxi/MAINTAINERS|1 + board/toradex/colibri_imx7/colibri_imx7.c | 37 +++ common/fdt_support.c| 35 +++ configs/tbs2910_defconfig |1 + configs/vining_2000_defconfig | 18 +- configs/warp7_defconfig |2 +- drivers/clk/imx/clk-imx8mm.c|2 +- include/configs/imx8qxp_mek.h |5 + include/configs/vining_2000.h |6 +- include/configs/warp7.h | 13 + include/fdt_support.h |1 + 25 files changed, 1456 insertions(+), 1071 deletions(-) Regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
Re: [U-Boot-Board-Maintainers] Raspberry pi 4 - u-boot - genet / scb
Hello Sascha, > > Am 07.12.19 um 07:23 schrieb Sascha Dewald: > > > Hello, > > > > > > is there any progress yet ? Sorry for being late on this. We have made some progress, ping from RPI to host is working now. Also, managed to received short files(< 63KB) via TFTP. but haven't managed to get proper handshaking going(that would enable us to receive bigger files too). Working on it and keep you posted about the progress. Thanks -Amit
Re: [U-Boot] imx8m: fix rom version check to unbreak some B0 chips
On 07/12/19 16:29, Patrick Wildt wrote:
> Ping?
>
> On Tue, Nov 19, 2019 at 09:42:06AM +0100, Patrick Wildt wrote:
>> Recently the version check was improved to be able to determine that
>> we're running on SoC revision 2.1. A check for B0 was tightened so
>> that it now must equal 0x20 instead of being bigger than 0x20. On
>> some B0 chips the value returned is 0x1020 instead of 0x20. This
>> means even though it's B0, the check will fail and code relying on
>> the correct chip revision will make wrong decisions. There is no
>> documentation of those bits, but it seems that NXP always uses a
>> byte to encode the revision. Thus remove the upper bits to fix the
>> regression.
>>
>> Signed-off-by: Patrick Wildt
>>
I pick it up for 2020.01, thanks for remind !
Best regards,
Stefano Babic
>> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
>> index 9a203e4736..4d42368057 100644
>> --- a/arch/arm/mach-imx/imx8m/soc.c
>> +++ b/arch/arm/mach-imx/imx8m/soc.c
>> @@ -216,6 +216,7 @@ u32 get_cpu_rev(void)
>> readl((void __iomem *)ROM_VERSION_A0);
>> if (rom_version != CHIP_REV_1_0) {
>> rom_version = readl((void __iomem
>> *)ROM_VERSION_B0);
>> +rom_version &= 0xff;
>> if (rom_version == CHIP_REV_2_0)
>> reg = CHIP_REV_2_0;
>> }
>> ___
>> U-Boot mailing list
>> U-Boot@lists.denx.de
>> https://lists.denx.de/listinfo/u-boot
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
Re: [PATCH 11/20] clk: imx: add i.IMXRT1050 clk driver
Forgotten to ask you...
On 12/9/19 11:49 AM, Giulio Benetti wrote:
Hi Lukasz,
On 12/8/19 3:40 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:30 +0100
Giulio Benetti wrote:
Add i.MXRT1050 clk driver support.
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/Kconfig | 16 ++
drivers/clk/imx/Makefile| 2 +
drivers/clk/imx/clk-imxrt1050.c | 292
include/dt-bindings/clock/imxrt1050-clock.h |
65 + 4 files changed, 375 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1050.c
create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0ba8bc9f63..d5738b5211 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -52,3 +52,19 @@ config CLK_IMX8MN
select CLK_CCF
help
This enables support clock driver for i.MX8MN platforms.
+
+config SPL_CLK_IMXRT1050
+ bool "SPL clock support for i.MXRT1050"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in
i.MXRT1050 +
+config CLK_IMXRT1050
+ bool "Clock support for i.MXRT1050"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1050 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 222c5a4e08..166cb7bb44 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -14,3 +14,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o
clk-pll14xx.o \ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
clk-composite-8m.o
+
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imxrt1050.c
b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644
index 00..44ca52c013
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1050_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1050_clk_disable(struct clk *clk)
+{
+ return __imxrt1050_clk_enable(clk, 0);
+}
+
+static int imxrt1050_clk_enable(struct clk *clk)
+{
+ return __imxrt1050_clk_enable(clk, 1);
+}
+
+static struct clk_ops imxrt1050_clk_ops = {
+ .set_rate = imxrt1050_clk_set_rate,
+ .get_rate = imxrt1050_clk_get_rate,
+ .enable = imxrt1050_clk_enable,
+ .disable = imxrt1050_clk_disable,
+};
+
+static const char * const pll_ref_sels[] = {"osc", "dummy", };
+static const char * const pll1_bypass_sels[] = {"pll1_arm",
"pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[]
= {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const
pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
+static const char * const pll5_bypass_sels[] = {"pll5_video",
"pll5_video_ref_sel", }; + +static const char *const
pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m",
"arm_podf", }; +static const char *const periph_sels[] = {
"pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] =
{ "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const
lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const
semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static
const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
+static const char *const lcdif_sels[] = { "pll2_sys",
"pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m",
"pll2_pfd1_594m", "pll3_pfd1_664_62m"}; + +static int
imxrt1050_clk_probe(struct udevice *dev) +{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
+ imx_clk_mux("pll1_arm_ref_sel", base + 0x0,
Re: [PATCH 13/20] ARM: dts: imxrt1050: add dtsi file
Hi Lukasz,
On 12/8/19 3:46 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:32 +0100
Giulio Benetti wrote:
Add dtsi file for i.MXRT1050.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 146 +++
include/dt-bindings/pinctrl/pins-imxrt1050.h | 993
+++ 2 files changed, 1139 insertions(+)
create mode 100644 arch/arm/dts/imxrt1050.dtsi
create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
new file mode 100644
index 00..4fcca098aa
--- /dev/null
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ aliases {
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ mmc0 =
+ serial0 =
+ };
+
+ clocks {
+ u-boot,dm-spl;
+
+ osc {
+ u-boot,dm-spl;
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ semc: semc@402f {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f 0x4000>;
+ clocks = < IMXRT_CLK_SEMC>;
+ pinctrl-0 = <_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ lpuart1: serial@40184000 {
+ compatible = "fsl,imxrt-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = ;
+ clocks = < IMXRT_CLK_LPUART1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc@401f8000 {
+ compatible = "fsl,imxrt-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ clks: ccm@400fc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = ,
+;
+ #clock-cells = <1>;
+ };
+
+ usdhc1: usdhc@402c {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-usdhc";
+ reg = <0x402c 0x1>;
+ interrupts = ;
+ clocks = < IMXRT_CLK_USDHC1>;
+ clock-names = "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@401b8000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio",
"fsl,imx35-gpio";
+ reg = <0x401b8000 0x4000>;
+ interrupts = ,
+;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@401bc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio",
"fsl,imx35-gpio";
+ reg = <0x401bc000 0x4000>;
+ interrupts = ,
+ ;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@401c {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio",
"fsl,imx35-gpio";
+ reg = <0x401c 0x4000>;
+ interrupts = ,
+ ;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@401c4000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio",
"fsl,imx35-gpio";
+ reg = <0x401c4000 0x4000>;
+ interrupts = ,
+ ;
+
Re: [PATCH 11/20] clk: imx: add i.IMXRT1050 clk driver
Hi Lukasz,
On 12/8/19 3:40 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:30 +0100
Giulio Benetti wrote:
Add i.MXRT1050 clk driver support.
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/Kconfig | 16 ++
drivers/clk/imx/Makefile| 2 +
drivers/clk/imx/clk-imxrt1050.c | 292
include/dt-bindings/clock/imxrt1050-clock.h |
65 + 4 files changed, 375 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1050.c
create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0ba8bc9f63..d5738b5211 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -52,3 +52,19 @@ config CLK_IMX8MN
select CLK_CCF
help
This enables support clock driver for i.MX8MN platforms.
+
+config SPL_CLK_IMXRT1050
+ bool "SPL clock support for i.MXRT1050"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in
i.MXRT1050 +
+config CLK_IMXRT1050
+ bool "Clock support for i.MXRT1050"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1050 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 222c5a4e08..166cb7bb44 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -14,3 +14,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o
clk-pll14xx.o \ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
clk-composite-8m.o
+
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imxrt1050.c
b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644
index 00..44ca52c013
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1050_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1050_clk_disable(struct clk *clk)
+{
+ return __imxrt1050_clk_enable(clk, 0);
+}
+
+static int imxrt1050_clk_enable(struct clk *clk)
+{
+ return __imxrt1050_clk_enable(clk, 1);
+}
+
+static struct clk_ops imxrt1050_clk_ops = {
+ .set_rate = imxrt1050_clk_set_rate,
+ .get_rate = imxrt1050_clk_get_rate,
+ .enable = imxrt1050_clk_enable,
+ .disable = imxrt1050_clk_disable,
+};
+
+static const char * const pll_ref_sels[] = {"osc", "dummy", };
+static const char * const pll1_bypass_sels[] = {"pll1_arm",
"pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[]
= {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const
pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
+static const char * const pll5_bypass_sels[] = {"pll5_video",
"pll5_video_ref_sel", }; + +static const char *const
pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m",
"arm_podf", }; +static const char *const periph_sels[] = {
"pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] =
{ "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const
lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const
semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static
const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
+static const char *const lcdif_sels[] = { "pll2_sys",
"pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m",
"pll2_pfd1_594m", "pll3_pfd1_664_62m"}; + +static int
imxrt1050_clk_probe(struct udevice *dev) +{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
+ imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+
Re: [PATCH 02/20] spl: fix entry_point equal to load_addr
Hi Lukasz,
First of all thank you for reviewing my patches and...
On 12/8/19 3:37 PM, Lukasz Majewski wrote:
On Wed, 4 Dec 2019 18:44:21 +0100
Giulio Benetti wrote:
At the moment entry_point is set to image_get_load(header) that sets
it to "load address" instead of "entry point", assuming entry_point is
equal to load_addr, but it's not true. Then load_addr is set to
"entry_point - header_size", but this is wrong too since load_addr is
not an entry point.
So use image_get_ep() for entry_point assignment and image_get_load()
for load_addr assignment.
Signed-off-by: Giulio Benetti
---
common/spl/spl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d51dbe9942..24da164b43 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -264,9 +264,9 @@ int spl_parse_image_header(struct spl_image_info
*spl_image, spl_image->entry_point = image_get_ep(header);
spl_image->size =
image_get_data_size(header); } else {
- spl_image->entry_point =
image_get_load(header);
+ spl_image->entry_point =
image_get_ep(header); /* Load including the header */
- spl_image->load_addr =
spl_image->entry_point -
+ spl_image->load_addr =
image_get_load(header) - header_size;
spl_image->size =
image_get_data_size(header) + header_size;
This may not be the case - but I do recall that there was a similar
issue between u-boot.bin and u-boot.imx being loaded.
...I erroneously sent this patch again in this series but it's been
already committed and then reverted at the moment and will be committed
on next version since it breaks a lot of boards that assume that "load
address" and "entry point" are the same. Here is the discussion:
https://lists.denx.de/pipermail/u-boot/2019-December/393010.html
What is the format of i.MXRT?
i.MXRT is a cortex-M7, so it needs "load address" to be different from
"entry point", since entry point is offset of 0x3FD from "load address".
This is done in board defconfig with:
CONFIG_SYS_UBOOT_START
different from:
CONFIG_SYS_TEXT_BASE
I'm also concerned about breaking already supported in-tree boards. Why
i.MXRT needs to make this change? And why other boards don't need that
fix? (do they all have load address equal to entry point ?)
Indeed, all these boards assume load address and entry point to be the same.
Best regards
--
Giulio Benetti
Benetti Engineering sas
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
[PATCH v2 5/5] colibri_vf: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
Usage example:
> tftpboot ${loadaddr} ${board_name}/u-boot-nand.imx
> run update_uboot
Signed-off-by: Igor Opaniuk
---
include/configs/colibri_vf.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 40c050a27e..1478ea844e 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -58,6 +58,10 @@
"ramdisk_addr_r=0x8210\0" \
"scriptaddr=0x8700\0"
+#define UBOOT_UPDATE \
+ "update_uboot=nand erase.part u-boot && " \
+ "nand write ${loadaddr} u-boot ${filesize}\0" \
+
#define NFS_BOOTCMD \
"nfsargs=ip=:eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
@@ -112,6 +116,7 @@
NFS_BOOTCMD \
SD_BOOTCMD \
UBI_BOOTCMD \
+ UBOOT_UPDATE \
"console=ttyLP0\0" \
"defargs=user_debug=30\0" \
"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
--
2.17.1
[PATCH v2 0/5] toradex: imx: add update_uboot wrapper
This patch series introduces universtal update_uboot
wrapper that helps to update U-Boot image on internal storage.
Example of usage:
> tftpboot ${loadaddr} ${board_name}/u-boot.img
> run update_uboot
> tftpboot ${loadaddr} ${board_name}/SPL
> run update_spl
v2:
- remove uboot_hwpart defition for NAND setups
Igor Opaniuk (5):
colibri_imx7: add update_uboot wrapper
apalis_imx6: add update_uboot wrapper
colibri_imx6: add update_uboot wrapper
colibri-imx6ull: add update_uboot wrapper
colibri_vf: add update_uboot wrapper
include/configs/apalis_imx6.h | 12
include/configs/colibri-imx6ull.h | 7 +++
include/configs/colibri_imx6.h| 12
include/configs/colibri_imx7.h| 17 +
include/configs/colibri_vf.h | 5 +
5 files changed, 53 insertions(+)
--
2.17.1
[PATCH v2 4/5] colibri-imx6ull: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
Usage example:
> tftpboot ${loadaddr} ${board_name}/u-boot-nand.imx
> run update_uboot
Signed-off-by: Igor Opaniuk
---
include/configs/colibri-imx6ull.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/configs/colibri-imx6ull.h
b/include/configs/colibri-imx6ull.h
index 0c36a57a0e..ea5ba6bfce 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -47,6 +47,12 @@
"ramdisk_addr_r=0x8220\0" \
"scriptaddr=0x8700\0"
+#define UBOOT_UPDATE \
+ "update_uboot=nand erase.part u-boot1 && " \
+ "nand write ${loadaddr} u-boot1 ${filesize} && " \
+ "nand erase.part u-boot2 && " \
+ "nand write ${loadaddr} u-boot2 ${filesize}\0"
+
#define NFS_BOOTCMD \
"nfsargs=ip=:eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
@@ -83,6 +89,7 @@
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
UBI_BOOTCMD \
+ UBOOT_UPDATE \
"console=ttymxc0\0" \
"defargs=user_debug=30\0" \
"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
--
2.17.1
[PATCH v2 3/5] colibri_imx6: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
> tftpboot ${loadaddr} ${board_name}/u-boot.img
> run update_uboot
> tftpboot ${loadaddr} ${board_name}/SPL
> run update_spl
Signed-off-by: Igor Opaniuk
---
include/configs/colibri_imx6.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 95b5a14b59..750463ef47 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -110,6 +110,17 @@
"imx6dl-colibri-eval-v3.dtb fat 0 1;" \
"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=8a\0" \
+ "uboot_spl_blk=2\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+ "update_spl=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_spl_blk} ${blkcnt}\0"
+
#define EMMC_BOOTCMD \
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\
"rw,noatime rootfstype=ext4 " \
@@ -163,6 +174,7 @@
"fdt_fixup=;\0" \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
+ UBOOT_UPDATE \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
--
2.17.1
[PATCH v2 2/5] apalis_imx6: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
Usage example:
> tftpboot ${loadaddr} ${board_name}/u-boot.img
> run update_uboot
> tftpboot ${loadaddr} ${board_name}/SPL
> run update_spl
Signed-off-by: Igor Opaniuk
---
include/configs/apalis_imx6.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 50a4391cd4..800f27ccbb 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -121,6 +121,17 @@
"imx6q-apalis-eval.dtb fat 0 1;" \
"imx6q-apalis-cam-eval.dtb fat 0 1"
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=8a\0" \
+ "uboot_spl_blk=2\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+ "update_spl=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_spl_blk} ${blkcnt}\0"
+
#define EMMC_BOOTCMD \
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
"ro,noatime rootfstype=ext4 rootwait\0" \
@@ -178,6 +189,7 @@
"fdt_fixup=;\0" \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
+ UBOOT_UPDATE \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
--
2.17.1
[PATCH v2 1/5] colibri_imx7: add update_uboot wrapper
From: Igor Opaniuk
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.
Usage example:
> tftpboot ${loadaddr} ${board_name}/u-boot-dtb.imx
> run update_uboot
Signed-off-by: Igor Opaniuk
---
include/configs/colibri_imx7.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index d92db7192e..88e1be1ef5 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -43,6 +43,22 @@
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP192.168.10.1
+#if defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=2\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0"
+#elif defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
+#define UBOOT_UPDATE \
+ "update_uboot=nand erase.part u-boot1 && " \
+ "nand write ${loadaddr} u-boot1 ${filesize} && " \
+ "nand erase.part u-boot2 && " \
+ "nand write ${loadaddr} u-boot2 ${filesize}\0"
+#endif
+
#ifndef PARTS_DEFAULT
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
@@ -163,6 +179,7 @@
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
MODULE_EXTRA_ENV_SETTINGS \
+ UBOOT_UPDATE \
"boot_file=zImage\0" \
"console=ttymxc0\0" \
"defargs=\0" \
--
2.17.1
Re: [U-Boot] [PATCH 0/2] Add support for booting EFI FIT images
On Sun, Dec 08, 2019 at 01:25:27AM +0100, Heinrich Schuchardt wrote:
> On 11/28/19 8:20 AM, Heinrich Schuchardt wrote:
> > On 11/27/19 8:45 PM, Cristian Ciocaltea wrote:
> > > On Tue, Nov 26, 2019 at 07:31:39PM +0100, Heinrich Schuchardt wrote:
> > > > On 11/24/19 9:11 PM, Cristian Ciocaltea wrote:
> > > > > Currently the only way to run an EFI binary like GRUB2 is via the
> > > > > 'bootefi' command, which cannot be used in a verified boot scenario.
> > > > >
> > > > > The obvious solution to this limitation is to add support for
> > > > > booting FIT images containing those EFI binaries.
> > > > >
> > > > > The implementation relies on a new image type - IH_OS_EFI - which
> > > > > can be created by using 'os = "efi"' inside an ITS file:
> > > > >
> > > > > / {
> > > > > #address-cells = <1>;
> > > > >
> > > > > images {
> > > > > efi-grub {
> > > > > description = "GRUB EFI";
> > > > > data = /incbin/("EFI/BOOT/bootarm.efi");
> > > > > type = "kernel_noload";
> > > > > arch = "arm";
> > > > > os = "efi";
> > > > > compression = "none";
> > > > > load = <0x0>;
> > > > > entry = <0x0>;
> > > > > hash-1 {
> > > > > algo = "sha256";
> > > > > };
> > > > > };
> > > > > };
> > > > >
> > > > > configurations {
> > > > > default = "config-grub";
> > > > > config-grub {
> > > > > kernel = "efi-grub";
> > > > > signature-1 {
> > > > > algo = "sha256,rsa2048";
> > > > > sign-images = "kernel";
> > > > > };
> > > > > };
> > > > > };
> > > > > };
> > > > >
> > > > > The bootm command has been extended to handle the IH_OS_EFI images.
> > > > > To enable this feature, a new configuration option has been added:
> > > > > BOOTM_EFI
> > > > >
> > > > > I tested the solution using the 'qemu_arm' board:
> > > > >
> > > > > => load scsi 0:1 ${kernel_addr_r} efi-image.fit
> > > > > => bootm ${kernel_addr_r}#config-grub
> > > >
> > > > Thanks a lot for the patch series which makes good sense to me.
> > > >
> > > > I think we should pass addresses and not strings to cmd/bootefi.c. This
> > > > will need a bit of refactoring as already addressed in a comment to
> > > > patch 2/2.
> > > >
> > > > Additionally the documentation in doc/uefi/u-boot_on_efi.rst and
> > > > doc/uImage.FIT/howto.txt should be updated.
> > > >
> > > > I cc the contributors given by
> > > > scripts/get_maintainer.pl -f common/bootm_os.c
> > > >
> > > > Best regards
> > > >
> > > > Heinrich
> > > >
> > >
> > > Thanks for the feedback, Heinrich!
> > >
> > > Instead of creating new function(s), I think we could simply extend
> > > int do_bootefi_image(const char *image_opt)
> > > with a new parameter to hold the fdt address and move here the call
> > > to 'efi_install_fdt()', which is now performed by 'do_bootefi()'.
> >
> > efi_install_fdt() has to be called for the 'bootefi bootmgr' command too
> > so the refactoring is a bit more complicated. I have started on that.
> >
> > The first step is to change efi_install_fdt() to expect the argument as
> > address instead of a string.
> >
> > https://github.com/xypron/u-boot-patches/blob/efi-next/0001-efi_loader-pass-address-to-efi_install_fdt.patch
> >
> >
> > fdt_addr==NULL indicates no device tree supplied by user.
> >
> > Best regards
> >
> > Heinrich
> >
> > >
> > > However, I'm not sure about changing the data types, i.e. from
> > > 'char *' to ulong, for the following reasons:
> > > 1. image_opt may have a different meaning in addition to efi address
> > > 2. fdt address may not be provided, so we need somehow to detect an >>
> > > invalid value
> > >
> > > Kind regards,
> > > Cristian
> > >
>
> Hello Christian,
>
> patch series
> efi_loader: prepare for FIT images
> https://lists.denx.de/pipermail/u-boot/2019-December/393192.html
> is now available. It offers these functions:
>
> /* Install device tree */
> efi_status_t efi_install_fdt(uintptr_t fdt_addr);
> /* Run loaded UEFI image */
> efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size);
>
> Could you, please, rebase your patches on this patch series.
>
> Please, call efi_install_fdt with EFI_FDT_USE_INTERNAL if no device tree
> is supplied by the FIT image.
>
> The patch series is also available in branch efi-2020-04 at
> https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
>
> Best regards
>
> Heinrich
Hello Heinrich,
Thanks for the patch series!
I will send the updated patches by latest tomorrow EOD.
You also mentioned updating the documentation in
doc/uefi/u-boot_on_efi.rst and doc/uImage.FIT/howto.txt.
I've checked those documents and their content is quite generic,
not particularly related to this work. The former describes
how to build and run u-boot as an EFI
Pull request: socfpga-next
The following changes since commit b38c3a641fc01fcd4eda5fa107ae3c247baa0196:
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
(2019-12-08 10:51:00 -0500)
are available in the git repository at:
https://github.com/goldsimon/u-boot.git socfpga-next
for you to fetch changes up to ed2d3002c23d1c5632a03a64676102f0445d627e:
arm: socfpga: agilex: Enable Agilex SoC build (2019-12-09 08:49:51 +0100)
Ley Foon Tan (24):
spl: Allow cache drivers to be used in SPL
arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
arm: socfpga: Convert reset manager from struct to defines
arm: socfpga: Convert system manager from struct to defines
arm: socfpga: Convert clock manager from struct to defines
arm: socfpga: agilex: Add base address for Intel Agilex SoC
arm: socfpga: Move firewall code to firewall file
arm: socfpga: Move Stratix10 and Agilex reset manager common code
arm: socfpga: agilex: Add reset manager support
arm: socfpga: Move Stratix10 and Agilex system manager common code
arm: socfpga: agilex: Add system manager support
arm: socfpga: Move Stratix10 and Agilex clock manager common code
arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
clk: agilex: Add clock driver for Agilex
arm: socfpga: agilex: Add clock wrapper functions
cache: Add Arteris Ncore cache coherent unit driver
arm: agilex: Add clock handoff offset for Agilex
ddr: altera: Restructure Stratix 10 SDRAM driver
ddr: altera: agilex: Add SDRAM driver for Agilex
board: intel: agilex: Add socdk board support for Intel Agilex SoC
arm: socfpga: agilex: Add SPL for Agilex SoC
arm: dts: agilex: Add base dtsi and devkit dts
configs: socfpga: Move Stratix10 and Agilex common CONFIGs
arm: socfpga: agilex: Enable Agilex SoC build
arch/arm/Kconfig | 4 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga-common-u-boot.dtsi | 8 +
arch/arm/dts/socfpga.dtsi | 2 +-
arch/arm/dts/socfpga_agilex-u-boot.dtsi |
96 +++
arch/arm/dts/socfpga_agilex.dtsi |
622 +++
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 39 +
arch/arm/dts/socfpga_agilex_socdk.dts |
141 +++
arch/arm/dts/socfpga_arria10.dtsi | 2 +-
arch/arm/dts/socfpga_arria10_socdk.dtsi | 8 +
arch/arm/dts/socfpga_stratix10.dtsi | 2 +-
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 +
arch/arm/mach-socfpga/Kconfig | 16 ++
arch/arm/mach-socfpga/Makefile| 17 ++
arch/arm/mach-socfpga/clock_manager.c | 14 +-
arch/arm/mach-socfpga/clock_manager_agilex.c |
85 ++
arch/arm/mach-socfpga/clock_manager_arria10.c |
155 +
arch/arm/mach-socfpga/clock_manager_gen5.c|
211 +--
arch/arm/mach-socfpga/clock_manager_s10.c |
218 ++--
arch/arm/mach-socfpga/firewall.c |
107
arch/arm/mach-socfpga/include/mach/base_addr_s10.h| 4 +
arch/arm/mach-socfpga/include/mach/clock_manager.h| 4 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 14 ++
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h|
133 ++-
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h |
112 +---
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h|
131 ++
arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h | 21 +++
arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} | 10 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +-
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
arch/arm/mach-socfpga/include/mach/reset_manager.h| 7 +-
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h| 43 +
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h | 22 +--
arch/arm/mach-socfpga/include/mach/reset_manager_s10.h|
118 -
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 38 +
arch/arm/mach-socfpga/include/mach/system_manager.h | 7 +-
arch/arm/mach-socfpga/include/mach/system_manager_arria10.h |
94 +++---
