Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
Am 6. September 2021 07:22:21 MESZ schrieb Bin Meng :
>On Mon, Sep 6, 2021 at 12:45 PM Heinrich Schuchardt wrote:
>>
>> Am 6. September 2021 03:47:39 MESZ schrieb Bin Meng :
>> >On Mon, Sep 6, 2021 at 1:21 AM Heinrich Schuchardt
>> >wrote:
>> >>
>> >> On 9/5/21 7:00 PM, Bin Meng wrote:
>> >> > Hi Heinrich,
>> >> >
>> >> > On Mon, Sep 6, 2021 at 12:50 AM Heinrich Schuchardt
>> >> > wrote:
>> >> >>
>> >> >> On 9/5/21 1:59 PM, Bin Meng wrote:
>> >> >>> On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt
>> >> >>> wrote:
>> >>
>> >> Provide sysreset driver using the SBI system reset extension.
>> >>
>> >> >>>
>> >> >>> This patch should be split into 2 patches, one for adding the sysreset
>> >> >>> DM driver, and the other one for EFI support.
>> >> >>>
>> >> Signed-off-by: Heinrich Schuchardt
>> >> ---
>> >> v3:
>> >> no change
>> >> ---
>> >> MAINTAINERS | 1 +
>> >> arch/riscv/cpu/cpu.c| 13 -
>> >> arch/riscv/include/asm/sbi.h| 1 +
>> >> arch/riscv/lib/sbi.c| 21 ++--
>> >> drivers/sysreset/Kconfig| 11
>> >> drivers/sysreset/Makefile | 1 +
>> >> drivers/sysreset/sysreset_sbi.c | 96
>> >> +
>> >> lib/efi_loader/Kconfig | 2 +-
>> >> 8 files changed, 140 insertions(+), 6 deletions(-)
>> >> create mode 100644 drivers/sysreset/sysreset_sbi.c
>> >>
>> >> diff --git a/MAINTAINERS b/MAINTAINERS
>> >> index 4cf0c33c5d..88d7aa2bc7 100644
>> >> --- a/MAINTAINERS
>> >> +++ b/MAINTAINERS
>> >> @@ -1017,6 +1017,7 @@ T:git
>> >> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>> >> F: arch/riscv/
>> >> F: cmd/riscv/
>> >> F: doc/usage/sbi.rst
>> >> +F: drivers/sysreset/sysreset_sbi.c
>> >> F: drivers/timer/andes_plmt_timer.c
>> >> F: drivers/timer/sifive_clint_timer.c
>> >> F: tools/prelink-riscv.c
>> >> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
>> >> index c894ac10b5..8e49b6d736 100644
>> >> --- a/arch/riscv/cpu/cpu.c
>> >> +++ b/arch/riscv/cpu/cpu.c
>> >> @@ -6,6 +6,7 @@
>> >> #include
>> >> #include
>> >> #include
>> >> +#include
>> >> #include
>> >> #include
>> >> #include
>> >> @@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
>> >>
>> >> int arch_early_init_r(void)
>> >> {
>> >> - return riscv_cpu_probe();
>> >> + int ret;
>> >> +
>> >> + ret = riscv_cpu_probe();
>> >> + if (ret)
>> >> + return ret;
>> >> +
>> >> + if (IS_ENABLED(CONFIG_SYSRESET_SBI))
>> >> + device_bind_driver(gd->dm_root, "sbi-sysreset",
>> >> + "sbi-sysreset", NULL);
>> >> +
>> >> + return 0;
>> >> }
>> >>
>> >> /**
>> >> diff --git a/arch/riscv/include/asm/sbi.h
>> >> b/arch/riscv/include/asm/sbi.h
>> >> index e9caa78d17..69cddda245 100644
>> >> --- a/arch/riscv/include/asm/sbi.h
>> >> +++ b/arch/riscv/include/asm/sbi.h
>> >> @@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
>> >> long sbi_get_spec_version(void);
>> >> int sbi_get_impl_id(void);
>> >> int sbi_probe_extension(int ext);
>> >> +void sbi_srst_reset(unsigned long type, unsigned long reason);
>> >>
>> >> #endif
>> >> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
>> >> index 77845a73ca..8508041f2a 100644
>> >> --- a/arch/riscv/lib/sbi.c
>> >> +++ b/arch/riscv/lib/sbi.c
>> >> @@ -8,13 +8,14 @@
>> >> */
>> >>
>> >> #include
>> >> +#include
>> >> #include
>> >> #include
>> >>
>> >> -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
>> >> - unsigned long arg1, unsigned long arg2,
>> >> - unsigned long arg3, unsigned long arg4,
>> >> - unsigned long arg5)
>> >> +struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned
>> >> long arg0,
>> >> + unsigned long arg1, unsigned
>> >> long arg2,
>> >> + unsigned long arg3, unsigned
>> >> long arg4,
>> >> + unsigned long arg5)
>> >> {
>> >> struct sbiret ret;
>> >>
>> >> @@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
>> >> return -ENOTSUPP;
>> >> }
>> >>
>> >> +/**
>> >> + * sbi_srst_reset() - invoke system reset extension
>> >> + *
>> >> + * @type: type
Re: [PATCH] arm: mvebu : sata_mv should probe all ports
On 05.09.21 23:48, Tony Dinh wrote:
While a board could have multiple SATA ports, some of the ports might
not have a disk attached to them. So while probing for disks,
sata_mv_probe() should continue probing all ports, and skip one with
no disk attached.
Tests with:
- Seagate Goflex Net (Marvell Kirkwood 88F6281) out-of-tree u-boot.
- Zyxel NSA325 (Marvell Kirkwood 88F6282 out-of-tree u-boot.
Observation:
If a board has 2 or more SATA ports, and there is only one disk
attached to one of the ports, sata_mv_probe() does not return
a successful probe status. And if only one disk is attached to the
2nd port (i.e. port 1), it is not probed at all.
Patch Description:
Let sata_mv_probe() continues probing all ports, even if there
is error in probing a given port, and then return a successful
status if there is at least one port was probed successfully.
Signed-off-by: Tony Dinh
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/ata/sata_mv.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index dadb2c7c2e..003222d47b 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -1068,6 +1068,7 @@ static int sata_mv_probe(struct udevice *dev)
int nr_ports;
int ret;
int i;
+ int status = -ENODEV; /* If the probe fails to detected any SATA port */
/* Get number of ports of this SATA controller */
nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
@@ -1078,7 +1079,7 @@ static int sata_mv_probe(struct udevice *dev)
IF_TYPE_SATA, -1, 512, 0, );
if (ret) {
debug("Can't create device\n");
- return ret;
+ continue;
}
priv = dev_get_plat(blk);
@@ -1088,18 +1089,23 @@ static int sata_mv_probe(struct udevice *dev)
ret = sata_mv_init_sata(blk, i);
if (ret) {
debug("%s: Failed to init bus\n", __func__);
- return ret;
+ continue;
}
/* Scan SATA port */
ret = sata_mv_scan_sata(blk, i);
if (ret) {
debug("%s: Failed to scan bus\n", __func__);
- return ret;
+ continue;
}
+
+ /* If we got here, the current SATA port was probed
+* successfully, so set the probe status to successful.
+*/
+ status = 0;
}
- return 0;
+ return status;
}
static int sata_mv_scan(struct udevice *dev)
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
On Mon, Sep 6, 2021 at 12:45 PM Heinrich Schuchardt wrote:
>
> Am 6. September 2021 03:47:39 MESZ schrieb Bin Meng :
> >On Mon, Sep 6, 2021 at 1:21 AM Heinrich Schuchardt
> >wrote:
> >>
> >> On 9/5/21 7:00 PM, Bin Meng wrote:
> >> > Hi Heinrich,
> >> >
> >> > On Mon, Sep 6, 2021 at 12:50 AM Heinrich Schuchardt
> >> > wrote:
> >> >>
> >> >> On 9/5/21 1:59 PM, Bin Meng wrote:
> >> >>> On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt
> >> >>> wrote:
> >>
> >> Provide sysreset driver using the SBI system reset extension.
> >>
> >> >>>
> >> >>> This patch should be split into 2 patches, one for adding the sysreset
> >> >>> DM driver, and the other one for EFI support.
> >> >>>
> >> Signed-off-by: Heinrich Schuchardt
> >> ---
> >> v3:
> >> no change
> >> ---
> >> MAINTAINERS | 1 +
> >> arch/riscv/cpu/cpu.c| 13 -
> >> arch/riscv/include/asm/sbi.h| 1 +
> >> arch/riscv/lib/sbi.c| 21 ++--
> >> drivers/sysreset/Kconfig| 11
> >> drivers/sysreset/Makefile | 1 +
> >> drivers/sysreset/sysreset_sbi.c | 96
> >> +
> >> lib/efi_loader/Kconfig | 2 +-
> >> 8 files changed, 140 insertions(+), 6 deletions(-)
> >> create mode 100644 drivers/sysreset/sysreset_sbi.c
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 4cf0c33c5d..88d7aa2bc7 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -1017,6 +1017,7 @@ T:git
> >> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> >> F: arch/riscv/
> >> F: cmd/riscv/
> >> F: doc/usage/sbi.rst
> >> +F: drivers/sysreset/sysreset_sbi.c
> >> F: drivers/timer/andes_plmt_timer.c
> >> F: drivers/timer/sifive_clint_timer.c
> >> F: tools/prelink-riscv.c
> >> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> >> index c894ac10b5..8e49b6d736 100644
> >> --- a/arch/riscv/cpu/cpu.c
> >> +++ b/arch/riscv/cpu/cpu.c
> >> @@ -6,6 +6,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >> #include
> >> #include
> >> #include
> >> @@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
> >>
> >> int arch_early_init_r(void)
> >> {
> >> - return riscv_cpu_probe();
> >> + int ret;
> >> +
> >> + ret = riscv_cpu_probe();
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (IS_ENABLED(CONFIG_SYSRESET_SBI))
> >> + device_bind_driver(gd->dm_root, "sbi-sysreset",
> >> + "sbi-sysreset", NULL);
> >> +
> >> + return 0;
> >> }
> >>
> >> /**
> >> diff --git a/arch/riscv/include/asm/sbi.h
> >> b/arch/riscv/include/asm/sbi.h
> >> index e9caa78d17..69cddda245 100644
> >> --- a/arch/riscv/include/asm/sbi.h
> >> +++ b/arch/riscv/include/asm/sbi.h
> >> @@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
> >> long sbi_get_spec_version(void);
> >> int sbi_get_impl_id(void);
> >> int sbi_probe_extension(int ext);
> >> +void sbi_srst_reset(unsigned long type, unsigned long reason);
> >>
> >> #endif
> >> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> >> index 77845a73ca..8508041f2a 100644
> >> --- a/arch/riscv/lib/sbi.c
> >> +++ b/arch/riscv/lib/sbi.c
> >> @@ -8,13 +8,14 @@
> >> */
> >>
> >> #include
> >> +#include
> >> #include
> >> #include
> >>
> >> -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> >> - unsigned long arg1, unsigned long arg2,
> >> - unsigned long arg3, unsigned long arg4,
> >> - unsigned long arg5)
> >> +struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned
> >> long arg0,
> >> + unsigned long arg1, unsigned
> >> long arg2,
> >> + unsigned long arg3, unsigned
> >> long arg4,
> >> + unsigned long arg5)
> >> {
> >> struct sbiret ret;
> >>
> >> @@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
> >> return -ENOTSUPP;
> >> }
> >>
> >> +/**
> >> + * sbi_srst_reset() - invoke system reset extension
> >> + *
> >> + * @type: type of reset
> >> + * @reason:reason for reset
> >> + */
> >> +void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long
> >> reason)
> >> +{
> >>
Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
Am 6. September 2021 03:47:39 MESZ schrieb Bin Meng :
>On Mon, Sep 6, 2021 at 1:21 AM Heinrich Schuchardt wrote:
>>
>> On 9/5/21 7:00 PM, Bin Meng wrote:
>> > Hi Heinrich,
>> >
>> > On Mon, Sep 6, 2021 at 12:50 AM Heinrich Schuchardt
>> > wrote:
>> >>
>> >> On 9/5/21 1:59 PM, Bin Meng wrote:
>> >>> On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt
>> >>> wrote:
>>
>> Provide sysreset driver using the SBI system reset extension.
>>
>> >>>
>> >>> This patch should be split into 2 patches, one for adding the sysreset
>> >>> DM driver, and the other one for EFI support.
>> >>>
>> Signed-off-by: Heinrich Schuchardt
>> ---
>> v3:
>> no change
>> ---
>> MAINTAINERS | 1 +
>> arch/riscv/cpu/cpu.c| 13 -
>> arch/riscv/include/asm/sbi.h| 1 +
>> arch/riscv/lib/sbi.c| 21 ++--
>> drivers/sysreset/Kconfig| 11
>> drivers/sysreset/Makefile | 1 +
>> drivers/sysreset/sysreset_sbi.c | 96
>> +
>> lib/efi_loader/Kconfig | 2 +-
>> 8 files changed, 140 insertions(+), 6 deletions(-)
>> create mode 100644 drivers/sysreset/sysreset_sbi.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 4cf0c33c5d..88d7aa2bc7 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1017,6 +1017,7 @@ T:git
>> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>> F: arch/riscv/
>> F: cmd/riscv/
>> F: doc/usage/sbi.rst
>> +F: drivers/sysreset/sysreset_sbi.c
>> F: drivers/timer/andes_plmt_timer.c
>> F: drivers/timer/sifive_clint_timer.c
>> F: tools/prelink-riscv.c
>> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
>> index c894ac10b5..8e49b6d736 100644
>> --- a/arch/riscv/cpu/cpu.c
>> +++ b/arch/riscv/cpu/cpu.c
>> @@ -6,6 +6,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
>>
>> int arch_early_init_r(void)
>> {
>> - return riscv_cpu_probe();
>> + int ret;
>> +
>> + ret = riscv_cpu_probe();
>> + if (ret)
>> + return ret;
>> +
>> + if (IS_ENABLED(CONFIG_SYSRESET_SBI))
>> + device_bind_driver(gd->dm_root, "sbi-sysreset",
>> + "sbi-sysreset", NULL);
>> +
>> + return 0;
>> }
>>
>> /**
>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>> index e9caa78d17..69cddda245 100644
>> --- a/arch/riscv/include/asm/sbi.h
>> +++ b/arch/riscv/include/asm/sbi.h
>> @@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
>> long sbi_get_spec_version(void);
>> int sbi_get_impl_id(void);
>> int sbi_probe_extension(int ext);
>> +void sbi_srst_reset(unsigned long type, unsigned long reason);
>>
>> #endif
>> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
>> index 77845a73ca..8508041f2a 100644
>> --- a/arch/riscv/lib/sbi.c
>> +++ b/arch/riscv/lib/sbi.c
>> @@ -8,13 +8,14 @@
>> */
>>
>> #include
>> +#include
>> #include
>> #include
>>
>> -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
>> - unsigned long arg1, unsigned long arg2,
>> - unsigned long arg3, unsigned long arg4,
>> - unsigned long arg5)
>> +struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long
>> arg0,
>> + unsigned long arg1, unsigned long
>> arg2,
>> + unsigned long arg3, unsigned long
>> arg4,
>> + unsigned long arg5)
>> {
>> struct sbiret ret;
>>
>> @@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
>> return -ENOTSUPP;
>> }
>>
>> +/**
>> + * sbi_srst_reset() - invoke system reset extension
>> + *
>> + * @type: type of reset
>> + * @reason:reason for reset
>> + */
>> +void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long
>> reason)
>> +{
>> + sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
>> + 0, 0, 0, 0);
>> +}
>> +
>> #ifdef CONFIG_SBI_V01
>>
>> /**
>> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
>> index ac77ffbc8b..6782331181 100644
>> ---
[PATCH] efi_loader: boot_service_capability_min should be capitalized
boot_service_capability_min is constant, it should be capitalized.
Signed-off-by: Masahisa Kojima
---
include/efi_tcg2.h| 2 +-
lib/efi_loader/efi_tcg2.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index c99384fb00..5a1a36212e 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -130,7 +130,7 @@ struct efi_tcg2_boot_service_capability {
};
/* up to and including the vendor ID (manufacturer_id) field */
-#define boot_service_capability_min \
+#define BOOT_SERVICE_CAPABILITY_MIN \
offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks)
#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index b268a02976..62ae102033 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -607,8 +607,8 @@ efi_tcg2_get_capability(struct efi_tcg2_protocol *this,
goto out;
}
- if (capability->size < boot_service_capability_min) {
- capability->size = boot_service_capability_min;
+ if (capability->size < BOOT_SERVICE_CAPABILITY_MIN) {
+ capability->size = BOOT_SERVICE_CAPABILITY_MIN;
efi_ret = EFI_BUFFER_TOO_SMALL;
goto out;
}
--
2.17.1
Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
On Mon, Sep 6, 2021 at 1:21 AM Heinrich Schuchardt wrote:
>
> On 9/5/21 7:00 PM, Bin Meng wrote:
> > Hi Heinrich,
> >
> > On Mon, Sep 6, 2021 at 12:50 AM Heinrich Schuchardt
> > wrote:
> >>
> >> On 9/5/21 1:59 PM, Bin Meng wrote:
> >>> On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt
> >>> wrote:
>
> Provide sysreset driver using the SBI system reset extension.
>
> >>>
> >>> This patch should be split into 2 patches, one for adding the sysreset
> >>> DM driver, and the other one for EFI support.
> >>>
> Signed-off-by: Heinrich Schuchardt
> ---
> v3:
> no change
> ---
> MAINTAINERS | 1 +
> arch/riscv/cpu/cpu.c| 13 -
> arch/riscv/include/asm/sbi.h| 1 +
> arch/riscv/lib/sbi.c| 21 ++--
> drivers/sysreset/Kconfig| 11
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_sbi.c | 96 +
> lib/efi_loader/Kconfig | 2 +-
> 8 files changed, 140 insertions(+), 6 deletions(-)
> create mode 100644 drivers/sysreset/sysreset_sbi.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4cf0c33c5d..88d7aa2bc7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1017,6 +1017,7 @@ T:git
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> F: arch/riscv/
> F: cmd/riscv/
> F: doc/usage/sbi.rst
> +F: drivers/sysreset/sysreset_sbi.c
> F: drivers/timer/andes_plmt_timer.c
> F: drivers/timer/sifive_clint_timer.c
> F: tools/prelink-riscv.c
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index c894ac10b5..8e49b6d736 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -6,6 +6,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
>
> int arch_early_init_r(void)
> {
> - return riscv_cpu_probe();
> + int ret;
> +
> + ret = riscv_cpu_probe();
> + if (ret)
> + return ret;
> +
> + if (IS_ENABLED(CONFIG_SYSRESET_SBI))
> + device_bind_driver(gd->dm_root, "sbi-sysreset",
> + "sbi-sysreset", NULL);
> +
> + return 0;
> }
>
> /**
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index e9caa78d17..69cddda245 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
> long sbi_get_spec_version(void);
> int sbi_get_impl_id(void);
> int sbi_probe_extension(int ext);
> +void sbi_srst_reset(unsigned long type, unsigned long reason);
>
> #endif
> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> index 77845a73ca..8508041f2a 100644
> --- a/arch/riscv/lib/sbi.c
> +++ b/arch/riscv/lib/sbi.c
> @@ -8,13 +8,14 @@
> */
>
> #include
> +#include
> #include
> #include
>
> -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> - unsigned long arg1, unsigned long arg2,
> - unsigned long arg3, unsigned long arg4,
> - unsigned long arg5)
> +struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long
> arg0,
> + unsigned long arg1, unsigned long
> arg2,
> + unsigned long arg3, unsigned long
> arg4,
> + unsigned long arg5)
> {
> struct sbiret ret;
>
> @@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
> return -ENOTSUPP;
> }
>
> +/**
> + * sbi_srst_reset() - invoke system reset extension
> + *
> + * @type: type of reset
> + * @reason:reason for reset
> + */
> +void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long
> reason)
> +{
> + sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
> + 0, 0, 0, 0);
> +}
> +
> #ifdef CONFIG_SBI_V01
>
> /**
> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
> index ac77ffbc8b..6782331181 100644
> --- a/drivers/sysreset/Kconfig
> +++ b/drivers/sysreset/Kconfig
> @@ -85,6 +85,17 @@ config SYSRESET_PSCI
> Enable PSCI SYSTEM_RESET function call. To use this, PSCI
> firmware
>
Re: [PATCH] RFC: Support an EFI-loader bootflow
Hi Simon, On Fri, Sep 03, 2021 at 02:53:52AM -0600, Simon Glass wrote: > Hi Takahiro, > > On Thu, 2 Sept 2021 at 20:27, AKASHI Takahiro > wrote: > > > > Simon, > > > > On Thu, Sep 02, 2021 at 10:40:57AM -0600, Simon Glass wrote: > > > Hi Takahiro, > > > > > > On Tue, 31 Aug 2021 at 00:14, AKASHI Takahiro > > > wrote: > > > > > > > > Simon, > > > > > > > > On Sat, Aug 28, 2021 at 02:35:21PM -0600, Simon Glass wrote: > > > > > This is just a demonstration of how to support EFI loader using > > > > > bootflow. > > > > > Various things need cleaning up, not least that the naming needs to be > > > > > finalised. I will deal with that in the v2 series. > > > > > > > > > > In order to support multiple methods of booting from the same device, > > > > > we > > > > > should probably separate out the different implementations (syslinux, > > > > > EFI loader > > > > > > > > I still believe that we'd better add "removable media" support > > > > to UEFI boot manager first (and then probably call this functionality > > ^^ > > > > > > from bootflow?). > > > > > > > > I admit that, in this case, we will have an issue that we will not > > > > recognize any device which is plugged in dynamically after UEFI > > > > subsystem is initialized. But this issue will potentially exist > > > > even with your approach. > > > > > > That can be fixed by dropping the UEFI tables and using driver model > > > instead. I may have mentioned that :-) > > > > I'm afraid that you don't get my point above. > > > > > > > > > > > and soon bootmgr, > > > > > > > > What will you expect in UEFI boot manager case? > > > > Boot parameters (options) as well as the boot order are well defined > > > > by Boot and BootOrder variables. How are they fit into your scheme? > > > > > > I haven't looked at boot manager yet, but I can't imagine it > > > presenting an insurmountable challenge. > > > > I don't say it's challenging. > > Since you have not yet explained your idea about how to specify > > the *boot order* in your scheme, I wonder how "Boot"/"BootOrder" > > be treated and honored. > > There might be a parallel world again. > > Well as I mentioned, I haven't looked at it yet. The original question > was how to do EFI LOADER and I did a patch to show that. > > Are we likely to see mixed-boot environments, that use distro boot for > some OSes and EFI for others? I hope not as it would be confusing. EFI > is the parallel world, as I see it. Yeah, I absolutely agree here. That is why I constantly insist "removable media" support should be implemented in UEFI boot manager in the first place. Please remember that "removable media" support is part of UEFI specification, UEFI boot manager and hence "EFI LOADER". # By "removable media" support, I mean that the image to be loaded # is determined by searching for the default file path, or /EFI/BOOT/xxx.efi, # in the system partition. The media can be, say, a fixed (non-removable) # HD on the system. # This is definitely part of UEFI environment. > It should be easy enough for the 'bootmgr' bootflow to read the EFI > variables and select the correct ordering. As I understand it, EFI > does not support lazy boot, so it is acceptable to probe all the > devices before selecting one? > > > > > > > > > > But anyway, we can use the following commands to run a specific > > > > boot flow in UEFI world: > > > > => efidebug boot next 1(or whatever else); bootefi bootmgr > > > > > > OK. > > > > > > As you probably noticed I was trying to have bootflow connect directly > > > to the code that does the booting so that 'CONFIG_CMDLINE' can be > > > disabled (e.g. for security reasons) and the boot will still work. > > > > # Maybe, it sounds kinda chicken and egg. > > > > Even now, you can code this way :) > > > >efi_set_variable(u"BootNext", ..., u"Boot0001"); > >do_efibootmgr(); > > > > That's it. My concern is what I mentioned above. > > OK. But then you would need to export those functions. I think it > would be better to split up the logic a bit and move things out of the > cmd/ directory (at some point). If we don't take "mixed-boot environments", adding efibootmger to bootflow mechanism, or implementing efibootmger using bootflow, makes little sense. > > > > Just a note: > > In the current distro_bootcmd, UEFI boot manager is also called > > *every time* one of boot media in "boot_targets" is scanned/enumerated. > > But it will make little sense because the current boot manager only > > allows/requires users to specify both the boot device and the image file > > path explicitly in a boot option, i.e. "Boot" variable, and tries > > all the boot options in "BootOrder" until it successfully launches > > one of those images. > > Yes, is the idea of lazy boot entirely impossible? Or is it still > possible to do that to some extent, e.g. by scanning until you find > the first thing in the boot order? If I correctly understand what 'lazy boot' means here, you can do
Re: Pull request for efi-2021-10-rc4
On Sat, Sep 04, 2021 at 11:08:28PM +0300, Ilias Apalodimas wrote: > Hi Tom, > > On Sat, 4 Sept 2021 at 21:08, Tom Rini wrote: > > > > On Sat, Sep 04, 2021 at 08:02:49PM +0200, Heinrich Schuchardt wrote: > > > > > > > > > Am 4. September 2021 19:39:49 MESZ schrieb Tom Rini : > > > >On Sat, Sep 04, 2021 at 07:03:48PM +0200, Heinrich Schuchardt wrote: > > > >> > > > >> > > > >> Am 4. September 2021 16:37:22 MESZ schrieb Tom Rini > > > >> : > > > >> >On Sat, Sep 04, 2021 at 03:08:38PM +0200, Heinrich Schuchardt wrote: > > > >> >> > > > >> >> > > > >> >> Am 4. September 2021 15:01:11 MESZ schrieb Tom Rini > > > >> >> : > > > >> >> >On Sat, Sep 04, 2021 at 11:56:47AM +0200, Heinrich Schuchardt > > > >> >> >wrote: > > > >> >> > > > > >> >> >> Dear Tom, > > > >> >> >> > > > >> >> >> The following changes since commit > > > >> >> >> 94509b79b13e69c209199af0757afbde8d2ebd6d: > > > >> >> >> > > > >> >> >> btrfs: Use default subvolume as filesystem root (2021-09-01 > > > >> >> >> 10:11:24 > > > >> >> >> -0400) > > > >> >> >> > > > >> >> >> are available in the Git repository at: > > > >> >> >> > > > >> >> >> https://source.denx.de/u-boot/custodians/u-boot-efi.git > > > >> >> >> tags/efi-2021-10-rc4 > > > >> >> >> > > > >> >> >> for you to fetch changes up to > > > >> >> >> 1dfa494610c5469cc28cf1f8538abf4be6c00324: > > > >> >> >> > > > >> >> >> efi_loader: fix efi_tcg2_hash_log_extend_event() parameter > > > >> >> >> check > > > >> >> >> (2021-09-04 09:15:09 +0200) > > > >> >> >> > > > >> >> >> > > > >> >> >> Pull request for efi-2021-10-rc4 > > > >> >> >> > > > >> >> >> Documentation: > > > >> >> >> > > > >> >> >> Remove invalid reference to configuration variable in UEFI > > > >> >> >> doc > > > >> >> >> > > > >> >> >> UEFI: > > > >> >> >> > > > >> >> >> Parameter checks for the EFI_TCG2_PROTOCOL > > > >> >> >> Improve support of preseeding UEFI variables. > > > >> >> >> Correct the calculation of the size of loaded images. > > > >> >> >> Allow for UEFI images with zero VirtualSize > > > >> >> >> > > > >> >> >> > > > >> >> >> Heinrich Schuchardt (5): > > > >> >> >> efi_loader: sections with zero VirtualSize > > > >> >> >> efi_loader: rounding of image size > > > >> >> >> efi_loader: don't load signature database from file > > > >> >> >> efi_loader: efi_auth_var_type for AuditMode, DeployedMode > > > >> >> >> efi_loader: correct determination of secure boot state > > > >> >> >> > > > >> >> >> Masahisa Kojima (3): > > > >> >> >> efi_loader: add missing parameter check for > > > >> >> >> EFI_TCG2_PROTOCOL api > > > >> >> >> efi_loader: fix boot_service_capability_min calculation > > > >> >> >> efi_loader: fix efi_tcg2_hash_log_extend_event() parameter > > > >> >> >> check > > > >> >> > > > > >> >> >And I don't see Simon's revert in here either. And he asked you > > > >> >> >about > > > >> >> >that yesterday: > > > >> >> >https://lore.kernel.org/r/capnjgz3erdjf0jb9s-cjk6y+feuyrywf0hnkf2trib4dr4u...@mail.gmail.com/ > > > >> >> > > > > >> >> >So at this point, are you asserting there is nothing to revert? > > > >> >> > > > >> >> Never. Simons "revert" is breaking functionality. The concept for > > > >> >> suporting blobs in devicetrees supplied by a prior bootstage has > > > >> >> not been defined yet. > > > >> > > > > >> >And to be clearer, reverting something that was introduced in one rc > > > >> >in > > > >> >a later rc isn't breaking functionality. U-Boot releases (well, the > > > >> >non-rc ones for sure) are on a very regular schedule. External > > > >> >projects > > > >> >may not depend on some feature introduced at -rcN unless they're > > > >> >willing > > > >> >to accept that some changes could happen before release. > > > >> > > > > >> > > > >> There is no value delivered by Simon's series. Neither does the image > > > >> get smaller nor does it fix anything. If he wants to enforce a design, > > > >> it must work for all use cases. But this requires some conceptual work. > > > > > > > >Yes, and what's the rush to not do the conceptual work? If I recall > > > >part of the thread correctly, yes, Simon didn't get his objections in > > > >before the patches were merged, but it was early enough in the release > > > >cycle that taking a step back and reverting was a reasonable request. > > > >What he had said wouldn't have changed if he had gotten the email out a > > > >few days earlier. > > > > > > > >So yes, please merge Simon's revert, or post and merge new more minimal > > > >revert that brings things to the same functional end. There are > > > >objections to this implementation, and thus far Simon has been > > > >responding all of the requests to better clarify all of the related code > > > >and concepts that have been asked of him, so that in the end an > > > >implementation that
Re: [PATCH v2 3/4] sunxi: Support SPL in both eGON and TOC0 images
On Sat, 21 Aug 2021 23:46:47 -0500
Samuel Holland wrote:
Hi,
> SPL uses the image header to detect the boot device and to find the
> offset of the next U-Boot stage. Since this information is stored
> differently in the eGON and TOC0 image headers, add code to find the
> correct value based on the image type currently in use.
many thanks for determining this at runtime!
> Signed-off-by: Samuel Holland
> ---
>
> Changes in v2:
> - Moved SPL header signature checks out of sunxi_image.h
> - Refactored SPL header signature checks to use fewer casts
>
> arch/arm/include/asm/arch-sunxi/spl.h | 2 --
> arch/arm/mach-sunxi/board.c | 50 +++
> 2 files changed, 43 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/spl.h
> b/arch/arm/include/asm/arch-sunxi/spl.h
> index 58cdf806d9a..157b11e4897 100644
> --- a/arch/arm/include/asm/arch-sunxi/spl.h
> +++ b/arch/arm/include/asm/arch-sunxi/spl.h
> @@ -19,8 +19,6 @@
> #define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
> #define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
>
> -#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
> -
> uint32_t sunxi_get_boot_device(void);
>
> #endif
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index d9b04f75fc4..b6f92bdc5e7 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -244,12 +244,40 @@ void s_init(void)
>
> #define SUNXI_INVALID_BOOT_SOURCE-1
>
> -static int sunxi_get_boot_source(void)
> +static struct boot_file_head *sunxi_egon_get_head(void)
> {
> - if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
> - return SUNXI_INVALID_BOOT_SOURCE;
> + struct boot_file_head *egon_head = (void *)SPL_ADDR;
> +
> + if (memcmp(egon_head, BOOT0_MAGIC, 8)) /* eGON.BT0 */
For eGON the magic is not at the beginning of the struct, so you need:
memcmp(_head->magic, BOOT0_MAGIC, 8)
Otherwise 99.9% of all Allwinner users will be very disappointed ;-)
And there is another problem: For 32-bit SoCs the SPL address is
literally 0 (SRAM A1), so the return value in the successful case is
NULL as well :-(
Maybe have a function to return an enum (EGON, TOC0, NONE/FEL) instead?
After all the address will always be SPL_ADDR.
Cheers,
Andre
> + return NULL;
> +
> + return egon_head;
> +}
> +
> +static struct toc0_main_info *sunxi_toc0_get_info(void)
> +{
> + struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
> +
> + if (memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8)) /* TOC0.GLH */
> + return NULL;
>
> - return readb(SPL_ADDR + 0x28);
> + return toc0_info;
> +}
> +
> +static int sunxi_get_boot_source(void)
> +{
> + struct boot_file_head *egon_head;
> + struct toc0_main_info *toc0_info;
> +
> + egon_head = sunxi_egon_get_head();
> + if (egon_head)
> + return readb(_head->boot_media);
> + toc0_info = sunxi_toc0_get_info();
> + if (toc0_info)
> + return readb(_info->platform[0]);
> +
> + /* Not a valid image, so we must have been booted via FEL. */
> + return SUNXI_INVALID_BOOT_SOURCE;
> }
>
> /* The sunxi internal brom will try to loader external bootloader
> @@ -297,10 +325,18 @@ uint32_t sunxi_get_boot_device(void)
> #ifdef CONFIG_SPL_BUILD
> static u32 sunxi_get_spl_size(void)
> {
> - if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
> - return 0;
> + struct boot_file_head *egon_head;
> + struct toc0_main_info *toc0_info;
> +
> + egon_head = sunxi_egon_get_head();
> + if (egon_head)
> + return readl(_head->length);
> + toc0_info = sunxi_toc0_get_info();
> + if (toc0_info)
> + return readl(_info->length);
>
> - return readl(SPL_ADDR + 0x10);
> + /* Not a valid image, so use the default U-Boot offset. */
> + return 0;
> }
>
> /*
Re: [PATCH v2 2/4] tools: mkimage: Add Allwinner TOC0 support
On Sat, 21 Aug 2021 23:46:46 -0500
Samuel Holland wrote:
Hi Samuel,
> Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and
> secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the
> existing sunxi_egon image type. The secure boot ROM (SBROM) uses a
> completely different image type, known as TOC0.
>
> A TOC0 image is composed of a header and two or more items. One item
> is the firmware binary. The others form a chain linking the firmware
> signature to the root-of-trust public key (ROTPK), which has its hash
> burned in the SoC's eFuses. Signatures are made using RSA-2048 + SHA256.
>
> The pseudo-ASN.1 structure is manually assembled; this is done to work
> around bugs/quirks in the boot ROM, which vary between SoCs. This TOC0
> implementation has been verified to work with the A50, A64, H5, H6,
> and H616 SBROMs, and it may work with other SoCs.
many thanks for sending this, it really opens up those secure boards in
a nice and easy manner.
>
> Signed-off-by: Samuel Holland
> ---
>
> Changes in v2:
> - Moved certificate and key item structures out of sunxi_image.h
> - Renamed "main" and "item" variables for clarity
> - Improved error messages, and added a hint about key generation
> - Added a comment explaining the purpose of the various key files
> - Mentioned testing this code on A50 in the commit message
>
> arch/arm/Kconfig | 1 +
> common/image.c| 1 +
> include/image.h | 1 +
> include/sunxi_image.h | 36 ++
> tools/Makefile| 3 +-
> tools/sunxi_toc0.c| 907 ++
> 6 files changed, 948 insertions(+), 1 deletion(-)
> create mode 100644 tools/sunxi_toc0.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d692139199c..799fe7d43af 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1014,6 +1014,7 @@ config ARCH_SUNXI
> select SUNXI_GPIO
> select SYS_NS16550
> select SYS_THUMB_BUILD if !ARM64
> + select TOOLS_LIBCRYPTO
Can you hold this back until we get the SPL_IMAGE_TYPE_SUNXI_TOC0
symbol in patch 4/4, and make it dependent on that, or make this
"default y if ARCH_SUNXI" in TOOLS_LIBCRYPTO's definition?
Otherwise this somewhat needlessly requires OpenSSL for *every* sunxi
board build, even though there is no board using it at the moment.
> select USB if DISTRO_DEFAULTS
> select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
> select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
> diff --git a/common/image.c b/common/image.c
> index 59c52a1f9ad..8f1634c1206 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -191,6 +191,7 @@ static const table_entry_t uimage_type[] = {
> { IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable
> Image" },
> { IH_TYPE_COPRO, "copro", "Coprocessor Image"},
> { IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image"
> },
> + { IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
> },
> { -1, "", "", },
> };
>
> diff --git a/include/image.h b/include/image.h
> index e20f0b69d58..a4efc090309 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -284,6 +284,7 @@ enum {
> IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */
> IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/
> IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */
> + IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
>
> IH_TYPE_COUNT, /* Number of image types */
> };
> diff --git a/include/sunxi_image.h b/include/sunxi_image.h
> index 5b2055c0af3..399ad0be999 100644
> --- a/include/sunxi_image.h
> +++ b/include/sunxi_image.h
> @@ -9,9 +9,12 @@
> *
> * Shared between mkimage and the SPL.
> */
> +
> #ifndef SUNXI_IMAGE_H
> #define SUNXI_IMAGE_H
>
> +#include
> +
> #define BOOT0_MAGIC "eGON.BT0"
> #define BROM_STAMP_VALUE 0x5f0a6c39
> #define SPL_SIGNATURE"SPL" /* marks "sunxi" SPL header */
> @@ -79,4 +82,37 @@ struct boot_file_head {
> /* Compile time check to assure proper alignment of structure */
> typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct
> boot_file_head) % 32)];
>
> +struct toc0_main_info {
> + uint8_t name[8];
> + __le32 magic;
> + __le32 checksum;
> + __le32 serial;
> + __le32 status;
> + __le32 num_items;
> + __le32 length;
> + uint8_t platform[4];
> + uint8_t reserved[8];
> + uint8_t end[4];
> +};
I second Pali's request for "packed" here. A struct is a C language
feature to organise your data, not to model foreign data packets. Yes,
it is (ab)used for this (all over U-Boot), and the compilers we work
with happen to generate valid code here, but indeed the C standard
makes no promises, unless you use "packed". It shouldn't make
much difference
Re: [PATCH v3 1/3] efi_loader: don't load signature database from file
Heinrich,
On Thu, Sep 02, 2021 at 11:35:29AM +0200, Heinrich Schuchardt wrote:
> The UEFI specification requires that the signature database may only be
> stored in tamper-resistant storage. So these variable may not be read
> from an unsigned file.
Even with TF-A (or other methods) assumed, I think the behavior here is
too restrictive.
If you think TF-A provides the base for "chain of trust", all what you
need to do is to protect PK and all the other auth variables should be
allowed to be restored even from an unsafe file because the changes of
values will be verified anyway by UEFI system as long as SetVariable()
is used.
Please think about why UEFI specification defines both PK and KEK.
The ability of setting/modifying KEK will add more flexibility of system
configuration.
-Takahiro Akashi
> Signed-off-by: Heinrich Schuchardt
> ---
> include/efi_variable.h | 5 +++-
> lib/efi_loader/efi_var_common.c | 2 --
> lib/efi_loader/efi_var_file.c | 41 -
> lib/efi_loader/efi_variable.c | 2 +-
> 4 files changed, 30 insertions(+), 20 deletions(-)
>
> diff --git a/include/efi_variable.h b/include/efi_variable.h
> index 4623a64142..2d97655e1f 100644
> --- a/include/efi_variable.h
> +++ b/include/efi_variable.h
> @@ -161,10 +161,13 @@ efi_status_t __maybe_unused efi_var_collect(struct
> efi_var_file **bufp, loff_t *
> /**
> * efi_var_restore() - restore EFI variables from buffer
> *
> + * Only if @safe is set secure boot related variables will be restored.
> + *
> * @buf: buffer
> + * @safe:restoring from tamper-resistant storage
> * Return: status code
> */
> -efi_status_t efi_var_restore(struct efi_var_file *buf);
> +efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe);
>
> /**
> * efi_var_from_file() - read variables from file
> diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c
> index 3d92afe2eb..005c03ea5f 100644
> --- a/lib/efi_loader/efi_var_common.c
> +++ b/lib/efi_loader/efi_var_common.c
> @@ -32,10 +32,8 @@ static const struct efi_auth_var_name_type name_type[] = {
> {u"KEK", _global_variable_guid, EFI_AUTH_VAR_KEK},
> {u"db", _guid_image_security_database, EFI_AUTH_VAR_DB},
> {u"dbx", _guid_image_security_database, EFI_AUTH_VAR_DBX},
> - /* not used yet
> {u"dbt", _guid_image_security_database, EFI_AUTH_VAR_DBT},
> {u"dbr", _guid_image_security_database, EFI_AUTH_VAR_DBR},
> - */
> };
>
> static bool efi_secure_boot;
> diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c
> index de076b8cbc..c7c6805ed0 100644
> --- a/lib/efi_loader/efi_var_file.c
> +++ b/lib/efi_loader/efi_var_file.c
> @@ -148,9 +148,10 @@ error:
> #endif
> }
>
> -efi_status_t efi_var_restore(struct efi_var_file *buf)
> +efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe)
> {
> struct efi_var_entry *var, *last_var;
> + u16 *data;
> efi_status_t ret;
>
> if (buf->reserved || buf->magic != EFI_VAR_FILE_MAGIC ||
> @@ -160,21 +161,29 @@ efi_status_t efi_var_restore(struct efi_var_file *buf)
> return EFI_INVALID_PARAMETER;
> }
>
> - var = buf->var;
> last_var = (struct efi_var_entry *)((u8 *)buf + buf->length);
> - while (var < last_var) {
> - u16 *data = var->name + u16_strlen(var->name) + 1;
> -
> - if (var->attr & EFI_VARIABLE_NON_VOLATILE && var->length) {
> - ret = efi_var_mem_ins(var->name, >guid, var->attr,
> - var->length, data, 0, NULL,
> - var->time);
> - if (ret != EFI_SUCCESS)
> - log_err("Failed to set EFI variable %ls\n",
> - var->name);
> - }
> - var = (struct efi_var_entry *)
> - ALIGN((uintptr_t)data + var->length, 8);
> + for (var = buf->var; var < last_var;
> + var = (struct efi_var_entry *)
> +ALIGN((uintptr_t)data + var->length, 8)) {
> +
> + data = var->name + u16_strlen(var->name) + 1;
> +
> + /*
> + * Secure boot related and non-volatile variables shall only be
> + * restored from U-Boot's preseed.
> + */
> + if (!safe &&
> + (efi_auth_var_get_type(var->name, >guid) !=
> + EFI_AUTH_VAR_NONE ||
> + !(var->attr & EFI_VARIABLE_NON_VOLATILE)))
> + continue;
> + if (!var->length)
> + continue;
> + ret = efi_var_mem_ins(var->name, >guid, var->attr,
> + var->length, data, 0, NULL,
> + var->time);
> + if (ret != EFI_SUCCESS)
> + log_err("Failed to set EFI variable %ls\n", var->name);
> }
>
[PATCH v2] Rename CONFIG_SPL_FIT_SHAxxx to CONFIG_SPL_SHAxxx
Rename these options to align the use in common/image-fit.c else if (CONFIG_IS_ENABLED(SHA1) && strcmp(algo, "sha1") == 0) ... else if (CONFIG_IS_ENABLED(SHA256) && strcmp(algo, "sha256") == 0) ... else if (CONFIG_IS_ENABLED(SHA384) && strcmp(algo, "sha384") == 0) ... else if (CONFIG_IS_ENABLED(SHA512) && strcmp(algo, "sha512") == 0) ... Signed-off-by: Chia-Wei Wang --- v2: - fix typo in the commit title common/spl/Kconfig | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index c155a3b5fc..c771ae028b 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -439,7 +439,7 @@ config SPL_MD5 applications where images may be changed maliciously, you should consider SHA256 or SHA384. -config SPL_FIT_SHA1 +config SPL_SHA1 bool "Support SHA1" depends on SPL_FIT select SHA1 @@ -451,7 +451,7 @@ config SPL_FIT_SHA1 due to the expanding computing power available to brute-force attacks. For more security, consider SHA256 or SHA384. -config SPL_FIT_SHA256 +config SPL_SHA256 bool "Support SHA256" depends on SPL_FIT select SHA256 @@ -460,7 +460,7 @@ config SPL_FIT_SHA256 checksum is a 256-bit (32-byte) hash value used to check that the image contents have not been corrupted. -config SPL_FIT_SHA384 +config SPL_SHA384 bool "Support SHA384" depends on SPL_FIT select SHA384 @@ -471,7 +471,7 @@ config SPL_FIT_SHA384 image contents have not been corrupted. Use this for the highest security. -config SPL_FIT_SHA512 +config SPL_SHA512 bool "Support SHA512" depends on SPL_FIT select SHA512 -- 2.17.1
[PATCH] arm: mvebu : sata_mv should probe all ports
While a board could have multiple SATA ports, some of the ports might
not have a disk attached to them. So while probing for disks,
sata_mv_probe() should continue probing all ports, and skip one with
no disk attached.
Tests with:
- Seagate Goflex Net (Marvell Kirkwood 88F6281) out-of-tree u-boot.
- Zyxel NSA325 (Marvell Kirkwood 88F6282 out-of-tree u-boot.
Observation:
If a board has 2 or more SATA ports, and there is only one disk
attached to one of the ports, sata_mv_probe() does not return
a successful probe status. And if only one disk is attached to the
2nd port (i.e. port 1), it is not probed at all.
Patch Description:
Let sata_mv_probe() continues probing all ports, even if there
is error in probing a given port, and then return a successful
status if there is at least one port was probed successfully.
Signed-off-by: Tony Dinh
---
drivers/ata/sata_mv.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index dadb2c7c2e..003222d47b 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -1068,6 +1068,7 @@ static int sata_mv_probe(struct udevice *dev)
int nr_ports;
int ret;
int i;
+ int status = -ENODEV; /* If the probe fails to detected any SATA port */
/* Get number of ports of this SATA controller */
nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
@@ -1078,7 +1079,7 @@ static int sata_mv_probe(struct udevice *dev)
IF_TYPE_SATA, -1, 512, 0, );
if (ret) {
debug("Can't create device\n");
- return ret;
+ continue;
}
priv = dev_get_plat(blk);
@@ -1088,18 +1089,23 @@ static int sata_mv_probe(struct udevice *dev)
ret = sata_mv_init_sata(blk, i);
if (ret) {
debug("%s: Failed to init bus\n", __func__);
- return ret;
+ continue;
}
/* Scan SATA port */
ret = sata_mv_scan_sata(blk, i);
if (ret) {
debug("%s: Failed to scan bus\n", __func__);
- return ret;
+ continue;
}
+
+ /* If we got here, the current SATA port was probed
+* successfully, so set the probe status to successful.
+*/
+ status = 0;
}
- return 0;
+ return status;
}
static int sata_mv_scan(struct udevice *dev)
--
2.20.1
Booting from NAND on an Armada-370 based machine -> Invalid header checksum
Hello,
I'm trying to unbrick a Netgear ReadyNAS 104 (Armada 370). (I
accidentally erased the u-boot partition in NAND when I tried to change
the NAND partitioning to make the Debian bullseye kernel+initramfs fit.)
I have the Vendor U-Boot image that I can boot using kwboot. Its first
byte is 0x8b which is the right for NAND booting. The image's size is
0xda548 bytes.
I wrote the image to the start of NAND and verified it to be correctly
written:
Marvell>> nand read 0x210 0 0xda548
NAND read: device 0 offset 0x0, size 0xda548
894280 bytes read: OK
Marvell>> dhcp
egiga1 wait for link .Done - link up.
...
DHCP client bound to address 192.168.77.145
Marvell>> tftp 0x200 192.168.77.175:u-boot-rn104-2.0.img
Using egiga1 device
TFTP from server 192.168.77.175; our IP address is 192.168.77.145
Filename 'u-boot-rn104-2.0.img'.
Load address: 0x200
Loading: #
done
Bytes transferred = 894280 (da548 hex)
Marvell>> cmp.b 0x200 0x210 0xda548
Total of 894280 bytes were the same
There are no bad blocks in this area.
Also the checksum is right as far as I understand:
$ python3
...
>>> a = open("/srv/tftp/u-boot-rn104-2.0.img", "rb")
>>> data = a.read(0x14000)
>>> len(data)
81920
>>> hex(sum(data[:31]) + sum(data[32:]))
'0x79f616'
So the checksum field should be 0x16 (at offset 31), which it is:
Marvell>> md.b 0x210
0210: 8b 00 00 00 48 65 0c 00 01 01 00 40 00 40 01 00
He.@.@..
02100010: 00 00 00 00 00 00 00 00 00 02 01 00 00 00 01 16
02100020: 02 01 18 35 02 00 00 00 5b 00 00 00 00 00 00 00
...5[...
02100030: ff 5f 2d e9 1c 00 00 fa 00 00 a0 e3 ff 9f bd e8
._-.
Still when trying to boot I get:
BootROM 1.08
Booting from NAND flash
BootROM: Invalid header checksum
BootROM: Bad header at offset 0001
BootROM: Bad header at offset 0002
BootROM: Bad header at offset 0003
BootROM: Bad header at offset 0004
BootROM: Bad header at offset 0005
BootROM: Bad header at offset 0006
BootROM: Bad header at offset 0007
BootROM: Bad header at offset 0008
BootROM: Bad header at offset 0009
BootROM: Bad header at offset 000A
BootROM: Bad header at offset 000B
BootROM: Bad header at offset 000C
BootROM: Bad header at offset 000D
BootROM: Bad header at offset 000E
BootROM: Bad header at offset 000F
BootROM: Bad header at offset 0010
BootROM: Bad header at offset 0011
BootROM: Bad header at offset 0012
BootROM: Bad header at offset 0013
BootROM: Bad header at offset 0014
BootROM: Bad header at offset 0015
BootROM: Bad header at offset 0016
BootROM: Bad header at offset 0017
BootROM: Bad header at offset 0018
BootROM: Bad header at offset 0019
BootROM: Bad header at offset 001A
BootROM: Bad header at offset 001B
BootROM: Bad header at offset 001C
BootROM: Bad header at offset 001D
BootROM: Bad header at offset 001E
BootROM: Bad header at offset 001F
BootROM: Bad header at offset 0020
BootROM: Bad header at offset 0021
BootROM: Bad header at offset 0022
...
Is there anything obvious I'm missing or doing wrong? Does "Invalid
header checksum" indicate that the 0x16 is wrong or is there another
checksum anywhere that I missed? Any other idea?
If you have an idea and prefer irc over email, I hang around e.g. in
#mvlinux on libera as ukleinek.
Best regards
Uwe
signature.asc
Description: PGP signature
tftp time outs
Dear All, I've noticed that when u-boot is downloading files from a tftp server (e.g. vmlinuz, initrd etc.) it starts to time out quite heavily "##T #T #T..." if I simply ping the NIC of the raspberry 4b on which it's running. Thanks for any comment or suggestion on this behavior.
Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
On 9/5/21 7:00 PM, Bin Meng wrote:
Hi Heinrich,
On Mon, Sep 6, 2021 at 12:50 AM Heinrich Schuchardt wrote:
On 9/5/21 1:59 PM, Bin Meng wrote:
On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt wrote:
Provide sysreset driver using the SBI system reset extension.
This patch should be split into 2 patches, one for adding the sysreset
DM driver, and the other one for EFI support.
Signed-off-by: Heinrich Schuchardt
---
v3:
no change
---
MAINTAINERS | 1 +
arch/riscv/cpu/cpu.c| 13 -
arch/riscv/include/asm/sbi.h| 1 +
arch/riscv/lib/sbi.c| 21 ++--
drivers/sysreset/Kconfig| 11
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_sbi.c | 96 +
lib/efi_loader/Kconfig | 2 +-
8 files changed, 140 insertions(+), 6 deletions(-)
create mode 100644 drivers/sysreset/sysreset_sbi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4cf0c33c5d..88d7aa2bc7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1017,6 +1017,7 @@ T:git
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
+F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c894ac10b5..8e49b6d736 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
int arch_early_init_r(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_SBI))
+ device_bind_driver(gd->dm_root, "sbi-sysreset",
+ "sbi-sysreset", NULL);
+
+ return 0;
}
/**
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index e9caa78d17..69cddda245 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
+void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 77845a73ca..8508041f2a 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -8,13 +8,14 @@
*/
#include
+#include
#include
#include
-struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
- unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4,
- unsigned long arg5)
+struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
{
struct sbiret ret;
@@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
return -ENOTSUPP;
}
+/**
+ * sbi_srst_reset() - invoke system reset extension
+ *
+ * @type: type of reset
+ * @reason:reason for reset
+ */
+void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+}
+
#ifdef CONFIG_SBI_V01
/**
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index ac77ffbc8b..6782331181 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -85,6 +85,17 @@ config SYSRESET_PSCI
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SBI
+ bool "Enable support for SBI System Reset"
+ depends on RISCV_SMODE && SBI_V02
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system reset and poweroff via the SBI system reset extension.
+ If the SBI implementation provides the extension, is board specific.
+ The extension was introduced in version 0.3 of the SBI specification.
+ The SBI system reset driver supports the UEFI ResetSystem() service
+ at runtime.
+
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
TARGET_SOCFPGA_ARRIA10)
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index de81c399d7..8e00be0779 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) +=
Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
Hi Heinrich,
On Mon, Sep 6, 2021 at 12:50 AM Heinrich Schuchardt wrote:
>
> On 9/5/21 1:59 PM, Bin Meng wrote:
> > On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt
> > wrote:
> >>
> >> Provide sysreset driver using the SBI system reset extension.
> >>
> >
> > This patch should be split into 2 patches, one for adding the sysreset
> > DM driver, and the other one for EFI support.
> >
> >> Signed-off-by: Heinrich Schuchardt
> >> ---
> >> v3:
> >> no change
> >> ---
> >> MAINTAINERS | 1 +
> >> arch/riscv/cpu/cpu.c| 13 -
> >> arch/riscv/include/asm/sbi.h| 1 +
> >> arch/riscv/lib/sbi.c| 21 ++--
> >> drivers/sysreset/Kconfig| 11
> >> drivers/sysreset/Makefile | 1 +
> >> drivers/sysreset/sysreset_sbi.c | 96 +
> >> lib/efi_loader/Kconfig | 2 +-
> >> 8 files changed, 140 insertions(+), 6 deletions(-)
> >> create mode 100644 drivers/sysreset/sysreset_sbi.c
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 4cf0c33c5d..88d7aa2bc7 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -1017,6 +1017,7 @@ T:git
> >> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> >> F: arch/riscv/
> >> F: cmd/riscv/
> >> F: doc/usage/sbi.rst
> >> +F: drivers/sysreset/sysreset_sbi.c
> >> F: drivers/timer/andes_plmt_timer.c
> >> F: drivers/timer/sifive_clint_timer.c
> >> F: tools/prelink-riscv.c
> >> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> >> index c894ac10b5..8e49b6d736 100644
> >> --- a/arch/riscv/cpu/cpu.c
> >> +++ b/arch/riscv/cpu/cpu.c
> >> @@ -6,6 +6,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >> #include
> >> #include
> >> #include
> >> @@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
> >>
> >> int arch_early_init_r(void)
> >> {
> >> - return riscv_cpu_probe();
> >> + int ret;
> >> +
> >> + ret = riscv_cpu_probe();
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (IS_ENABLED(CONFIG_SYSRESET_SBI))
> >> + device_bind_driver(gd->dm_root, "sbi-sysreset",
> >> + "sbi-sysreset", NULL);
> >> +
> >> + return 0;
> >> }
> >>
> >> /**
> >> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> >> index e9caa78d17..69cddda245 100644
> >> --- a/arch/riscv/include/asm/sbi.h
> >> +++ b/arch/riscv/include/asm/sbi.h
> >> @@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
> >> long sbi_get_spec_version(void);
> >> int sbi_get_impl_id(void);
> >> int sbi_probe_extension(int ext);
> >> +void sbi_srst_reset(unsigned long type, unsigned long reason);
> >>
> >> #endif
> >> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> >> index 77845a73ca..8508041f2a 100644
> >> --- a/arch/riscv/lib/sbi.c
> >> +++ b/arch/riscv/lib/sbi.c
> >> @@ -8,13 +8,14 @@
> >>*/
> >>
> >> #include
> >> +#include
> >> #include
> >> #include
> >>
> >> -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> >> - unsigned long arg1, unsigned long arg2,
> >> - unsigned long arg3, unsigned long arg4,
> >> - unsigned long arg5)
> >> +struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long
> >> arg0,
> >> + unsigned long arg1, unsigned long
> >> arg2,
> >> + unsigned long arg3, unsigned long
> >> arg4,
> >> + unsigned long arg5)
> >> {
> >> struct sbiret ret;
> >>
> >> @@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
> >> return -ENOTSUPP;
> >> }
> >>
> >> +/**
> >> + * sbi_srst_reset() - invoke system reset extension
> >> + *
> >> + * @type: type of reset
> >> + * @reason:reason for reset
> >> + */
> >> +void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long
> >> reason)
> >> +{
> >> + sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
> >> + 0, 0, 0, 0);
> >> +}
> >> +
> >> #ifdef CONFIG_SBI_V01
> >>
> >> /**
> >> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
> >> index ac77ffbc8b..6782331181 100644
> >> --- a/drivers/sysreset/Kconfig
> >> +++ b/drivers/sysreset/Kconfig
> >> @@ -85,6 +85,17 @@ config SYSRESET_PSCI
> >>Enable PSCI SYSTEM_RESET function call. To use this, PSCI
> >> firmware
> >>must be running on your system.
> >>
> >> +config SYSRESET_SBI
> >> + bool "Enable support for SBI System Reset"
> >> + depends on RISCV_SMODE && SBI_V02
> >> + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
> >> + help
> >> + Enable system reset and poweroff via the SBI system reset
> >> extension.
> >> + If the SBI implementation provides the extension, is board
> >> specific.
> >> +
Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
On 9/5/21 1:59 PM, Bin Meng wrote:
On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt wrote:
Provide sysreset driver using the SBI system reset extension.
This patch should be split into 2 patches, one for adding the sysreset
DM driver, and the other one for EFI support.
Signed-off-by: Heinrich Schuchardt
---
v3:
no change
---
MAINTAINERS | 1 +
arch/riscv/cpu/cpu.c| 13 -
arch/riscv/include/asm/sbi.h| 1 +
arch/riscv/lib/sbi.c| 21 ++--
drivers/sysreset/Kconfig| 11
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_sbi.c | 96 +
lib/efi_loader/Kconfig | 2 +-
8 files changed, 140 insertions(+), 6 deletions(-)
create mode 100644 drivers/sysreset/sysreset_sbi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4cf0c33c5d..88d7aa2bc7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1017,6 +1017,7 @@ T:git
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
+F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c894ac10b5..8e49b6d736 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
int arch_early_init_r(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_SBI))
+ device_bind_driver(gd->dm_root, "sbi-sysreset",
+ "sbi-sysreset", NULL);
+
+ return 0;
}
/**
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index e9caa78d17..69cddda245 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
+void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 77845a73ca..8508041f2a 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -8,13 +8,14 @@
*/
#include
+#include
#include
#include
-struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
- unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4,
- unsigned long arg5)
+struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
{
struct sbiret ret;
@@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
return -ENOTSUPP;
}
+/**
+ * sbi_srst_reset() - invoke system reset extension
+ *
+ * @type: type of reset
+ * @reason:reason for reset
+ */
+void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+}
+
#ifdef CONFIG_SBI_V01
/**
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index ac77ffbc8b..6782331181 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -85,6 +85,17 @@ config SYSRESET_PSCI
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SBI
+ bool "Enable support for SBI System Reset"
+ depends on RISCV_SMODE && SBI_V02
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system reset and poweroff via the SBI system reset extension.
+ If the SBI implementation provides the extension, is board specific.
+ The extension was introduced in version 0.3 of the SBI specification.
+ The SBI system reset driver supports the UEFI ResetSystem() service
+ at runtime.
+
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
TARGET_SOCFPGA_ARRIA10)
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index de81c399d7..8e00be0779 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SBI) +=
Re: Booting from NAND on an Armada-370 based machine -> Invalid header checksum
Hello!
On Sunday 05 September 2021 17:48:16 Uwe Kleine-König wrote:
> Hello,
>
> I'm trying to unbrick a Netgear ReadyNAS 104 (Armada 370). (I
> accidentally erased the u-boot partition in NAND when I tried to change
> the NAND partitioning to make the Debian bullseye kernel+initramfs fit.)
>
> I have the Vendor U-Boot image that I can boot using kwboot. Its first
> byte is 0x8b which is the right for NAND booting. The image's size is
> 0xda548 bytes.
>
> I wrote the image to the start of NAND and verified it to be correctly
> written:
>
> Marvell>> nand read 0x210 0 0xda548
>
> NAND read: device 0 offset 0x0, size 0xda548
>894280 bytes read: OK
>
> Marvell>> dhcp
> egiga1 wait for link .Done - link up.
> ...
> DHCP client bound to address 192.168.77.145
>
> Marvell>> tftp 0x200 192.168.77.175:u-boot-rn104-2.0.img
> Using egiga1 device
> TFTP from server 192.168.77.175; our IP address is 192.168.77.145
> Filename 'u-boot-rn104-2.0.img'.
> Load address: 0x200
> Loading: #
> done
> Bytes transferred = 894280 (da548 hex)
>
> Marvell>> cmp.b 0x200 0x210 0xda548
> Total of 894280 bytes were the same
>
> There are no bad blocks in this area.
>
> Also the checksum is right as far as I understand:
>
> $ python3
> ...
> >>> a = open("/srv/tftp/u-boot-rn104-2.0.img", "rb")
> >>> data = a.read(0x14000)
> >>> len(data)
> 81920
> >>> hex(sum(data[:31]) + sum(data[32:]))
> '0x79f616'
>
> So the checksum field should be 0x16 (at offset 31), which it is:
>
> Marvell>> md.b 0x210
> 0210: 8b 00 00 00 48 65 0c 00 01 01 00 40 00 40 01 00
> He.@.@..
So...
Image version = 0x01
Header Size MSB = 0x01
Header Size LSB = 0x00 0x40 = 0x4000
So header size is 0x014000 = 81920
> 02100010: 00 00 00 00 00 00 00 00 00 02 01 00 00 00 01 16
>
Checksum = 0x16
Which seems that the header checksum is correct.
> 02100020: 02 01 18 35 02 00 00 00 5b 00 00 00 00 00 00 00
> ...5[...
> 02100030: ff 5f 2d e9 1c 00 00 fa 00 00 a0 e3 ff 9f bd e8
> ._-.
>
> Still when trying to boot I get:
>
> BootROM 1.08
> Booting from NAND flash
> BootROM: Invalid header checksum
> BootROM: Bad header at offset 0001
> BootROM: Bad header at offset 0002
> BootROM: Bad header at offset 0003
> BootROM: Bad header at offset 0004
> BootROM: Bad header at offset 0005
> BootROM: Bad header at offset 0006
> BootROM: Bad header at offset 0007
> BootROM: Bad header at offset 0008
> BootROM: Bad header at offset 0009
> BootROM: Bad header at offset 000A
> BootROM: Bad header at offset 000B
> BootROM: Bad header at offset 000C
> BootROM: Bad header at offset 000D
> BootROM: Bad header at offset 000E
> BootROM: Bad header at offset 000F
> BootROM: Bad header at offset 0010
> BootROM: Bad header at offset 0011
> BootROM: Bad header at offset 0012
> BootROM: Bad header at offset 0013
> BootROM: Bad header at offset 0014
> BootROM: Bad header at offset 0015
> BootROM: Bad header at offset 0016
> BootROM: Bad header at offset 0017
> BootROM: Bad header at offset 0018
> BootROM: Bad header at offset 0019
> BootROM: Bad header at offset 001A
> BootROM: Bad header at offset 001B
> BootROM: Bad header at offset 001C
> BootROM: Bad header at offset 001D
> BootROM: Bad header at offset 001E
> BootROM: Bad header at offset 001F
> BootROM: Bad header at offset 0020
> BootROM: Bad header at offset 0021
> BootROM: Bad header at offset 0022
> ...
>
> Is there anything obvious I'm missing or doing wrong? Does "Invalid
> header checksum" indicate that the 0x16 is wrong or is there another
> checksum anywhere that I missed? Any other idea?
Image version 1 has only one header checksum (at 0x1F) and one data
checksum (4 bytes at the end of data image). But data checksum can be
verified only after loading data image to the RAM, which can happen only
after executing binary headers. If you are using standard DDR training
(prevent in binary headers) then it should print some debug log on UART.
And if you do not see it then error should refer to header checksum at
0x1F offset.
Could you run latest version of 'mkimage -l' from U-Boot git master on
your image to verify that image is really valid?
> If you have an idea and prefer irc over email, I hang around e.g. in
> #mvlinux on libera as ukleinek.
>
> Best regards
> Uwe
[PATCH] mtd: spinand: macronix: Fix ECC Status Read
From: Haolin Li According to datasheet, the upper four bits are reserved or used for reflecting the ECC status of the accumulated pages. The error bits number for the worst segment of the current page is encoded on lower four bits. Fix it by masking the upper bits. This same issue has been already fixed in the linux kernel by: "mtd: spinand: macronix: Fix ECC Status Read" (sha1: f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d) Apply the same fix in the U-Boot driver. Signed-off-by: Haolin Li --- drivers/mtd/nand/spi/macronix.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index f4a8e81639..6d643a8000 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -14,6 +14,8 @@ #include #define SPINAND_MFR_MACRONIX 0xC2 +#define MACRONIX_ECCSR_MASK0x0F + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -59,7 +61,13 @@ static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr) SPI_MEM_OP_DUMMY(1, 1), SPI_MEM_OP_DATA_IN(1, eccsr, 1)); - return spi_mem_exec_op(spinand->slave, ); + int ret = spi_mem_exec_op(spinand->slave, ); + + if (ret) + return ret; + + *eccsr &= MACRONIX_ECCSR_MASK; + return 0; } static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, -- 2.25.1
Re: [PATCH] drivers: net: phy: in112525: fix out of bounds write
On Thu, Sep 2, 2021 at 2:44 PM Cosmin-Florin Aluchenesei
wrote:
>
> Changed declarations of line_temp, reg_addr and reg_data arrays in order to
> avoid out-of-bounds write which may be caused by the following writing:
> line_temp[column_cnt] = '\0'; (Increased size from 80 to 81).
>
> Signed-off-by: Cosmin-Florin Aluchenesei
> ---
> drivers/net/phy/in112525.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/phy/in112525.c b/drivers/net/phy/in112525.c
> index 2ce1ab1195..e286fa8f14 100644
> --- a/drivers/net/phy/in112525.c
> +++ b/drivers/net/phy/in112525.c
> @@ -224,9 +224,9 @@ struct phy_device *inphi_phydev;
>
> int in112525_upload_firmware(struct phy_device *phydev)
> {
> - char line_temp[0x50] = {0};
> - char reg_addr[0x50] = {0};
> - char reg_data[0x50] = {0};
> + char line_temp[0x51] = {0};
> + char reg_addr[0x51] = {0};
> + char reg_data[0x51] = {0};
> int i, line_cnt = 0, column_cnt = 0;
> struct in112525_reg_config fw_temp;
> char *addr = NULL;
> --
> 2.21.0
>
We don't have such a driver in U-boot upstream master, which tree are
you using ?
Re: Subject: [PATCH 0/6] Add support for SDM845 based boards, and SM-G9600
On Tue, Aug 31, 2021 at 11:42 AM Дмитрий Санковский wrote: > > From 94e21cc200e09c51752e4bb86cfac320a92c48a5 Mon Sep 17 00:00:00 2001 > From: Dzmitry Sankouski > Date: Tue, 31 Aug 2021 11:25:37 +0300 > Subject: [PATCH 0/6] Add support for SDM845 based boards, and SM-G9600 > > Snapdragon 845 - hi-end qualcomm chip, introduced in late 2017. > Mostly used in flagship phones and tablets of 2018. > Features: > - arm64 arch > - total of 8 Kryo 385 Gold / Silver cores > - Hexagon 685 DSP > - Adreno 630 GPU > > Tested only as second-stage bootloader. > > Samsung S9 SM-G9600 - Snapdragon SDM845 version of the phone, > for China \ Hong Kong markets. > Has unlockable bootloader, unlike SM-G960U (American market version), > which allows running u-boot as a chain-loaded bootloader. > > Dzmitry Sankouski (6): > serial: qcom: add support for GENI serial driver > spmi: msm: add arbiter version 5 support > pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoC > clocks: qcom: add clocks for SDM845 debug uart > SoC: qcom: add support for SDM845 > board: samsung: add Samsung Galaxy S9/S9+(SM-G96x0) board > > MAINTAINERS | 2 + > arch/arm/dts/Makefile | 1 + > arch/arm/dts/sdm845.dtsi | 118 > arch/arm/dts/starqltechn-uboot.dtsi | 39 ++ > arch/arm/dts/starqltechn.dts | 53 ++ > arch/arm/mach-snapdragon/Kconfig | 17 + > arch/arm/mach-snapdragon/Makefile | 4 + > arch/arm/mach-snapdragon/clock-sdm845.c | 92 +++ > arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + > arch/arm/mach-snapdragon/clock-snapdragon.h | 3 +- > .../include/mach/sysmap-sdm845.h | 42 ++ > arch/arm/mach-snapdragon/init_sdm845.c| 82 +++ > arch/arm/mach-snapdragon/pinctrl-sdm845.c | 44 ++ > arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + > arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + > arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 + > board/samsung/starqltechn/Kconfig | 14 + > board/samsung/starqltechn/MAINTAINERS | 6 + > board/samsung/starqltechn/Makefile| 9 + > board/samsung/starqltechn/starqltechn.c | 10 + > configs/starqltechn_defconfig | 33 + > .../serial/msm-geni-serial.txt| 6 + > drivers/gpio/msm_gpio.c | 1 + > drivers/gpio/pm8916_gpio.c| 8 +- > drivers/serial/Kconfig| 17 + > drivers/serial/Makefile | 1 + > drivers/serial/serial_msm_geni.c | 579 ++ > drivers/spmi/spmi-msm.c | 156 +++-- > include/configs/sdm845.h | 32 + > include/configs/starqltechn.h | 16 + > 30 files changed, 1365 insertions(+), 54 deletions(-) > create mode 100644 arch/arm/dts/sdm845.dtsi > create mode 100644 arch/arm/dts/starqltechn-uboot.dtsi > create mode 100644 arch/arm/dts/starqltechn.dts > create mode 100644 arch/arm/mach-snapdragon/clock-sdm845.c > create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h > create mode 100644 arch/arm/mach-snapdragon/init_sdm845.c > create mode 100644 arch/arm/mach-snapdragon/pinctrl-sdm845.c > create mode 100644 arch/arm/mach-snapdragon/sysmap-sdm845.c > create mode 100644 board/samsung/starqltechn/Kconfig > create mode 100644 board/samsung/starqltechn/MAINTAINERS > create mode 100644 board/samsung/starqltechn/Makefile > create mode 100644 board/samsung/starqltechn/starqltechn.c > create mode 100644 configs/starqltechn_defconfig > create mode 100644 doc/device-tree-bindings/serial/msm-geni-serial.txt > create mode 100644 drivers/serial/serial_msm_geni.c > create mode 100644 include/configs/sdm845.h > create mode 100644 include/configs/starqltechn.h > > -- > 2.20.1 > Hi. Nicely done, please run checkpatch on everything, I think I noticed some spacing errors, but I'm not certain. Also, please add board documentation file, the earlier snapdragon boards have an example under the board directory, but you should place yours under doc/board/qcom/sdm845.rst See the other boards there for reference. Thanks, Ramon.
Re: Subject: [PATCH 1/6 v3] serial: qcom: add support for GENI serial driver
On Thu, Sep 2, 2021 at 5:47 PM Дмитрий Санковский wrote: > > From e92b90fcc81565c39eefe63a56051736bd392716 Mon Sep 17 00:00:00 2001 > From: Dzmitry Sankouski > Date: Fri, 27 Aug 2021 17:47:22 +0300 > Subject: [PATCH 1/6 v3] serial: qcom: add support for GENI serial driver > > Generic Interface (GENI) Serial Engine (SE) based uart > can be found on newer qualcomm SOCs, starting from SDM845. > Tested on Samsung SM-G9600(starqltechn) > by chain-loading u-boot with stock bootloader. > > Signed-off-by: Dzmitry Sankouski > Cc: Ramon Fried > --- > Changes for v2: > - change functions return type to void, where possible > - remove '.' from summary line > Changes for v3: > - move function open brace on new line > - use tab between define name and value > - define: wrap expression with braces, remove braces from constants > > MAINTAINERS | 1 + > .../serial/msm-geni-serial.txt| 6 + > drivers/serial/Kconfig| 17 + > drivers/serial/Makefile | 1 + > drivers/serial/serial_msm_geni.c | 602 ++ > 5 files changed, 627 insertions(+) > create mode 100644 doc/device-tree-bindings/serial/msm-geni-serial.txt > create mode 100644 drivers/serial/serial_msm_geni.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 776ff703b9..52ddc99cda 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -390,6 +390,7 @@ F: drivers/gpio/msm_gpio.c > F: drivers/mmc/msm_sdhci.c > F: drivers/phy/msm8916-usbh-phy.c > F: drivers/serial/serial_msm.c > +F: drivers/serial/serial_msm_geni.c > F: drivers/smem/msm_smem.c > F: drivers/usb/host/ehci-msm.c > > diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt > b/doc/device-tree-bindings/serial/msm-geni-serial.txt > new file mode 100644 > index 00..9eadc2561b > --- /dev/null > +++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt > @@ -0,0 +1,6 @@ > +Qualcomm GENI UART > + > +Required properties: > +- compatible: must be "qcom,msm-geni-uart" > +- reg: start address and size of the registers > +- clock: interface clock (must accept baudrate as a frequency) > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > index 93348c0929..b420a5720d 100644 > --- a/drivers/serial/Kconfig > +++ b/drivers/serial/Kconfig > @@ -278,6 +278,14 @@ config DEBUG_UART_S5P >will need to provide parameters to make this work. The driver will >be available until the real driver-model serial is running. > > +config DEBUG_UART_MSM_GENI > + bool "Qualcomm snapdragon" > + depends on ARCH_SNAPDRAGON > + help > + Select this to enable a debug UART using the serial_msm driver. You > + will need to provide parameters to make this work. The driver will > + be available until the real driver-model serial is running. > + > config DEBUG_UART_MESON > bool "Amlogic Meson" > depends on MESON_SERIAL > @@ -783,6 +791,15 @@ config MSM_SERIAL >for example APQ8016 and MSM8916. >Single baudrate is supported in current implementation (115200). > > +config MSM_GENI_SERIAL > + bool "Qualcomm on-chip GENI UART" > + help > + Support UART based on Generic Interface (GENI) Serial Engine (SE), used on > Qualcomm Snapdragon SoCs. > + Should support all qualcomm SOCs with Qualcomm Universal Peripheral (QUP) > Wrapper cores, > + i.e. newer ones, starting from SDM845. > + Driver works in FIFO mode. > + Multiple baudrates supported. > + > config OCTEON_SERIAL_BOOTCMD > bool "MIPS Octeon PCI remote bootcmd input" > depends on ARCH_OCTEON > diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile > index 3cbea8156f..d44caf4ea2 100644 > --- a/drivers/serial/Makefile > +++ b/drivers/serial/Makefile > @@ -62,6 +62,7 @@ obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o > obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o > obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o > obj-$(CONFIG_MSM_SERIAL) += serial_msm.o > +obj-$(CONFIG_MSM_GENI_SERIAL) += serial_msm_geni.o > obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o > obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o > obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o > diff --git a/drivers/serial/serial_msm_geni.c > b/drivers/serial/serial_msm_geni.c > new file mode 100644 > index 00..391d47b538 > --- /dev/null > +++ b/drivers/serial/serial_msm_geni.c > @@ -0,0 +1,602 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Qualcomm GENI serial engine UART driver > + * > + * (C) Copyright 2021 Dzmitry Sankouski > + * > + * Based on Linux driver. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define UART_OVERSAMPLING 32 > +#define STALE_TIMEOUT 160 > +#define SE_UART_RX_STALE_CNT 0x294 > +#define S_GENI_CMD_ABORT (BIT(1)) > + > +#define SE_GENI_S_CMD_CTRL_REG 0x634 > +#define SE_GENI_M_CMD_CTRL_REG 0x604 > + > +/* GENI_M_CMD_CTRL_REG */ > +#define M_GENI_CMD_CANCEL
Re: Subject: [PATCH 6/6] board: samsung: add Samsung Galaxy S9/S9+(SM-G96x0) board
On Tue, Aug 31, 2021 at 11:46 AM Дмитрий Санковский
wrote:
>
> From 94e21cc200e09c51752e4bb86cfac320a92c48a5 Mon Sep 17 00:00:00 2001
> From: Dzmitry Sankouski
> Date: Sun, 29 Aug 2021 21:57:33 +0300
> Subject: [PATCH 6/6] board: samsung: add Samsung Galaxy S9/S9+(SM-G96x0) board
>
> Samsung S9 SM-G9600 - Snapdragon SDM845 version of the phone,
> for China \ Hong Kong markets.
> Has unlockable bootloader, unlike SM-G960U (American market version),
> which allows running u-boot as a chain-loaded bootloader.
>
> Signed-off-by: Dzmitry Sankouski
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/starqltechn-uboot.dtsi | 39 ++
> arch/arm/dts/starqltechn.dts| 53 +
> arch/arm/mach-snapdragon/Kconfig| 13 ++
> board/samsung/starqltechn/Kconfig | 14 +++
> board/samsung/starqltechn/MAINTAINERS | 6 +++
> board/samsung/starqltechn/Makefile | 9 +
> board/samsung/starqltechn/starqltechn.c | 10 +
> configs/starqltechn_defconfig | 33 +++
> include/configs/starqltechn.h | 16
> 10 files changed, 194 insertions(+)
> create mode 100644 arch/arm/dts/starqltechn-uboot.dtsi
> create mode 100644 arch/arm/dts/starqltechn.dts
> create mode 100644 board/samsung/starqltechn/Kconfig
> create mode 100644 board/samsung/starqltechn/MAINTAINERS
> create mode 100644 board/samsung/starqltechn/Makefile
> create mode 100644 board/samsung/starqltechn/starqltechn.c
> create mode 100644 configs/starqltechn_defconfig
> create mode 100644 include/configs/starqltechn.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 82a0790cc0..90d922dab7 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -467,6 +467,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb
> \
>
> dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
> dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
> +dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
>
> dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
>
> diff --git a/arch/arm/dts/starqltechn-uboot.dtsi
> b/arch/arm/dts/starqltechn-uboot.dtsi
> new file mode 100644
> index 00..d8d75e018a
> --- /dev/null
> +++ b/arch/arm/dts/starqltechn-uboot.dtsi
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski
> + *
> + */
> +
> +/
> +{
> + soc {
> + u-boot,dm-pre-reloc;
> + gcc {
> + clock-controller@10 {
> + u-boot,dm-pre-reloc;
> + };
> + serial@0xa84000 {
> + u-boot,dm-pre-reloc;
> + };
> + gpio_north@390 {
> + u-boot,dm-pre-reloc;
> + };
> + pinctrl@390 {
> + u-boot,dm-pre-reloc;
> + };
> + };
> + };
> +};
> +
> +_pon {
> + key_vol_down {
> + gpios = <_pon 1 0>;
> + label = "key_vol_down";
> + };
> + key_power {
> + gpios = <_pon 0 0>;
> + label = "key_power";
> + };
> +};
> diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
> new file mode 100644
> index 00..387420f30b
> --- /dev/null
> +++ b/arch/arm/dts/starqltechn.dts
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Samsung S9 SM-G9600 (starqltechn) board device tree source
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "sdm845.dtsi"
> +
> +/ {
> + model = "Samsung S9 (SM-G9600)";
> + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + aliases {
> + serial0 = _uart;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x8000 0 0xfe1b>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc: soc {
> + serial@0xa84000 {
> + status = "ok";
> + };
> +
> + pinctrl@390 {
> + muic_i2c: muic_i2c {
> + pins = "GPIO_33", "GPIO_34";
> + drive-strength = <0x2>;
> + function = "gpio";
> + bias-disable;
> + };
> + };
> + };
> +};
> +
> +#include "starqltechn-uboot.dtsi"
> diff --git a/arch/arm/mach-snapdragon/Kconfig
> b/arch/arm/mach-snapdragon/Kconfig
> index 1a6a608967..90c9fcca2c 100644
> --- a/arch/arm/mach-snapdragon/Kconfig
> +++ b/arch/arm/mach-snapdragon/Kconfig
> @@ -40,9 +40,22 @@ config TARGET_DRAGONBOARD820C
>- 3GiB RAM
>- 32GiB UFS drive
>
> +config TARGET_STARQLTECHN
> + bool "Samsung S9 SM-G9600(starqltechn)"
> + help
> + Support for Samsung S9 SM-G9600(starqltechn) board.
> + Features:
> + - Qualcomm Snapdragon SDM845 SoC
> + - 4GiB RAM
> + - 64GiB UFS drive
> + select MISC_INIT_R
> + select SDM845
> + select DM_ETH if NET
> +
> endchoice
>
> source "board/qualcomm/dragonboard410c/Kconfig"
> source "board/qualcomm/dragonboard820c/Kconfig"
> +source "board/samsung/starqltechn/Kconfig"
>
> endif
> diff --git a/board/samsung/starqltechn/Kconfig
>
Re: Subject: [PATCH 5/6] SoC: qcom: add support for SDM845
On Tue, Aug 31, 2021 at 11:45 AM Дмитрий Санковский
wrote:
>
> From 1deb063fe8d0e527b0fd412505b7614462c7fd19 Mon Sep 17 00:00:00 2001
> From: Dzmitry Sankouski
> Date: Sun, 29 Aug 2021 21:55:31 +0300
> Subject: [PATCH 5/6] SoC: qcom: add support for SDM845
>
> Hi-end qualcomm chip, introduced in late 2017.
> Mostly used in flagship phones and tablets of 2018.
> Features:
> - arm64 arch
> - total of 8 Kryo 385 Gold / Silver cores
> - Hexagon 685 DSP
> - Adreno 630 GPU
>
> Tested only as second-stage bootloader.
>
> Signed-off-by: Dzmitry Sankouski
> Cc: Ramon Fried
> ---
> arch/arm/dts/sdm845.dtsi | 118 ++
> arch/arm/mach-snapdragon/Kconfig | 4 +
> arch/arm/mach-snapdragon/Makefile | 4 +
> .../include/mach/sysmap-sdm845.h | 42 +++
> arch/arm/mach-snapdragon/init_sdm845.c| 82
> arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 +
> include/configs/sdm845.h | 32 +
> 7 files changed, 313 insertions(+)
> create mode 100644 arch/arm/dts/sdm845.dtsi
> create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
> create mode 100644 arch/arm/mach-snapdragon/init_sdm845.c
> create mode 100644 arch/arm/mach-snapdragon/sysmap-sdm845.c
> create mode 100644 include/configs/sdm845.h
>
> diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
> new file mode 100644
> index 00..bf32c6995d
> --- /dev/null
> +++ b/arch/arm/dts/sdm845.dtsi
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm SDM845 chip device tree source
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "skeleton64.dtsi"
> +
> +/ {
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0x>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@10 {
> + u-boot,dm-pre-reloc;
> + compatible = "qcom,gcc-sdm845";
> + reg = <0x0010 0x1f>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + gpio_north: gpio_north@390 {
> + u-boot,dm-pre-reloc;
> + #gpio-cells = <2>;
> + compatible = "qcom,sdm845-pinctrl";
> + reg = <0x390 0x40>;
> + gpio-count = <150>;
> + gpio-controller;
> + gpio-ranges = <_north 0 0 150>;
> + gpio-bank-name = "soc_north.";
> + };
> +
> + tlmm_north: pinctrl_north@390 {
> + u-boot,dm-pre-reloc;
> + compatible = "qcom,tlmm-sdm845";
> + reg = <0x0390 0x40>;
> + gpio-count = <150>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <_north 0 0 150>;
> +
> + /* DEBUG UART */
> + qup_uart9: qup-uart9-default {
> + pinmux {
> + pins = "GPIO_4", "GPIO_5";
> + function = "qup9";
> + };
> + };
> + };
> +
> + debug_uart: serial@0xa84000 {
> + compatible = "qcom,msm-geni-uart";
> + reg = <0xa84000 0x4000>;
> + reg-names = "se_phys";
> + clock-names = "se-clk";
> + clocks = < 0x58>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_uart9>;
> + qcom,wrapper-core = <0x8a>;
> + status = "disabled";
> + };
> +
> + spmi@c44 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0xc44 0x1100>,
> + <0xc60 0x200>,
> + <0xe60 0x10>;
> + reg-names = "cnfg", "core", "obsrvr";
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> +
> + qcom,revid@100 {
> + compatible = "qcom,qpnp-revid";
> + reg = <0x100 0x100>;
> + linux,phandle = <0x3ac>;
> + phandle = <0x3ac>;
> + };
> +
> + pmic0: pm8998@0 {
> + compatible = "qcom,spmi-pmic";
> + reg = <0x0 0x1>;
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> +
> + pm8998_pon: pm8998_pon@800 {
> + compatible = "qcom,pm8998-pwrkey";
> + reg = <0x800 0x100>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + gpio-bank-name="pm8998_key.";
> + };
> +
> + pm8998_gpios: pm8998_gpios@c000 {
> + compatible = "qcom,pm8998-gpio";
> + reg = <0xc000 0x1a00>;
> + gpio-controller;
> + gpio-count = <21>;
> + #gpio-cells = <2>;
> + gpio-bank-name="pm8998.";
> + };
> + };
> +
> + pmic1: pm8998@1 {
> + compatible = "qcom,spmi-pmic";
> + reg = <0x1 0x0>;
> + #address-cells = <0x2>;
> + #size-cells = <0x0>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/mach-snapdragon/Kconfig
> b/arch/arm/mach-snapdragon/Kconfig
> index 0ec74fa5d3..1a6a608967 100644
> --- a/arch/arm/mach-snapdragon/Kconfig
> +++ b/arch/arm/mach-snapdragon/Kconfig
> @@ -9,6 +9,10 @@ config SYS_MALLOC_F_LEN
> config SPL_SYS_MALLOC_F_LEN
> default 0x2000
>
> +config SDM845
> + bool "Qualcomm Snapdragon 845 SoC"
> + default n
> +
> choice
> prompt "Snapdragon board select"
>
> diff --git a/arch/arm/mach-snapdragon/Makefile
> b/arch/arm/mach-snapdragon/Makefile
> index 709919fce4..962855eb8c 100644
> --- a/arch/arm/mach-snapdragon/Makefile
> +++ b/arch/arm/mach-snapdragon/Makefile
> @@ -2,6 +2,9 @@
> #
> # (C) Copyright 2015 Mateusz Kulikowski
>
> +obj-$(CONFIG_SDM845) += clock-sdm845.o
> +obj-$(CONFIG_SDM845) += sysmap-sdm845.o
> +obj-$(CONFIG_SDM845) +=
Re: Subject: [PATCH 4/6] clocks: qcom: add clocks for SDM845 debug uart
On Tue, Aug 31, 2021 at 11:45 AM Дмитрий Санковский
wrote:
>
> From 647a2cd58fff0e9d7e232dc5970071c5c91bb09f Mon Sep 17 00:00:00 2001
> From: Dzmitry Sankouski
> Date: Sun, 29 Aug 2021 21:54:57 +0300
> Subject: [PATCH 4/6] clocks: qcom: add clocks for SDM845 debug uart
>
> Allows to change clock frequency of debug uart,
> thus supporting wide range of baudrates.
> Enable / disable functionality is not implemented yet.
> In most use cases of SDM845 (i.e. mobile phones and tablets)
> it's not needed, because qualcomm first stage bootloader leaves it
> initialized, and on the other hand there's no possibility to
> replace signed first stage bootloader with u-boot.
>
> Signed-off-by: Dzmitry Sankouski
> Cc: Ramon Fried
> ---
> arch/arm/mach-snapdragon/clock-sdm845.c | 92 +
> arch/arm/mach-snapdragon/clock-snapdragon.c | 1 +
> arch/arm/mach-snapdragon/clock-snapdragon.h | 3 +-
> 3 files changed, 95 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-snapdragon/clock-sdm845.c
>
> diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c
> b/arch/arm/mach-snapdragon/clock-sdm845.c
> new file mode 100644
> index 00..9572639238
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/clock-sdm845.c
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm SDM845
> + *
> + * (C) Copyright 2017 Jorge Ramirez Ortiz
> + * (C) Copyright 2021 Dzmitry Sankouski
> + *
> + * Based on Little Kernel driver, simplified
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "clock-snapdragon.h"
> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
> +
> +struct freq_tbl {
> + uint freq;
> + uint src;
> + u8 pre_div;
> + u16 m;
> + u16 n;
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> + F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
> + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> + F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> + F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> + F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> + F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> + F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> + F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
> + F(10240, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
> + F(11200, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
> + F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
> + F(12000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
> + F(12800, CFG_CLK_SRC_GPLL0, 1, 16, 75),
> + { }
> +};
> +
> +static const struct bcr_regs uart2_regs = {
> + .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
> + .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
> + .M = SE9_UART_APPS_M,
> + .N = SE9_UART_APPS_N,
> + .D = SE9_UART_APPS_D,
> +};
> +
> +const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
> +{
> + if (!f)
> + return NULL;
> +
> + if (!f->freq)
> + return f;
> +
> + for (; f->freq; f++)
> + if (rate <= f->freq)
> + return f;
> +
> + /* Default to our fastest rate */
> + return f - 1;
> +}
> +
> +static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
> +{
> + const struct freq_tbl *freq =
> qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
> +
> + clk_rcg_set_rate_mnd(priv->base, _regs,
> + freq->pre_div, freq->m, freq->n, freq->src);
> +
> + return 0;
> +}
> +
> +ulong msm_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case 0x58: /*UART2*/
> + return clk_init_uart(priv, rate);
> + default:
> + return 0;
> + }
> +}
> diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c
> b/arch/arm/mach-snapdragon/clock-snapdragon.c
> index 2b76371718..3deb08ac4a 100644
> --- a/arch/arm/mach-snapdragon/clock-snapdragon.c
> +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
> @@ -135,6 +135,7 @@ static const struct udevice_id msm_clk_ids[] = {
> { .compatible = "qcom,gcc-apq8016" },
> { .compatible = "qcom,gcc-msm8996" },
> { .compatible = "qcom,gcc-apq8096" },
> + { .compatible = "qcom,gcc-sdm845" },
> { }
> };
>
> diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h
> b/arch/arm/mach-snapdragon/clock-snapdragon.h
> index 58fab40a2e..2ac53b538d 100644
> --- a/arch/arm/mach-snapdragon/clock-snapdragon.h
> +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> - * Qualcomm APQ8016, APQ8096
> + * Qualcomm APQ8016, APQ8096, SDM845
> *
> * (C) Copyright 2017 Jorge Ramirez-Ortiz
> */
> @@ -9,6 +9,7 @@
>
> #define CFG_CLK_SRC_CXO (0 << 8)
> #define CFG_CLK_SRC_GPLL0 (1 << 8)
> +#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
> #define CFG_CLK_SRC_MASK (7 << 8)
>
> struct pll_vote_clk {
> --
> 2.20.1
>
Why can't we boot this directly and bypass the first stage bootloader ?
Reviewed-by: Ramon Fried
Re: Subject: [PATCH 3/6] pinctrl: qcom: add pinctrl and gpio drivers for SDM845
On Tue, Aug 31, 2021 at 11:44 AM Дмитрий Санковский
wrote:
>
> From 520bc565a5a6f62c59f87bbd15a194ee61c103af Mon Sep 17 00:00:00 2001
> From: Dzmitry Sankouski
> Date: Sun, 29 Aug 2021 21:53:40 +0300
> Subject: [PATCH 3/6] pinctrl: qcom: add pinctrl and gpio drivers for SDM845
> SoC
>
> Signed-off-by: Dzmitry Sankouski
> Cc: Ramon Fried
> ---
> arch/arm/mach-snapdragon/pinctrl-sdm845.c | 44 +++
> arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 +
> arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 +
> drivers/gpio/msm_gpio.c | 1 +
> drivers/gpio/pm8916_gpio.c| 8 ++--
> 5 files changed, 52 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/mach-snapdragon/pinctrl-sdm845.c
>
> diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c
> b/arch/arm/mach-snapdragon/pinctrl-sdm845.c
> new file mode 100644
> index 00..6d66582aa6
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/pinctrl-sdm845.c
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm SDM845 pinctrl
> + *
> + * (C) Copyright 2021 Dzmitry Sankouski
> + *
> + */
> +
> +#include "pinctrl-snapdragon.h"
> +#include
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN];
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> + {"qup9", 1},
> + {"gpio", 0},
> +};
> +
> +static const char *sdm845_get_function_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *sdm845_get_pin_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> + return pin_name;
> +}
> +
> +static unsigned int sdm845_get_function_mux(unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].val;
> +}
> +
> +struct msm_pinctrl_data sdm845_data = {
> + .pin_count = 150,
> + .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> + .get_function_name = sdm845_get_function_name,
> + .get_function_mux = sdm845_get_function_mux,
> + .get_pin_name = sdm845_get_pin_name,
> +};
> diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
> b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
> index e6b87c3573..c0ed943036 100644
> --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
> +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
> @@ -116,6 +116,7 @@ static struct pinctrl_ops msm_pinctrl_ops = {
> static const struct udevice_id msm_pinctrl_ids[] = {
> { .compatible = "qcom,tlmm-apq8016", .data = (ulong)_data },
> { .compatible = "qcom,tlmm-apq8096", .data = (ulong)_data },
> + { .compatible = "qcom,tlmm-sdm845", .data = (ulong)_data },
> { }
> };
>
> diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
> b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
> index 61d466f4d8..ea524312a0 100644
> --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
> +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
> @@ -27,5 +27,6 @@ struct pinctrl_function {
>
> extern struct msm_pinctrl_data apq8016_data;
> extern struct msm_pinctrl_data apq8096_data;
> +extern struct msm_pinctrl_data sdm845_data;
>
> #endif
> diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
> index e1ff84c1c0..a3c3cd7824 100644
> --- a/drivers/gpio/msm_gpio.c
> +++ b/drivers/gpio/msm_gpio.c
> @@ -120,6 +120,7 @@ static const struct udevice_id msm_gpio_ids[] = {
> { .compatible = "qcom,msm8916-pinctrl" },
> { .compatible = "qcom,apq8016-pinctrl" },
> { .compatible = "qcom,ipq4019-pinctrl" },
> + { .compatible = "qcom,sdm845-pinctrl" },
> { }
> };
>
> diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c
> index 40b0f2578b..7ad95784a8 100644
> --- a/drivers/gpio/pm8916_gpio.c
> +++ b/drivers/gpio/pm8916_gpio.c
> @@ -202,6 +202,7 @@ static int pm8916_gpio_of_to_plat(struct udevice *dev)
> static const struct udevice_id pm8916_gpio_ids[] = {
> { .compatible = "qcom,pm8916-gpio" },
> { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
> + { .compatible = "qcom,pm8998-gpio" },
> { }
> };
>
> @@ -266,7 +267,7 @@ static int pm8941_pwrkey_probe(struct udevice *dev)
> return log_msg_ret("bad type", -ENXIO);
>
> reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
> - if (reg != 0x1)
> + if ((reg & 0x5) == 0)
> return log_msg_ret("bad subtype", -ENXIO);
>
> return 0;
> @@ -287,11 +288,12 @@ static int pm8941_pwrkey_of_to_plat(struct udevice *dev)
> static const struct udevice_id pm8941_pwrkey_ids[] = {
> { .compatible = "qcom,pm8916-pwrkey" },
> { .compatible = "qcom,pm8994-pwrkey" },
> + { .compatible = "qcom,pm8998-pwrkey" },
> { }
> };
>
> -U_BOOT_DRIVER(pwrkey_pm8941) = {
> - .name = "pwrkey_pm8916",
> +U_BOOT_DRIVER(pwrkey_pm89xx) = {
> + .name = "pwrkey_pm89xx",
> .id = UCLASS_GPIO,
> .of_match = pm8941_pwrkey_ids,
> .of_to_plat = pm8941_pwrkey_of_to_plat,
> --
> 2.20.1
>
Reviewed-by: Ramon Fried
Re: Subject: [PATCH 2/6 v2] spmi: msm: add arbiter version 5 support
On Tue, Aug 31, 2021 at 11:43 AM Дмитрий Санковский
wrote:
>
> From b65826c49fee93dd7ded11a848814d8fa79fdb2e Mon Sep 17 00:00:00 2001
> From: Dzmitry Sankouski
> Date: Sat, 28 Aug 2021 13:53:42 +0300
> Subject: [PATCH 2/6 v2] spmi: msm: add arbiter version 5 support
>
> Currently driver supports only version 1 and 2.
> Version 5 has slightly different registers structure
>
> Signed-off-by: Dzmitry Sankouski
> Cc: Ramon Fried
> ---
> Changes for v2:
> - change string formats in debug statements
>
> MAINTAINERS | 1 +
> drivers/spmi/spmi-msm.c | 156 +++-
> 2 files changed, 107 insertions(+), 50 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 52ddc99cda..6b8b0783d2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -392,6 +392,7 @@ F: drivers/phy/msm8916-usbh-phy.c
> F: drivers/serial/serial_msm.c
> F: drivers/serial/serial_msm_geni.c
> F: drivers/smem/msm_smem.c
> +F: drivers/spmi/spmi-msm.c
> F: drivers/usb/host/ehci-msm.c
>
> ARM STI
> diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
> index 5a335e50aa..c5bc55bc6f 100644
> --- a/drivers/spmi/spmi-msm.c
> +++ b/drivers/spmi/spmi-msm.c
> @@ -19,39 +19,63 @@
> DECLARE_GLOBAL_DATA_PTR;
>
> /* PMIC Arbiter configuration registers */
> -#define PMIC_ARB_VERSION 0x
> -#define PMIC_ARB_VERSION_V2_MIN 0x2001
> -
> -#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
> -#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
> -
> -#define SPMI_REG_CMD0 0x0
> -#define SPMI_REG_CONFIG 0x4
> -#define SPMI_REG_STATUS 0x8
> -#define SPMI_REG_WDATA 0x10
> -#define SPMI_REG_RDATA 0x18
> -
> -#define SPMI_CMD_OPCODE_SHIFT 27
> -#define SPMI_CMD_SLAVE_ID_SHIFT 20
> -#define SPMI_CMD_ADDR_SHIFT 12
> -#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
> -#define SPMI_CMD_BYTE_CNT_SHIFT 0
> -
> -#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
> -#define SPMI_CMD_EXT_REG_READ_LONG 0x01
> -
> -#define SPMI_STATUS_DONE 0x1
> +#define PMIC_ARB_VERSION 0x
> +#define PMIC_ARB_VERSION_V2_MIN 0x2001
> +#define PMIC_ARB_VERSION_V3_MIN 0x3000
> +#define PMIC_ARB_VERSION_V5_MIN 0x5000
> +
> +#define APID_MAP_OFFSET_V1_V2_V3 (0x800)
> +#define APID_MAP_OFFSET_V5 (0x900)
> +#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
> +#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
> +#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
> +#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
> +
> +#define SPMI_REG_CMD0 0x0
> +#define SPMI_REG_CONFIG 0x4
> +#define SPMI_REG_STATUS 0x8
> +#define SPMI_REG_WDATA 0x10
> +#define SPMI_REG_RDATA 0x18
> +
> +#define SPMI_CMD_OPCODE_SHIFT 27
> +#define SPMI_CMD_SLAVE_ID_SHIFT 20
> +#define SPMI_CMD_ADDR_SHIFT 12
> +#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
> +#define SPMI_CMD_BYTE_CNT_SHIFT 0
> +
> +#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
> +#define SPMI_CMD_EXT_REG_READ_LONG 0x01
> +
> +#define SPMI_STATUS_DONE 0x1
> +
> +#define SPMI_MAX_CHANNELS 128
> +#define SPMI_MAX_SLAVES 16
> +#define SPMI_MAX_PERIPH 256
> +
> +enum arb_ver {
> + V1 = 1,
> + V2,
> + V3,
> + V5 = 5
> +};
>
> -#define SPMI_MAX_CHANNELS 128
> -#define SPMI_MAX_SLAVES 16
> -#define SPMI_MAX_PERIPH 256
> +/*
> + * PMIC arbiter version 5 uses different register offsets for read/write vs
> + * observer channels.
> + */
> +enum pmic_arb_channel {
> + PMIC_ARB_CHANNEL_RW,
> + PMIC_ARB_CHANNEL_OBS,
> +};
>
> struct msm_spmi_priv {
> - phys_addr_t arb_chnl; /* ARB channel mapping base */
> + phys_addr_t arb_chnl; /* ARB channel mapping base */
> phys_addr_t spmi_core; /* SPMI core */
> - phys_addr_t spmi_obs; /* SPMI observer */
> + phys_addr_t spmi_obs; /* SPMI observer */
> /* SPMI channel map */
> uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
> + /* SPMI bus arbiter version */
> + u32 arb_ver;
> };
>
> static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
> @@ -59,6 +83,7 @@ static int msm_spmi_write(struct udevice *dev, int usid,
> int pid, int off,
> {
> struct msm_spmi_priv *priv = dev_get_priv(dev);
> unsigned channel;
> + unsigned int ch_offset;
> uint32_t reg = 0;
>
> if (usid >= SPMI_MAX_SLAVES)
> @@ -69,8 +94,8 @@ static int msm_spmi_write(struct udevice *dev, int usid,
> int pid, int off,
> channel = priv->channel_map[usid][pid];
>
> /* Disable IRQ mode for the current channel*/
> - writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
> - SPMI_REG_CONFIG);
> + writel(0x0,
> + priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
>
> /* Write single byte */
> writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
> @@ -82,6 +107,12 @@ static int msm_spmi_write(struct udevice *dev, int usid,
> int pid, int off,
> reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
> reg |= 1; /* byte count */
>
> + if (priv->arb_ver == V5) {
> + ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
> + } else {
> + ch_offset = SPMI_CH_OFFSET(channel);
> + }
> +
> /* Send write command */
> writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) +
Re: [PATCH] serial: qcom: add support for GENI serial driver.
On Sat, Aug 28, 2021 at 1:05 PM Дмитрий Санковский wrote: > > From 7e77653742d9b6767ad1967dda2556f802ee9d60 Mon Sep 17 00:00:00 2001 > From: Dzmitry Sankouski > Date: Fri, 27 Aug 2021 17:47:22 +0300 > Subject: [PATCH] serial: qcom: add support for GENI serial driver. > > Generic Interface (GENI) Serial Engine (SE) based uart > can be found on newer qualcomm SOCs, starting from SDM845. > Tested on Samsung SM-G9600(starqltechn) > by chain-loading u-boot with stock bootloader. > > Signed-off-by: Dzmitry Sankouski > --- > MAINTAINERS | 1 + > .../serial/msm-geni-serial.txt| 6 + > drivers/serial/Kconfig| 17 + > drivers/serial/Makefile | 1 + > drivers/serial/serial_msm_geni.c | 605 ++ > 5 files changed, 630 insertions(+) > create mode 100644 doc/device-tree-bindings/serial/msm-geni-serial.txt > create mode 100644 drivers/serial/serial_msm_geni.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 776ff703b9..52ddc99cda 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -390,6 +390,7 @@ F: drivers/gpio/msm_gpio.c > F: drivers/mmc/msm_sdhci.c > F: drivers/phy/msm8916-usbh-phy.c > F: drivers/serial/serial_msm.c > +F: drivers/serial/serial_msm_geni.c > F: drivers/smem/msm_smem.c > F: drivers/usb/host/ehci-msm.c > > diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt > b/doc/device-tree-bindings/serial/msm-geni-serial.txt > new file mode 100644 > index 00..9eadc2561b > --- /dev/null > +++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt > @@ -0,0 +1,6 @@ > +Qualcomm GENI UART > + > +Required properties: > +- compatible: must be "qcom,msm-geni-uart" > +- reg: start address and size of the registers > +- clock: interface clock (must accept baudrate as a frequency) > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > index 93348c0929..b420a5720d 100644 > --- a/drivers/serial/Kconfig > +++ b/drivers/serial/Kconfig > @@ -278,6 +278,14 @@ config DEBUG_UART_S5P >will need to provide parameters to make this work. The driver will >be available until the real driver-model serial is running. > > +config DEBUG_UART_MSM_GENI > + bool "Qualcomm snapdragon" > + depends on ARCH_SNAPDRAGON > + help > + Select this to enable a debug UART using the serial_msm driver. You > + will need to provide parameters to make this work. The driver will > + be available until the real driver-model serial is running. > + > config DEBUG_UART_MESON > bool "Amlogic Meson" > depends on MESON_SERIAL > @@ -783,6 +791,15 @@ config MSM_SERIAL >for example APQ8016 and MSM8916. >Single baudrate is supported in current implementation (115200). > > +config MSM_GENI_SERIAL > + bool "Qualcomm on-chip GENI UART" > + help > + Support UART based on Generic Interface (GENI) Serial Engine (SE), used on > Qualcomm Snapdragon SoCs. > + Should support all qualcomm SOCs with Qualcomm Universal Peripheral (QUP) > Wrapper cores, > + i.e. newer ones, starting from SDM845. > + Driver works in FIFO mode. > + Multiple baudrates supported. > + > config OCTEON_SERIAL_BOOTCMD > bool "MIPS Octeon PCI remote bootcmd input" > depends on ARCH_OCTEON > diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile > index 3cbea8156f..d44caf4ea2 100644 > --- a/drivers/serial/Makefile > +++ b/drivers/serial/Makefile > @@ -62,6 +62,7 @@ obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o > obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o > obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o > obj-$(CONFIG_MSM_SERIAL) += serial_msm.o > +obj-$(CONFIG_MSM_GENI_SERIAL) += serial_msm_geni.o > obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o > obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o > obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o > diff --git a/drivers/serial/serial_msm_geni.c > b/drivers/serial/serial_msm_geni.c > new file mode 100644 > index 00..f3c6c329d3 > --- /dev/null > +++ b/drivers/serial/serial_msm_geni.c > @@ -0,0 +1,605 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Qualcomm GENI serial engine UART driver > + * > + * (C) Copyright 2021 Dzmitry Sankouski > + * > + * Based on Linux driver. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define UART_OVERSAMPLING (32) > +#define STALE_TIMEOUT (160) > +#define SE_UART_RX_STALE_CNT (0x294) > +#define S_GENI_CMD_ABORT (BIT(1)) > + > +#define SE_GENI_S_CMD_CTRL_REG (0x634) > +#define SE_GENI_M_CMD_CTRL_REG (0x604) > + > +/* GENI_M_CMD_CTRL_REG */ > +#define M_GENI_CMD_CANCEL BIT(2) > +#define M_GENI_CMD_ABORT BIT(1) > +#define M_GENI_DISABLE BIT(0) > + > +/* GENI_S_CMD0 fields */ > +#define S_OPCODE_MSK GENMASK(31, 27) > +#define S_OPCODE_SHFT 27 > +#define S_PARAMS_MSK GENMASK(26, 0) > + > +/* GENI_STATUS fields */ > +#define M_GENI_CMD_ACTIVE BIT(0) > +#define
Re: [PATCH v3 2/3] cmd/sbi: use constants instead of numerical values
On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt wrote: > > Use constants for extension IDs. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Sean Anderson > Reviewed-by: Leo Yu-Chi Liang > --- > v3: > no change > --- > cmd/riscv/sbi.c | 30 +++--- > 1 file changed, 15 insertions(+), 15 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v3 1/3] riscv: add missing SBI extension definitions
On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt wrote: > > Add the System Reset Extension and the Hart State Management Extension > definitions. > > Add missing RFENCE Extension enum values. > > The SBI 0.1 extension constants are needed for the sbi command. Remove > an #ifdef. > > Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > Signed-off-by: Heinrich Schuchardt > --- > v3: > add SBI_HSM_HART_STATUS_SUSPENDED, > SBI_HSM_HART_STATUS_SUSPEND_PENDING, > SBI_HSM_HART_STATUS_RESUME_PENDING > v2: > correct constants that were blindly copied from Linux > --- > arch/riscv/include/asm/sbi.h | 40 ++-- > 1 file changed, 38 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v3 3/3] sysreset: provide SBI based sysreset driver
On Sun, Sep 5, 2021 at 4:38 PM Heinrich Schuchardt wrote:
>
> Provide sysreset driver using the SBI system reset extension.
>
This patch should be split into 2 patches, one for adding the sysreset
DM driver, and the other one for EFI support.
> Signed-off-by: Heinrich Schuchardt
> ---
> v3:
> no change
> ---
> MAINTAINERS | 1 +
> arch/riscv/cpu/cpu.c| 13 -
> arch/riscv/include/asm/sbi.h| 1 +
> arch/riscv/lib/sbi.c| 21 ++--
> drivers/sysreset/Kconfig| 11
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_sbi.c | 96 +
> lib/efi_loader/Kconfig | 2 +-
> 8 files changed, 140 insertions(+), 6 deletions(-)
> create mode 100644 drivers/sysreset/sysreset_sbi.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4cf0c33c5d..88d7aa2bc7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1017,6 +1017,7 @@ T:git
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> F: arch/riscv/
> F: cmd/riscv/
> F: doc/usage/sbi.rst
> +F: drivers/sysreset/sysreset_sbi.c
> F: drivers/timer/andes_plmt_timer.c
> F: drivers/timer/sifive_clint_timer.c
> F: tools/prelink-riscv.c
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index c894ac10b5..8e49b6d736 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -6,6 +6,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
>
> int arch_early_init_r(void)
> {
> - return riscv_cpu_probe();
> + int ret;
> +
> + ret = riscv_cpu_probe();
> + if (ret)
> + return ret;
> +
> + if (IS_ENABLED(CONFIG_SYSRESET_SBI))
> + device_bind_driver(gd->dm_root, "sbi-sysreset",
> + "sbi-sysreset", NULL);
> +
> + return 0;
> }
>
> /**
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index e9caa78d17..69cddda245 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
> long sbi_get_spec_version(void);
> int sbi_get_impl_id(void);
> int sbi_probe_extension(int ext);
> +void sbi_srst_reset(unsigned long type, unsigned long reason);
>
> #endif
> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> index 77845a73ca..8508041f2a 100644
> --- a/arch/riscv/lib/sbi.c
> +++ b/arch/riscv/lib/sbi.c
> @@ -8,13 +8,14 @@
> */
>
> #include
> +#include
> #include
> #include
>
> -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> - unsigned long arg1, unsigned long arg2,
> - unsigned long arg3, unsigned long arg4,
> - unsigned long arg5)
> +struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5)
> {
> struct sbiret ret;
>
> @@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
> return -ENOTSUPP;
> }
>
> +/**
> + * sbi_srst_reset() - invoke system reset extension
> + *
> + * @type: type of reset
> + * @reason:reason for reset
> + */
> +void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long reason)
> +{
> + sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
> + 0, 0, 0, 0);
> +}
> +
> #ifdef CONFIG_SBI_V01
>
> /**
> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
> index ac77ffbc8b..6782331181 100644
> --- a/drivers/sysreset/Kconfig
> +++ b/drivers/sysreset/Kconfig
> @@ -85,6 +85,17 @@ config SYSRESET_PSCI
> Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
> must be running on your system.
>
> +config SYSRESET_SBI
> + bool "Enable support for SBI System Reset"
> + depends on RISCV_SMODE && SBI_V02
> + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
> + help
> + Enable system reset and poweroff via the SBI system reset extension.
> + If the SBI implementation provides the extension, is board specific.
> + The extension was introduced in version 0.3 of the SBI
> specification.
> + The SBI system reset driver supports the UEFI ResetSystem() service
> + at runtime.
> +
> config SYSRESET_SOCFPGA
> bool "Enable support for Intel SOCFPGA family"
> depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
> TARGET_SOCFPGA_ARRIA10)
> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
> index de81c399d7..8e00be0779 100644
> --- a/drivers/sysreset/Makefile
> +++ b/drivers/sysreset/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
>
[PATCH v3 3/3] sysreset: provide SBI based sysreset driver
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt
---
v3:
no change
---
MAINTAINERS | 1 +
arch/riscv/cpu/cpu.c| 13 -
arch/riscv/include/asm/sbi.h| 1 +
arch/riscv/lib/sbi.c| 21 ++--
drivers/sysreset/Kconfig| 11
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_sbi.c | 96 +
lib/efi_loader/Kconfig | 2 +-
8 files changed, 140 insertions(+), 6 deletions(-)
create mode 100644 drivers/sysreset/sysreset_sbi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4cf0c33c5d..88d7aa2bc7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1017,6 +1017,7 @@ T:git
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
+F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c894ac10b5..8e49b6d736 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -138,7 +139,17 @@ int arch_cpu_init_dm(void)
int arch_early_init_r(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_SBI))
+ device_bind_driver(gd->dm_root, "sbi-sysreset",
+ "sbi-sysreset", NULL);
+
+ return 0;
}
/**
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index e9caa78d17..69cddda245 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -154,5 +154,6 @@ void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
+void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 77845a73ca..8508041f2a 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -8,13 +8,14 @@
*/
#include
+#include
#include
#include
-struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
- unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4,
- unsigned long arg5)
+struct sbiret __efi_runtime sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
{
struct sbiret ret;
@@ -108,6 +109,18 @@ int sbi_probe_extension(int extid)
return -ENOTSUPP;
}
+/**
+ * sbi_srst_reset() - invoke system reset extension
+ *
+ * @type: type of reset
+ * @reason:reason for reset
+ */
+void __efi_runtime sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+}
+
#ifdef CONFIG_SBI_V01
/**
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index ac77ffbc8b..6782331181 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -85,6 +85,17 @@ config SYSRESET_PSCI
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SBI
+ bool "Enable support for SBI System Reset"
+ depends on RISCV_SMODE && SBI_V02
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system reset and poweroff via the SBI system reset extension.
+ If the SBI implementation provides the extension, is board specific.
+ The extension was introduced in version 0.3 of the SBI specification.
+ The SBI system reset driver supports the UEFI ResetSystem() service
+ at runtime.
+
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
TARGET_SOCFPGA_ARRIA10)
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index de81c399d7..8e00be0779 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
diff --git a/drivers/sysreset/sysreset_sbi.c b/drivers/sysreset/sysreset_sbi.c
new file
[PATCH v3 2/3] cmd/sbi: use constants instead of numerical values
Use constants for extension IDs.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Sean Anderson
Reviewed-by: Leo Yu-Chi Liang
---
v3:
no change
---
cmd/riscv/sbi.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 90c0811e14..65a2c93290 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -29,21 +29,21 @@ static struct sbi_imp implementations[] = {
};
static struct sbi_ext extensions[] = {
- { 0x, "sbi_set_timer" },
- { 0x0001, "sbi_console_putchar" },
- { 0x0002, "sbi_console_getchar" },
- { 0x0003, "sbi_clear_ipi" },
- { 0x0004, "sbi_send_ipi" },
- { 0x0005, "sbi_remote_fence_i" },
- { 0x0006, "sbi_remote_sfence_vma" },
- { 0x0007, "sbi_remote_sfence_vma_asid" },
- { 0x0008, "sbi_shutdown" },
- { 0x0010, "SBI Base Functionality" },
- { 0x54494D45, "Timer Extension" },
- { 0x00735049, "IPI Extension" },
- { 0x52464E43, "RFENCE Extension" },
- { 0x0048534D, "Hart State Management Extension" },
- { 0x53525354, "System Reset Extension" },
+ { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" },
+ { SBI_EXT_0_1_CONSOLE_PUTCHAR,"sbi_console_putchar" },
+ { SBI_EXT_0_1_CONSOLE_GETCHAR,"sbi_console_getchar" },
+ { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" },
+ { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" },
+ { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" },
+ { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" },
+ { SBI_EXT_BASE, "SBI Base Functionality" },
+ { SBI_EXT_TIME, "Timer Extension" },
+ { SBI_EXT_IPI,"IPI Extension" },
+ { SBI_EXT_RFENCE, "RFENCE Extension" },
+ { SBI_EXT_HSM,"Hart State Management Extension"
},
+ { SBI_EXT_SRST, "System Reset Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
--
2.30.2
[PATCH v3 1/3] riscv: add missing SBI extension definitions
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt
---
v3:
add SBI_HSM_HART_STATUS_SUSPENDED,
SBI_HSM_HART_STATUS_SUSPEND_PENDING,
SBI_HSM_HART_STATUS_RESUME_PENDING
v2:
correct constants that were blindly copied from Linux
---
arch/riscv/include/asm/sbi.h | 40 ++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 53ca316180..e9caa78d17 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -12,7 +12,6 @@
#include
enum sbi_ext_id {
-#ifdef CONFIG_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@@ -22,11 +21,12 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
-#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
+ SBI_EXT_HSM = 0x48534D,
+ SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
@@ -51,6 +51,42 @@ enum sbi_ext_rfence_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+};
+
+enum sbi_ext_hsm_fid {
+ SBI_EXT_HSM_HART_START = 0,
+ SBI_EXT_HSM_HART_STOP,
+ SBI_EXT_HSM_HART_STATUS,
+ SBI_EXT_HSM_HART_SUSPEND,
+};
+
+enum sbi_hsm_hart_status {
+ SBI_HSM_HART_STATUS_STARTED = 0,
+ SBI_HSM_HART_STATUS_STOPPED,
+ SBI_HSM_HART_STATUS_START_PENDING,
+ SBI_HSM_HART_STATUS_STOP_PENDING,
+ SBI_HSM_HART_STATUS_SUSPENDED,
+ SBI_HSM_HART_STATUS_SUSPEND_PENDING,
+ SBI_HSM_HART_STATUS_RESUME_PENDING,
+};
+
+enum sbi_ext_srst_fid {
+ SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+ SBI_SRST_RESET_REASON_NONE = 0,
+ SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#ifdef CONFIG_SBI_V01
--
2.30.2
[PATCH v3 0/3] riscv: enable SBI system reset
The purpose of this series is to provide the UEFI ResetSystem() service at runtime on RISC-V systems. With SBI v0.3 a system reset extension is available. This allows to implement reboot and poweroff in U-Boot in a system independent way. * Provide missing constants * Provide a system reset driver using the system reset extension. * Provide a UEFI runtime implementation for system reset v3: add SBI_HSM_HART_STATUS_SUSPENDED, SBI_HSM_HART_STATUS_SUSPEND_PENDING, SBI_HSM_HART_STATUS_RESUME_PENDING v2: correct constants that were blindly copied from Linux Heinrich Schuchardt (3): riscv: add missing SBI extension definitions cmd/sbi: use constants instead of numerical values sysreset: provide SBI based sysreset driver MAINTAINERS | 1 + arch/riscv/cpu/cpu.c| 13 - arch/riscv/include/asm/sbi.h| 41 +- arch/riscv/lib/sbi.c| 21 ++-- cmd/riscv/sbi.c | 30 +-- drivers/sysreset/Kconfig| 11 drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sbi.c | 96 + lib/efi_loader/Kconfig | 2 +- 9 files changed, 193 insertions(+), 23 deletions(-) create mode 100644 drivers/sysreset/sysreset_sbi.c -- 2.30.2
