Re: [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s
On Thu, Feb 22, 2024 at 03:52:03PM +0100, thomas.per...@bootlin.com wrote: > From: Thomas Perrot > > It appears that there is some timing marginality either in the > board layout or the SoC that results in occasional data corruption > on some boards. > We observed this issue on some of the new HiFive Unmatched RevB > boards during volume production as well as some of the original > HiFive Unmatched boards from 2021 in our possession. This means > that there are other boards out there that might have the issue > too. > > We have done some limited testing with DDR4 at 1600MT/s and > faulty boards (failing at 1866MT/s) passed. > We plan further testing after we procure a temperature chamber. > > Signed-off-by: Thomas Perrot > --- > arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
On Tue, Mar 05, 2024 at 07:00:11PM -0800, Bo Gan wrote: > Previously PLL node was missing from SPL dts. This caused BUS_ROOT > to stay on OSC clock (24Mhz). As a result, all peripherals have to > run at a much lower frequency, and loading from sdcard/emmc is slow. > Thus, enabling PLL node in dts to fix this. > > Signed-off-by: Bo Gan > --- > arch/riscv/dts/jh7110-u-boot.dtsi | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v3 16/16] rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support
On 2024/3/4 19:30, Quentin Schulz wrote:
From: Quentin Schulz
ADC support is implied by the Rockchip arch Kconfig but that means it
should be possible to disable ADC support and still be able to build.
However the weak implementation of rockchip_dnl_key_pressed() currently
blindly use functions from the ADC subsystem which do not exist when ADC
is not enabled, failing the build.
Therefore, let's encapsulate this logic with a check on the ADC symbol
being selected.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/boot_mode.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-rockchip/boot_mode.c
b/arch/arm/mach-rockchip/boot_mode.c
index eb8f65ae4e9..f9be396aa55 100644
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -40,6 +40,7 @@ void set_back_to_bootrom_dnl_flag(void)
__weak int rockchip_dnl_key_pressed(void)
{
+#if CONFIG_IS_ENABLED(ADC)
unsigned int val;
struct udevice *dev;
struct uclass *uc;
@@ -69,6 +70,9 @@ __weak int rockchip_dnl_key_pressed(void)
return true;
else
return false;
+#else
+ return false;
+#endif
}
void rockchip_dnl_mode_check(void)
Re: [PATCH v3 15/16] button: add missing ADC dependency for BUTTON_ADC
On 2024/3/4 19:30, Quentin Schulz wrote: From: Quentin Schulz The BUTTON_ADC symbol guards the compilation of button-adc driver whose name very well makes it explicit that it requires ADC support to be enabled. Fix build issue of button-adc driver when ADC support isn't enabled by making sure it cannot be built without ADC support. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- drivers/button/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig index 097b05f822e..3918b05ae03 100644 --- a/drivers/button/Kconfig +++ b/drivers/button/Kconfig @@ -12,6 +12,7 @@ config BUTTON config BUTTON_ADC bool "Button adc" depends on BUTTON + depends on ADC help Enable support for buttons which are connected to Analog to Digital Converter device. The ADC driver must use driver model. Buttons are
Re: [PATCH v3 14/16] adc: add missing depends on ADC for controller drivers
On 2024/3/4 19:30, Quentin Schulz wrote: From: Quentin Schulz The ADC controller drivers are obviously all depending on ADC symbol being selected. While they don't seem to fail to build without, they won't be useful without that symbol selected, so let's make sure the options aren't shown in menuconfig when ADC isn't selected. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- drivers/adc/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index a01d73846b7..c9cdbe6942d 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -13,6 +13,7 @@ config ADC config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" + depends on ADC help This enables basic driver for Exynos ADC compatible with Exynos54xx. It provides: @@ -22,6 +23,7 @@ config ADC_EXYNOS config ADC_SANDBOX bool "Enable Sandbox ADC test driver" + depends on ADC help This enables driver for Sandbox ADC device emulation. It provides: @@ -31,6 +33,7 @@ config ADC_SANDBOX config SARADC_MESON bool "Enable Amlogic Meson SARADC driver" + depends on ADC imply REGMAP help This enables driver for Amlogic Meson SARADC. @@ -41,6 +44,7 @@ config SARADC_MESON config SARADC_ROCKCHIP bool "Enable Rockchip SARADC driver" + depends on ADC help This enables driver for Rockchip SARADC. It provides:
Re: [PATCH v3 13/16] rockchip: jaguar-rk3588: enable SARADC and derivatives
On 2024/3/4 19:30, Quentin Schulz wrote: From: Quentin Schulz The SARADC is used on Jaguar for multiple things: - channel 0 is used (at runtime) as a BIOS button, - channel 2 is exposed on the Mezzanine connector for customer specific logic, - channel 5 and 6 are used for identification, Since the SARADC requires a vref-supply provided by the RK806 PMIC, its support and the support for its regulators are also enabled. The button, adc, pmic and regulator commands are also enabled for CLI use in U-Boot for debugging and scripting purposes. The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable Rockchip SPI controller driver. Finally, the SARADC channel 1 on Jaguar is hardwired so will never change in the lifetime of a unit, for that reason, disable the Rockchip Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/jaguar-rk3588_defconfig | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index f55bfb1c82b..275d70ae008 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -15,6 +15,7 @@ CONFIG_ENV_SIZE=0x1f000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_TARGET_JAGUAR_RK3588=y @@ -47,6 +48,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -59,6 +61,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_MII is not set # CONFIG_CMD_BLOCK_CACHE is not set # CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EROFS=y CONFIG_CMD_SQUASHFS=y @@ -73,7 +76,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y -# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y CONFIG_SPL_CLK=y CONFIG_CLK_GPIO=y CONFIG_ROCKCHIP_GPIO=y @@ -101,10 +105,14 @@ CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y CONFIG_SPL_RAM=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y
Re: [PATCH v3 11/16] rockchip: adc: rockchip-saradc: add support for RK3588
On 2024/3/4 19:30, Quentin Schulz wrote:
From: Quentin Schulz
This adds support for the SARADCv2 found on RK3588.
There is no stop callback as it is currently configured in single
conversion mode, where the ADC is powered down after a single conversion
has been made.
Due to what seems to be a silicon bug, a controller reset needs to be
issued before starting a channel conversion otherwise Rockchip says that
channel 1 will error whatever that means. This is aligned with upstream
and downstream Linux kernel as well as downstream U-Boot.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/adc/rockchip-saradc.c | 102 +-
1 file changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index b5df58fe3eb..10ded1b088f 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -10,12 +10,17 @@
#include
#include
#include
-#include
+#include
+#include
+#include
#include
+#include
#include
#include
#include
+#define usleep_range(a, b) udelay((b))
+
#define SARADC_CTRL_CHN_MASK GENMASK(2, 0)
#define SARADC_CTRL_POWER_CTRLBIT(3)
#define SARADC_CTRL_IRQ_ENABLEBIT(5)
@@ -30,8 +35,37 @@ struct rockchip_saradc_regs_v1 {
unsigned int dly_pu_soc;
};
+struct rockchip_saradc_regs_v2 {
+ unsigned int conv_con;
+#define SARADC2_SINGLE_MODEBIT(5)
+#define SARADC2_START BIT(4)
+#define SARADC2_CONV_CHANNELS GENMASK(3, 0)
+ unsigned int t_pd_soc;
+ unsigned int t_as_soc;
+ unsigned int t_das_soc;
+ unsigned int t_sel_soc;
+ unsigned int high_comp[16];
+ unsigned int low_comp[16];
+ unsigned int debounce;
+ unsigned int ht_int_en;
+ unsigned int lt_int_en;
+ unsigned int reserved[24];
+ unsigned int mt_int_en;
+ unsigned int end_int_en;
+#define SARADC2_EN_END_INT BIT(0)
+ unsigned int st_con;
+ unsigned int status;
+ unsigned int end_int_st;
+ unsigned int ht_int_st;
+ unsigned int lt_int_st;
+ unsigned int mt_int_st;
+ unsigned int data[16];
+ unsigned int auto_ch_en;
+};
+
union rockchip_saradc_regs {
struct rockchip_saradc_regs_v1 *v1;
+ struct rockchip_saradc_regs_v2 *v2;
};
struct rockchip_saradc_data {
int num_bits;
@@ -46,6 +80,7 @@ struct rockchip_saradc_priv {
union rockchip_saradc_regs regs;
int active_channel;
const struct rockchip_saradc_data *data;
+ struct reset_ctl*reset;
};
int rockchip_saradc_channel_data_v1(struct udevice *dev, int channel,
@@ -66,6 +101,22 @@ int rockchip_saradc_channel_data_v1(struct udevice *dev,
int channel,
return 0;
}
+int rockchip_saradc_channel_data_v2(struct udevice *dev, int channel,
+ unsigned int *data)
+{
+ struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+ if (!(readl(>regs.v2->end_int_st) & SARADC2_EN_END_INT))
+ return -EBUSY;
+
+ /* Read value */
+ *data = readl(>regs.v2->data[channel]);
+
+ /* Acknowledge the interrupt */
+ writel(SARADC2_EN_END_INT, >regs.v2->end_int_st);
+
+ return 0;
+}
int rockchip_saradc_channel_data(struct udevice *dev, int channel,
unsigned int *data)
{
@@ -104,6 +155,40 @@ int rockchip_saradc_start_channel_v1(struct udevice *dev,
int channel)
return 0;
}
+static void rockchip_saradc_reset_controller(struct reset_ctl *reset)
+{
+ reset_assert(reset);
+ usleep_range(10, 20);
+ reset_deassert(reset);
+}
+
+int rockchip_saradc_start_channel_v2(struct udevice *dev, int channel)
+{
+ struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+ /*
+* Downstream says
+* """If read other chn at anytime, then chn1 will error, assert
+* controller as a workaround."""
+*/
+ if (priv->reset)
+ rockchip_saradc_reset_controller(priv->reset);
+
+ writel(0xc, >regs.v2->t_das_soc);
+ writel(0x20, >regs.v2->t_pd_soc);
+
+ /* Acknowledge any previous interrupt */
+ writel(SARADC2_EN_END_INT, >regs.v2->end_int_st);
+
+ rk_clrsetreg(>regs.v2->conv_con,
+SARADC2_CONV_CHANNELS | SARADC2_START |
SARADC2_SINGLE_MODE,
+FIELD_PREP(SARADC2_CONV_CHANNELS, channel) |
+FIELD_PREP(SARADC2_START, 1) |
+FIELD_PREP(SARADC2_SINGLE_MODE, 1));
+
+ return 0;
+}
+
int rockchip_saradc_start_channel(struct udevice *dev, int channel)
{
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
@@ -162,6 +247,8 @@ int rockchip_saradc_probe(struct
Re: [PATCH v3 12/16] power: pmic: rk8xx: fix duplicate prompt
On 2024/3/4 19:30, Quentin Schulz wrote: From: Quentin Schulz SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it difficult to know at first glance in menuconfig what's for what, let's fix this by adding "in SPL" at the end of the prompt for the SPL symbol. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- drivers/power/pmic/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 9b61b18e11f..562c1a3b122 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -250,7 +250,7 @@ config PMIC_RK8XX This driver implements register read/write operations. config SPL_PMIC_RK8XX - bool "Enable support for Rockchip PMIC RK8XX" + bool "Enable support for Rockchip PMIC RK8XX in SPL" depends on SPL_DM_PMIC ---help--- The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
Re: [PATCH v4 11/20] rockchip: rk3588: disable force_jtag by default
On 2024/3/11 20:01, Quentin Schulz wrote:
From: Quentin Schulz
Rockchip SoCs can automatically switch between jtag and sdmmc based on
the following rules:
- all the SDMMC pins including SDMMC_DET set as SDMMC function in GRF,
- force_jtag bit in GRF is 1,
- SDMMC_DET is low (no card detected),
Note that the BootROM may mux all SDMMC pins in their SDMMC function or
not, depending on the boot medium that were tried.
Because SDMMC_DET pin is not guaranteed to be used as an SD card card
detect pin, it could be low at boot or even switch at runtime, which
would enable the jtag function and render the SD card unusable.
This is the case for RK3588 Jaguar for example which has an SD card
connector without an SD card card detect signal and has SDMMC_DET
connected to ground.
Because enabling JTAG at runtime could be a security issue and also to
make sure that we have a consistent behavior on all boards by default,
let's disable this force_jtag feature.
However, let's make it easy to reenable it for debugging purposes by
hiding it behind a Kconfig symbol.
Note that soc_con[0] is reserved. But considering that it's way more
user-friendly to access soc_con1 from the TRM with soc_con[1] than
soc_con[0], and that soc_con0 would actually be located at 4 bytes
before soc_con1, let's just make soc_con0 part of the soc_con array.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/include/asm/arch-rockchip/grf_rk3588.h | 24
arch/arm/mach-rockchip/Kconfig | 24
arch/arm/mach-rockchip/rk3588/rk3588.c | 11 +++
3 files changed, 59 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
index e0694068bb1..f0ecff97f0b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
@@ -32,4 +32,28 @@ struct rk3588_pmu1grf {
check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0);
+#define SYS_GRF_BASE 0xfd58c000
+
+struct rk3588_sysgrf {
+ unsigned int wdt_con0;
+ unsigned int reserved0[(0x0010 - 0x) / 4 - 1];
+ unsigned int uart_con[2];
+ unsigned int reserved1[(0x00c0 - 0x0014) / 4 - 1];
+ unsigned int gic_con0;
+ unsigned int reserved2[(0x0200 - 0x00c0) / 4 - 1];
+ unsigned int memcfg_con[32];
+ unsigned int reserved3[(0x0300 - 0x027c) / 4 - 1];
+ /* soc_con0 is reserved */
+ unsigned int soc_con[14];
+ unsigned int reserved4[(0x0380 - 0x0334) / 4 - 1];
+ unsigned int soc_status[4];
+ unsigned int reserved5[(0x0500 - 0x038c) / 4 - 1];
+ unsigned int otp_key08;
+ unsigned int otp_key0d;
+ unsigned int otp_key0e;
+ unsigned int reserved6[(0x0600 - 0x0508) / 4 - 1];
+ unsigned int chip_id;
+};
+
+check_member(rk3588_sysgrf, chip_id, 0x0600);
#endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1bc7ee90427..343361a5327 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -501,6 +501,30 @@ config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
This enables support code in the BOOT0 hook for the SPL stage
to allow multiple entries.
+config ROCKCHIP_DISABLE_FORCE_JTAG
+ bool "Disable force_jtag feature"
+ default y
+ depends on SPL
+ help
+ Rockchip SoCs can automatically switch between jtag and sdmmc based
+ on the following rules:
+ - all the SDMMC pins including SDMMC_DET set as SDMMC function in
+ GRF,
+ - force_jtag bit in GRF is 1,
+ - SDMMC_DET is low (no card detected),
+
+ Some HW design may not route the SD card card detect to SDMMC_DET
+ pin, thus breaking the SD card support in some cases because JTAG
+ would be auto-enabled by mistake.
+
+ Also, enabling JTAG at runtime may be an undesired feature, e.g.
+ because it could be a security vulnerability.
+
+ This disables force_jtag feature, which you may want for debugging
+ purposes.
+
+ If unsure, say Y.
+
config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
bool "TPL requires early-return (for RK3188-style BROM) to BROM"
depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 38e95a6e2b2..d18c4e4b411 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -35,6 +36,8 @@
#define BUS_IOC_GPIO2D_IOMUX_SEL_H0x5c
#define BUS_IOC_GPIO3A_IOMUX_SEL_L0x60
+#define SYS_GRF_FORCE_JTAG BIT(14)
+
/**
* Boot-device identifiers used by the BROM on RK3588 when device is booted
* from SPI flash.
Re: [PATCH v1 2/2] board: starfive: maintainer: Add visionfive2 PCIe driver
On Fri, Mar 08, 2024 at 02:53:36PM +0800, Minda Chen wrote: > Add PCIe driver file to visionfive2 board MAINTAINERS list. > > Signed-off-by: Minda Chen > --- > board/starfive/visionfive2/MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v1 1/2] board: starfive: Update maintainer of VisionFive v2 board
On Fri, Mar 08, 2024 at 02:53:35PM +0800, Minda Chen wrote: > Update the maintainer of Starfive VisionFive v2 board. > > Signed-off-by: Minda Chen > --- > board/starfive/visionfive2/MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
[PATCH V4] mtd: spinand: Add support for XTX SPINAND
Add support for XTX XT26G0xA and XT26xxxD. The driver is ported from
linux-6.7.1. This driver is tested on Banana BPI-R3 with XT26G01A and
XT26G12D.
Signed-off-by: Bruce Suen
Reviewed-by: Frieder Schrempf
---
V3->V4:
- modify commit message minor flaws
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/xtx.c| 266 ++
include/linux/mtd/spinand.h | 1 +
4 files changed, 269 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/spi/xtx.c
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index f172f4787f..65b836b34c 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
-spinand-objs += toshiba.o winbond.o
+spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 8ca33459f9..62c28aa422 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -829,6 +829,7 @@ static const struct spinand_manufacturer
*spinand_manufacturers[] = {
_spinand_manufacturer,
_spinand_manufacturer,
_c8_spinand_manufacturer,
+ _spinand_manufacturer,
};
static int spinand_manufacturer_match(struct spinand_device *spinand,
diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c
new file mode 100644
index 00..aee1849a71
--- /dev/null
+++ b/drivers/mtd/nand/spi/xtx.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author:
+ * Felix Matouschek
+ */
+
+#include
+#ifndef __UBOOT__
+#include
+#include
+#endif
+#include
+
+#define SPINAND_MFR_XTX0x0B
+
+#define XT26G0XA_STATUS_ECC_MASK GENMASK(5, 2)
+#define XT26G0XA_STATUS_ECC_NO_DETECTED(0 << 2)
+#define XT26G0XA_STATUS_ECC_8_CORRECTED(3 << 4)
+#define XT26G0XA_STATUS_ECC_UNCOR_ERROR(2 << 4)
+
+#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6)
+#define XT26XXXD_STATUS_ECC_NO_DETECTED (0)
+#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1)
+#define XT26XXXD_STATUS_ECC_8_CORRECTED (3)
+#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 48;
+ region->length = 16;
+
+ return 0;
+}
+
+static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 1;
+ region->length = 47;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {
+ .ecc = xt26g0xa_ooblayout_ecc,
+ .rfree = xt26g0xa_ooblayout_free,
+};
+
+static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ status = status & XT26G0XA_STATUS_ECC_MASK;
+
+ switch (status) {
+ case XT26G0XA_STATUS_ECC_NO_DETECTED:
+ return 0;
+ case XT26G0XA_STATUS_ECC_8_CORRECTED:
+ return 8;
+ case XT26G0XA_STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+ default:
+ break;
+ }
+
+ /* At this point values greater than (2 << 4) are invalid */
+ if (status > XT26G0XA_STATUS_ECC_UNCOR_ERROR)
+ return -EINVAL;
+
+ /* (1 << 2) through (7 << 2) are 1-7 corrected errors */
+ return status >> 2;
+}
+
+static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = mtd->oobsize / 2;
+ region->length = mtd->oobsize / 2;
+
+ return 0;
+}
+
+static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if
[PATCH v3 3/4] clk: qcom: add support for power domains uclass
Now sub-drivers for particular SoCs can register them as power domain
drivers. This is needed for upcoming SM8150 support, because it needs
to power up the Ethernet module.
Signed-off-by: Volodymyr Babchuk
---
Caleb suggested to use "imply POWER_DOMAIN", not "depends
POWER_DOMAIN" in the Kconfig, but this does not work:
$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm
scripts/kconfig/conf --syncconfig Kconfig
drivers/clk/Kconfig:3:error: recursive dependency detected!
drivers/clk/Kconfig:3: symbol CLK is selected by IMX8M_POWER_DOMAIN
drivers/power/domain/Kconfig:35:symbol IMX8M_POWER_DOMAIN depends on
POWER_DOMAIN
drivers/power/domain/Kconfig:3: symbol POWER_DOMAIN is implied by CLK_QCOM
drivers/clk/qcom/Kconfig:3: symbol CLK_QCOM depends on CLK
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
Changes in v3:
- Added "depends POWER_DOMAIN" to Kconfig (see note)
- Use readl_poll_timeout() instead of open coded wait loop
- Print warning if power domain can't be enabled/disabled
Changes in v2:
- Reworked qcom_cc_bind() function
- Added timeout to qcom_power_set()
- Minor fixes in register names and formatting
drivers/clk/qcom/Kconfig | 2 +-
drivers/clk/qcom/clock-qcom.c | 132 ++
drivers/clk/qcom/clock-qcom.h | 6 ++
3 files changed, 126 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0df0d1881a..8dae635ac2 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -2,7 +2,7 @@ if ARCH_SNAPDRAGON || ARCH_IPQ40XX
config CLK_QCOM
bool
- depends on CLK && DM_RESET
+ depends on CLK && DM_RESET && POWER_DOMAIN
def_bool n
menu "Qualcomm clock drivers"
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 729d190c54..7a5938a06a 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -22,7 +22,9 @@
#include
#include
#include
+#include
#include
+#include
#include "clock-qcom.h"
@@ -30,6 +32,13 @@
#define CBCR_BRANCH_ENABLE_BIT BIT(0)
#define CBCR_BRANCH_OFF_BIT BIT(31)
+#define GDSC_SW_COLLAPSE_MASK BIT(0)
+#define GDSC_POWER_DOWN_COMPLETE BIT(15)
+#define GDSC_POWER_UP_COMPLETE BIT(16)
+#define GDSC_PWR_ON_MASK BIT(31)
+#define CFG_GDSCR_OFFSET 0x4
+#define GDSC_STATUS_POLL_TIMEOUT_US1500
+
/* Enable clock controlled by CBC soft macro */
void clk_enable_cbc(phys_addr_t cbcr)
{
@@ -223,7 +232,7 @@ U_BOOT_DRIVER(qcom_clk) = {
int qcom_cc_bind(struct udevice *parent)
{
struct msm_clk_data *data = (struct msm_clk_data
*)dev_get_driver_data(parent);
- struct udevice *clkdev, *rstdev;
+ struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
struct driver *drv;
int ret;
@@ -238,20 +247,41 @@ int qcom_cc_bind(struct udevice *parent)
if (ret)
return ret;
- /* Bail out early if resets are not specified for this platform */
- if (!data->resets)
- return ret;
+ if (data->resets) {
+ /* Get a handle to the common reset handler */
+ drv = lists_driver_lookup_name("qcom_reset");
+ if (!drv) {
+ ret = -ENOENT;
+ goto unbind_clkdev;
+ }
+
+ /* Register the reset controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_reset",
(ulong)data,
+ dev_ofnode(parent), );
+ if (ret)
+ goto unbind_clkdev;
+ }
- /* Get a handle to the common reset handler */
- drv = lists_driver_lookup_name("qcom_reset");
- if (!drv)
- return -ENOENT;
+ if (data->power_domains) {
+ /* Get a handle to the common power domain handler */
+ drv = lists_driver_lookup_name("qcom_power");
+ if (!drv) {
+ ret = -ENOENT;
+ goto unbind_rstdev;
+ }
+ /* Register the power domain controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_power",
(ulong)data,
+ dev_ofnode(parent), );
+ if (ret)
+ goto unbind_rstdev;
+ }
- /* Register the reset controller */
- ret = device_bind_with_driver_data(parent, drv, "qcom_reset",
(ulong)data,
- dev_ofnode(parent), );
- if (ret)
- device_unbind(clkdev);
+ return 0;
+
+unbind_rstdev:
+ device_unbind(rstdev);
+unbind_clkdev:
+ device_unbind(clkdev);
return ret;
}
@@ -306,3 +336,79 @@ U_BOOT_DRIVER(qcom_reset) = {
.ops = _reset_ops,
.probe =
[PATCH v3 2/4] clk: qcom: clear div mask before assigning a new divider
The current behaviour does a bitwise OR of the previous and new divider values, this is wrong as some bits maybe be set already. We need to clear all the divider bits before applying new ones. This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. Signed-off-by: Volodymyr Babchuk Reviewed-by: Caleb Connolly --- (no changes since v2) Changes in v2: - Reworded the commit message - Added Caleb's R-b tag drivers/clk/qcom/clock-qcom.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7c683e5192..729d190c54 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -117,7 +117,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, /* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr); - cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | +CFG_SRC_DIV_MASK); cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ if (div) -- 2.43.0
[PATCH v3 4/4] pinctrl: qcom: pass pin number to get_function_mux callback
This patch is the preparation for SM8150 support. This new SoC
depending on the particular pin can have different numbers for the
same function. For example "rgmii" function for GPIO4 has id=2 while
for GPIO59 it has id=1. So, to support this type of SoCs,
get_function_mux() callback needs to know for which pin the function
is requested.
Signed-off-by: Volodymyr Babchuk
Reviewed-by: Caleb Connolly
Reviewed-by: Sumit Garg
---
Changes in v3:
- Added Sumit's R-b tag
Changes in v2:
- Added Caleb's R-b tag
drivers/pinctrl/qcom/pinctrl-apq8016.c | 3 ++-
drivers/pinctrl/qcom/pinctrl-apq8096.c | 3 ++-
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 3 ++-
drivers/pinctrl/qcom/pinctrl-qcom.c| 4 ++--
drivers/pinctrl/qcom/pinctrl-qcom.h| 3 ++-
drivers/pinctrl/qcom/pinctrl-qcs404.c | 3 ++-
drivers/pinctrl/qcom/pinctrl-sdm845.c | 3 ++-
7 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index db0e212468..a9a00f4b08 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -49,7 +49,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
}
}
-static unsigned int apq8016_get_function_mux(unsigned int selector)
+static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin,
+unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c
b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index 880df8fe3c..9697cb5beb 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -44,7 +44,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
}
}
-static unsigned int apq8096_get_function_mux(unsigned int selector)
+static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin,
+unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 74c04ab87c..4479230313 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -40,7 +40,8 @@ static const char *ipq4019_get_pin_name(struct udevice *dev,
return pin_name;
}
-static unsigned int ipq4019_get_function_mux(unsigned int selector)
+static unsigned int ipq4019_get_function_mux(__maybe_unused unsigned int pin,
+unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c
b/drivers/pinctrl/qcom/pinctrl-qcom.c
index ee0624df29..909e566acf 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -83,14 +83,14 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int
pin_selector,
unsigned int func_selector)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+ u32 func = priv->data->get_function_mux(pin_selector, func_selector);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(>data->pin_data, pin_selector))
return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
- TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
- priv->data->get_function_mux(func_selector) << 2);
+ TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
return 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h
b/drivers/pinctrl/qcom/pinctrl-qcom.h
index 07f2eae9ba..49b7bfbc00 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.h
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
@@ -18,7 +18,8 @@ struct msm_pinctrl_data {
int functions_count;
const char *(*get_function_name)(struct udevice *dev,
unsigned int selector);
- unsigned int (*get_function_mux)(unsigned int selector);
+ unsigned int (*get_function_mux)(unsigned int pin,
+unsigned int selector);
const char *(*get_pin_name)(struct udevice *dev,
unsigned int selector);
};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c
b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index 3a2d468599..4b7c670c90 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -94,7 +94,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
}
}
-static unsigned int qcs404_get_function_mux(unsigned int selector)
+static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git
[PATCH v3 0/4]
Set of pre-req patches for Qualcomm SA8155P-ADP board support. This path series consist of generic qcom changes that may benefit different boards. It is the part of the bigger series that adds SA8155P-ADP support, but I am posting this limited set because there are other developers who depend on those changes and I am not ready to post other patches of the bigger series. Changes in v3: - Replaced fdt_valid() with fdt_check_header() - Added "depends POWER_DOMAIN" to Kconfig (see note) - Use readl_poll_timeout() instead of open coded wait loop - Print warning if power domain can't be enabled/disabled Changes in v2: - New patch in v2 - Reworked qcom_cc_bind() function - Added timeout to qcom_power_set() - Minor fixes in register names and formatting Volodymyr Babchuk (4): qcom: board: validate fdt before trying to use it clk: qcom: clear div mask before assigning a new divider clk: qcom: add support for power domains uclass pinctrl: qcom: pass pin number to get_function_mux callback arch/arm/mach-snapdragon/board.c | 5 +- drivers/clk/qcom/Kconfig | 2 +- drivers/clk/qcom/clock-qcom.c | 135 ++--- drivers/clk/qcom/clock-qcom.h | 6 ++ drivers/pinctrl/qcom/pinctrl-apq8016.c | 3 +- drivers/pinctrl/qcom/pinctrl-apq8096.c | 3 +- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 3 +- drivers/pinctrl/qcom/pinctrl-qcom.c| 4 +- drivers/pinctrl/qcom/pinctrl-qcom.h| 3 +- drivers/pinctrl/qcom/pinctrl-qcs404.c | 3 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 3 +- 11 files changed, 146 insertions(+), 24 deletions(-) -- 2.43.0
[PATCH v3 1/4] qcom: board: validate fdt before trying to use it
There are cases when previous bootloader stage leaves some seemingly
valid value in r0, which in fact does not point to valid FDT
blob. This behavior was encountered when trying to boot U-Boot as
"hyp" loader on SA8155P-ADP.
To be sure that we really got the pointer to a device tree we need to
validate it with fdt_check_header() function.
Note: This approach is not 100% fool-proof, as get_prev_bl_fdt_addr()
theoretically can return a pointer to a region that is not physically
mapped and we will get data abort exception when fdt_check_header()
will try to access it. But at this early boot stage we don't know
where RAM is anyways so there is little we can do.
Signed-off-by: Volodymyr Babchuk
Reviewed-by: Sumit Garg
---
Changes in v3:
- Replaced fdt_valid() with fdt_check_header()
- Added Sumit's R-B tag
Changes in v2:
- New patch in v2
arch/arm/mach-snapdragon/board.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index f12f5791a1..6f762fc948 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#include
@@ -93,7 +94,9 @@ void *board_fdt_blob_setup(int *err)
* try and use the FDT built into U-Boot if there is one...
* This avoids having a hard dependency on the previous stage bootloader
*/
- if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt,
SZ_4K))) {
+
+ if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K)
||
+ fdt_check_header((void *)fdt))) {
debug("%s: Using built in FDT, bootloader gave us %#llx\n",
__func__, fdt);
return (void *)gd->fdt_blob;
}
--
2.43.0
[PATCH] patman: Properly document the patchwork_url setting
The "Series-patchwork-url:" tag description says that it overrides the
settings file but doesn't specify the name of the setting. Elsewhere
in the documentation about the "useful" settings we see a setting that
sounds promising called "patchwork_server" that's actually not a valid
setting. It should be "patchwork_url".
Fix these problems so the doc is right and more useful.
Signed-off-by: Douglas Anderson
---
tools/patman/patman.rst | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst
index e01355824c59..f4588c00fc11 100644
--- a/tools/patman/patman.rst
+++ b/tools/patman/patman.rst
@@ -144,7 +144,7 @@ patman.py. For reference, the useful ones (at the moment)
shown below
process_tags: False
verbose: True
smtp_server: /path/to/sendmail
-patchwork_server: https://patchwork.ozlabs.org
+patchwork_url: https://patchwork.ozlabs.org
If you want to adjust settings (or aliases) that affect just a single
project you can add a section that looks like [project_settings] or
@@ -248,9 +248,9 @@ Series-links: [id | version:id]...
Series-patchwork-url: url
This allows specifying the Patchwork URL for a branch. This overrides
-both the setting files and the command-line argument. The URL should
-include the protocol and web site, with no trailing slash, for example
-'https://patchwork.ozlabs.org/project'
+both the setting files ("patchwork_url") and the command-line argument.
+The URL should include the protocol and web site, with no trailing slash,
+for example 'https://patchwork.ozlabs.org/project'
Cover-letter:
Sets the cover letter contents for the series. The first line
--
2.44.0.278.ge034bb2e1d-goog
Re: [PATCH v6 00/11] An effort to bring DT bindings compliance within U-Boot
Hi Sumit, On Sun, Mar 10, 2024 at 11:24 PM Sumit Garg wrote: > > Hi Tony, > > On Mon, 11 Mar 2024 at 09:20, Tony Dinh wrote: > > > > Hi Sumit, > > Hi Tom, > > > > On Mon, Mar 4, 2024 at 4:29 AM Fabio Estevam wrote: > > > > > > On Mon, Mar 4, 2024 at 9:15 AM Sumit Garg wrote: > > > > > > > I suppose the earlier reference patch wasn't complete, can you rather > > > > try its v4 [1] instead? > > > > > > > > [1] > > > > https://patchwork.ozlabs.org/project/uboot/patch/20240304121257.3551104-1-sumit.g...@linaro.org/ > > > > > > This one works, thanks! > > > > I'm testing this for a Marvell Armada 385 board (Synology DS116). I'm > > on the next branch, but perhaps something is still missing. > > > > diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig > > index 02ddc0e7918..1fbedcf91cf 100644 > > --- a/configs/ds116_defconfig > > +++ b/configs/ds116_defconfig > > @@ -16,7 +16,7 @@ CONFIG_SF_DEFAULT_SPEED=5000 > > CONFIG_ENV_SIZE=0x1 > > CONFIG_ENV_OFFSET=0x7E > > CONFIG_ENV_SECT_SIZE=0x1 > > -CONFIG_DEFAULT_DEVICE_TREE="armada-385-synology-ds116" > > +CONFIG_DEFAULT_DEVICE_TREE="marvell/armada-385-synology-ds116" > > CONFIG_SPL_TEXT_BASE=0x4030 > > CONFIG_SPL_SERIAL=y > > CONFIG_SPL_STACK=0x4002c000 > > @@ -29,7 +29,6 @@ CONFIG_PCI=y > > CONFIG_DEBUG_UART=y > > CONFIG_AHCI=y > > CONFIG_BOOTSTD_FULL=y > > -CONFIG_BOOTSTD_DEFAULTS=y > > CONFIG_BOOTDELAY=10 > > CONFIG_USE_PREBOOT=y > > CONFIG_SYS_CONSOLE_INFO_QUIET=y > > @@ -57,6 +56,7 @@ CONFIG_CMD_CACHE=y > > CONFIG_CMD_TIME=y > > CONFIG_CMD_MTDPARTS=y > > > > CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(u-boot),7040k(kernel),64k(u-boot-env),-(data)" > > +CONFIG_OF_UPSTREAM=y > > CONFIG_ENV_OVERWRITE=y > > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > > CONFIG_VERSION_VARIABLE=y > > > > # make ds116_defconfig > > > > # grep -i ds116 .config > > CONFIG_SYS_BOARD="ds116" > > CONFIG_SYS_CONFIG_NAME="ds116" > > CONFIG_TARGET_DS116=y > > CONFIG_DEFAULT_DEVICE_TREE="marvell/armada-385-synology-ds116" > > CONFIG_IDENT_STRING="\nSynology DS116" > > CONFIG_SYS_PROMPT="DS116> " > > CONFIG_OF_LIST="marvell/armada-385-synology-ds116" > > CONFIG_SPL_OF_LIST="marvell/armada-385-synology-ds116" > > > > Built it, and looks like vendor Marvell is missing during the Make > > file execution. > > > > make -f ./scripts/Makefile.build obj=dts dtbs > > make -f ./scripts/Makefile.build obj=dts/upstream/src/arm dtbs > > scripts/Makefile.build:57: dts/upstream/src/arm/Makefile: No such file > > or directory > > As you are building for the 32-bit Arm, you have to add a Makefile > here [1] similar to this one [2] for arm64. > > [1] > https://source.denx.de/u-boot/u-boot/-/tree/next/dts/upstream/src/arm?ref_type=heads > [2] > https://source.denx.de/u-boot/u-boot/-/blob/next/dts/upstream/src/arm64/Makefile?ref_type=heads Thanks! It works great with that Make file. All the best, Tony > > -Sumit > > > make[2]: *** No rule to make target 'dts/upstream/src/arm/Makefile'. Stop. > > make[1]: *** [dts/Makefile:54: arch-dtbs] Error 2 > > make: *** [Makefile:1166: dts/dt.dtb] Error 2 > > make: *** Waiting for unfinished jobs > > make: Leaving directory '/usr/src/u-boot' > > > > I also tried Bryan's patch like you've suggested to Fabio. But it > > seems Bryan's patch was already in the next branch. Did I miss > > something? > > > > All the best , > > Tony
Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board
Caleb Connolly writes:
> On 11/03/2024 18:23, Volodymyr Babchuk wrote:
>> Hi Caleb,
>> Caleb Connolly writes:
>>
>>> On 06/03/2024 21:24, Volodymyr Babchuk wrote:
Hi Caleb,
Caleb Connolly writes:
[...]
+};
+
+ {
+ /* U-Boot pinctrl driver does not understand multiple tiles */
+ reg = <0x0 0x0300 0x0 0x100>;
+ /delete-property/ reg-names;
>>>
>>> This won't be needed if we can make the tiles offset in the pinctrl
>>> driver compatible:
>>>
>>> #define WEST 0x
>>> #define EAST 0x0040
>>> #define NORTH 0x0080
>>> #define SOUTH 0x00C0
>>
>> Hmm, I assume that in this case pinctrl driver should map all the four
>> tiles independently? Are there guarantees in U-Boot that four separate
>> memory regions will be mapped into virtual memory with the same relative
>> positions? Linux clearly don't make such guarantees.
>
> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
> far as reading the address from DT, nothing else, so this is totally
> fine and is how the other SoCs do it.
For me it looks like we are depending on implementation details
knowledge. I.e MMU API does not provide such guarantees, but drivers
know how ARM MMU code is working internally and drivers depend on
exactly this behavior. But if you are saying that it is totally fine,
I'll rework the patch. No big deal. Actually, I already tried this and
it is working fine.
+
+ /* U-Boot ethernet driver wants to drive reset as GPIO */
+ /delete-node/ phy-reset-pins;
>>>
>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>> as GPIO only.
>>>
>> Well, yes. This also puzzles me up, but for some reason it stops working
>> if I leave this node intact. Looks like I need to look at this deeper
>> before posting the next version.
>
> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
> misbehave, can you check if this patch fixes it (there is a bug in the
> line "return msm_gpio_direction_input(dev, gpio);", it should become
> just "msm_gpio_direction_input(dev, gpio);").
>
> I had the exact same issue with the gpio-regulator driver and this was
> the solution I ended up going with.
>
> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787...@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
> [lore[.]kernel[.]org]
It is exactly this. With your patch I don't need to /delete-node/
anymore. I'll add a comment in the cover message that this series are
depended on your patch.
>>>
>>> Please can you split the power domain and clock patches into a separate
>>> series? As I'd like to depend on them for the next revision of my
>>> series, and we'd otherwise have a cyclical dependency.
>> Of course.
>> As I understood, you are interested in "clk: qcom: clear div mask
>> before
>> assigning a new divider" and "clk: qcom: add support for power domains
>> uclass", correct?
>
> Yes.
Okay, I'll send it today.
> I tried the power domain stuff out on SMD845 today and ran into
> quite a few issues. Specifically as a lot of the devices reference the
> rpmhpd power domain which we don't support (and don't *need* to
> support) in U-Boot. I'm not sure what the best way forward will be for
> this. Maybe a "nop" power domain driver?
Are you sure that they are not required?
"nop" power domain always is the option. Especially if it prints some
warning about an unknown device. I had quite a lot of issues with clock and
pin drivers that silently ignore unknown devices...
> Do you have the same issues on sm8150?
Yes and no. No, because I was lucky so far and devices I tried to use in
U-Boot does not require rpmhpd. Looking at DTS, I may only encounter
issues with sdhc_2, which requires rpmhpd for some reason. Also UFS
requires clock from rpmhcc.
And "yes", because I have found root cause for my troubles with UFS in
Linux kernel, when I am skipping hyp.mbn. This is not strictly related
to U-Boot, but you may be interested in this: apparently Qualcomm's
hypervisor enables access to RPM (maybe brings it out of reset?). cmd-db
shared memory region can't be accessed if I skip the hypervisor and try
to boot directly into Linux. So now I am looking for ways to enable it.
--
WBR, Volodymyr
Re: [PATCH] sunxi: h616: add initial support for T95 AXP313 TV Box
Hi,
On Mon, 11 Mar 2024 at 11:38, Kamil Kasperski wrote:
>
> Hello Andre,
> Thanks for your reply and thanks for pointing some stuff out.
>
> > What is "mbox"? Do you have any more information about this vendor?
>
> "MBOX" refers to the "Model" string from system properties.
> The problem is that it's quite hard to pin the correct vendor, since
> the OS is built based on Google Pixel 2.
> You can see that the fingerprint contains strings only for this phone:
> [ro.build.fingerprint]:
> [google/walley/walleye:10/QP1A.191105.004/eng.cmj.20220408.125005:userdebug/test-keys]
> Setting the device model as Vendor string seemed to be the most safe bet.
> If you have any other suggestions, please let me know.
Maybe a suggestion could be "YAGALA"
If you look on amazon, aliexpress you could find some vendors setting
the brand to this name.
Regards,
>
> > But please note that the devicetree needs to go through the Linux
> > mailing lists and repo first, and we automatically copy it from the
> > Linux tree once it has been merged there.
>
> Thanks for pointing that out. I'll contact Linux maintainers
> and will send updated patch.
>
> Best regards,
> Kamil
>
>
> niedz., 10 mar 2024 o 23:00 Andre Przywara
> napisał(a):
> >
> > On Sat, 9 Mar 2024 19:24:26 +
> > Kamil Kasperski wrote:
> >
> > Hi Kamil,
> >
> > many thanks for sending a patch, that looks mostly good from the
> > technical point of view, only some smaller comments.
> >
> > But please note that the devicetree needs to go through the Linux
> > mailing lists and repo first, and we automatically copy it from the
> > Linux tree once it has been merged there. This is to ensure proper
> > review and checks with the Linux tooling.
> >
> > So can you please send just the .dts file to the DT and sunxi
> > maintainers the respective lists, as reported by get_maintainer.pl?
> > Then we can take it from there.
> >
> > > T95 is a most commonly known for being a box with a pre-installed malware.
> > > It uses Allwinner H616 and comes with eMMC and DDR3 memory.
> > > This device comes with two versions - one with AXP305 PMIC and another
> > > with AXP313 PMIC.
> > > The AXP313 version comes with Secure Boot enabled and locked bootloader,
> > > so the u-boot has to be built with TOC0.
> > > DRAM settings are taken from Allwinner's boot0 for this box.
> >
> > Ah, thanks for figuring those out, that's very helpful.
> >
> > >
> > > Cc: Andre Przywara
> > >
> > > Signed-off-by: Kamil Kasperski
> > > ---
> > > arch/arm/dts/Makefile | 3 +-
> > > arch/arm/dts/sun50i-h616-t95-axp313.dts | 148
> > > configs/t95_axp313_defconfig| 27 +
> > > 3 files changed, 177 insertions(+), 1 deletion(-)
> > > create mode 100644 arch/arm/dts/sun50i-h616-t95-axp313.dts
> > > create mode 100644 configs/t95_axp313_defconfig
> > >
> > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > index b102ffb5f6..144daf6c48 100644
> > > --- a/arch/arm/dts/Makefile
> > > +++ b/arch/arm/dts/Makefile
> > > @@ -842,7 +842,8 @@ dtb-$(CONFIG_MACH_SUN50I_H616) += \
> > > sun50i-h618-orangepi-zero2w.dtb \
> > > sun50i-h618-orangepi-zero3.dtb \
> > > sun50i-h618-transpeed-8k618-t.dtb \
> > > - sun50i-h616-x96-mate.dtb
> > > + sun50i-h616-x96-mate.dtb \
> > > + sun50i-h616-t95-axp313.dtb
> > > dtb-$(CONFIG_MACH_SUN50I) += \
> > > sun50i-a64-amarula-relic.dtb \
> > > sun50i-a64-bananapi-m64.dtb \
> > > diff --git a/arch/arm/dts/sun50i-h616-t95-axp313.dts
> > > b/arch/arm/dts/sun50i-h616-t95-axp313.dts
> > > new file mode 100644
> > > index 00..b006f363d5
> > > --- /dev/null
> > > +++ b/arch/arm/dts/sun50i-h616-t95-axp313.dts
> > > @@ -0,0 +1,148 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright (C) 2021 Arm Ltd.
> >
> > Please change this copyright you and this year.
> >
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "sun50i-h616.dtsi"
> > > +
> > > +#include
> > > +#include
> > > +
> > > +/ {
> > > + model = "T95 (AXP313)";
> > > + compatible = "mbox,t95-axp313", "allwinner,sun50i-h616";
> >
> > What is "mbox"? Do you have any more information about this vendor?
> > In any case a new vendor would need to be added to
> > Documentation/devicetree/bindings/vendor-prefixes.yaml, in a separate
> > patch. Also you need a patch to add this compatible combination to
> > Documentation/devicetree/bindings/arm/sunxi.yaml.
> >
> > Cheers,
> > Andre
> >
> > > +
> > > + aliases {
> > > + serial0 =
> > > + };
> > > +
> > > + chosen {
> > > + stdout-path = "serial0:115200n8";
> > > + };
> > > +
> > > + reg_vcc5v: vcc5v {
> > > + /* board wide 5V supply directly from the DC input */
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "vcc-5v";
> > > + regulator-min-microvolt = <500>;
> > > +
Re: [PATCH 1/2] lmb: Avoid to add identical region in lmb_add_region_flags()
Hello Patrice, On Mon, Mar 11, 2024 at 03:39:17PM +0100, Patrice Chotard wrote: > In case lmb_add_region_flags() is called with the same parameter than > an already existing lmb and this lmb is adjacent to its previous lmb with > different flag, this lmb is added again. Is this On Mon, Mar 11, 2024 at 03:39:18PM +0100, Patrice Chotard wrote: > In case a new region is adjacent to a previous region with > similar flag, this region is merged with its predecessor, but no > check are done if this new added region is overlapping another region > present in lmb (see reserved[3] which overlaps reserved[4]). or this, related to some ERROR: reserving fdt memory region failed message in your opinion? More details in https://lore.kernel.org/all/fe9431c5-6806-1b7a-f9f4-dbe97ee13...@toradex.com/ Francesco
Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board
On 11/03/2024 18:23, Volodymyr Babchuk wrote:
Hi Caleb,
Caleb Connolly writes:
On 06/03/2024 21:24, Volodymyr Babchuk wrote:
Hi Caleb,
Caleb Connolly writes:
[...]
+};
+
+ {
+ /* U-Boot pinctrl driver does not understand multiple tiles */
+ reg = <0x0 0x0300 0x0 0x100>;
+ /delete-property/ reg-names;
This won't be needed if we can make the tiles offset in the pinctrl
driver compatible:
#define WEST 0x
#define EAST 0x0040
#define NORTH 0x0080
#define SOUTH 0x00C0
Hmm, I assume that in this case pinctrl driver should map all the four
tiles independently? Are there guarantees in U-Boot that four separate
memory regions will be mapped into virtual memory with the same relative
positions? Linux clearly don't make such guarantees.
U-Boot doesn't use virtual addresses on arm platforms, it only goes as
far as reading the address from DT, nothing else, so this is totally
fine and is how the other SoCs do it.
For me it looks like we are depending on implementation details
knowledge. I.e MMU API does not provide such guarantees, but drivers
know how ARM MMU code is working internally and drivers depend on
exactly this behavior. But if you are saying that it is totally fine,
I'll rework the patch. No big deal. Actually, I already tried this and
it is working fine.
+
+ /* U-Boot ethernet driver wants to drive reset as GPIO */
+ /delete-node/ phy-reset-pins;
I suppose this is not needed as phy-reset-pins also configures the pin
as GPIO only.
Well, yes. This also puzzles me up, but for some reason it stops working
if I leave this node intact. Looks like I need to look at this deeper
before posting the next version.
Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
misbehave, can you check if this patch fixes it (there is a bug in the
line "return msm_gpio_direction_input(dev, gpio);", it should become
just "msm_gpio_direction_input(dev, gpio);").
I had the exact same issue with the gpio-regulator driver and this was
the solution I ended up going with.
https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787...@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
[lore[.]kernel[.]org]
It is exactly this. With your patch I don't need to /delete-node/
anymore. I'll add a comment in the cover message that this series are
depended on your patch.
Please can you split the power domain and clock patches into a separate
series? As I'd like to depend on them for the next revision of my
series, and we'd otherwise have a cyclical dependency.
Of course.
As I understood, you are interested in "clk: qcom: clear div mask before
assigning a new divider" and "clk: qcom: add support for power domains
uclass", correct?
Yes. I tried the power domain stuff out on SMD845 today and ran into
quite a few issues. Specifically as a lot of the devices reference the
rpmhpd power domain which we don't support (and don't *need* to support)
in U-Boot. I'm not sure what the best way forward will be for this.
Maybe a "nop" power domain driver?
Do you have the same issues on sm8150?
--
// Caleb (they/them)
Re: About U-Boot License
On Mon, Mar 11, 2024 at 05:40:19AM +, Kang Lion wrote: > Dear DAS > > > This is lion. Nice to meet you. > > > I'm sending you an e-mail because I have a question about the U-Boot license. > I would like to know about the obligation to disclose the U-Boot code > currently provided by Xilinx(zynqMP). > > > 1. When we use a commercial OS code called RTEMS, we use U-Boot as the > bootloader. > At this time, even if RTEMS OS is commercial, if we merge an image such as an > open source called U-Boot to make a final image and use it, should I release > all the codes? I want to know the scope of disclosure. > > Do we even have to disclose commercial RTEMS OS + Application? > > > 2. Or do you see only U-Boot as a separate image, and since the OS is > commercial, there is no need to interpret it separately and disclose it? > > At this time, should the U-Boot be disclosed according to the license or not? > I wonder. > > > cf) We will just change small part for only definition, but I'm afraid that > we have to disclosure our every code of RTEMS and Application. > > That's why I'm questing it now. > > I know you're busy, but please answer me. This is a question for your company's lawyers. U-Boot can of course be used to launch a proprietary OS. Changes you make to U-Boot need to comply with the license. -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board
Hi Caleb,
Caleb Connolly writes:
> On 06/03/2024 21:24, Volodymyr Babchuk wrote:
>>
>> Hi Caleb,
>>
>> Caleb Connolly writes:
>>
>> [...]
>> +};
>> +
>> + {
>> + /* U-Boot pinctrl driver does not understand multiple tiles */
>> + reg = <0x0 0x0300 0x0 0x100>;
>> + /delete-property/ reg-names;
>
> This won't be needed if we can make the tiles offset in the pinctrl
> driver compatible:
>
> #define WEST 0x
> #define EAST 0x0040
> #define NORTH 0x0080
> #define SOUTH 0x00C0
Hmm, I assume that in this case pinctrl driver should map all the four
tiles independently? Are there guarantees in U-Boot that four separate
memory regions will be mapped into virtual memory with the same relative
positions? Linux clearly don't make such guarantees.
>>>
>>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>>> far as reading the address from DT, nothing else, so this is totally
>>> fine and is how the other SoCs do it.
>>
>> For me it looks like we are depending on implementation details
>> knowledge. I.e MMU API does not provide such guarantees, but drivers
>> know how ARM MMU code is working internally and drivers depend on
>> exactly this behavior. But if you are saying that it is totally fine,
>> I'll rework the patch. No big deal. Actually, I already tried this and
>> it is working fine.
>>
>> +
>> + /* U-Boot ethernet driver wants to drive reset as GPIO */
>> + /delete-node/ phy-reset-pins;
>
> I suppose this is not needed as phy-reset-pins also configures the pin
> as GPIO only.
>
Well, yes. This also puzzles me up, but for some reason it stops working
if I leave this node intact. Looks like I need to look at this deeper
before posting the next version.
>>>
>>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>>> misbehave, can you check if this patch fixes it (there is a bug in the
>>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>>> just "msm_gpio_direction_input(dev, gpio);").
>>>
>>> I had the exact same issue with the gpio-regulator driver and this was
>>> the solution I ended up going with.
>>>
>>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787...@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>>> [lore[.]kernel[.]org]
>>
>> It is exactly this. With your patch I don't need to /delete-node/
>> anymore. I'll add a comment in the cover message that this series are
>> depended on your patch.
>
> Please can you split the power domain and clock patches into a separate
> series? As I'd like to depend on them for the next revision of my
> series, and we'd otherwise have a cyclical dependency.
Of course.
As I understood, you are interested in "clk: qcom: clear div mask before
assigning a new divider" and "clk: qcom: add support for power domains
uclass", correct?
--
WBR, Volodymyr
[PATCH 19/19] mtd: spi-nor: Enable DDR mode functionality with Macronix flash
Added SFDP fixups for Macronix octal flash, with the requirement
of the Invert Dual-byte opcode in Octal DDR mode.
Reference: linux-xlnx@08cf794
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c | 49 +-
drivers/mtd/spi/spi-nor-ids.c | 2 ++
2 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6b396ce681..9c2d70585a 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -4089,18 +4089,18 @@ static int spi_nor_macronix_octal_dtr_enable(struct
spi_nor *nor)
{
struct spi_mem_op op;
int ret;
- u8 buf;
+ u8 *buf = nor->cmd_buf;
ret = write_enable(nor);
if (ret)
return ret;
- buf = SPINOR_REG_MXIC_DC_20;
+ *buf = SPINOR_REG_MXIC_DC_20;
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(1, , 1));
+ SPI_MEM_OP_DATA_OUT(1, buf, 1));
ret = spi_mem_exec_op(nor->spi, );
if (ret)
@@ -4115,18 +4115,33 @@ static int spi_nor_macronix_octal_dtr_enable(struct
spi_nor *nor)
if (ret)
return ret;
- buf = SPINOR_REG_MXIC_OPI_DTR_EN;
+ nor->spi->flags |= SPI_XFER_SET_DDR;
+ *buf = SPINOR_REG_MXIC_OPI_DTR_EN;
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(1, , 1));
+ SPI_MEM_OP_DATA_OUT(1, buf, 1));
ret = spi_mem_exec_op(nor->spi, );
if (ret) {
dev_err(nor->dev, "Failed to enable octal DTR mode\n");
return ret;
}
+
+ /* Read flash ID to make sure the switch was successful. */
+ op = (struct spi_mem_op)
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
+ SPI_MEM_OP_ADDR(4, 0, 1),
+ SPI_MEM_OP_DUMMY(4, 1),
+ SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2),
buf, 1));
+
+ spi_nor_setup_op(nor, , SNOR_PROTO_8_8_8_DTR);
+
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
+
nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
return 0;
@@ -4134,6 +4149,20 @@ static int spi_nor_macronix_octal_dtr_enable(struct
spi_nor *nor)
static void macronix_octal_default_init(struct spi_nor *nor)
{
+ u8 id_byte1, id_byte2;
+ /*
+* Macronix Read Id bytes are always output in STR mode. Since tuning
+* is based on Read Id command, adjust the Read Id bytes that will
+* match the Read Id output in DTR mode.
+*/
+ id_byte1 = nor->spi->device_id[1];
+ id_byte2 = nor->spi->device_id[2];
+ nor->spi->device_id[1] = nor->spi->device_id[0];
+ nor->spi->device_id[2] = id_byte1;
+ nor->spi->device_id[3] = id_byte1;
+ nor->spi->device_id[4] = id_byte2;
+ nor->spi->device_id[5] = id_byte2;
+
nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
}
@@ -4144,8 +4173,16 @@ static void macronix_octal_post_sfdp_fixup(struct
spi_nor *nor,
* Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
* SPI_NOR_OCTAL_DTR_READ flag exists.
*/
- if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
+ if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR) {
params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+
spi_nor_set_read_settings(>reads[SNOR_CMD_READ_8_8_8_DTR],
+ 0, 20, SPINOR_OP_MXIC_DTR_RD,
+ SNOR_PROTO_8_8_8_DTR);
+ nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
+ nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
+ params->rdsr_dummy = 8;
+ params->rdsr_addr_nbytes = 0;
+ }
}
static struct spi_nor_fixups macronix_octal_fixups = {
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 34fba49592..cd3fcda70c 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -275,6 +275,8 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("mx25um51345g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_4B_OPCODES |
[PATCH 18/19] mtd: spi-nor: Enable DDR mode functionality with Gigadevice flash
Enable the utilization of mt35xu512aba_fixups for GIGADEVICE
octal flash to operate in DDR mode.
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c | 9 -
drivers/mtd/spi/spi-nor-ids.c | 2 +-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 27579cbf15..6b396ce681 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3977,7 +3977,7 @@ static struct spi_nor_fixups s28hx_t_fixups = {
};
#endif /* CONFIG_SPI_FLASH_S28HX_T */
-#if defined(CONFIG_SPI_FLASH_MT35XU) || defined(CONFIG_SPI_FLASH_ISSI)
+#if defined(CONFIG_SPI_FLASH_MT35XU) || defined(CONFIG_SPI_FLASH_ISSI) ||
defined(CONFIG_SPI_FLASH_GIGADEVICE)
static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
{
struct spi_mem_op op;
@@ -4356,6 +4356,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)
}
#endif
+#if defined(CONFIG_SPI_FLASH_GIGADEVICE)
+ if (!strcmp(nor->info->name, "gd25lx256e")) {
+ nor->fixups = _fixups;
+ return;
+ }
+#endif
+
#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
nor->fixups = _octal_fixups;
#endif /* SPI_FLASH_MACRONIX */
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index c5c46c1a0c..34fba49592 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -192,7 +192,7 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
-SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
+SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
SPI_NOR_HAS_TB | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
},
/* adding these 1.8V OSPI flash parts */
{INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024,SECT_4K |
--
2.27.0
[PATCH 17/19] mtd: spi-nor: Enable DDR mode functionality with ISSI flash
Enable the utilization of mt35xu512aba_fixups for ISSI octal
flash to operate in DDR mode.
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c | 10 +-
drivers/mtd/spi/spi-nor-ids.c | 4 ++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f1dbeb4725..27579cbf15 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3977,7 +3977,7 @@ static struct spi_nor_fixups s28hx_t_fixups = {
};
#endif /* CONFIG_SPI_FLASH_S28HX_T */
-#ifdef CONFIG_SPI_FLASH_MT35XU
+#if defined(CONFIG_SPI_FLASH_MT35XU) || defined(CONFIG_SPI_FLASH_ISSI)
static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
{
struct spi_mem_op op;
@@ -4348,6 +4348,14 @@ void spi_nor_set_fixups(struct spi_nor *nor)
}
#endif
+#if defined(CONFIG_SPI_FLASH_ISSI)
+ if (!strcmp(nor->info->name, "is25wx256") ||
+ !strcmp(nor->info->name, "is25lx512")) {
+ nor->fixups = _fixups;
+ return;
+ }
+#endif
+
#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
nor->fixups = _octal_fixups;
#endif /* SPI_FLASH_MACRONIX */
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index f8ef87783e..c5c46c1a0c 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -239,9 +239,9 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
- SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
SPI_NOR_4B_OPCODES) },
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
{ INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024,
- SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES |
SPI_NOR_HAS_TB) },
+ SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB
| SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
--
2.27.0
[PATCH 15/19] spi: mtd: Use split reads if multi-die flag is set
From: T Karthik Reddy
Some flash devices have multiple dies in it & has die cross over
issue. When SPI_NOR_MULTI_DIE flag is set in flash id table use
it to enable split reads to avoid above issue. Define SPI_NOR_MULTI_DIE
new flag to flash id flags. Remove SPI_FLASH_SPLIT_READ config and
related code from the zynq and zynqmp qspi drivers as it is redundant.
Signed-off-by: T Karthik Reddy
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 9c09f97ce2..2cbdea60b0 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -70,6 +70,7 @@ struct flash_info {
#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */
#define SPI_NOR_OCTAL_DTR_PP BIT(18) /* Flash supports Octal DTR page
program */
+#define SPI_NOR_MULTI_DIE BIT(19) /* Flash has multi dies & need split
reads*/
};
extern const struct flash_info spi_nor_ids[];
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 8a3cff94db..f1dbeb4725 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -4470,6 +4470,9 @@ int spi_nor_scan(struct spi_nor *nor)
if (info->flags & SPI_NOR_NO_ERASE)
mtd->flags |= MTD_NO_ERASE;
+ if (info->flags & SPI_NOR_MULTI_DIE)
+ nor->spi->multi_die = true;
+
nor->page_size = params.page_size;
mtd->writebufsize = nor->page_size;
--
2.27.0
[PATCH 16/19] arm64: versal: Enable soft reset support for xspi flashes
Activate the xSPI Software Reset support, which will be utilized to transition from octal DTR mode to legacy mode during shutdown and boot (if enabled). Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 78141bd45f..92c95e6b5d 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -93,6 +93,8 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=10 CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y -- 2.27.0
[PATCH 14/19] mtd: spi-nor: Enable DTR octal flash program
From: Ashok Reddy Soma
Define a flag SPI_NOR_OCTAL_DTR_PP and if enabled in spi-nor-ids table,
enable octal DTR page program in the framework.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 7 +--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d3ef69ec74..9c09f97ce2 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -69,6 +69,7 @@ struct flash_info {
#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */
+#define SPI_NOR_OCTAL_DTR_PP BIT(18) /* Flash supports Octal DTR page
program */
};
extern const struct flash_info spi_nor_ids[];
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index ffb9a48316..8a3cff94db 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3076,8 +3076,11 @@ static int spi_nor_init_params(struct spi_nor *nor,
* Since xSPI Page Program opcode is backward compatible with
* Legacy SPI, use Legacy SPI opcode there as well.
*/
- spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP_8_8_8_DTR],
- SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
+ if (info->flags & SPI_NOR_OCTAL_DTR_PP) {
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP_8_8_8_DTR],
+ SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
+ }
if (info->flags & SPI_NOR_QUAD_READ) {
params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
--
2.27.0
[PATCH 13/19] mtd: spi-nor: Add support for cross die read in dual flash configuration
From: Ashok Reddy Soma
In a dual parallel configuration, halve the read offset.
Determine whether the read offset points to the lower or
upper flash in a dual stacked configuration and set the
corresponding flags accordingly.
Include support for cases where the read involves an odd
number of bytes.
Extend support for cross-die reads in flash memory devices
that contain multiple dies within them.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c | 42 ++
include/spi.h | 3 ++-
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index e0398a7a29..ffb9a48316 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1528,11 +1528,9 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
from, size_t len,
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
int ret;
- loff_t offset = from;
- u32 read_len = 0;
- u32 rem_bank_len = 0;
- u8 bank;
- bool is_ofst_odd = false;
+ u32 offset = from;
+ u32 bank_size, stack_shift = 0, read_len = 0, rem_bank_len = 0;
+ u8 bank, cur_bank, nxt_bank, is_ofst_odd = 0;
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
@@ -1565,6 +1563,40 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
from, size_t len,
}
}
+ if (nor->addr_width == 4) {
+ /*
+* Some flash devices like N25Q512 have multiple dies
+* in it. Read operation in these devices is bounded
+* by its die segment. In a continuous read, across
+* multiple dies, when the last byte of the selected
+* die segment is read, the next byte read is the
+* first byte of the same die segment. This is Die
+* cross over issue. So to handle this issue, split
+* a read transaction, that spans across multiple
+* banks, into one read per bank. Bank size is 16MB
+* for single and dual stacked mode and 32MB for dual
+* parallel mode.
+*/
+ if (nor->spi && nor->spi->multi_die) {
+ bank_size = SZ_16M;
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ bank_size <<= 1;
+ cur_bank = offset / bank_size;
+ nxt_bank = (offset + len) / bank_size;
+ if (cur_bank != nxt_bank)
+ rem_bank_len = (bank_size *
+ (cur_bank + 1)) -
+ offset;
+ else
+ rem_bank_len = (mtd->size >>
+ stack_shift) -
+ offset;
+ } else {
+ rem_bank_len = (mtd->size >> stack_shift) -
+ offset;
+ }
+ }
+
if (nor->flags & SNOR_F_HAS_PARALLEL)
offset /= 2;
diff --git a/include/spi.h b/include/spi.h
index ade30fab73..7b6c49cfc5 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -166,7 +166,7 @@ struct spi_slave {
unsigned int max_write_size;
void *memory_map;
- u8 flags;
+ u32 flags;
#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
@@ -180,6 +180,7 @@ struct spi_slave {
*/
bool multi_cs_cap;
u32 bytemode;
+ bool multi_die; /* flash with multiple dies */
};
/**
--
2.27.0
[PATCH 12/19] mtd: spi-nor: Update erase operation function
If the system is in a dual parallel configuration, it's necessary to
halve the erase size since the erase command operates on two flashes
simultaneously. When dealing with a dual-stacked configuration,
determine whether the erase offset refers to the top or bottom flash,
and subsequently, adjust the flag for the relevant flash.
Consequently, the argument for the spi_nor_erase_sector function has
been modified from addr to offset.
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b9326d2b47..e0398a7a29 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1095,7 +1095,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
}
}
#ifdef CONFIG_SPI_FLASH_BAR
- ret = write_bar(nor, addr);
+ ret = write_bar(nor, offset);
if (ret < 0)
goto erase_err;
#endif
@@ -1107,7 +1107,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
ret = spi_nor_erase_chip(nor);
} else {
- ret = spi_nor_erase_sector(nor, addr);
+ ret = spi_nor_erase_sector(nor, offset);
}
if (ret < 0)
goto erase_err;
--
2.27.0
[PATCH 11/19] spi: cadence_qspi: Add spi mem dtr support ops
From: T Karthik Reddy
In DDR mode, current default spi_mem_dtr_supports_op() function does
not allow mixed DTR operation functionality. So implement cadence
specific cadence_spi_mem_dtr_supports_op() function to verifying only
the command buswidth and command opcode bytes which satisfies the DTR
protocol.
Signed-off-by: T Karthik Reddy
Signed-off-by: Tejas Bhumkar
---
drivers/spi/cadence_qspi.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index d312bafd90..f1c8efe59c 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -708,6 +708,21 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
return err;
}
+static bool cadence_spi_mem_dtr_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ /*
+* In DTR mode, except op->cmd all other parameters like address,
+* dummy and data could be 0.
+* So lets only check if the cmd buswidth and number of opcode bytes
+* are true for DTR to support.
+*/
+ if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2)
+ return false;
+
+ return true;
+}
+
static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
@@ -730,7 +745,7 @@ static bool cadence_spi_mem_supports_op(struct spi_slave
*slave,
return false;
if (all_true)
- return spi_mem_dtr_supports_op(slave, op);
+ return cadence_spi_mem_dtr_supports_op(slave, op);
else
return spi_mem_default_supports_op(slave, op);
}
--
2.27.0
[PATCH 10/19] mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled
From: Ashok Reddy Soma
With 'commit bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map")', support
for spi_nor_parse_sccr is added under SFDP. But the flag
SNOR_F_IO_MODE_EN_VOLATILE in spi_nor_octal_dtr_enable is always
checked. Check this flag only if SPI_FLASH_SFDP_SUPPORT enabled.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index e8640cbf07..b9326d2b47 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -4135,8 +4135,9 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
nor->write_proto == SNOR_PROTO_8_8_8_DTR))
return 0;
- if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
- return 0;
+ if (CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT))
+ if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
+ return 0;
ret = nor->octal_dtr_enable(nor);
if (ret)
--
2.27.0
[PATCH 06/19] spi: cadence_qspi: Initialize read and write watermark registers
From: Ashok Reddy Soma Read and Write watermark registers are not initialized. Set read watermark to half of the FIFO and write watermark to 1/8 of the FIFO size. Read watermark indicates if SRAM fill level is above this watermark, interrupt will be generated and read or DMA can be performed. Write watermark indicates the maximum fill level of SRAM when write is performed to device. These values of 1/2 for read and 1/8 for write are chosen similar to Linux driver. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 35a21a2727..8ea40551c1 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -356,6 +356,14 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) /* Indirect mode configurations */ writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION); + /* Program read watermark -- 1/2 of the FIFO. */ + writel(priv->fifo_depth * priv->fifo_width / 2, + priv->regbase + CQSPI_REG_INDIRECTRDWATERMARK); + + /* Program write watermark -- 1/8 of the FIFO. */ + writel(priv->fifo_depth * priv->fifo_width / 8, + priv->regbase + CQSPI_REG_INDIRECTWRWATERMARK); + /* Disable all interrupts */ writel(0, priv->regbase + CQSPI_REG_IRQMASK); -- 2.27.0
[PATCH 08/19] arm64: versal: Enable defconfig for Micron octal flashes
The Micron MT35 series octal flashes can be activated through the configuration option CONFIG_SPI_FLASH_MT35XU. To ensure their detection, enable this option in the default defconfig for octal flashes. Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index c9b8a6de01..78141bd45f 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -98,6 +98,7 @@ CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -- 2.27.0
[PATCH 09/19] mtd: spi-nor: Update block protection flags for flash parts
From: Venkatesh Yadav Abbarapu
The block protection flags for Gigadevice, Spansion, and ISSI flash
memory have been modified. Additionally, new flags for
SPI_NOR_OCTAL_DTR_READ and octal DTR page programming have been
introduced for Micron OSPI flashes. Furthermore, the flashes mt35xu01g
and mt35xu02g have been incorporated into the CONFIG_SPI_FLASH_MT35XU
configuration, so that in driver mt35xu512aba_fixups will be applied.
Signed-off-by: Venkatesh Yadav Abbarapu
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-ids.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 4e83b8c94c..f8ef87783e 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -123,9 +123,9 @@ const struct flash_info spi_nor_ids[] = {
{INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
SPI_NOR_4B_OPCODES) },
{INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
- SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES |
SPI_NOR_HAS_TB)},
{INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
- SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES |
SPI_NOR_HAS_TB)},
{INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K |
@@ -218,11 +218,11 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_TB) },
{ INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_TB) },
{ INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_TB) },
{ INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
{ INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
{ INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
@@ -326,11 +326,15 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_MT35XU
- { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
- { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
+ { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
+ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
+ { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
- { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
- { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least
@@ -339,8 +343,8 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
- { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
[PATCH 07/19] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes
From: Ashok Reddy Soma
Enable mt35xu512aba_fixups for all mt35 series flashes to work
in DTR mode, and return after nor->fixups is updated, otherwise
it will get overwritten with macronix_octal_fixups.
This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU
is enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.
Additionally, a new flag, "SPI_XFER_SET_DDR," has been introduced
to instruct the Ospi controller driver to switch to DDR mode.
Signed-off-by: Ashok Reddy Soma
Co-developed-by: Tejas Bhumkar
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c | 8 +++-
drivers/spi/cadence_qspi.c | 2 +-
include/spi.h | 1 +
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 5895b5de09..e8640cbf07 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3975,6 +3975,7 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor
*nor)
if (ret)
return ret;
+ nor->spi->flags |= SPI_XFER_SET_DDR;
*buf = SPINOR_MT_OCT_DTR;
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
@@ -4302,8 +4303,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)
#endif
#ifdef CONFIG_SPI_FLASH_MT35XU
- if (!strcmp(nor->info->name, "mt35xu512aba"))
+ if (!strcmp(nor->info->name, "mt35xu512aba") ||
+ !strcmp(nor->info->name, "mt35xl512aba") ||
+ !strcmp(nor->info->name, "mt35xu01g") ||
+ !strcmp(nor->info->name, "mt35xu02g")) {
nor->fixups = _fixups;
+ return;
+ }
#endif
#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index dd6aef9ab5..d312bafd90 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -702,7 +702,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
break;
}
- if (op->cmd.dtr)
+ if ((spi->flags & SPI_XFER_SET_DDR) && op->cmd.dtr)
err = cadence_spi_setup_ddrmode(spi, op);
return err;
diff --git a/include/spi.h b/include/spi.h
index ab51c8428b..ade30fab73 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -172,6 +172,7 @@ struct spi_slave {
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
#define SPI_XFER_U_PAGEBIT(4)
#define SPI_XFER_STACKED BIT(5)
+#define SPI_XFER_SET_DDR BIT(6)
/*
* Flag indicating that the spi-controller has multi chip select
* capability and can assert/de-assert more than one chip select
--
2.27.0
[PATCH 05/19] spi: cadence_qspi: Clean up registers in init
From: Ashok Reddy Soma This patch cleans up the cadence qspi registers in the init. The register contents may be invalid if this controller is used in previous boot and comes to uboot after a softreset (no power on reset). This may cause issues in uboot. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7576dacfb0..35a21a2727 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -340,12 +340,34 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) /* Configure the remap address register, no remap */ writel(0, priv->regbase + CQSPI_REG_REMAP); + /* Clear instruction read config register */ + writel(0, priv->regbase + CQSPI_REG_RD_INSTR); + + /* Reset the Delay lines */ + writel(CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK, + priv->regbase + CQSPI_REG_PHY_CONFIG); + + reg = readl(priv->regbase + CQSPI_REG_RD_DATA_CAPTURE); + reg &= ~CQSPI_REG_READCAPTURE_DQS_ENABLE; + reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK +<< CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + writel(reg, priv->regbase + CQSPI_REG_RD_DATA_CAPTURE); + /* Indirect mode configurations */ writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION); /* Disable all interrupts */ writel(0, priv->regbase + CQSPI_REG_IRQMASK); + reg = readl(priv->regbase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_DTR_PROT_EN_MASK; + reg &= ~CQSPI_REG_CONFIG_PHY_ENABLE_MASK; + reg &= ~CQSPI_REG_CONFIG_DIRECT; + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK + << CQSPI_REG_CONFIG_CHIPSELECT_LSB); + + writel(reg, priv->regbase + CQSPI_REG_CONFIG); + cadence_qspi_apb_controller_enable(priv->regbase); } -- 2.27.0
[PATCH 04/19] spi: cadence_qspi: Write aligned byte length to ahbbase
From: Ashok Reddy Soma
Incase of non-aligned length of flash data, ahbbase address is written
directly with byte count. This is causing AHB bus error's sometimes and
resulting in kernel crash while booting linux. To avoid this write 4 byte
aligned byte count to ahbbase address.
Also use a temporary variable with 0x data and overwrite this
temp with unaligned bytes data before writing to ahbbase.
The value 0x is chosen as this is flash memory, worst case we
will write 0xff to any location which doesn't effect any bits.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/spi/cadence_qspi_apb.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 4404b0ba07..7576dacfb0 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -891,10 +891,12 @@ cadence_qspi_apb_indirect_write_execute(struct
cadence_spi_priv *priv,
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
writesl(priv->ahbbase, bb_txbuf, write_bytes >> 2);
- if (write_bytes % 4)
- writesb(priv->ahbbase,
- bb_txbuf + rounddown(write_bytes, 4),
- write_bytes % 4);
+ if (write_bytes % 4) {
+ unsigned int temp = 0x;
+
+ memcpy(, bb_txbuf + rounddown(write_bytes, 4),
write_bytes % 4);
+ writel(temp, priv->ahbbase);
+ }
ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_SDRAMLEVEL,
CQSPI_REG_SDRAMLEVEL_WR_MASK <<
--
2.27.0
[PATCH 03/19] spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver
From: T Karthik Reddy
Set cmd, address & data buswidth to octal. Handle dummy clock
cycles incase of reads & writes. Convert odd bytes to even
bytes lengths in ddr mode, as we cannot rx/tx odd data in
ddr mode.
Disable the DMA once the transfer is done to avoid disabling
it at other places.
Signed-off-by: T Karthik Reddy
Signed-off-by: Tejas Bhumkar
---
drivers/spi/cadence_ospi_versal.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/cadence_ospi_versal.c
b/drivers/spi/cadence_ospi_versal.c
index 30abb7b431..2c5bdd5f26 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -23,7 +23,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
const struct spi_mem_op *op)
{
u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
- u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
+ u8 opcode, addr_bytes, *rxbuf, dummy_cycles, unaligned_byte;
n_rx = op->data.nbytes;
rxbuf = op->data.buf.in;
@@ -67,13 +67,14 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
writel(CQSPI_REG_INDIRECTRD_DONE, priv->regbase +
CQSPI_REG_INDIRECTRD);
rxbuf += bytes_to_dma;
- }
- if (rx_rem) {
+ /* Disable DMA on completion */
reg = readl(priv->regbase + CQSPI_REG_CONFIG);
reg &= ~CQSPI_REG_CONFIG_ENBL_DMA;
writel(reg, priv->regbase + CQSPI_REG_CONFIG);
+ }
+ if (rx_rem) {
reg = readl(priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
reg += bytes_to_dma;
writel(reg, priv->regbase + CQSPI_REG_CMDADDRESS);
@@ -81,10 +82,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
addr_bytes = readl(priv->regbase + CQSPI_REG_SIZE) &
CQSPI_REG_SIZE_ADDRESS_MASK;
- opcode = CMD_4BYTE_FAST_READ;
- dummy_cycles = 8;
- writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
- priv->regbase + CQSPI_REG_RD_INSTR);
+ opcode = (u8)readl(priv->regbase + CQSPI_REG_RD_INSTR);
+ if (opcode == CMD_4BYTE_OCTAL_READ &&
+ priv->edge_mode != CQSPI_EDGE_MODE_DDR)
+ opcode = CMD_4BYTE_FAST_READ;
reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
@@ -96,7 +97,12 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
CQSPI_REG_RD_INSTR_DUMMY_MASK;
reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) <<
CQSPI_REG_CMDCTRL_DUMMY_LSB;
- reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) <<
+ if (priv->edge_mode == CQSPI_EDGE_MODE_DDR && (rx_rem % 2) != 0)
+ unaligned_byte = 1;
+ else
+ unaligned_byte = 0;
+ reg |= (((rx_rem - 1 + unaligned_byte) &
+ CQSPI_REG_CMDCTRL_RD_BYTES_MASK) <<
CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
ret = cadence_qspi_apb_exec_flash_cmd(priv->regbase, reg);
if (ret)
--
2.27.0
[PATCH 02/19] spi: cadence-qspi: reset the ospi controller
From: T Karthik Reddy
The Cadence driver must switch between SDR and DTR modes as
directed by commands from the spi-nor framework. It should
avoid reinitializing SDR/DTR tuning if it has already been
completed.
Additionally, functionality has been added to reset the
controller when transitioning from DTR to SDR mode. This
reset is achieved using the reset_assert and reset_deassert
APIs for the OSPI controller. In cases where the ZYNQMP_FIRMWARE
configuration is disabled in mini U-Boot, the controller is
reset directly using register writes.
The configuration of the chip select in the Cadence QSPI driver
is now determined based on the flags received from the SPI-NOR
framework.
Signed-off-by: T Karthik Reddy
Signed-off-by: Tejas Bhumkar
---
drivers/spi/cadence_ospi_versal.c | 29 ++
drivers/spi/cadence_qspi.c| 63 ---
drivers/spi/cadence_qspi.h| 7
3 files changed, 94 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/cadence_ospi_versal.c
b/drivers/spi/cadence_ospi_versal.c
index 70682490e6..30abb7b431 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -151,6 +151,35 @@ int cadence_qspi_versal_set_dll_mode(struct udevice *dev)
return -ENOTSUPP;
}
+int cadence_spi_versal_ctrl_reset(struct cadence_spi_priv *priv)
+{
+ int ret;
+
+ if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) {
+ /* Assert ospi controller */
+ ret = reset_assert(priv->resets->resets);
+ if (ret)
+ return ret;
+
+ udelay(10);
+
+ /* Deassert ospi controller */
+ ret = reset_deassert(priv->resets->resets);
+ if (ret)
+ return ret;
+ } else {
+ /* Assert ospi controller */
+ setbits_le32((u32 *)OSPI_CTRL_RST, 1);
+
+ udelay(10);
+
+ /* Deassert ospi controller */
+ clrbits_le32((u32 *)OSPI_CTRL_RST, 1);
+ }
+
+ return 0;
+}
+
#if defined(CONFIG_DM_GPIO)
int cadence_qspi_versal_flash_reset(struct udevice *dev)
{
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 0a1257352a..dd6aef9ab5 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -148,7 +148,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
/* just to ensure we do once only when speed or chip select change */
priv->qspi_calibrated_hz = hz;
- priv->qspi_calibrated_cs = spi_chip_select(bus);
+ priv->qspi_calibrated_cs = priv->cs;
return 0;
}
@@ -173,7 +173,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint
hz)
priv->read_delay);
} else if (priv->previous_hz != hz ||
priv->qspi_calibrated_hz != hz ||
- priv->qspi_calibrated_cs != spi_chip_select(bus)) {
+ priv->qspi_calibrated_cs != priv->cs) {
/*
* Calibration required for different current SCLK speed,
* requested SCLK speed or chip select
@@ -574,6 +574,9 @@ static int cadence_spi_setup_ddrmode(struct spi_slave *spi,
const struct spi_mem
struct cadence_spi_priv *priv = dev_get_priv(bus);
int ret;
+ if (priv->ddr_init)
+ return 0;
+
ret = priv_setup_ddrmode(bus);
if (ret)
return ret;
@@ -584,7 +587,47 @@ static int cadence_spi_setup_ddrmode(struct spi_slave
*spi, const struct spi_mem
printf("DDR tuning failed with error %d\n", ret);
return ret;
}
- priv->ddr_init = 1;
+ priv->ddr_init = true;
+
+ return 0;
+}
+
+static int cadence_spi_setup_strmode(struct udevice *bus)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ void *base = priv->regbase;
+ int ret;
+
+ if (!priv->ddr_init)
+ return 0;
+
+ /* Reset ospi controller */
+ ret = cadence_spi_versal_ctrl_reset(priv);
+ if (ret) {
+ printf("Cadence ctrl reset failed err: %d\n", ret);
+ return ret;
+ }
+
+ ret = wait_for_bit_le32(base + CQSPI_REG_CONFIG,
+ BIT(CQSPI_REG_CONFIG_IDLE_LSB),
+ 1, CQSPI_TIMEOUT_MS, 0);
+ if (ret) {
+ printf("spi_wait_idle error : 0x%x\n", ret);
+ return ret;
+ }
+
+ cadence_qspi_apb_controller_init(priv);
+ priv->edge_mode = CQSPI_EDGE_MODE_SDR;
+ priv->extra_dummy = 0;
+ priv->previous_hz = 0;
+ priv->qspi_calibrated_hz = 0;
+
+ /* Setup default speed and calibrate */
+ ret = cadence_spi_set_speed(bus, 0);
+ if (ret)
+ return ret;
+
+ priv->ddr_init = false;
return 0;
}
@@ -598,9 +641,19 @@ static int
[PATCH 01/19] spi: cadence_qspi: Add support for DDR PHY mode
From: T Karthik Reddy
Support has been added for DDR PHY mode in both DLL bypass
mode and master DLL mode.
To switch the OSPI controller from SDR to DDR mode, Rx DLL
tuning involves adjusting the TX delay, incrementing the
RX delay, and verifying correct flash IDs by reading from
the flash.
Moreover, support has been extended to enable DDR mode for
Micron flash. In the spi_nor_micron_octal_dtr_enable function,
the cmd->buf is utilized to read the flash ID during
RX DLL tuning.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: T Karthik Reddy
Co-developed-by: Tejas Bhumkar
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-core.c| 50 +++--
drivers/spi/cadence_ospi_versal.c | 25 +++
drivers/spi/cadence_qspi.c| 300 ++
drivers/spi/cadence_qspi.h| 50 +
drivers/spi/cadence_qspi_apb.c| 33 +++-
include/spi.h | 3 +
6 files changed, 436 insertions(+), 25 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index faf02c7778..5895b5de09 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1511,8 +1511,10 @@ static const struct flash_info *spi_nor_read_id(struct
spi_nor *nor)
info = spi_nor_ids;
for (; info->name; info++) {
if (info->id_len) {
- if (!memcmp(info->id, id, info->id_len))
+ if ((!memcmp(info->id, id, info->id_len)) &&
+ memcpy(nor->spi->device_id, id,
SPI_NOR_MAX_ID_LEN)) {
return info;
+ }
}
}
@@ -3944,7 +3946,7 @@ static struct spi_nor_fixups s28hx_t_fixups = {
static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
{
struct spi_mem_op op;
- u8 buf;
+ u8 *buf = nor->cmd_buf;
u8 addr_width = 3;
int ret;
@@ -3953,12 +3955,12 @@ static int spi_nor_micron_octal_dtr_enable(struct
spi_nor *nor)
if (ret)
return ret;
- buf = 20;
+ *buf = 20;
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1),
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(1, , 1));
+ SPI_MEM_OP_DATA_OUT(1, buf, 1));
ret = spi_mem_exec_op(nor->spi, );
if (ret)
return ret;
@@ -3973,18 +3975,33 @@ static int spi_nor_micron_octal_dtr_enable(struct
spi_nor *nor)
if (ret)
return ret;
- buf = SPINOR_MT_OCT_DTR;
+ *buf = SPINOR_MT_OCT_DTR;
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1),
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(1, , 1));
+ SPI_MEM_OP_DATA_OUT(1, buf, 1));
ret = spi_mem_exec_op(nor->spi, );
if (ret) {
dev_err(nor->dev, "Failed to enable octal DTR mode\n");
return ret;
}
+ /* Read flash ID to make sure the switch was successful. */
+ op = (struct spi_mem_op)
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0),
+ SPI_MEM_OP_ADDR(0, 0, 0),
+ SPI_MEM_OP_DUMMY(8, 0),
+ SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, buf, 0));
+
+ spi_nor_setup_op(nor, , SNOR_PROTO_8_8_8_DTR);
+
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
+
+ nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+
return 0;
}
@@ -3996,18 +4013,19 @@ static void mt35xu512aba_default_init(struct spi_nor
*nor)
static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor,
struct spi_nor_flash_parameter *params)
{
- /* Set the Fast Read settings. */
- params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
- spi_nor_set_read_settings(>reads[SNOR_CMD_READ_8_8_8_DTR],
- 0, 20, SPINOR_OP_MT_DTR_RD,
- SNOR_PROTO_8_8_8_DTR);
-
- params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+ if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR) {
+ /* Set the Fast Read settings. */
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+
spi_nor_set_read_settings(>reads[SNOR_CMD_READ_8_8_8_DTR],
+ 0, 20, SPINOR_OP_MT_DTR_RD,
+ SNOR_PROTO_8_8_8_DTR);
- nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
- params->rdsr_dummy = 8;
- params->rdsr_addr_nbytes = 0;
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+ nor->cmd_ext_type =
[PATCH 00/19] Add support for DDR PHY mode
Enable DDR PHY mode support for Micron,ISSI,GIGA and Macronix Flash. We are dividing the below series into three sets. This represents the initial set, wherein we have activated DDR mode support for flashes. https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhum...@amd.com/ The series is based on: https://lore.kernel.org/all/20240304031046.25998-1-venkatesh.abbar...@amd.com/ --- Ashok Reddy Soma (7): spi: cadence_qspi: Write aligned byte length to ahbbase spi: cadence_qspi: Clean up registers in init spi: cadence_qspi: Initialize read and write watermark registers mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled mtd: spi-nor: Add support for cross die read in dual flash configuration mtd: spi-nor: Enable DTR octal flash program T Karthik Reddy (5): spi: cadence_qspi: Add support for DDR PHY mode spi: cadence-qspi: reset the ospi controller spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver spi: cadence_qspi: Add spi mem dtr support ops spi: mtd: Use split reads if multi-die flag is set Tejas Bhumkar (6): arm64: versal: Enable defconfig for Micron octal flashes mtd: spi-nor: Update erase operation function arm64: versal: Enable soft reset support for xspi flashes mtd: spi-nor: Enable DDR mode functionality with ISSI flash mtd: spi-nor: Enable DDR mode functionality with Gigadevice flash mtd: spi-nor: Enable DDR mode functionality with Macronix flash Venkatesh Yadav Abbarapu (1): mtd: spi-nor: Update block protection flags for flash parts configs/xilinx_versal_virt_defconfig | 3 + drivers/mtd/spi/sf_internal.h| 2 + drivers/mtd/spi/spi-nor-core.c | 185 ++--- drivers/mtd/spi/spi-nor-ids.c| 36 +-- drivers/spi/cadence_ospi_versal.c| 76 +- drivers/spi/cadence_qspi.c | 378 ++- drivers/spi/cadence_qspi.h | 57 drivers/spi/cadence_qspi_apb.c | 73 +- include/spi.h| 7 +- 9 files changed, 740 insertions(+), 77 deletions(-) -- 2.27.0
[ANN] U-Boot v2024.04-rc4 released
Hey all, It's release day and so here's -rc4, and I'll be updating the next branch with this as well shortly. In terms of a changelog, git log --merges v2024.04-rc3..v2024.04-rc4 contains what I've pulled but as always, better PR messages and tags will provide better results here. At this point there's one more -rc before the release on April 2nd, 2024. If there are regression fixes that you know of please speak up so we can ensure they're in the release. Otherwise changes should be targetting the next branch. Thanks all! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] lmb: Avoid to add identical region in lmb_add_region_flags()
On 3/11/2024 8:09 PM, Patrice Chotard wrote:
In case lmb_add_region_flags() is called with the same parameter than
an already existing lmb and this lmb is adjacent to its previous lmb with
different flag, this lmb is added again.
Same parameter means , addr and size and different flags correct ?
Instead breaking the loop, continue, at the next iteration, we are able
to detect that this region already exist.
Once region already exist detected, then you can think of returning
error , no ?
Issue reproduced on STM32MP157-DK2 with SCMI DT, bdinfo command's output
shows:
Before this patch, the last LMB [0xde00-0xdfff] is duplicated:
...
lmb_dump_all:nnn
memory.cnt = 0x1 / max = 0x2
memory[0] [0xc000-0xdfff], 0x2000 bytes flags: 0
reserved.cnt = 0x6 / max = 0x10
reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4
reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4
reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4
reserved[3][0xdaadf000-0xdfff], 0x05521000 bytes flags: 0
reserved[4][0xde00-0xdfff], 0x0200 bytes flags: 4
reserved[5][0xde00-0xdfff], 0x0200 bytes flags: 4
...
After this patch:
...
lmb_dump_all:
memory.cnt = 0x1 / max = 0x2
memory[0] [0xc000-0xdfff], 0x2000 bytes flags: 0
reserved.cnt = 0x5 / max = 0x10
reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4
reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4
reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4
reserved[3][0xdaadf000-0xdfff], 0x05521000 bytes flags: 0
reserved[4][0xde00-0xdfff], 0x0200 bytes flags: 4
...
Fixes: 59c0ea5df33f ("lmb: Add support of flags for no-map properties")
Signed-off-by: Patrice Chotard
---
lib/lmb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/lmb.c b/lib/lmb.c
index 44f98205310..b6afb731440 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -285,14 +285,14 @@ static long lmb_add_region_flags(struct lmb_region *rgn,
phys_addr_t base,
adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
if (adjacent > 0) {
if (flags != rgnflags)
- break;
+ continue;
rgn->region[i].base -= size;
rgn->region[i].size += size;
coalesced++;
break;
} else if (adjacent < 0) {
if (flags != rgnflags)
- break;
+ continue;
rgn->region[i].size += size;
coalesced++;
break;
Re: [PATCH 3/5] configs: phycore-imx8mp_defconfig: Use redundant environment
Hi Leonard, On Mon, Mar 11, 2024 at 11:32 AM Leonard Anderweit wrote: > I also got an error while applying this to next. To apply cleanly this > series requires the commit 19f657600781 (configs: Resync with > savedefconfig) which is on master but not on next. > > If this missing commit is intended I'll resend this series based on > next. At this point, the master branch is open only for bug fixes. This series is targeted at the next branch, so please send a v2 based on next and I will apply it.
[RFC PATCH 1/3] ARM: dts: at91sam9260: Add modern NAND controller nodes
Required for using the new dm enabled nand-controller driver on sam9260
family based boards. Ported from Linux v6.8. Node for old NAND driver
binding kept in place for now, so we can change nan controller driver
board by board.
Signed-off-by: Alexander Dahl
---
arch/arm/dts/at91sam9260.dtsi | 47 +++
1 file changed, 47 insertions(+)
diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi
index 4ea4202737c..c320c82c6dd 100644
--- a/arch/arm/dts/at91sam9260.dtsi
+++ b/arch/arm/dts/at91sam9260.dtsi
@@ -99,6 +99,16 @@
reg = <0xea00 0x200>;
};
+ smc: smc@ec00 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xec00 0x200>;
+ };
+
+ matrix: matrix@ee00 {
+ compatible = "atmel,at91sam9260-matrix",
"syscon";
+ reg = <0xee00 0x200>;
+ };
+
pmc: pmc@fc00 {
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfc00 0x100>;
@@ -575,6 +585,16 @@
; /* PC14 gpio enable pin pull_up */
};
+
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ ;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+;
+ };
};
macb {
@@ -1030,6 +1050,33 @@
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
+
+ ebi: ebi@1000 {
+ compatible = "atmel,at91sam9260-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <>;
+ atmel,matrix = <>;
+ reg = <0x1000 0x8000>;
+ ranges = <0x0 0x0 0x1000 0x1000
+ 0x1 0x0 0x2000 0x1000
+ 0x2 0x0 0x3000 0x1000
+ 0x3 0x0 0x4000 0x1000
+ 0x4 0x0 0x5000 0x1000
+ 0x5 0x0 0x6000 0x1000
+ 0x6 0x0 0x7000 0x1000
+ 0x7 0x0 0x8000 0x1000>;
+ clocks = <>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible =
"atmel,at91sam9260-nand-controller";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
};
i2c@0 {
--
2.39.2
[RFC PATCH 0/3] mtd: nand: raw: atmel: Using dm driver for older sam9 SoCs
Hello raw NAND fans, today I thought it would be interesting to have all that automatic NAND flash timings setting usable with an old board featuring a at91sam9g20 SoC, which would pave the way to get rid of the old atmel raw nand driver eventually. My "let's try this quickly" ended up in "damn this took hours and now I'm stuck". Those older SoCs have no hardware ecc engine like the sama5d2 or sam9x60 have, which the Linux driver can work with. (The U-Boot driver was ported from Linux back then.) The problem is NAND flash detection fails because the atmel nand controller drivers fails on probing. In fact `atmel_nand_controller_init()` tries to set the pointer `nc->pmecc` by calling `devm_atmel_pmecc_get()`. That one probably gets a -EPROBE_DEFER returned by `atmel_pmecc_get_by_node()` and then `atmel_nand_controller_init()` returns -EPROBE_DEFER too and probing the driver fails. I suspect it should work fine if `nc->pmecc` would be NULL, but I have no idea what would be the right place to implement this. I also suspect that -EPROBE_DEFER contradicts the U-Boot driver model somehow? The raw/atmel/nand-controller driver was adapted (quite a bit) to work with U-Boot, but maybe some aspects of U-Boot driver model where not considered correctly? The attached patches are what I have so far, marked them as RFC because my actual goal of using the new dm based driver for the old SoC was not completed. Greets Alex P.S.: Patch stack based on next. Alexander Dahl (3): ARM: dts: at91sam9260: Add modern NAND controller nodes memory: atmel-ebi: Add compatible for older 9260 cores mtd: nand: raw: atmel: Remove redundant PMECC probe arch/arm/dts/at91sam9260.dtsi| 47 drivers/memory/atmel_ebi.c | 1 + drivers/mtd/nand/raw/atmel/nand-controller.c | 7 --- drivers/mtd/nand/raw/atmel/pmecc.c | 1 + 4 files changed, 49 insertions(+), 7 deletions(-) base-commit: beedf675b36841ce1e09157a87a6505317e6 -- 2.39.2
[RFC PATCH 3/3] mtd: nand: raw: atmel: Remove redundant PMECC probe
Always probing pmecc in the generic nand controller probe function and
bailing out if pmecc is missing, prevents the driver to be usable for
SoCs which do not have a pmecc hardware ecc engine like older sam9 SoCs,
for example at91sam9g20. Tested on sam9x60 that the call, which the
comment was moved to, is sufficient to probe the pmecc.
Signed-off-by: Alexander Dahl
---
drivers/mtd/nand/raw/atmel/nand-controller.c | 7 ---
drivers/mtd/nand/raw/atmel/pmecc.c | 1 +
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c
b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 0e0441472b8..b36f3a3ccac 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -2203,7 +2203,6 @@ static const struct udevice_id
atmel_nand_controller_of_ids[] = {
static int atmel_nand_controller_probe(struct udevice *dev)
{
const struct atmel_nand_controller_caps *caps;
- struct udevice *pmecc_dev;
caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev);
if (!caps) {
@@ -2211,12 +2210,6 @@ static int atmel_nand_controller_probe(struct udevice
*dev)
return -EINVAL;
}
- /* Probe pmecc driver */
- if (uclass_get_device(UCLASS_MTD, 1, _dev)) {
- printf("%s: get device fail\n", __func__);
- return -EINVAL;
- }
-
return caps->ops->probe(dev, caps);
}
diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c
b/drivers/mtd/nand/raw/atmel/pmecc.c
index 51f6bd2e65b..e500a0fe3f8 100644
--- a/drivers/mtd/nand/raw/atmel/pmecc.c
+++ b/drivers/mtd/nand/raw/atmel/pmecc.c
@@ -913,6 +913,7 @@ struct atmel_pmecc *devm_atmel_pmecc_get(struct udevice
*userdev)
ret = ofnode_parse_phandle_with_args(userdev->node_,
"ecc-engine",
NULL, 0, 0, );
+ /* Probe pmecc driver */
ret = uclass_get_device_by_ofnode(UCLASS_MTD, args.node, );
if (ret)
return NULL;
--
2.39.2
[RFC PATCH 2/3] memory: atmel-ebi: Add compatible for older 9260 cores
Required for using the new dm enabled nand controller driver on old
boards like the at91sam9g20-ek.
Signed-off-by: Alexander Dahl
---
drivers/memory/atmel_ebi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/memory/atmel_ebi.c b/drivers/memory/atmel_ebi.c
index 4739eef1b75..503e2ea707b 100644
--- a/drivers/memory/atmel_ebi.c
+++ b/drivers/memory/atmel_ebi.c
@@ -23,6 +23,7 @@ static int atmel_ebi_probe(struct udevice *dev)
}
static const struct udevice_id atmel_ebi_match[] = {
+ {.compatible = "atmel,at91sam9260-ebi"},
{.compatible = "microchip,sam9x60-ebi"},
{.compatible = "atmel,sama5d3-ebi"},
{ /* Sentinel */ }
--
2.39.2
Re: [PATCH v3] test/py: reset: Add a test for reset command
On Mon, Mar 11, 2024 at 04:14:04PM +0100, Michal Simek wrote: > > > On 3/11/24 16:09, Tom Rini wrote: > > On Mon, Mar 11, 2024 at 03:52:57PM +0100, Michal Simek wrote: > > > > > > > > > On 3/11/24 15:39, Tom Rini wrote: > > > > On Mon, Mar 11, 2024 at 02:40:59PM +0530, Love Kumar wrote: > > > > > Hi, > > > > > > > > > > On 11/03/24 2:11 pm, Angelo Dureghello wrote: > > > > > > Hi, > > > > > > > > > > > > jfyi, > > > > > > > > > > > > reset support added in qemu > > > > > > merged as commit d3c79c3974. > > > > > > > > > > > > Regards, > > > > > > angelo > > > > > > > > > > > The other issue was with echo commands: > > > > > => echo $modeboot > > > > > $modeboot > > > > > > > > > > => echo $? > > > > > $? > > > > > > > > > > Does HUSH shell is enabled by default for this? > > > > > > > > It is not, so at least the saveenv test needs to depend on HUSH_PARSER > > > > too. > > > > > > Based on logs on this platform echo $? doesn't return any value. > > > There is any config for it which is not enabled for this platform. > > > Do you know which Kconfig symbol it is? > > > > > > Depending on HUSH is likely big hammer but I was not able to find that > > > exact > > > Kconfig symbol just for $? > > > > Well, if we don't have the hush parser we have a much more limited > > parser enabled and I bet that's why (I think there's no variable > > expansion). > > ok. Then this test should be limited to HUSH too based on how it is written. > I think it should be okish limitation and if someone wants to test it on > systems without HUSH enabled it should just update it. If is fine for you? Yup, sounds good. And I'll take the next iteration of this test patch when I also grab the patch I posted to cherry-pick the missing reset functionality in our QEMU. -- Tom signature.asc Description: PGP signature
Re: [PATCH v3] test/py: reset: Add a test for reset command
On 3/11/24 16:09, Tom Rini wrote: On Mon, Mar 11, 2024 at 03:52:57PM +0100, Michal Simek wrote: On 3/11/24 15:39, Tom Rini wrote: On Mon, Mar 11, 2024 at 02:40:59PM +0530, Love Kumar wrote: Hi, On 11/03/24 2:11 pm, Angelo Dureghello wrote: Hi, jfyi, reset support added in qemu merged as commit d3c79c3974. Regards, angelo The other issue was with echo commands: => echo $modeboot $modeboot => echo $? $? Does HUSH shell is enabled by default for this? It is not, so at least the saveenv test needs to depend on HUSH_PARSER too. Based on logs on this platform echo $? doesn't return any value. There is any config for it which is not enabled for this platform. Do you know which Kconfig symbol it is? Depending on HUSH is likely big hammer but I was not able to find that exact Kconfig symbol just for $? Well, if we don't have the hush parser we have a much more limited parser enabled and I bet that's why (I think there's no variable expansion). ok. Then this test should be limited to HUSH too based on how it is written. I think it should be okish limitation and if someone wants to test it on systems without HUSH enabled it should just update it. If is fine for you? Thanks, Michal
Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board
On 06/03/2024 21:24, Volodymyr Babchuk wrote:
>
> Hi Caleb,
>
> Caleb Connolly writes:
>
> [...]
> +};
> +
> + {
> + /* U-Boot pinctrl driver does not understand multiple tiles */
> + reg = <0x0 0x0300 0x0 0x100>;
> + /delete-property/ reg-names;
This won't be needed if we can make the tiles offset in the pinctrl
driver compatible:
#define WEST 0x
#define EAST 0x0040
#define NORTH 0x0080
#define SOUTH 0x00C0
>>>
>>> Hmm, I assume that in this case pinctrl driver should map all the four
>>> tiles independently? Are there guarantees in U-Boot that four separate
>>> memory regions will be mapped into virtual memory with the same relative
>>> positions? Linux clearly don't make such guarantees.
>>
>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>> far as reading the address from DT, nothing else, so this is totally
>> fine and is how the other SoCs do it.
>
> For me it looks like we are depending on implementation details
> knowledge. I.e MMU API does not provide such guarantees, but drivers
> know how ARM MMU code is working internally and drivers depend on
> exactly this behavior. But if you are saying that it is totally fine,
> I'll rework the patch. No big deal. Actually, I already tried this and
> it is working fine.
>
> +
> + /* U-Boot ethernet driver wants to drive reset as GPIO */
> + /delete-node/ phy-reset-pins;
I suppose this is not needed as phy-reset-pins also configures the pin
as GPIO only.
>>> Well, yes. This also puzzles me up, but for some reason it stops working
>>> if I leave this node intact. Looks like I need to look at this deeper
>>> before posting the next version.
>>
>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>> misbehave, can you check if this patch fixes it (there is a bug in the
>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>> just "msm_gpio_direction_input(dev, gpio);").
>>
>> I had the exact same issue with the gpio-regulator driver and this was
>> the solution I ended up going with.
>>
>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787...@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>> [lore[.]kernel[.]org]
>
> It is exactly this. With your patch I don't need to /delete-node/
> anymore. I'll add a comment in the cover message that this series are
> depended on your patch.
Please can you split the power domain and clock patches into a separate
series? As I'd like to depend on them for the next revision of my
series, and we'd otherwise have a cyclical dependency.
>
> (and sorry for the mangled link. It is our corporate mail server doing)
>
>
>>>
> +};
> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS
> b/board/qualcomm/sa8155p-adp/MAINTAINERS
> new file mode 100644
> index 00..03fac84f51
> --- /dev/null
> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
> @@ -0,0 +1,5 @@
> +Qualcomm SA8155P Automotive Development Platform
> +M: Volodymyr Babchuk
> +S: Maintained
> +F: board/qualcomm/sa8155p-adp/
> +F: configs/sa8155p-adp_defconfig
> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
> new file mode 100644
> index 00..b6969767f8
> --- /dev/null
> +++ b/configs/sa8155p_adp_defconfig
> @@ -0,0 +1,35 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=1900
> +CONFIG_POSITION_INDEPENDENT=y
> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> +CONFIG_ARCH_SNAPDRAGON=y
> +CONFIG_TEXT_BASE=0x8571
Being position independent shouldn't require a hardcoded U-Boot text
base. Can you try if we can get rid of this?
>>>
>>> Well, it is required if we want to load U-Boot instead of hyp.mbn. We
>>> need correct addresses in the ELF file so Qualcomm loader will not
>>> reject it right away.
>>>
> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
> +CONFIG_SYS_LOAD_ADDR=0x8571
Ditto.
> +CONFIG_REMAKE_ELF=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_SYS_CBSIZE=512
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_HUSH_PARSER=y
> +CONFIG_OF_UPSTREAM=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CLK=y
> +CONFIG_CLK_QCOM_SM8150=y
> +CONFIG_MSM_GPIO=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_DM_MDIO=y
> +CONFIG_DM_ETH_PHY=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_QCOM=y
> +CONFIG_PHY=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCONF=y
> +CONFIG_PINCTRL_QCOM_SM8150=y
> +CONFIG_POWER_DOMAIN=y
>
Re: [PATCH v3] test/py: reset: Add a test for reset command
On Mon, Mar 11, 2024 at 03:52:57PM +0100, Michal Simek wrote: > > > On 3/11/24 15:39, Tom Rini wrote: > > On Mon, Mar 11, 2024 at 02:40:59PM +0530, Love Kumar wrote: > > > Hi, > > > > > > On 11/03/24 2:11 pm, Angelo Dureghello wrote: > > > > Hi, > > > > > > > > jfyi, > > > > > > > > reset support added in qemu > > > > merged as commit d3c79c3974. > > > > > > > > Regards, > > > > angelo > > > > > > > The other issue was with echo commands: > > > => echo $modeboot > > > $modeboot > > > > > > => echo $? > > > $? > > > > > > Does HUSH shell is enabled by default for this? > > > > It is not, so at least the saveenv test needs to depend on HUSH_PARSER > > too. > > Based on logs on this platform echo $? doesn't return any value. > There is any config for it which is not enabled for this platform. > Do you know which Kconfig symbol it is? > > Depending on HUSH is likely big hammer but I was not able to find that exact > Kconfig symbol just for $? Well, if we don't have the hush parser we have a much more limited parser enabled and I bet that's why (I think there's no variable expansion). -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] Please pull u-boot-imx-master-20240311
On Mon, Mar 11, 2024 at 10:05:24AM -0300, Fabio Estevam wrote: > Hi Tom, > > Please pull from u-boot-imx, thanks. > > The following changes since commit 0981f8900f2b1f45a3f282b704012b5374fdd7a6: > > Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2024-03-09 > 11:29:48 -0500) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git > tags/u-boot-imx-master-20240311 > > for you to fetch changes up to 4484c7b3c38dcb21244a882d0b81d141db1ed162: > > arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8 (2024-03-11 08:43:42 > -0300) > > u-boot-imx-master-20240311 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3] test/py: reset: Add a test for reset command
On 3/11/24 15:39, Tom Rini wrote: On Mon, Mar 11, 2024 at 02:40:59PM +0530, Love Kumar wrote: Hi, On 11/03/24 2:11 pm, Angelo Dureghello wrote: Hi, jfyi, reset support added in qemu merged as commit d3c79c3974. Regards, angelo The other issue was with echo commands: => echo $modeboot $modeboot => echo $? $? Does HUSH shell is enabled by default for this? It is not, so at least the saveenv test needs to depend on HUSH_PARSER too. Based on logs on this platform echo $? doesn't return any value. There is any config for it which is not enabled for this platform. Do you know which Kconfig symbol it is? Depending on HUSH is likely big hammer but I was not able to find that exact Kconfig symbol just for $? thanks, Michal
Re: [PATCH v2 2/5] apq8016: Add support for UART1 clocks and pinmux
On 11/03/2024 13:32, Stephan Gerhold wrote:
> On Mon, Mar 11, 2024 at 12:27:11PM +, Caleb Connolly wrote:
>> On 11/03/2024 11:10, Sumit Garg wrote:
>>> SE HMIBSC board uses UART1 as the main debug console, so add
>>> corresponding clocks and pinmux support. Along with that update
>>> instructions to enable clocks for debug UART support.
>>>
>>> Signed-off-by: Sumit Garg
>>> ---
>>> drivers/clk/qcom/clock-apq8016.c | 50 +-
>>> drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
>>> drivers/serial/serial_msm.c| 6 ++--
>>> 3 files changed, 47 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/clk/qcom/clock-apq8016.c
>>> b/drivers/clk/qcom/clock-apq8016.c
>>> index e6647f7c41d..a620a10a520 100644
>>> --- a/drivers/clk/qcom/clock-apq8016.c
>>> +++ b/drivers/clk/qcom/clock-apq8016.c
>>> @@ -43,6 +43,14 @@
>>> #define BLSP1_UART2_APPS_N (0x3040)
>>> #define BLSP1_UART2_APPS_D (0x3044)
>>>
>>> +#define BLSP1_UART1_BCR(0x2038)
>>> +#define BLSP1_UART1_APPS_CBCR (0x203C)
>>> +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044)
>>> +#define BLSP1_UART1_APPS_CFG_RCGR (0x2048)
>>> +#define BLSP1_UART1_APPS_M (0x204C)
>>> +#define BLSP1_UART1_APPS_N (0x2050)
>>> +#define BLSP1_UART1_APPS_D (0x2054)
>>> +
>>> /* GPLL0 clock control registers */
>>> #define GPLL0_STATUS_ACTIVE BIT(17)
>>>
>>> [...]
>>> @@ -94,6 +102,33 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int
>>> slot, uint rate)
>>> return rate;
>>> }
>>>
>>> +static const struct bcr_regs uart1_regs = {
>>> + .cfg_rcgr = BLSP1_UART1_APPS_CFG_RCGR,
>>> + .cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR,
>>> + .M = BLSP1_UART1_APPS_M,
>>> + .N = BLSP1_UART1_APPS_N,
>>> + .D = BLSP1_UART1_APPS_D,
>>> +};
>>> +
>>> +/* UART: 115200 */
>>> +static int apq8016_clk_init_uart1(phys_addr_t base)
>>
>> I know we're still dealing with some tech debt here, but I'm not a big
>> fan of this approach. I notice that the RCG and CBCR registers are all
>> offset by exactly 0xff0 between UART1 and UART2, what about adding a
>> second "index" parameter to apq8016_clk_init_uart() and then offsetting
>> the addresses by (0xff0 * index)?
>>
>
> This would work for MSM8916 where you have just two UARTs, but it might
> be misleading since the UART blocks are actually separated in 4 KiB
> (0x1000) blocks and not offset by 0xff0. UART2 is a special case that
> has different offsets within the 4 KiB block, for some weird reason.
>
> If you want to calculate the register offsets properly you would need
> special handling for UART2, e.g. I have the following (admittedly rather
> ugly) define in the TF-A port for MSM8916 and similar [1]:
>
> #define GCC_BLSP1_UART_APPS_CBCR(n) (GCC_BASE + \
> (((n) == 2) ? (0x0302c) : (0x0203c + (((n) - 1) * 0x1000
>
> where n is the UART number (here 1 or 2). As a different example,
> MDM9607 has 5 UARTs (1 to 5) and there only UART2 is special-cased,
> while all others follow the standard offset with 0x1000 offset.
fwiw I would also be fine with just treating it like a binary switch and
only allowing UART1 or UART2 to be selected if that's simpler.
>
> Thanks,
> Stephan
>
> [1]:
> https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/qti/msm8916/msm8916_setup.c?h=v2.10#n40
--
// Caleb (they/them)
[PATCH 2/2] lmb: Fix adjacent region merge in lmb_add_region_flags()
In case a new region is adjacent to a previous region with
similar flag, this region is merged with its predecessor, but no
check are done if this new added region is overlapping another region
present in lmb (see reserved[3] which overlaps reserved[4]).
This occurs when the LMB [0xdaafd000-0xddb18000] is added and overlaps
the LMB [0xdbaf4380-0xddff].
Call lmb_overlaps_region() before merging the new region with the
adjacent region already present in lmb.
In case of adjacent region found, code is 90% similar in case
adjacent region is located before/after the new region.
Factorize adjacent region management in lmb_add_region_flags().
Issue reproduced on STM32MP157-DK2 with SCMI DT, bdinfo command's output
shows:
before this patch:
...
lmb_dump_all:
memory.cnt = 0x1 / max = 0x2
memory[0] [0xc000-0xdfff], 0x2000 bytes flags: 0
reserved.cnt = 0x5 / max = 0x10
reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4
reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4
reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4
reserved[3][0xdaadf000-0xdfff], 0x05521000 bytes flags: 0
reserved[4][0xde00-0xdfff], 0x0200 bytes flags: 4
...
after this patch:
...
lmb_dump_all:
memory.cnt = 0x1 / max = 0x2
memory[0] [0xc000-0xdfff], 0x2000 bytes flags: 0
reserved.cnt = 0x6 / max = 0x10
reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4
reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4
reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4
reserved[3][0xdaadf000-0xdaaf7fff], 0x00019000 bytes flags: 0
reserved[4][0xdbaf4380-0xddff], 0x0250bc80 bytes flags: 0
reserved[5][0xde00-0xdfff], 0x0200 bytes flags: 4
...
Fixes: 4ed6552f7159 ("[new uImage] Introduce lmb from linux kernel for memory
mgmt of boot images")
Signed-off-by: Patrice Chotard
---
lib/lmb.c | 55 ---
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/lib/lmb.c b/lib/lmb.c
index b6afb731440..f583b10f776 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -130,6 +130,22 @@ static void lmb_fix_over_lap_regions(struct lmb_region
*rgn, unsigned long r1,
lmb_remove_region(rgn, r2);
}
+static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
+ phys_size_t size)
+{
+ unsigned long i;
+
+ for (i = 0; i < rgn->cnt; i++) {
+ phys_addr_t rgnbase = rgn->region[i].base;
+ phys_size_t rgnsize = rgn->region[i].size;
+
+ if (lmb_addrs_overlap(base, size, rgnbase, rgnsize))
+ break;
+ }
+
+ return (i < rgn->cnt) ? i : -1;
+}
+
void lmb_init(struct lmb *lmb)
{
#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
@@ -257,7 +273,7 @@ static long lmb_add_region_flags(struct lmb_region *rgn,
phys_addr_t base,
phys_size_t size, enum lmb_flags flags)
{
unsigned long coalesced = 0;
- long adjacent, i;
+ long adjacent, i, overlap;
if (rgn->cnt == 0) {
rgn->region[0].base = base;
@@ -283,19 +299,19 @@ static long lmb_add_region_flags(struct lmb_region *rgn,
phys_addr_t base,
}
adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
- if (adjacent > 0) {
- if (flags != rgnflags)
- continue;
- rgn->region[i].base -= size;
- rgn->region[i].size += size;
- coalesced++;
- break;
- } else if (adjacent < 0) {
+ if (adjacent != 0) {
if (flags != rgnflags)
continue;
- rgn->region[i].size += size;
- coalesced++;
- break;
+ overlap = lmb_overlaps_region(rgn, base, size);
+ if (overlap < 0) {
+ /* no overlap detected, extend region */
+ if (adjacent > 0)
+ rgn->region[i].base -= size;
+ rgn->region[i].size += size;
+ coalesced++;
+ break;
+ }
+ continue;
} else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
/* regions overlap */
return -1;
@@ -420,21 +436,6 @@ long lmb_reserve(struct lmb *lmb, phys_addr_t base,
phys_size_t size)
return lmb_reserve_flags(lmb, base, size, LMB_NONE);
}
-static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
- phys_size_t size)
-{
- unsigned long i;
-
-
[PATCH 1/2] lmb: Avoid to add identical region in lmb_add_region_flags()
In case lmb_add_region_flags() is called with the same parameter than
an already existing lmb and this lmb is adjacent to its previous lmb with
different flag, this lmb is added again.
Instead breaking the loop, continue, at the next iteration, we are able
to detect that this region already exist.
Issue reproduced on STM32MP157-DK2 with SCMI DT, bdinfo command's output
shows:
Before this patch, the last LMB [0xde00-0xdfff] is duplicated:
...
lmb_dump_all:nnn
memory.cnt = 0x1 / max = 0x2
memory[0] [0xc000-0xdfff], 0x2000 bytes flags: 0
reserved.cnt = 0x6 / max = 0x10
reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4
reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4
reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4
reserved[3][0xdaadf000-0xdfff], 0x05521000 bytes flags: 0
reserved[4][0xde00-0xdfff], 0x0200 bytes flags: 4
reserved[5][0xde00-0xdfff], 0x0200 bytes flags: 4
...
After this patch:
...
lmb_dump_all:
memory.cnt = 0x1 / max = 0x2
memory[0] [0xc000-0xdfff], 0x2000 bytes flags: 0
reserved.cnt = 0x5 / max = 0x10
reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4
reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4
reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4
reserved[3][0xdaadf000-0xdfff], 0x05521000 bytes flags: 0
reserved[4][0xde00-0xdfff], 0x0200 bytes flags: 4
...
Fixes: 59c0ea5df33f ("lmb: Add support of flags for no-map properties")
Signed-off-by: Patrice Chotard
---
lib/lmb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/lmb.c b/lib/lmb.c
index 44f98205310..b6afb731440 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -285,14 +285,14 @@ static long lmb_add_region_flags(struct lmb_region *rgn,
phys_addr_t base,
adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
if (adjacent > 0) {
if (flags != rgnflags)
- break;
+ continue;
rgn->region[i].base -= size;
rgn->region[i].size += size;
coalesced++;
break;
} else if (adjacent < 0) {
if (flags != rgnflags)
- break;
+ continue;
rgn->region[i].size += size;
coalesced++;
break;
--
2.25.1
Re: [PATCH v3] test/py: reset: Add a test for reset command
On Mon, Mar 11, 2024 at 02:40:59PM +0530, Love Kumar wrote: > Hi, > > On 11/03/24 2:11 pm, Angelo Dureghello wrote: > > Hi, > > > > jfyi, > > > > reset support added in qemu > > merged as commit d3c79c3974. > > > > Regards, > > angelo > > > The other issue was with echo commands: > => echo $modeboot > $modeboot > > => echo $? > $? > > Does HUSH shell is enabled by default for this? It is not, so at least the saveenv test needs to depend on HUSH_PARSER too. -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 5/5] board: add support for Schneider HMIBSC board
On Mon, Mar 11, 2024 at 04:40:26PM +0530, Sumit Garg wrote:
> Support for Schneider Electric HMIBSC. Features:
> - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> - 2GiB RAM
> - 64GiB eMMC, SD slot
> - WiFi and Bluetooth
> - 2x Host, 1x Device USB port
> - HDMI
> - Discrete TPM2 chip over SPI
>
> Features enabled in U-Boot:
> - RAUC updates
> - Environment protection
> - USB based ethernet adaptors
>
> Signed-off-by: Sumit Garg
I'm entirely sure which requirements or conventions we are following for
adding device trees directly to U-Boot instead of Linux. My understanding
is that the goal is to get U-Boot DTs as close as possible to the
upstream Linux DTs, so I effectively looked at this as if it were
submitted to linux-arm-msm. I think most of my comments should be
trivial to fix anyway without much effort. :-)
With the comments fixed it would be likely also easy to get it in
upstream in Linux, so I wonder if it's worth first adding it here in
U-Boot (I know you discussed this on v1 already a bit).
> ---
> arch/arm/dts/apq8016-hmibsc.dts| 496 +
> board/schneider/hmibsc/MAINTAINERS | 6 +
> configs/hmibsc_defconfig | 87 +
> doc/board/index.rst| 1 +
> doc/board/schneider/hmibsc.rst | 45 +++
> doc/board/schneider/index.rst | 9 +
> include/configs/hmibsc.h | 57
> 7 files changed, 701 insertions(+)
> create mode 100644 arch/arm/dts/apq8016-hmibsc.dts
> create mode 100644 board/schneider/hmibsc/MAINTAINERS
> create mode 100644 configs/hmibsc_defconfig
> create mode 100644 doc/board/schneider/hmibsc.rst
> create mode 100644 doc/board/schneider/index.rst
> create mode 100644 include/configs/hmibsc.h
>
> diff --git a/arch/arm/dts/apq8016-hmibsc.dts b/arch/arm/dts/apq8016-hmibsc.dts
> new file mode 100644
> index 000..490ab5fd2fa
> --- /dev/null
> +++ b/arch/arm/dts/apq8016-hmibsc.dts
> @@ -0,0 +1,496 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024, Linaro Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "msm8916-pm8916.dtsi"
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + model = "Schneider Electric HMIBSC Board";
> + compatible = "qcom,apq8016-hmibsc", "qcom,apq8016";
A Schneider Electric specific compatible would be likely more accurate,
since I assume this board wasn't designed by Qualcomm?
I would personally also prefer to use the "apq8016--.dts"
naming convention that we typically use for smartphones/tablets
upstream, although you can also keep it as-is since e.g. apq8039-t2.dts
is also named without vendor.
> +
> + aliases {
> + serial0 = _uart1;
> + serial1 = _uart2;
> + usid0 = _0;
> + i2c1 = _i2c6;
> + i2c3 = _i2c4;
> + i2c4 = _i2c3;
> + spi0 = _spi5;
You might want to add mmcX aliases here to ensure consistent naming of
eMMC and SD card (this used to be in msm8916.dtsi but not anymore).
> [...]
> +_i2c6 {
> + status = "okay";
> + label = "I2C1";
> +
> + rtc1: s35390a@30 {
rtc@
> + compatible = "sii,s35390a";
> + reg = <0x30>;
> + };
> +
> + eeprom1: 24c256@50 {
eeprom@
> + compatible = "atmel,24c256";
> + reg = <0x50>;
> + };
> +};
> +
> +_i2c3 {
i2c3 should come before i2c6 (sorted alphabetically)
> + status = "okay";
> + label = "I2C4";
> +
> + eeprom: 24c32@50 {
eeprom@
> + compatible = "onsemi,24c32";
> + reg = <0x50>;
> + };
> +};
> +
> [...]
> +
> +_0 {
> + pon@800 {
> + pwrkey {
> + status = "okay";
> + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
This line would really benefit from a comment that explains what exactly
it does and why this is done. :)
It looks like you are redefining the pwrkey with the resin interrupt.
I guess your goal is to have KEY_POWER assigned to the resin pin?
In that case, I think it would be cleaner to describe this using:
_resin {
status = "okay";
linux,code = ;
};
and leave the pwrkey node alone (or perhaps disable it if it causes
trouble).
Aside from the confusion, I think overriding only the interrupt of the
pwrkey will also misbehave in unexpected ways since e.g. the Linux
pm8941-pwrkey driver will still write the configured debounce time and
pull up to the pwrkey registers, and not to the resin ones.
> + };
> + };
> +};
> +
> [...]
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_rs232_high _rs232_low>;
> +
> + sdc2_cd_default: sdc2-cd-default-state {
> + pins = "gpio38";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + usb_id_default: usb-id-default-state {
> +
Re: [PATCH 3/5] configs: phycore-imx8mp_defconfig: Use redundant environment
Hi Fabio, Am Montag, dem 11.03.2024 um 11:05 -0300 schrieb Fabio Estevam: > Hi Leonard, > > On Mon, Mar 11, 2024 at 10:04 AM Leonard Anderweit > wrote: > > > > Add support for the redundant environment. > > > > Signed-off-by: Leonard Anderweit > > Please rebase this series against U-Boot next branch and resend. This series is based on the latest master branch. > > There is an error while applying this patch against next. I also got an error while applying this to next. To apply cleanly this series requires the commit 19f657600781 (configs: Resync with savedefconfig) which is on master but not on next. If this missing commit is intended I'll resend this series based on next. Regards, Leonard > > Thanks
Re: [PATCH 3/5] configs: phycore-imx8mp_defconfig: Use redundant environment
Hi Leonard, On Mon, Mar 11, 2024 at 10:04 AM Leonard Anderweit wrote: > > Add support for the redundant environment. > > Signed-off-by: Leonard Anderweit Please rebase this series against U-Boot next branch and resend. There is an error while applying this patch against next. Thanks
[PATCH] CI: Cherry-pick reset support for m68k for QEMU
In order to support the reset pytest on QEMU on m68k platforms we need to grab this change from upstream. Signed-off-by: Tom Rini --- tools/docker/Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 274255456619..136bc01f0937 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -184,6 +184,7 @@ RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \ git config user.email u-b...@denx.de && \ git format-patch 0c7ffc977195~..0c7ffc977195 && \ git am 0001-hw-net-cadence_gem-Fix-MDIO_OP_xxx-values.patch && \ + git cherry-pick d3c79c3974 && \ ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ make -j$(nproc) all install && \ rm -rf /tmp/qemu -- 2.34.1
Re: [PATCH v2 2/5] apq8016: Add support for UART1 clocks and pinmux
On Mon, Mar 11, 2024 at 12:27:11PM +, Caleb Connolly wrote:
> On 11/03/2024 11:10, Sumit Garg wrote:
> > SE HMIBSC board uses UART1 as the main debug console, so add
> > corresponding clocks and pinmux support. Along with that update
> > instructions to enable clocks for debug UART support.
> >
> > Signed-off-by: Sumit Garg
> > ---
> > drivers/clk/qcom/clock-apq8016.c | 50 +-
> > drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
> > drivers/serial/serial_msm.c| 6 ++--
> > 3 files changed, 47 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/clock-apq8016.c
> > b/drivers/clk/qcom/clock-apq8016.c
> > index e6647f7c41d..a620a10a520 100644
> > --- a/drivers/clk/qcom/clock-apq8016.c
> > +++ b/drivers/clk/qcom/clock-apq8016.c
> > @@ -43,6 +43,14 @@
> > #define BLSP1_UART2_APPS_N (0x3040)
> > #define BLSP1_UART2_APPS_D (0x3044)
> >
> > +#define BLSP1_UART1_BCR(0x2038)
> > +#define BLSP1_UART1_APPS_CBCR (0x203C)
> > +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044)
> > +#define BLSP1_UART1_APPS_CFG_RCGR (0x2048)
> > +#define BLSP1_UART1_APPS_M (0x204C)
> > +#define BLSP1_UART1_APPS_N (0x2050)
> > +#define BLSP1_UART1_APPS_D (0x2054)
> > +
> > /* GPLL0 clock control registers */
> > #define GPLL0_STATUS_ACTIVE BIT(17)
> >
> > [...]
> > @@ -94,6 +102,33 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int
> > slot, uint rate)
> > return rate;
> > }
> >
> > +static const struct bcr_regs uart1_regs = {
> > + .cfg_rcgr = BLSP1_UART1_APPS_CFG_RCGR,
> > + .cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR,
> > + .M = BLSP1_UART1_APPS_M,
> > + .N = BLSP1_UART1_APPS_N,
> > + .D = BLSP1_UART1_APPS_D,
> > +};
> > +
> > +/* UART: 115200 */
> > +static int apq8016_clk_init_uart1(phys_addr_t base)
>
> I know we're still dealing with some tech debt here, but I'm not a big
> fan of this approach. I notice that the RCG and CBCR registers are all
> offset by exactly 0xff0 between UART1 and UART2, what about adding a
> second "index" parameter to apq8016_clk_init_uart() and then offsetting
> the addresses by (0xff0 * index)?
>
This would work for MSM8916 where you have just two UARTs, but it might
be misleading since the UART blocks are actually separated in 4 KiB
(0x1000) blocks and not offset by 0xff0. UART2 is a special case that
has different offsets within the 4 KiB block, for some weird reason.
If you want to calculate the register offsets properly you would need
special handling for UART2, e.g. I have the following (admittedly rather
ugly) define in the TF-A port for MSM8916 and similar [1]:
#define GCC_BLSP1_UART_APPS_CBCR(n) (GCC_BASE + \
(((n) == 2) ? (0x0302c) : (0x0203c + (((n) - 1) * 0x1000
where n is the UART number (here 1 or 2). As a different example,
MDM9607 has 5 UARTs (1 to 5) and there only UART2 is special-cased,
while all others follow the standard offset with 0x1000 offset.
Thanks,
Stephan
[1]:
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/qti/msm8916/msm8916_setup.c?h=v2.10#n40
Re: [PATCH] arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8
On Sun, Mar 10, 2024 at 1:59 PM Adam Ford wrote: > > The device tree has evolved over time, so re-sync. This also > partial reverts one change on the PCIe, because U-Boot doesn't > have a proper driver. However, since the clock is configured > to generate a 100MHz reference clock by default, a proper driver > isn't really necessary. > > Signed-off-by: Adam Ford Applied, thanks.
Re: [PATCH] toradex: tdx-cfg-block: add 0087 i.mx8m mini product variant
On Fri, Mar 8, 2024 at 11:18 AM Joao Paulo Goncalves wrote: > > From: Joao Paulo Goncalves > > Add new product id 0087 Verdin iMX8M Mini Quad 2GB IT. > > Signed-off-by: Joao Paulo Goncalves Applied, thanks.
Re: [PATCH] configs: imx8mp_beacon: Fall back to using TF-A
On Thu, Mar 7, 2024 at 8:59 AM Adam Ford wrote:
>
> When the board was originally added, it enabled some features which
> allowed it to bypass Trusted Firmware, but as the feature set of
> Linux grew and more features became available, the U-Boot config
> options which bypassed TF-A caused issues, so it needs to return
> to the standard operating mode of using TF-A or the system no
> longer boots.
>
> Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit")
> Signed-off-by: Adam Ford
Applied, thanks.
Re: [PATCH v3 0/2] board: phytec_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1
On Wed, Mar 6, 2024 at 1:18 PM Benjamin Hahn wrote: > > PCL-070 supports 2GHz RAM-timings from pcb_rev 1 and newer. PCM-070 > supports 2GHz RAM-timings only from pcb_rev 3 and newer. > > Signed-off-by: Benjamin Hahn Applied all, thanks.
[PATCH 4/5] include: env: Add phytec RAUC boot logic
Add logic for booting systems with the RAUC update mechanism. This can
be reused by other phytec boards.
Signed-off-by: Leonard Anderweit
---
include/env/phytec/rauc.env | 52 +
1 file changed, 52 insertions(+)
create mode 100644 include/env/phytec/rauc.env
diff --git a/include/env/phytec/rauc.env b/include/env/phytec/rauc.env
new file mode 100644
index ..89e17ff70ec6
--- /dev/null
+++ b/include/env/phytec/rauc.env
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* Logic to select a boot partition based on environment variables and switch
+ * to the other if the boot fails. */
+
+doraucboot=0
+
+raucbootpart0=1
+raucrootpart0=5
+raucbootpart1=2
+raucrootpart1=6
+
+raucinit=
+ echo Booting RAUC A/B system;
+ test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1";
+ test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3;
+ test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3;
+ env set raucstatus;
+ for BOOT_SLOT in "${BOOT_ORDER}"; do
+ if test "x${raucstatus}" != "x"; then
+ echo Skipping remaing slots!;
+ elif test "x${BOOT_SLOT}" = "xsystem0"; then
+ if test ${BOOT_system0_LEFT} -gt 0; then
+ echo Found valid slot A, ${BOOT_system0_LEFT}
attempts remaining;
+ setexpr BOOT_system0_LEFT ${BOOT_system0_LEFT}
- 1;
+ env set mmcpart ${raucbootpart0};
+ env set mmcroot ${raucrootpart0};
+ env set raucargs rauc.slot=system0;
+ env set raucstatus success;
+ fi;
+ elif test "x${BOOT_SLOT}" = "xsystem1"; then
+ if test ${BOOT_system1_LEFT} -gt 0; then
+ echo Found valid slot B, ${BOOT_system1_LEFT}
attempts remaining;
+ setexpr BOOT_system1_LEFT ${BOOT_system1_LEFT}
- 1;
+ env set mmcpart ${raucbootpart1};
+ env set mmcroot ${raucrootpart1};
+ env set raucargs rauc.slot=system1;
+ env set raucstatus success;
+ fi;
+ fi;
+ done;
+ if test -n "${raucstatus}"; then
+ env delete raucstatus;
+ env save;
+ else
+ echo WARN: No valid slot found;
+ env set BOOT_system0_LEFT 3;
+ env set BOOT_system1_LEFT 3;
+ env delete raucstatus;
+ env save;
+ reset;
+ fi;
--
2.25.1
[PATCH 5/5] board: phytec: phycore_imx8mp: Add RAUC boot logic to environment
Add RAUC boot logic to the environment. This is the first board to
utilize this environment.
Signed-off-by: Leonard Anderweit
---
board/phytec/phycore_imx8mp/phycore_imx8mp.env | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
index 73202c3b129a..d58d25476f6b 100644
--- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -1,9 +1,14 @@
+#include
+
bootcmd=
if test ${dofastboot} = 1; then
fastboot 0;
fi;
mmc dev ${mmcdev};
if mmc rescan; then
+ if test ${doraucboot} = 1; then
+ run raucinit;
+ fi;
if run loadimage; then
run mmcboot;
else
@@ -23,7 +28,7 @@ loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
${image}
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
mmcargs=
setenv bootargs console=${console}
- root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw
+ root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
mmcautodetect=yes
mmcboot=
echo Booting from mmc ...;
--
2.25.1
[PATCH 3/5] configs: phycore-imx8mp_defconfig: Use redundant environment
Add support for the redundant environment. Signed-off-by: Leonard Anderweit --- configs/phycore-imx8mp_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index fd492eba3c10..6c67f14b5559 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x96 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3e CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 CONFIG_SYS_LOAD_ADDR=0x4048 CONFIG_FIT=y @@ -77,6 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -- 2.25.1
[PATCH 2/5] phycore_imx8mp: Move default bootcmd to board env
Move the default bootcmd from the defconfig to the board environment.
No change in functionality.
Signed-off-by: Leonard Anderweit
---
board/phytec/phycore_imx8mp/phycore_imx8mp.env | 12
configs/phycore-imx8mp_defconfig | 2 --
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
index 6d15b7f3dc9f..73202c3b129a 100644
--- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -1,3 +1,15 @@
+bootcmd=
+ if test ${dofastboot} = 1; then
+ fastboot 0;
+ fi;
+ mmc dev ${mmcdev};
+ if mmc rescan; then
+ if run loadimage; then
+ run mmcboot;
+ else
+ run netboot;
+ fi;
+ fi;
console=ttymxc0,115200
dofastboot=0
emmc_dev=2
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index b3a7bbd79bb6..fd492eba3c10 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -25,8 +25,6 @@ CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev
${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run
netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
--
2.25.1
[PATCH 1/5] phycore_imx8mp: Move environment from include/config to board
Move the environment into the board directory and convert it from a C
header to a text file. Sort the variables alphabetically.
No functional changes.
Signed-off-by: Leonard Anderweit
---
.../phytec/phycore_imx8mp/phycore_imx8mp.env | 45 +++
include/configs/phycore_imx8mp.h | 43 --
2 files changed, 45 insertions(+), 43 deletions(-)
create mode 100644 board/phytec/phycore_imx8mp/phycore_imx8mp.env
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
new file mode 100644
index ..6d15b7f3dc9f
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -0,0 +1,45 @@
+console=ttymxc0,115200
+dofastboot=0
+emmc_dev=2
+fastboot_raw_partition_all=0 4194304
+fastboot_raw_partition_bootloader=64 8128
+fdt_addr=0x4800
+fdt_file=CONFIG_DEFAULT_FDT_FILE
+image=Image
+ip_dyn=yes
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+mmcargs=
+ setenv bootargs console=${console}
+ root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw
+mmcautodetect=yes
+mmcboot=
+ echo Booting from mmc ...;
+ run mmcargs;
+ if run loadfdt; then
+ booti ${loadaddr} - ${fdt_addr};
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+mmcdev=CONFIG_SYS_MMC_ENV_DEV
+mmcpart=1
+mmcroot=2
+netargs=
+ setenv bootargs console=${console} root=/dev/nfs ip=dhcp
+ nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+ echo Booting from net ...;
+ run netargs;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ ${get_cmd} ${loadaddr} ${image};
+ if ${get_cmd} ${fdt_addr} ${fdt_file}; then
+ booti ${loadaddr} - ${fdt_addr};
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+nfsroot=/nfs
+sd_dev=1
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 11a17be7fe1d..206c4d50d276 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -13,49 +13,6 @@
#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
512)
-#define CFG_EXTRA_ENV_SETTINGS \
- "image=Image\0" \
- "console=ttymxc0,115200\0" \
- "fdt_addr=0x4800\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "ip_dyn=yes\0" \
- "dofastboot=0\0" \
- "fastboot_raw_partition_bootloader=64 8128\0" \
- "fastboot_raw_partition_all=0 4194304\0" \
- "emmc_dev=2\0" \
- "sd_dev=1\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=2\0" \
- "mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if run loadfdt; then " \
- "booti ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi;\0 " \
- "nfsroot=/nfs\0" \
- "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
- "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${loadaddr} ${image}; " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "booti ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi;\0" \
-
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x4000
--
2.25.1
[PATCH 0/5] Add RAUC boot logic for phycore_imx8mp
This series adds RAUC boot logic for the phycore_imx8mp. The first patch converts the environment from a CFG_EXTRA_ENV_SETTINGS #define to a text environment for better readability and maintainability. The second patch moves the default bootcmd from the defconfig to the board environment. The third patch enables the redundant environment on phycore_imx8mp. Patch 4 adds RAUC boot logic common to all phytec boards. Patch 5 adds the RAUC boot logic to phycore_imx8mp. Leonard Anderweit (5): phycore_imx8mp: Move environment from include/config to board phycore_imx8mp: Move default bootcmd to board env configs: phycore-imx8mp_defconfig: Use redundant environment include: env: Add phytec RAUC boot logic board: phytec: phycore_imx8mp: Add RAUC boot logic to environment .../phytec/phycore_imx8mp/phycore_imx8mp.env | 62 +++ configs/phycore-imx8mp_defconfig | 4 +- include/configs/phycore_imx8mp.h | 43 - include/env/phytec/rauc.env | 52 4 files changed, 116 insertions(+), 45 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/phycore_imx8mp.env create mode 100644 include/env/phytec/rauc.env -- 2.25.1
Issue with Enabling CONFIG_NETCONSOLE in Boot-loader
Hello Team, I hope this email finds you well. I'm currently facing an issue with enabling the CONFIG_Netconsole flag under the bootloader. Despite CONFIG_NETCONSOLE being already enabled in the build system, I'm encountering difficulties in getting it to work. Here's what I've tried so far: 1. Enabled CONFIG_NETCONSOLE in the build system. 2. Set the environment variables as follows: * |setenv nc 'setenv stdout nc;setenv stdin nc'| * |setenv ncip 192.168.1.1| 3. Saved the environment using |saveenv|. 4. Executed |run ncc|. However, I encountered the following errors: |## Error inserting "stdout" variable, errno=22 ## Error inserting "stdin" variable, errno=22 | Upon checking the environment variables using |printenv|, I see that the |stdout|, |stdin|, and |stderr| variables are set to |serial@ff812000|. Here's the relevant part of the environment: |tderr=serial@ff812000 stdin=serial@ff812000 stdout=serial@ff812000 | I'm seeking your assistance in resolving this issue. Any guidance or solutions would be greatly appreciated. Thank you for your attention to this matter. Best regards, Ahmed - => setenv nc 'setenv stdout nc;setenv stdin nc' => setenv ncip 192.168.1.1 => saveenv Saving Environment to NVRAM... OK => run ncc ## Error inserting "stdout" variable, errno=22 ## Error inserting "stdin" variable, errno=22 => printenv arch=arm baudrate=115200 board=v14 board_name=v14 bootcmd=secure_boot bootcount=1 bootdelay=2 bootlimit=3 cpu=armv8 env_boot_magic=8192 fdtcontroladdr=6fcdffa0 initrd_high=0x loadaddr=0x100 ncc=setenv stdout ncc;setenv stdin ncc nccip=192.168.1.1 nummacaddrs=10 rootfs_opts=root= rdinit=/sbin/init silent=yes soc=bcm4912 stderr=serial@ff812000 stdin=serial@ff812000 stdout=serial@ff812000 u-boot-mode=nominal uboot-prestage-version=U-Boot TPL 2019.07 (Feb 16 2023 - 15:59:27 +0800) vendor=arcadyan Environment size: 597/16380 bytes => version U-Boot 2022.07 (Jun 15 2023 - 20:18:39 +) aarch64-buildroot-linux-gnu-gcc.br_real (Buildroot bcm9xxx-linux-4.19-gcc-10.3-glibc-2.32_v1.0.0) 10.3.0 GNU ld (GNU Binutils) 2.36.1
[GIT PULL] Please pull u-boot-imx-master-20240311
Hi Tom, Please pull from u-boot-imx, thanks. The following changes since commit 0981f8900f2b1f45a3f282b704012b5374fdd7a6: Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2024-03-09 11:29:48 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-master-20240311 for you to fetch changes up to 4484c7b3c38dcb21244a882d0b81d141db1ed162: arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8 (2024-03-11 08:43:42 -0300) u-boot-imx-master-20240311 -- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19896 - Use TF-A on imx8mp_beacon to fix boot regression. - Use latest 6.8 dts for imx8mp_beacon. - Fix the RAM initialization for phycore_imx8mp PCL-070 rev 1. - Describe the 0087 i.mx8m mini product variant in tdx-cfg-block. Adam Ford (2): configs: imx8mp_beacon: Fall back to using TF-A arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8 Benjamin Hahn (2): board: phytec: common: phytec_som_detection: Add phytec_get_som_type board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1 Joao Paulo Goncalves (1): toradex: tdx-cfg-block: add 0087 i.mx8m mini product variant arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi | 11 ++ arch/arm/dts/imx8mp-beacon-kit.dts | 245 - arch/arm/dts/imx8mp-beacon-som.dtsi| 71 + board/phytec/common/phytec_som_detection.c | 10 ++ board/phytec/common/phytec_som_detection.h | 8 + board/phytec/phycore_imx8mp/spl.c | 6 +- board/toradex/common/tdx-cfg-block.c | 1 + board/toradex/common/tdx-cfg-block.h | 1 + configs/imx8mp_beacon_defconfig| 7 - 9 files changed, 345 insertions(+), 15 deletions(-)
Re: [PATCH v2 4/5] pinctrl: qcom: Add support for driving GPIO pins output
Hi Sumit,
On 11/03/2024 11:10, Sumit Garg wrote:
> Add support for driving the GPIO pins as output low or high.
Ohh, this is why it was never working for me >,<
>
> Signed-off-by: Sumit Garg
> ---
> drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
> drivers/pinctrl/qcom/pinctrl-qcom.c| 26 +-
> 2 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index cb0e2227079..04b501c563d 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
> };
>
> static const struct pinctrl_function msm_pinctrl_functions[] = {
> + {"gpio", 0},
Please split this into a separate patch.
> {"blsp_uart1", 2},
> {"blsp_uart2", 2},
> };
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c
> b/drivers/pinctrl/qcom/pinctrl-qcom.c
> index ee0624df296..932be7c4840 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcom.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
> @@ -29,15 +29,25 @@ struct msm_pinctrl_priv {
> #define GPIO_CONFIG_REG(priv, x) \
> (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
>
> -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
> -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
> -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
> -#define TLMM_GPIO_DISABLE BIT(9)
> +#define GPIO_IN_OUT_REG(priv, x) \
> + (GPIO_CONFIG_REG(priv, x) + 0x4)
> +
> +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
> +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
> +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
> +#define TLMM_GPIO_OUTPUT_MASKBIT(1)
> +#define TLMM_GPIO_OE_MASKBIT(9)
> +
> +/* GPIO_IN_OUT register shifts. */
> +#define GPIO_IN 0
> +#define GPIO_OUT 1
Are there two separate bits? GPIO_IN is never used? Maybe just define
GPIO_OUT as BIT(0) instead?
>
> static const struct pinconf_param msm_conf_params[] = {
> { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
> { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
> { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
> + { "output-high", PIN_CONFIG_OUTPUT, 1, },
> + { "output-low", PIN_CONFIG_OUTPUT, 0, },
> };
>
> static int msm_get_functions_count(struct udevice *dev)
> @@ -89,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int
> pin_selector,
> return 0;
>
> clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
> - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
> + TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK,
> priv->data->get_function_mux(func_selector) << 2);
> return 0;
> }
> @@ -117,6 +127,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned
> int pin_selector,
> clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv,
> pin_selector),
> TLMM_GPIO_PULL_MASK, argument);
> break;
> + case PIN_CONFIG_OUTPUT:
> + writel(argument << GPIO_OUT,
Then this can be "argument ? GPIO_OUT : GPIO_IN" which feels much
cleaner. Or even just !!argument if it's bit 0.
> +priv->base + GPIO_IN_OUT_REG(priv, pin_selector));
> + setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
> + TLMM_GPIO_OE_MASK);
> + break;
> default:
> return 0;
> }
--
// Caleb (they/them)
Re: [PATCH v2 3/5] serial_msm: Enable RS232 flow control
On 11/03/2024 11:10, Sumit Garg wrote: > SE HMIBSC board debug console requires RS232 flow control, so enable > corresponding support if RS232 gpios are present. > > Signed-off-by: Sumit Garg Reviewed-by: Caleb Connolly > --- > drivers/serial/serial_msm.c | 13 - > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c > index eaf024a55b0..7b2a3fdb2c1 100644 > --- a/drivers/serial/serial_msm.c > +++ b/drivers/serial/serial_msm.c > @@ -53,10 +53,11 @@ > #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ > #define UARTDM_RF 0x140 /* UART Receive FIFO register */ > > -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC > -#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 > -#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 > -#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 > +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC > +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 > +#define MSM_BOOT_UART_DM_CMD_RESET_RX0x10 > +#define MSM_BOOT_UART_DM_CMD_RESET_TX0x20 > +#define MSM_UART_MR1_RX_RDY_CTL BIT(7) > > DECLARE_GLOBAL_DATA_PTR; > > @@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv) > mdelay(5); > > writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); > - writel(0x0, priv->base + UARTDM_MR1); > + > + /* Enable RS232 flow control to support RS232 db9 connector */ > + writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1); > writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); > writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); > writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); -- // Caleb (they/them)
Re: [PATCH v2 1/5] qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
On 11/03/2024 11:10, Sumit Garg wrote:
> Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow
> ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is
> loaded as a first stage bootloader. It leads to secondary CPUs bringup
> failure and later causing the Linux kernel to freeze.
>
> So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's
> actually required.
>
> Fixes: 059d526af312 ("mach-snapdragon: generalise board support")
> Signed-off-by: Sumit Garg
Reviewed-by: Caleb Connolly
> ---
> arch/arm/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 65fa7ba4ce7..27f3d9a43e1 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1090,7 +1090,7 @@ config ARCH_SNAPDRAGON
> select BOARD_LATE_INIT
> select OF_BOARD
> select SAVE_PREV_BL_FDT_ADDR
> - select LINUX_KERNEL_IMAGE_HEADER
> + select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
> imply CMD_DM
>
> config ARCH_SOCFPGA
--
// Caleb (they/them)
Re: [PATCH v2 2/5] apq8016: Add support for UART1 clocks and pinmux
Hi Sumit,
On 11/03/2024 11:10, Sumit Garg wrote:
> SE HMIBSC board uses UART1 as the main debug console, so add
> corresponding clocks and pinmux support. Along with that update
> instructions to enable clocks for debug UART support.
>
> Signed-off-by: Sumit Garg
> ---
> drivers/clk/qcom/clock-apq8016.c | 50 +-
> drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
> drivers/serial/serial_msm.c| 6 ++--
> 3 files changed, 47 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/qcom/clock-apq8016.c
> b/drivers/clk/qcom/clock-apq8016.c
> index e6647f7c41d..a620a10a520 100644
> --- a/drivers/clk/qcom/clock-apq8016.c
> +++ b/drivers/clk/qcom/clock-apq8016.c
> @@ -43,6 +43,14 @@
> #define BLSP1_UART2_APPS_N (0x3040)
> #define BLSP1_UART2_APPS_D (0x3044)
>
> +#define BLSP1_UART1_BCR (0x2038)
> +#define BLSP1_UART1_APPS_CBCR(0x203C)
> +#define BLSP1_UART1_APPS_CMD_RCGR(0x2044)
> +#define BLSP1_UART1_APPS_CFG_RCGR(0x2048)
> +#define BLSP1_UART1_APPS_M (0x204C)
> +#define BLSP1_UART1_APPS_N (0x2050)
> +#define BLSP1_UART1_APPS_D (0x2054)
> +
> /* GPLL0 clock control registers */
> #define GPLL0_STATUS_ACTIVE BIT(17)
>
> @@ -77,7 +85,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
> };
>
> /* SDHCI */
> -static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
> +static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint
> rate)
This seems like an unrelated change, I don't think we need to namespace
this function as it's static.
> {
> int div = 15; /* 100MHz default */
>
> @@ -94,6 +102,33 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int
> slot, uint rate)
> return rate;
> }
>
> +static const struct bcr_regs uart1_regs = {
> + .cfg_rcgr = BLSP1_UART1_APPS_CFG_RCGR,
> + .cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR,
> + .M = BLSP1_UART1_APPS_M,
> + .N = BLSP1_UART1_APPS_N,
> + .D = BLSP1_UART1_APPS_D,
> +};
> +
> +/* UART: 115200 */
> +static int apq8016_clk_init_uart1(phys_addr_t base)
I know we're still dealing with some tech debt here, but I'm not a big
fan of this approach. I notice that the RCG and CBCR registers are all
offset by exactly 0xff0 between UART1 and UART2, what about adding a
second "index" parameter to apq8016_clk_init_uart() and then offsetting
the addresses by (0xff0 * index)?
This will get cleaner once we drop the bcr_regs struct.
> +{
> + /* Enable AHB clock */
> + clk_enable_vote_clk(base, _blsp1_ahb_clk);
> +
> + /* 7372800 uart block clock @ GPLL0 */
> + clk_rcg_set_rate_mnd(base, _regs, 1, 144, 15625,
> + CFG_CLK_SRC_GPLL0, 16);
> +
> + /* Vote for gpll0 clock */
> + clk_enable_gpll0(base, _vote_clk);
> +
> + /* Enable core clk */
> + clk_enable_cbc(base + BLSP1_UART1_APPS_CBCR);
> +
> + return 0;
> +}
> +
> static const struct bcr_regs uart2_regs = {
> .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
> .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
> @@ -103,7 +138,7 @@ static const struct bcr_regs uart2_regs = {
> };
>
> /* UART: 115200 */
> -int apq8016_clk_init_uart(phys_addr_t base)
> +int apq8016_clk_init_uart2(phys_addr_t base)
> {
> /* Enable AHB clock */
> clk_enable_vote_clk(base, _blsp1_ahb_clk);
> @@ -127,14 +162,13 @@ static ulong apq8016_clk_set_rate(struct clk *clk,
> ulong rate)
>
> switch (clk->id) {
> case GCC_SDCC1_APPS_CLK: /* SDC1 */
> - return clk_init_sdc(priv, 0, rate);
> - break;
> + return apq8016_clk_init_sdc(priv, 0, rate);
> case GCC_SDCC2_APPS_CLK: /* SDC2 */
> - return clk_init_sdc(priv, 1, rate);
> - break;
> + return apq8016_clk_init_sdc(priv, 1, rate);
> case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
> - return apq8016_clk_init_uart(priv->base);
> - break;
> + return apq8016_clk_init_uart2(priv->base);
> + case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */
> + return apq8016_clk_init_uart1(priv->base);
> default:
> return 0;
> }
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index db0e2124684..cb0e2227079 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
> };
>
> static const struct pinctrl_function msm_pinctrl_functions[] = {
> + {"blsp_uart1", 2},
> {"blsp_uart2", 2},
> };
>
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index ac4280c6c4c..eaf024a55b0 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -248,12 +248,14 @@ static struct msm_serial_data init_serial_data = {
> #include
>
> /* Uncomment to turn on UART clocks when debugging U-Boot
[PATCH v4 20/20] rockchip: ringneck_px30: update website link
From: Quentin Schulz The original link returns a custom 404, so let's point to a link that works today instead. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- board/theobroma-systems/ringneck_px30/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS index 601830fe45b..97baf334d02 100644 --- a/board/theobroma-systems/ringneck_px30/MAINTAINERS +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -8,4 +8,4 @@ F: doc/board/theobroma-systems/ F: include/configs/ringneck_px30.h F: arch/arm/dts/px30-ringneck* F: configs/ringneck-px30_defconfig -W: https://www.theobroma-systems.com/px30-uq7#tech-spec +W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/ -- 2.44.0
[PATCH v4 17/20] rockchip: puma-rk3399: MAINTAINERS: use glob for dtses
From: Quentin Schulz There are multiple Device Trees in U-Boot git repo for Puma, so let's make the MAINTAINERS entry match them all. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- board/theobroma-systems/puma_rk3399/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS index 93f570fc4f9..23701b3f0ed 100644 --- a/board/theobroma-systems/puma_rk3399/MAINTAINERS +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -5,7 +5,7 @@ S: Maintained F: board/theobroma-systems/puma_rk3399 F: board/theobroma-systems/common F: include/configs/puma_rk3399.h -F: arch/arm/dts/rk3399-puma.dts +F: arch/arm/dts/rk3399-puma* F: configs/puma-rk3399_defconfig W: https://www.theobroma-systems.com/rk3399-q7/tech-specs T: git git://git.theobroma-systems.com/puma-u-boot.git -- 2.44.0
[PATCH v4 19/20] rockchip: ringneck_px30: migrate README to doc/board in rST format
From: Quentin Schulz This migrates the plaintext README in board/theobroma-systems/ringneck_px30 to doc/board/theobroma-systems and while doing so, update the instructions and rewrite it in rST. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- board/theobroma-systems/ringneck_px30/MAINTAINERS | 1 + board/theobroma-systems/ringneck_px30/README | 70 + doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/ringneck_px30.rst | 95 +++ 4 files changed, 98 insertions(+), 69 deletions(-) diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS index 06e1beaab14..601830fe45b 100644 --- a/board/theobroma-systems/ringneck_px30/MAINTAINERS +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -4,6 +4,7 @@ M: Klaus Goger S: Maintained F: board/theobroma-systems/ringneck_px30 F: board/theobroma-systems/common +F: doc/board/theobroma-systems/ F: include/configs/ringneck_px30.h F: arch/arm/dts/px30-ringneck* F: configs/ringneck-px30_defconfig diff --git a/board/theobroma-systems/ringneck_px30/README b/board/theobroma-systems/ringneck_px30/README index e756b3a8ffc..915baf4a9a0 100644 --- a/board/theobroma-systems/ringneck_px30/README +++ b/board/theobroma-systems/ringneck_px30/README @@ -1,69 +1 @@ -Introduction - - -The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230 -connector) system-on-module from Theobroma Systems[1], featuring the -Rockchip PX30. - -It provides the following feature set: - * up to 4GB DDR4 - * up to 128GB on-module eMMC (with 8-bit 1.8V interface) - * SD card (on a baseboard) via edge connector - * Fast Ethernet with on-module TI DP83825I PHY - * MIPI-DSI/LVDS - * MIPI-CSI - * USB -- 1x USB 2.0 dual-role -- 3x USB 2.0 host - * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: -- low-power RTC functionality (ISL1208 emulation) -- fan controller (AMC6821 emulation) -- USB<->CAN bridge controller (STM32 only) - * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi - * on-module NXP SE05x Secure Element - -Here is the step-by-step to boot to U-Boot on px30. - -Get the Source and build ATF binary -=== - - > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git - -Compile the ATF -=== - - > cd trusted-firmware-a - > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=px30 bl31 - > cp build/px30/release/bl31/bl31.elf ../u-boot/bl31.elf - -Compile the U-Boot -== - - > cd ../u-boot - > make CROSS_COMPILE=aarch64-linux-gnu- ringneck-px30_defconfig all - -Flash the image -=== - -Copy u-boot-rockchip.bin to offset 32k for SD/eMMC. - -SD-Card - - > dd if=u-boot-rockchip.bin of=/dev/sdb seek=64 - -eMMC - - -rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with -help of the Rockchip loader binary. - - > git clone https://github.com/rockchip-linux/rkdeveloptool - > cd rkdeveloptool - > autoreconf -i && ./configure && make - > git clone https://github.com/rockchip-linux/rkbin.git - > cd rkbin - > ./tools/boot_merger RKBOOT/PX30MINIALL.ini - > cd .. - > ./rkdeveloptool db rkbin/px30_loader_v1.16.131.bin - > ./rkdeveloptool wl 64 ../u-boot-rockchip.bin +See doc/board/theobroma-systems/ringneck_px30.rst. diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst index 0720128ad52..b4da2616c37 100644 --- a/doc/board/theobroma-systems/index.rst +++ b/doc/board/theobroma-systems/index.rst @@ -8,3 +8,4 @@ Theobroma Systems jaguar_rk3588 puma_rk3399 + ringneck_px30 diff --git a/doc/board/theobroma-systems/ringneck_px30.rst b/doc/board/theobroma-systems/ringneck_px30.rst new file mode 100644 index 000..c16b9ed17ed --- /dev/null +++ b/doc/board/theobroma-systems/ringneck_px30.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +PX30-uQ7 Ringneck += + +The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230 +connector) system-on-module from Theobroma Systems, featuring the Rockchip PX30. + +It provides the following feature set: + + * up to 4GB DDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card (on a baseboard) via edge connector + * Fast Ethernet with on-module TI DP83825I PHY + * MIPI-DSI/LVDS + * MIPI-CSI + * USB + +- 1x USB 2.0 dual-role +- 3x USB 2.0 host + + * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: + +- low-power RTC functionality (ISL1208 emulation) +- fan controller (AMC6821 emulation) +- USB<->CAN bridge controller (STM32 only) + + * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi + * on-module NXP SE05x Secure Element + +Here is the step-by-step to boot to U-Boot on PX30-uQ7 Ringneck from
[PATCH v4 18/20] rockchip: rk3399-puma: migrate README to doc/board in rST format
From: Quentin Schulz This migrates the plaintext README in board/theobroma-systems/puma_rk3399 to doc/board/theobroma-systems and while doing so, update the instructions and rewrite it in rST. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- board/theobroma-systems/puma_rk3399/MAINTAINERS | 1 + board/theobroma-systems/puma_rk3399/README | 90 + doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/puma_rk3399.rst | 126 4 files changed, 129 insertions(+), 89 deletions(-) diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS index 23701b3f0ed..7e84a5be262 100644 --- a/board/theobroma-systems/puma_rk3399/MAINTAINERS +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -4,6 +4,7 @@ M: Klaus Goger S: Maintained F: board/theobroma-systems/puma_rk3399 F: board/theobroma-systems/common +F: doc/board/theobroma-systems F: include/configs/puma_rk3399.h F: arch/arm/dts/rk3399-puma* F: configs/puma-rk3399_defconfig diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index 649aa3c543d..39c9d618866 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -1,89 +1 @@ -Introduction - - -The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip -RK3399 in a Qseven-compatible form-factor. - -RK3399-Q7 features: - * CPU: ARMv8 64bit Big-Little architecture, - * Big: dual-core Cortex-A72 - * Little: quad-core Cortex-A53 - * IRAM: 200KB - * DRAM: 4GB-128MB dual-channel - * eMMC: onboard eMMC - * SD/MMC - * GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY - * USB: - * USB3.0 dual role port - * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub - * Display: HDMI/eDP/MIPI - * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF) - * NOR Flash: onboard SPI NOR - * Companion Controller: onboard additional Cortex-M0 microcontroller - * RTC - * fan controller - * CAN - -Here is the step-by-step to boot to U-Boot on rk3399. - -Get the Source and build ATF binary -=== - - > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git - -Compile the ATF -=== - - > cd trusted-firmware-a - > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 - > cp build/rk3399/release/bl31/bl31.elf ../u-boot/bl31.elf - -Compile the U-Boot -== - - > cd ../u-boot - > make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all - -Flash the image -=== - -Copy u-boot-rockchip.bin to offset 32k for SD/eMMC. -Copy u-boot-rockchip-spi.bin to offset 0 for NOR-flash. - -SD-Card - - > dd if=u-boot-rockchip.bin of=/dev/sdb seek=64 - -eMMC - - -rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with -help of the Rockchip loader binary. - - > git clone https://github.com/rockchip-linux/rkdeveloptool - > cd rkdeveloptool - > autoreconf -i && ./configure && make - > git clone https://github.com/rockchip-linux/rkbin.git - > cd rkbin - > ./tools/boot_merger RKBOOT/RK3399MINIALL.ini - > cd .. - > ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin - > ./rkdeveloptool wl 64 ../u-boot-rockchip.bin - -NOR-Flash -- - -rkdeveloptool allows to flash the on-board SPI via the USB OTG interface with -help of the Rockchip loader binary. - - > git clone https://github.com/rockchip-linux/rkdeveloptool - > cd rkdeveloptool - > autoreconf -i && ./configure && make - > git clone https://github.com/rockchip-linux/rkbin.git - > cd rkbin - > ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini - > cd .. - > ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin - > ./rkdeveloptool ef - > ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin +See doc/board/theobroma-systems/puma_rk3399.rst. diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst index 945f7a2f976..0720128ad52 100644 --- a/doc/board/theobroma-systems/index.rst +++ b/doc/board/theobroma-systems/index.rst @@ -7,3 +7,4 @@ Theobroma Systems :maxdepth: 2 jaguar_rk3588 + puma_rk3399 diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst new file mode 100644 index 000..5bc6385e451 --- /dev/null +++ b/doc/board/theobroma-systems/puma_rk3399.rst @@ -0,0 +1,126 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +RK3399-Q7 Puma +== + +The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip +RK3399 in a Qseven-compatible form-factor. + +RK3399-Q7 features: + + * CPU: ARMv8 64bit Big-Little architecture, + + * Big: dual-core
[PATCH v4 16/20] board: rockchip: add Theobroma-Systems RK3588 Jaguar SBC
From: Quentin Schulz
JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and
is targeting Autonomous Mobile Robots (AMR).
It features:
* LPDDR4X (up to 16GB)
* 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131)
* PCIe 3.0 4-lane on M.2 M-key connector
* PCIe 2.1 1-lane on M.2 E-key
* USB 2.0 on M.2 E-key
* 2x USB3 OTG type-c ports with DP Alt-Mode
* USB2 host port
* HDMI output
* 2x camera connectors, each exposing:
* 2-lane MIPI-CSI
* 1v2, 1v8, 2v8 power rails
* I2C bus
* GPIOs
* PPS input
* CAN
* RS485 UART
* FAN connector
* SD card slot
* eMMC (up to 256GB)
* RTC backup battery
* Companion microcontroller
* ISL1208 RTC emulation
* AMC6821 PWM emulation
* On/off buzzer control
* Secure Element
* 80-pin Mezzanine connector for daughterboards:
* GPIOs
* 1Gbps Ethernet
* PCIe 2.1 1-lane
* 2x 2-lane MIPI-CSI
* ADC channel
* I2C bus
* PWM
* UART
* SPI
* SDIO
* CAN
* I2S
* 1v8, 3v3, 5v0, dc-in (12-24V) power rails
The Device Tree comes from next-20240110 Linux kernel.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3588-jaguar-u-boot.dtsi | 33 +
arch/arm/dts/rk3588-jaguar.dts | 803 +
arch/arm/mach-rockchip/rk3588/Kconfig | 28 +
board/theobroma-systems/jaguar_rk3588/Kconfig | 16 +
board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 13 +
board/theobroma-systems/jaguar_rk3588/Makefile | 10 +
.../jaguar_rk3588/jaguar_rk3588.c | 53 ++
configs/jaguar-rk3588_defconfig| 114 +++
doc/board/index.rst| 1 +
doc/board/rockchip/rockchip.rst| 1 +
doc/board/theobroma-systems/index.rst | 9 +
doc/board/theobroma-systems/jaguar_rk3588.rst | 100 +++
include/configs/jaguar_rk3588.h| 15 +
14 files changed, 1197 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b102ffb5f68..f31f3904ffd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -194,6 +194,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
+ rk3588-jaguar.dtb \
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
new file mode 100644
index 000..dcda4f99d6e
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on
RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts
new file mode 100644
index 000..4ce70fb75a3
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar.dts
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include
+#include
+#include
+#include
+#include
+#include "rk3588.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-SBC Jaguar";
+ compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ /* Can be controlled through SW2 but also GPIO1 on CP2102 on
P20 */
+ button-bios-disable {
+ label = "BIOS_DISABLE";
+ linux,code = ;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ aliases {
+ ethernet0 =
+ mmc0 =
+ mmc1 =
+ rtc0 = _twi;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ /* DCIN is 12-24V but standard is 12V */
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt =
[PATCH v4 14/20] rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h
From: Quentin Schulz The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/include/asm/arch-rockchip/hardware.h| 2 ++ arch/arm/mach-rockchip/cpu-info.c| 1 - arch/arm/mach-rockchip/px30/px30.c | 1 - arch/arm/mach-rockchip/rk3036/rk3036.c | 1 - arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 1 - arch/arm/mach-rockchip/rk3066/rk3066.c | 1 - arch/arm/mach-rockchip/rk3188/rk3188.c | 1 - arch/arm/mach-rockchip/rk322x/rk322x.c | 1 - arch/arm/mach-rockchip/rk3288/rk3288.c | 1 - arch/arm/mach-rockchip/rk3308/rk3308.c | 1 - arch/arm/mach-rockchip/rk3328/rk3328.c | 1 - arch/arm/mach-rockchip/rk3368/rk3368.c | 1 - arch/arm/mach-rockchip/rk3399/rk3399.c | 1 - arch/arm/mach-rockchip/rk3568/rk3568.c | 1 - arch/arm/mach-rockchip/rk3588/rk3588.c | 1 - arch/arm/mach-rockchip/rv1126/rv1126.c | 1 - board/elgin/elgin_rv1108/elgin_rv1108.c | 1 - board/firefly/firefly-rk3308/roc_cc_rk3308.c | 1 - board/google/gru/gru.c | 1 - board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 1 - board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 1 - board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 1 - board/rockchip/evb_rv1108/evb_rv1108.c | 1 - board/theobroma-systems/puma_rk3399/puma-rk3399.c| 1 - board/vamrs/rock960_rk3399/rock960-rk3399.c | 1 - drivers/clk/rockchip/clk_pll.c | 1 - drivers/clk/rockchip/clk_px30.c | 1 - drivers/clk/rockchip/clk_rk3036.c| 1 - drivers/clk/rockchip/clk_rk3066.c| 1 - drivers/clk/rockchip/clk_rk3128.c| 1 - drivers/clk/rockchip/clk_rk3188.c| 1 - drivers/clk/rockchip/clk_rk322x.c| 1 - drivers/clk/rockchip/clk_rk3288.c| 1 - drivers/clk/rockchip/clk_rk3308.c| 1 - drivers/clk/rockchip/clk_rk3328.c| 1 - drivers/clk/rockchip/clk_rk3368.c| 1 - drivers/clk/rockchip/clk_rk3399.c| 1 - drivers/clk/rockchip/clk_rk3568.c| 1 - drivers/clk/rockchip/clk_rk3588.c| 1 - drivers/clk/rockchip/clk_rv1108.c| 1 - drivers/clk/rockchip/clk_rv1126.c| 1 - drivers/gpio/rk_gpio.c | 1 - drivers/net/gmac_rockchip.c | 1 - drivers/ram/rockchip/dmc-rk3368.c| 1 - drivers/ram/rockchip/sdram_px30.c| 1 - drivers/ram/rockchip/sdram_rk3066.c | 1 - drivers/ram/rockchip/sdram_rk3188.c | 1 - drivers/ram/rockchip/sdram_rk322x.c | 1 - drivers/ram/rockchip/sdram_rk3288.c | 1 - drivers/ram/rockchip/sdram_rk3399.c | 1 - drivers/ram/rockchip/sdram_rv1126.c | 1 - drivers/rng/rockchip_rng.c | 1 - drivers/sysreset/sysreset_rockchip.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c| 1 - drivers/video/rockchip/rk3288_hdmi.c | 1 - drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3288_vop.c | 1 - drivers/video/rockchip/rk3399_hdmi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk3399_vop.c | 1 - drivers/video/rockchip/rk_edp.c | 1 - drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/rockchip/rk_lvds.c | 1 - 63 files changed, 2 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index 62e8bed8f31..e4662a2d52d 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#include + #define RK_CLRSETBITS(clr, set)clr) | (set)) << 16) | (set)) #define RK_SETBITS(set)RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr)
[PATCH v4 13/20] rockchip: migrate hardware.h inclusion into appropriate files
From: Quentin Schulz hardware.h is only defining macros which are "wrappers" around writel(). writel() is however not available in hardware.h, needs to be included. This means in order to use the wrappers in hardware.h, one also needs to include the header. However, this cannot be done currently because hardware.h is included in include/configs files, which are implicitly included by every code file by default, which makes the compilation of arch/arm/cpu/armv8/u-boot.lds fail because ALIGN (the ARM assembly directive) got redefined by some of the include files coming from . Because nothing in the include/configs file actually use hardware.h, let's remove the inclusion of hardware.h from the include/configs files and explicitly add it wherever it is required. This prepares for the next commit where will be included in hardware.h. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/rk3066/rk3066.c | 1 + drivers/ram/rockchip/dmc-rk3368.c | 1 + drivers/ram/rockchip/sdram_rk3188.c| 1 + drivers/ram/rockchip/sdram_rk3288.c| 1 + include/configs/rk3036_common.h| 1 - include/configs/rk3066_common.h| 1 - include/configs/rk3188_common.h| 1 - include/configs/rk322x_common.h| 1 - include/configs/rk3288_common.h| 1 - include/configs/rk3368_common.h| 1 - include/configs/rv1108_common.h| 1 - 11 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 78c7d894f90..6661b788295 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -7,6 +7,7 @@ #include #include #include +#include #define GRF_BASE 0x20008000 diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index f36be941a38..859fc47030f 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index ad9f936df55..d23d4231798 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index c99118fd612..3177051dd12 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index c2abd14e114..0bf9e8b9a2e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 2400 diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index d70c8f77d48..6a3b6900463 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3066_COMMON_H #define __CONFIG_RK3066_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x1008 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index a8cee1e44d4..98f2c25f3cf 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x1008 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 15f77df3e17..bab4ca015f7 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK322X_COMMON_H #define __CONFIG_RK322X_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 2400 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 3063076a97a..0c449e31099 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 2400 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index ccb5369b901..d488f8d477a 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#include #include #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 3bf70a0e0ae..ff28236a21d 100644 ---
[PATCH v4 15/20] rockchip: rk3588: bind MMC controllers in U-Boot proper pre-reloc
From: Quentin Schulz
Since commit 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as
pre-reloc after relocation"), bootph-pre-ram doesn't make U-Boot proper
bind the device before relocation.
While this is usually not much of an issue, it is when there's a lookup
for devices by code running before the relocation. Such is the case of
env_init() which calls env_driver_lookup() which calls
env_get_location() which is a weak symbol and may call
arch_env_get_location() also a weak symbol. Those are two functions that
may traverse UCLASS to find some devices (e.g.
board/theobroma-systems/common/common.c:arch_env_get_location()).
This allows something in the env_init() call stack to be able to use
uclasses for SD and eMMC controller on RK3588S/RK3588. This aligns the
behavior with what seems to be all SoCs except RK356x family.
Additionally, if any other env function (e.g. env_load) were to be used
before relocation, this is also required as otherwise it wouldn't be
able to find the MMC device(s).
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
arch/arm/dts/rk3588s-u-boot.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index bf3b1ea8a3c..ac67c777ade 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -188,11 +188,13 @@
{
bootph-pre-ram;
+ bootph-some-ram;
u-boot,spl-fifo-mode;
};
{
bootph-pre-ram;
+ bootph-some-ram;
u-boot,spl-fifo-mode;
};
--
2.44.0
[PATCH v4 12/20] rockchip: rk3588: add constants for some register address spaces
From: Quentin Schulz
It's one thing to have the register mapped via a well-defined struct but
it's another to be able to make use of it. For that to happen, one needs
to cast the physical address memory of the beginning of the register
address space with the struct. Since this cannot change, let's hardcode
it in the include files so that users do not need to duplicate this line
of code in their own implementation.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
arch/arm/include/asm/arch-rockchip/ioc_rk3588.h | 6 ++
arch/arm/mach-rockchip/rk3588/rk3588.c | 4
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index 7f4a9085392..a4507e5fdd7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -63,6 +63,8 @@ struct rk3588_pll {
unsigned int reserved0[3];
};
+#define CRU_BASE 0xfd7c
+
struct rk3588_cru {
struct rk3588_pll pll[18];
unsigned int reserved0[16];/* Address Offset: 0x0240 */
diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
index 5a656f850c7..7ad98466c39 100644
--- a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
@@ -5,6 +5,8 @@
#ifndef _ASM_ARCH_IOC_RK3588_H
#define _ASM_ARCH_IOC_RK3588_H
+#define BUS_IOC_BASE 0xfd5f8000
+
struct rk3588_bus_ioc {
unsigned int reserved[3]; /* Address Offset: 0x */
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
@@ -48,6 +50,8 @@ struct rk3588_bus_ioc {
check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
+#define PMU1_IOC_BASE 0xfd5f
+
struct rk3588_pmu1_ioc {
unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x */
unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
@@ -70,6 +74,8 @@ struct rk3588_pmu1_ioc {
check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
+#define PMU2_IOC_BASE 0xfd5f4000
+
struct rk3588_pmu2_ioc {
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x */
unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index d18c4e4b411..7a190e6aa18 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -26,10 +26,6 @@
#define FW_SYSM_MST26_REG 0xa8
#define FW_SYSM_MST27_REG 0xac
-#define PMU1_IOC_BASE 0xfd5f
-#define PMU2_IOC_BASE 0xfd5f4000
-
-#define BUS_IOC_BASE 0xfd5f8000
#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
--
2.44.0
[PATCH v4 11/20] rockchip: rk3588: disable force_jtag by default
From: Quentin Schulz
Rockchip SoCs can automatically switch between jtag and sdmmc based on
the following rules:
- all the SDMMC pins including SDMMC_DET set as SDMMC function in GRF,
- force_jtag bit in GRF is 1,
- SDMMC_DET is low (no card detected),
Note that the BootROM may mux all SDMMC pins in their SDMMC function or
not, depending on the boot medium that were tried.
Because SDMMC_DET pin is not guaranteed to be used as an SD card card
detect pin, it could be low at boot or even switch at runtime, which
would enable the jtag function and render the SD card unusable.
This is the case for RK3588 Jaguar for example which has an SD card
connector without an SD card card detect signal and has SDMMC_DET
connected to ground.
Because enabling JTAG at runtime could be a security issue and also to
make sure that we have a consistent behavior on all boards by default,
let's disable this force_jtag feature.
However, let's make it easy to reenable it for debugging purposes by
hiding it behind a Kconfig symbol.
Note that soc_con[0] is reserved. But considering that it's way more
user-friendly to access soc_con1 from the TRM with soc_con[1] than
soc_con[0], and that soc_con0 would actually be located at 4 bytes
before soc_con1, let's just make soc_con0 part of the soc_con array.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/grf_rk3588.h | 24
arch/arm/mach-rockchip/Kconfig | 24
arch/arm/mach-rockchip/rk3588/rk3588.c | 11 +++
3 files changed, 59 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
index e0694068bb1..f0ecff97f0b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
@@ -32,4 +32,28 @@ struct rk3588_pmu1grf {
check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0);
+#define SYS_GRF_BASE 0xfd58c000
+
+struct rk3588_sysgrf {
+ unsigned int wdt_con0;
+ unsigned int reserved0[(0x0010 - 0x) / 4 - 1];
+ unsigned int uart_con[2];
+ unsigned int reserved1[(0x00c0 - 0x0014) / 4 - 1];
+ unsigned int gic_con0;
+ unsigned int reserved2[(0x0200 - 0x00c0) / 4 - 1];
+ unsigned int memcfg_con[32];
+ unsigned int reserved3[(0x0300 - 0x027c) / 4 - 1];
+ /* soc_con0 is reserved */
+ unsigned int soc_con[14];
+ unsigned int reserved4[(0x0380 - 0x0334) / 4 - 1];
+ unsigned int soc_status[4];
+ unsigned int reserved5[(0x0500 - 0x038c) / 4 - 1];
+ unsigned int otp_key08;
+ unsigned int otp_key0d;
+ unsigned int otp_key0e;
+ unsigned int reserved6[(0x0600 - 0x0508) / 4 - 1];
+ unsigned int chip_id;
+};
+
+check_member(rk3588_sysgrf, chip_id, 0x0600);
#endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1bc7ee90427..343361a5327 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -501,6 +501,30 @@ config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
This enables support code in the BOOT0 hook for the SPL stage
to allow multiple entries.
+config ROCKCHIP_DISABLE_FORCE_JTAG
+ bool "Disable force_jtag feature"
+ default y
+ depends on SPL
+ help
+ Rockchip SoCs can automatically switch between jtag and sdmmc based
+ on the following rules:
+ - all the SDMMC pins including SDMMC_DET set as SDMMC function in
+ GRF,
+ - force_jtag bit in GRF is 1,
+ - SDMMC_DET is low (no card detected),
+
+ Some HW design may not route the SD card card detect to SDMMC_DET
+ pin, thus breaking the SD card support in some cases because JTAG
+ would be auto-enabled by mistake.
+
+ Also, enabling JTAG at runtime may be an undesired feature, e.g.
+ because it could be a security vulnerability.
+
+ This disables force_jtag feature, which you may want for debugging
+ purposes.
+
+ If unsure, say Y.
+
config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
bool "TPL requires early-return (for RK3188-style BROM) to BROM"
depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 38e95a6e2b2..d18c4e4b411 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -35,6 +36,8 @@
#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
+#define SYS_GRF_FORCE_JTAG BIT(14)
+
/**
* Boot-device identifiers used by the BROM on RK3588 when device is booted
* from SPI flash. IOMUX used for SPI flash affect the value used by the BROM
@@ -134,6 +137,9 @@ void
[PATCH v4 09/20] rockchip: merge misc.c into board.c
From: Quentin Schulz
The functions aren't used anywhere else than in board.c, therefore,
let's not expose them anymore at all.
This merges misc.c and board.c together and removes the functions from
the misc.h header file.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/misc.h | 5 --
arch/arm/mach-rockchip/Makefile | 1 -
arch/arm/mach-rockchip/board.c| 125 +++
arch/arm/mach-rockchip/misc.c | 135 --
4 files changed, 125 insertions(+), 141 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h
b/arch/arm/include/asm/arch-rockchip/misc.h
index 4155af8c3b0..ef37ff1661a 100644
--- a/arch/arm/include/asm/arch-rockchip/misc.h
+++ b/arch/arm/include/asm/arch-rockchip/misc.h
@@ -6,9 +6,4 @@
* Rohan Garg
*/
-int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
- const u32 cpuid_length,
- u8 *cpuid);
-int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
-int rockchip_setup_macaddr(void);
void rockchip_capsule_update_board_setup(void);
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1dc92066bbf..c07bdaee4c3 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -23,7 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# meaning "turn it off".
obj-y += boot_mode.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
-obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
ifeq ($(CONFIG_TPL_BUILD),)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index d5cb59c10fa..80b4514852f 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -1,20 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ * Rohan Garg
+ *
+ * Based on puma-rk3399.c:
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -297,6 +309,119 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason
reason)
#endif
#ifdef CONFIG_MISC_INIT_R
+int rockchip_setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+
+ /* Only generate a MAC address, if none is set in the environment */
+ if (env_get("ethaddr"))
+ return 0;
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return -1;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, );
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return -1;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ /* Make a valid MAC address for ethernet1 */
+ mac_addr[5] ^= 0x01;
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+ const u32 cpuid_length,
+ u8 *cpuid)
+{
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ struct udevice *dev;
+ int ret;
+
+ /* retrieve the device */
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_efuse), );
+#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), );
+#endif
+ if (ret) {
+ debug("%s: could not find efuse device\n", __func__);
+ return -1;
+ }
+
+ /* read the cpu_id range from the efuses */
+ ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
+ if (ret < 0) {
+ debug("%s: reading cpuid from the efuses failed\n",
+ __func__);
+ return -1;
+ }
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
+{
+ u8 low[cpuid_length / 2], high[cpuid_length / 2];
+ char cpuid_str[cpuid_length * 2 + 1];
+ u64
[PATCH v4 10/20] rockchip: transform rockchip_capsule_update_board_setup into a weak function symbol
From: Quentin Schulz
There's only one user of rockchip_capsule_update_board_setup, which is
in board.c, and only one board defines it, so instead of having a header
only for one function symbol, let's just use a weak symbol instead.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Reviewed-by: Dragan Simic
Reviewed-by: Peter Robinson
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/misc.h | 9 -
arch/arm/mach-rockchip/board.c| 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h
b/arch/arm/include/asm/arch-rockchip/misc.h
deleted file mode 100644
index ef37ff1661a..000
--- a/arch/arm/include/asm/arch-rockchip/misc.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * RK3399: Architecture common definitions
- *
- * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
- * Rohan Garg
- */
-
-void rockchip_capsule_update_board_setup(void);
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 80b4514852f..4f666aee706 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -32,7 +32,6 @@
#include
#include
#include
-#include
#include
#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
@@ -148,6 +147,10 @@ void set_dfu_alt_info(char *interface, char *devstr)
env_set("dfu_alt_info", buf);
}
+__weak void rockchip_capsule_update_board_setup(void)
+{
+}
+
static void gpt_capsule_update_setup(void)
{
int p, i, ret;
--
2.44.0
[PATCH v4 08/20] rockchip: theobroma-systems: ringneck: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_boottargets differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
.../theobroma-systems/ringneck_px30/ringneck-px30.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index ff7e414303d..bfebfe5136d 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -4,29 +4,11 @@
*/
#include
-#include
#include
#include "../common/common.h"
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
setup_boottargets();
return 0;
--
2.44.0
[PATCH v4 07/20] rockchip: theobroma-systems: puma: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_iodomain() and setup_boottargets differ from the original
misc_init_r from Rockchip mach code, so let's use
rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
board/theobroma-systems/puma_rk3399/puma-rk3399.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index a82f97b2d54..98a818b135d 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -10,7 +10,6 @@
#include
#include
#include
-#include
#include "../common/common.h"
static void setup_iodomain(void)
@@ -27,25 +26,8 @@ static void setup_iodomain(void)
rk_setreg(>io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
setup_iodomain();
setup_boottargets();
--
2.44.0
[PATCH v4 06/20] rockchip: pine64: rockpro64: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Reviewed-by: Dragan Simic
Reviewed-by: Peter Robinson
Signed-off-by: Quentin Schulz
---
board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
index d79084614f1..d0a694ead1d 100644
--- a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
+++ b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#define GRF_IO_VSEL_BT565_SHIFT 0
#define PMUGRF_CON0_VSEL_SHIFT 8
@@ -31,26 +30,11 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
+ return 0;
}
#endif
--
2.44.0
[PATCH v4 05/20] rockchip: pine64: pinephone-pro: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip (the side effect being that
rockchip_setup_macaddr() is back).
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Reviewed-by: Dragan Simic
Reviewed-by: Peter Robinson
Signed-off-by: Quentin Schulz
---
.../pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index b6ccbb9c1c4..de75ee329d8 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include
#define GRF_IO_VSEL_BT565_GPIO2AB 1
@@ -56,23 +55,11 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
+ return 0;
- return ret;
}
#endif
--
2.44.0
[PATCH v4 03/20] rockchip: google: gru: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
board/google/gru/gru.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index fbcf845e87d..ecbf702b035 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#define GRF_IO_VSEL_BT656_SHIFT 0
#define GRF_IO_VSEL_AUDIO_SHIFT 1
@@ -85,24 +84,9 @@ static void setup_iodomain(void)
1 << PMUGRF_CON0_VOL_SHIFT));
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
+ return 0;
}
--
2.44.0
