From: Rick Chen
Disable AVAILABLE_HARTS mechanism to make sure that all harts
can boot to Kernel shell successfully.
Signed-off-by: Rick Chen
---
configs/ae350_rv32_spl_defconfig | 1 +
configs/ae350_rv64_spl_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/ae350_rv32_sp
From: Rick Chen
In SMP all harts will register themself in available_hart
during start up. Then main hart will send IPI to other harts
according to this variables. But this mechanism may not
guarantee that all other harts can jump to next stage.
When main hart is sending IPI to other hart accord
From: Rick Chen
It will fail to boot with ae350_rv[32|64]_spl_xip_defconfig.
It need to add OONFIG_XIP to get the specific HW address for DTB.
Also drop OF_SEPARATE in board_fdt_blob_setup() because it will
never reach here anyway.It only allow OF_BOARD to call
board_fdt_blob_setup() in fdtdec_se
From: Rick Chen
Disable BINMAN_FDT for ae350 boards which don't actually use it.
Fixes: 836eac7c6fe3 ("fdt: Make OF_BOARD a bool option")
Signed-off-by: Rick Chen
---
configs/ae350_rv32_spl_defconfig | 1 +
configs/ae350_rv32_spl_xip_defconfig | 1 +
configs/ae350_rv64_spl_defconfig |
From: Rick Chen
Enable OF_HAS_PRIOR_STAGE for ae350 boards with OF_BOARD
Fixes: 239d22c79520 ("fdt: Enable OF_HAS_PRIOR_STAGE for most boards with
OF_BOARD")
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/AndesTech/ax2
From: Rick Chen
It will need larger heap size for u-boot-spl to load u-boot.itb which
be generated from binman than USE_SPL_FIT_GENERATOR.
Signed-off-by: Rick Chen
---
configs/ae350_rv32_spl_defconfig | 1 +
configs/ae350_rv32_spl_xip_defconfig | 1 +
configs/ae350_rv64_spl_defconfig |
From: Rick Chen
Add Leo as co-maintainer for RISC-V.
Signed-off-by: Rick Chen
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a7a62df..ee89d50 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -947,6 +947,7 @@ F: arch/powerpc/cpu/mpc86xx/
RIS
From: Rick Chen
Use fdtdec_get_addr_size_auto_noparent to read the "reg" property
instead of fdtdec_get_addr. This will increase the compatibility
of dtb parsing.
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
From: Rick Chen
For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan
From: Rick Chen
Those are required for cfi-flash driver to get correct address information.
Also modify size description correctly.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
arch/riscv/dts/ae350_32.dts | 4 +++-
arch/riscv/dts/ae350_64.dts | 4 +++-
2 files changed, 6 insertions(+
+---
+Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be
+cloned and build for AE350 as below:
+
+git clone https://github.com/riscv/opensbi.git
+cd opensbi
+make PLATFORM=andes/ae350
+
+Copy OpenSBI FW_DYNAMIC image
(build\platform\andes\ae350\firmware
From: Rick Chen
Add CPU2 and CPU3 information in cpus node
to support four cores SMP booting.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
arch/riscv/dts/ae350_32.dts | 57 ++---
arch/riscv/dts/ae350_64.dts | 57
From: Rick Chen
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
common/spl/Kconfig | 7 +++
drivers/Makefile | 1 +
2 files changed, 8 insertions(+)
diff --git a/co
From: Rick Chen
To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++---
1 f
From: Rick Chen
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
arch/riscv/cpu/ax25/cache.c | 60 ++---
1 file changed, 46 inserti
From: Rick Chen
Fix two wrong settings of andes plic driver as below:
1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
int can help to fix wrong plic enabling setting in RV64.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc
From: Rick Chen
This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.
With ae350_rv[32|64]_spl_defconfigs:
U-Boot SPL will be loaded by g
From: Rick Chen
This series add support for SPL to AX25-AE350.
U-Boot SPL can boot from RAM or ROM and jump to
OPenSbi(FW_DYNAMIC firmware) and U-Boot proper from
RAM or MMC devices.
Also fix some bugs of andes plic driver and improve cache
configurations for SPL.
Changes in v2:
- Remove
SPL_CPU_SUPPORT
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
--
2.7.4
___
U-Boot mailing
From: Rick Chen
For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan
From: Rick Chen
Add CPU2 and CPU3 informations in cpus node
to support four cores SMP booting.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
arch/riscv/dts/ae350_32.dts | 51 ++---
arch/riscv/dts/ae350_64.dts | 51 +++
From: Rick Chen
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
arch/riscv/cpu/ax25/cache.c | 60 ++---
1 file changed, 46 inserti
From: Rick Chen
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
common/spl/Kconfig | 7 +++
drivers/Makefile | 1 +
2 files changed, 8 insertions(+)
diff --git a/co
From: Rick Chen
To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSbi.
Signed-off-by: Rick Chen
Cc: KC Lin
Cc: Alan Kao
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++---
1 f
From: Rick Chen
It will work fine due to hart 0 always will be main
hart coincidentally. When develop SPL flow, I try to
force other harts to be main hart. And it will go
wrong in sending IPI flow. So fix it.
Having this fix, any hart can be main hart in U-Boot SPL
theoretically, but it still fa
From: Rick Chen
This patch provides four configurations
which can support U-Boot SPL to boot from
RAM or FLASH and then boot FIT image
including OpenSBI FW_DYNAMIC firmware
and U-Boot proper images from RAM or
MMC boot devices.
With ae350_rv[32|64]_spl_defconfigs:
U-Boot SPL will be loaded by g
some specific features
which are provided by Andes Technology AndeStar V5 families.
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
From: Rick Chen
This series add support for SPL to AX25-AE350.
U-Boot SPL can boots from RAM or ROM and jump to
OPenSbi(FW_DYNAMIC firmware) and U-Boot proper from
RAM or MMC devices.
Also fix some bugs for andes plic driver and improve cache
configurations for SPL.
Following are the booting
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL 6
+#endif
void flush_dcache_all(void)
{
- /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-
From: Rick Chen
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.
5l2cache";
+ cache-level = <2>;
+ cache-size = <0x4>;
+ reg = <0xe050 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is */
+
From: Rick Chen
Select the v5l2 UCLASS_CACHE driver for ax25.
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
---
arch/riscv/cpu/ax25/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..49be775 100644
From: Rick Chen
Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
---
arch/ri
From: Rick Chen
Add cache enable and disable ops for test coverage.
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
---
drivers/cache/sandbox_cache.c | 13 +
test/dm/cache.c | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/cache/sandbox_cac
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen
Cc: KC Lin
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.
Also implement L2 cache flush and disable before jump
From: Rick Chen
Add cache enable/disable ops to the DM cache uclass driver
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
---
drivers/cache/cache-uclass.c | 20
include/cache.h | 31 +++
2 files changed, 51 insertions(+
From: Rick Chen
Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().
This way can support to skip some harts which maybe mark as
unavailable, but the cpu node exist indeed.
Signed-off-by: Rick Chen
Cc: KC Lin
---
arch/riscv/lib/andes_plic.c | 36 +++
From: Rick Chen
Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().
This way can support to skip some harts which maybe mark as
unavailable, but the cpu node exist indeed.
Signed-off-by: Rick Chen
Cc: KC Lin
---
arch/riscv/lib/andes_plic.c | 36 +++
From: Rick Chen
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL 6
+#endif
void flush_dcache_all(void)
{
- /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-
From: Rick Chen
Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen
Cc: KC Lin
---
arch/riscv/cpu/ax25/cache.c |
5l2cache";
+ cache-level = <2>;
+ cache-size = <0x4>;
+ reg = <0xe050 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is */
+
From: Rick Chen
Select the v5l2 UCLASS_CACHE driver for ax25.
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
---
arch/riscv/cpu/ax25/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..49be775 100644
From: Rick Chen
Add L2 cache enable and disable ops for test coverage.
Signed-off-by: Rick Chen
Cc: KC Lin
---
drivers/cache/sandbox_cache.c | 13 +
test/dm/cache.c | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen
Cc: KC Lin
From: Rick Chen
The L2 cache will be enabled in init flow of dm cache
driver when it detect L2 node in dtb.
When U-Boot jumps to Linux Kernel, the disable ops will
be called to flush and disable the L2 cache via the dm
cache driver.
Signed-off-by: Rick Chen
Cc: KC Lin
---
drivers/cache/cache
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.
Also implement L2 cache flush and disable before jump
From: Rick Chen
Flush and disable cache in cleanup_before_linux()
which will be called before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen
Cc: Greentime Hu
Cc: KC Lin
---
arch/riscv/cpu/ax25/cpu.c | 26
operation */
+#define CCTL_L1D_WBINVAL_ALL 6
+#endif
void flush_dcache_all(void)
{
- /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-* The implementati
From: Rick Chen
Select the v5l2 UCLASS_CACHE driver for ax25.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Cc: KC Lin
---
arch/riscv/cpu/ax25/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..49be775 100644
--- a
5l2cache";
+ cache-level = <2>;
+ cache-size = <0x4>;
+ reg = <0xe050 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is */
+
From: Rick Chen
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Cc: KC Lin
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen
Cc: Greentime Hu
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.
Also implement L2 cache flush and disable before jump
From: Rick Chen
The L2 cache will be enabled in init flow of dm cache
driver when it detect L2 node in dtb.
When U-Boot jump to Linux Kernel, the disable ops will
be called to flush and disable the L2 cache via the dm
cache driver.
Signed-off-by: Rick Chen
Cc: KC Lin
---
drivers/cache/cache-
From: Rick Chen
Macpaul have left Andestech for a while, and this mail address
macp...@andestech.com can not received mail anymore.
It might encounter account creation problem in this switching
to gitlab about nds32 tree.
So change the nds32 maintainer as Rick Chen
Signed-off-by: Rick Chen
C
*/
+#define CCTL_L1D_WBINVAL_ALL 6
+#endif
void flush_dcache_all(void)
{
- /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-* The implementation of the
From: Rick Chen
Flush and disable cache in cleanup_before_linux()
which will be called before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/cpu/ax25/cpu.c | 4
1 file chan
ot;cache";
+ cache-level = <2>;
+ cache-size = <0x4>;
+ reg = <0xe050 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ // The value format is
+
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen
Cc: Greentime Hu
From: Rick Chen
Select the v5l2 UCLASS_CACHE driver for AE350.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
board/AndesTech/ax25-ae350/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board/AndesTech/ax25-ae350/Kconfig
index 5e682b6..dd299d9 1
From: Rick Chen
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/boar
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.
Also implement L2 cache flush and disable before jump
From: Rick Chen
This patch will fix Travis failure item as below:
https://travis-ci.org/rickchen36/u-boot-riscv/jobs/529605196
Check for configs without MAINTAINERS entry
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
board/AndesTech/ax25-ae350/MAINTAINERS | 2 ++
1 file changed, 2 insertions
From: Rick Chen
When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
2 files changed, 2 insertion
From: Rick Chen
When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of
CONFIG_OF_BOARD.
Also remove unused code about prior_stage_fdt_address.
And modify CONFIG_SYS_FDT_BASE as flash address.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
From: Rick Chen
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
configs/ae350_rv32_xip_defconfig | 37 +
configs/ae350_rv64_xip_defconfig | 38
From: Rick Chen
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.
When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewe
From: Rick Chen
In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was
booting from flash by disab
From: Rick Chen
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen
From: Rick Chen
When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of
CONFIG_OF_BOARD.
Also remove unused code about prior_stage_fdt_address.
And modify CONFIG_SYS_FDT_BASE as flash address.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 4 --
From: Rick Chen
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.
When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/cpu/cpu.c |
From: Rick Chen
When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
2 files changed, 2 insertion
From: Rick Chen
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
configs/ae350_rv32_xip_defconfig | 37 +
configs/ae350_rv64_xip_defconfig | 38
From: Rick Chen
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen
From: Rick Chen
In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was
booting from flash by disab
From: Rick Chen
When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
2 files changed, 2 insertion
From: Rick Chen
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen
From: Rick Chen
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.
When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/cpu/cpu.c
From: Rick Chen
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
configs/ae350_rv32_xip_defconfig | 37 +
configs/ae350_rv64_xip_defconfig | 38
From: Rick Chen
In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was
booting from flash by disab
From: Rick Chen
When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs
From: Rick Chen
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
configs/ae350_rv32_xip_defconfig | 36
configs/ae350_rv64_xip_defconfig | 37 +
2 files changed, 7
From: Rick Chen
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 was booting from flash.
When AE350 was booting from falsh, prior_stage_fdt_address will be in
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv
From: Rick Chen
In smp flow these two features only can be enabled when U-Boot
booting from ram. It shall be disabled when U-Boot booting from
flash.
Add CONFIG_XIP to NOT select this two features. It's default value
will say NO for booting from ram.
AE350 will encounter the the write failure p
From: Rick Chen
In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was
booting from flash by disab
From: Rick Chen
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 was booting from flash.
When AE350 was booting from falsh, prior_stage_fdt_address will be in
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv
From: Rick Chen
When AE350 was booting from ram, use OF_PRIOR_STAGE instead
of OF_PRIOR_STAGE.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/ae350_r
From: Rick Chen
Add two defconfig to support AE350 SMP boot from flash
by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
configs/ae350_rv32_xip_defconfig | 37 +
configs/ae350_rv64_xip_defconfig | 38 ++
From: Rick Chen
In smp flow this two features only can be enabled when U-Boot
boot from ram. It shall be disabled when U-Boot boot from flash.
Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
this two features. Their default value will say YES for booting
from ram.
AE350 will encoun
From: Rick Chen
In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was
booting from flash by disab
From: Rick Chen
It occurs since commit 27cb7300ffda
("Ensure device tree DTS is compiled").
More details can refer to
89c2b5c02049aea746b1edee0b4e1d8519dec2f4
ARM: fix arch/arm/dts/Makefile
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/dts/Makefile | 2 ++
1 file changed, 2 insert
From: Rick Chen
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
board/AndesTech/ax25-ae350/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board/AndesTech/ax25-ae350/Kconfig
index 44cb302..5e682b6 1
From: Rick Chen
Signed-off-by: Rick Chen
Cc: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Lukas Auer
---
arch/riscv/dts/ae350_32.dts | 81 +
arch/riscv/dts/ae350_64.dts | 81 +
2 files changed, 118 ins
5 files changed, 67 insertions(+)
create mode 100644 arch/riscv/lib/andes_plmt.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 511768b..ae8ff7b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config ANDES_PLIC
The Andes PLIC block
ISCV_MMODE
help
Provide Andes Technology AndeStar V5 families specific cache support.
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
+ imply ANDES_PLMT if RISCV_MMODE
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index 5837b48..e13c7de
Add a SYSCON driver for Andestech's PLMT
riscv: ax25: Add platform-specific Kconfig options
riscv: ax25: Andes specific cache shall only support in M-mode
riscv: dts: ae350 support SMP
riscv: ae350: enable SMP
arch/riscv/Kconfig | 18 ++
arch/riscv/cpu/ax
SYSCON
+ help
+ The Andes PLIC block holds memory-mapped claim and pending registers
+ associated with software interrupt.
+
config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
1 - 100 of 275 matches
Mail list logo