Hi Heinrich, hi Bin,
On Tue, 2020-04-14 at 07:08 +0800, Bin Meng wrote:
> Hi Heinrich,
>
> On Tue, Apr 14, 2020 at 7:05 AM Heinrich Schuchardt
> wrote:
> > On 4/6/20 10:44 PM, Atish Patra wrote:
> > > Linux booting protocol mandates that register "a0" contains the hartid.
> > > However, U-boot
Hi Rick,
On Fri, 2019-12-06 at 16:26 +0800, Rick Chen wrote:
> HI Lukas
>
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Wednesday, December 04, 2019 5:40 AM
> > To: u-boot@lists.denx.de
> > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel;
> > An
> > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> > > > > > > > > Hi Anup & Lukas
> > > > > > > > >
> > > > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道：
> > > > >
; On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> > > > > > Hi Anup & Lukas
> > > > > >
> > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道：
> > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Au
Hi Rick,
On Fri, 2019-11-08 at 15:27 +0800, Rick Chen wrote:
> Hi Atish
>
> > Hi Atish
> >
> > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> > > > Hi Anup & Lukas
> > > >
> > > > Anup Patel 於 2019年11月7
On Thu, 2019-11-07 at 17:57 +0530, Anup Patel wrote:
> On Thu, Nov 7, 2019 at 5:14 PM Auer, Lukas
> wrote:
> > On Thu, 2019-11-07 at 16:14 +0530, Anup Patel wrote:
> > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > > wrote:
> > > > On Thu, 2
On Thu, 2019-11-07 at 16:14 +0530, Anup Patel wrote:
> On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> wrote:
> > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote:
> > > > Hi Anup
> > > >
> &g
On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote:
> > Hi Anup
> >
> > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote:
> > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote:
> > > > > Hi Anup
> > > > >
> > > > > > On Wed, Nov 6, 2019 at
Hi Jagan,
On Wed, 2019-10-02 at 15:57 +0530, Jagan Teki wrote:
> On Mon, Sep 30, 2019 at 3:35 PM Bin Meng wrote:
> > Hi Jagan,
> >
> > On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki
> > wrote:
> > > Sync the hifive-unleashed-a00 dts from Linux with
> > > below commit details:
> > > commit 11ae2d89
Hi Jagan,
On Sun, 2019-09-29 at 13:12 +0530, Jagan Teki wrote:
> Sync the hifive-unleashed-a00 dts from Linux with
> below commit details:
> commit 11ae2d892139a1086f257188d457ddcb71ab5257
> Author: Paul Walmsley
> Date: Thu Jul 25 13:41:31 2019 -0700
>
> riscv: dts: fu540-c000: drop "time
Hi Jean-Jacques,
On Fri, 2019-09-20 at 17:28 +0200, Jean-Jacques Hiblot wrote:
> To reduce the complexity of the Makefile, let the generator tell what its
> dependencies are. For this purpose use the "--deps" option.
>
We recently added a generic FIT generator script for RISC-V, located at
arch/
Hi Rick,
On Wed, 2019-08-14 at 20:15 +, Auer, Lukas wrote:
> Hi Rick,
>
> On Wed, 2019-08-14 at 10:20 +0800, Rick Chen wrote:
> > Hi Lukas
> >
> > > > From: Tom Rini [mailto:tr...@konsulko.com]
> > > > Sent: Wednesday, August 14, 2019 1
On Fri, 2019-08-16 at 11:00 -0700, Alistair Francis wrote:
> Add the mmc0 device as a BOOT_TARGET_DEVICES.
>
> Signed-off-by: Alistair Francis
> ---
> include/configs/sifive-fu540.h | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Lukas Auer
_
Hi Rick,
On Wed, 2019-08-14 at 10:20 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Tom Rini [mailto:tr...@konsulko.com]
> > > Sent: Wednesday, August 14, 2019 12:50 AM
> > > To: Open Source Project uboot
> > > Cc: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> > > Subject: Re: [U-Boot] Pull r
Hi Bin,
On Thu, 2019-08-08 at 21:25 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Aug 8, 2019 at 7:22 PM Auer, Lukas
> wrote:
> > Hi Bin,
> >
> > On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote:
> > > We should not count in hart that is marked as no
Hi Bin,
On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote:
> We should not count in hart that is marked as not available in the
> device tree in riscv_cpu_get_count().
>
I think it might make sense to also exclude harts that are not listed
as available in the available_harts mask. So the same lo
On Wed, 2019-08-07 at 23:04 -0700, Bin Meng wrote:
> When 'make qemu-riscv64_defconfig', there is a build warning:
>
> board/emulation/qemu-riscv/Kconfig:24:
> warning: config symbol defined without type
>
> Fix it by specifying the config symbol type to 'hex'.
>
> Signed-off-by: Bin Meng
>
Hi Rick,
On Fri, 2019-08-02 at 14:18 +0530, Anup Patel wrote:
> On Fri, Aug 2, 2019 at 2:11 PM Rick Chen wrote:
> > Hi Lukas
> >
> > > Hi Rick,
> > >
> > > On Thu, 2019-08-01 at 11:32 +0800, Rick Chen wrote:
> > > > Hi Lukas
> > > >
> > > > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunho
Hi Rick,
On Thu, 2019-08-01 at 11:32 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Sunday, July 28, 2019 11:57 PM
> > > To: u-boot@lists.denx.de
> > > Cc: Atish Patra; Rick Jian-Zhi Chen(陳建志); Bin Meng; Sagar Kadam; Alistair
> > >
Hi Anup,
On Mon, 2019-07-29 at 14:14 +0530, Anup Patel wrote:
> On Sun, Jul 28, 2019 at 9:27 PM Lukas Auer
> wrote:
> > This series adds support for SPL to RISC-V U-Boot. Images can be booted
> > via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the
> > former case, OpenSBI and
Hi Anup,
On Mon, 2019-07-29 at 14:02 +0530, Anup Patel wrote:
> On Sun, Jul 28, 2019 at 9:55 PM Lukas Auer
> wrote:
> > RISC-V OpenSBI is an open-source implementation of the RISC-V Supervisor
> > Binary Interface (SBI) specification. It is required by Linux and U-Boot
> > running in supervisor m
Hi Bin,
On Wed, 2019-07-24 at 21:49 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Jul 24, 2019 at 5:23 PM Auer, Lukas
> wrote:
> > Hi Bin,
> >
> > On Wed, 2019-07-24 at 10:55 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> > >
Hi Bin,
On Wed, 2019-07-24 at 10:55 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Jul 24, 2019 at 5:34 AM Auer, Lukas
> wrote:
> > Hi Bin,
> >
> > On Tue, 2019-07-23 at 16:32 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> > >
Hi Bin,
On Tue, 2019-07-23 at 16:32 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Jul 22, 2019 at 2:00 AM Lukas Auer
> wrote:
> > This series adds support for SPL to RISC-V U-Boot. Images can be booted
> > via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the
> > former case,
Hi Bin,
On Thu, 2019-07-18 at 17:01 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Jul 18, 2019 at 4:54 PM Auer, Lukas
> wrote:
> > Hi Bin,
> >
> > On Wed, 2019-07-10 at 23:43 -0700, Bin Meng wrote:
> > > We should prefer accessing CSRs using their
Hi Bin,
On Wed, 2019-07-10 at 23:43 -0700, Bin Meng wrote:
> We should prefer accessing CSRs using their CSR numbers
> because:
> 1. It compiles fine with older toolchains.
> 2. We can use latest CSR names in #define macro names of CSR
>numbers as-per RISC-V spec.
> 3. We can access newly adde
On Wed, 2019-07-10 at 23:43 -0700, Bin Meng wrote:
> This syncs csr.h with Linux kernel 5.2, and imports asm.h that
> is required by csr.h.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/include/asm/asm.h | 68
>
> arch/riscv/include/asm/csr.h | 6
Hi Rick,
On Wed, 2019-06-05 at 17:39 +0800, Bin Meng wrote:
> Hi Rick,
>
> On Wed, Jun 5, 2019 at 5:38 PM Rick Chen wrote:
> > Hi Bin
> >
> > > Hi Rick,
> > >
> > > On Tue, May 28, 2019 at 5:45 PM Andes wrote:
> > > > From: Rick Chen
> > > >
> > > > Use CCTL command to do d-cache write back
Hi Rick,
On Wed, 2019-06-05 at 16:58 +0800, Rick Chen wrote:
> Hi Bin
>
> Bin Meng 於 2019年6月4日 週二 上午10:48寫道：
> > Hi Rick,
> >
> > On Tue, May 28, 2019 at 5:44 PM Andes wrote:
> > > From: Rick Chen
> > >
> > > Add a v5l2 cache controller driver that is usually found on
> > > Andes RISC-V ae35
gt; > > > > > On Jun 2, 2019, at 9:22 PM, Rick Chen wrote:
> > > > > >
> > > > > > Hi Troy
> > > > > >
> > > > > > > > From: Troy Benjegerdes [mailto
On Tue, 2019-05-28 at 15:47 +0530, Padmarao Begari wrote:
> This patch adds Microchip MPFS Icicle board support.
> For now, NS16550 serial driver is only enabled.
> The Microchip MPFS Icicle defconfig by default builds
> U-Boot for M-Mode with SMP support.
>
> Signed-off-by: Padmarao Begari
> Rev
Hi Padmarao,
On Mon, 2019-05-27 at 11:13 +0530, Padmarao Begari wrote:
> Hi Lukas,
>
> On Mon, May 20, 2019 at 5:33 PM Auer, Lukas
> wrote:
> > Hi Padmarao,
> >
> > On Mon, 2019-05-13 at 16:18 +0530, Padmarao Begari wrote:
> > > This patch adds Microch
On Wed, 2019-05-15 at 08:42 -0700, Bin Meng wrote:
> Since we have added the PCI support to the 'virt' target, enable
> e1000 and NVME as alternate network and storage devices for these
> virtio based devices.
>
> Signed-off-by: Bin Meng
> ---
>
> board/emulation/qemu-riscv/Kconfig | 2 ++
> 1
On Wed, 2019-05-15 at 08:42 -0700, Bin Meng wrote:
> QEMU 4.0.0 'virt' target integrates a generic ECAM PCI host.
> Enable the driver for it.
>
> Signed-off-by: Bin Meng
> ---
>
> board/emulation/qemu-riscv/Kconfig | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Lukas Auer
Tested-
On Wed, 2019-05-22 at 00:09 -0700, Bin Meng wrote:
> At present the link speed change callback is a nop. According to
> macb device tree bindings, an optional "tx_clk" is used to clock
> the ethernet controller's TX_CLK under different link speed.
>
> In 10/100 MII mode, transmit logic must be clo
Hi Padmarao,
On Mon, 2019-05-13 at 16:18 +0530, Padmarao Begari wrote:
> This patch adds Microchip MPFS Icicle board support.
> For now, NS16550 serial driver is only enabled.
> The Microchip MPFS Icicle defconfig by default builds
> U-Boot for M-Mode with SMP support.
>
> Signed-off-by: Padmarao
On Thu, 2019-05-16 at 02:12 -0700, Bin Meng wrote:
> Enable the new GEMGXL MGMT driver so that GEM 10/100 Mbps works now.
>
> Signed-off-by: Bin Meng
>
> ---
>
> board/sifive/fu540/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Thanks for the patch series. I tested it successfully on a Si
Hi Bin,
On Thu, 2019-05-16 at 02:12 -0700, Bin Meng wrote:
> At present the link speed change callback is a nop. According to
> macb device tree bindings, an optional "tx_clk" is used to clock
> the ethernet controller's TX_CLK under different link speed.
>
> In 10/100 MII mode, transmit logic mu
Hi Bin,
On Thu, 2019-05-16 at 02:12 -0700, Bin Meng wrote:
> This adds a clock driver to support the GEMGXL management IP block
> found in FU540 SoCs to control GEM TX clock operation mode for
> 10/100/1000 Mbps.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/clk/sifive/Kconfig | 7 +
On Thu, 2019-05-16 at 02:12 -0700, Bin Meng wrote:
> This updates DM version macb_linkspd_cb() signature for future
> expansion, eg: adding an implementation for link speed changes.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/net/macb.c | 22 +-
> 1 file changed, 21 insert
On Wed, 2019-05-15 at 17:25 +0900, takahiro.aka...@linaro.org wrote:
> On Wed, May 15, 2019 at 08:14:18AM +0000, Auer, Lukas wrote:
> > On Wed, 2019-05-15 at 15:39 +0800, Bin Meng wrote:
> > > On Wed, May 15, 2019 at 3:12 PM AKASHI Takahiro
> > > wrote:
> > >
On Wed, 2019-05-15 at 15:39 +0800, Bin Meng wrote:
> On Wed, May 15, 2019 at 3:12 PM AKASHI Takahiro
> wrote:
> > On Wed, May 15, 2019 at 02:45:19PM +0800, Bin Meng wrote:
> > > On Wed, May 15, 2019 at 1:55 PM AKASHI Takahiro
> > > wrote:
> > > > As of v2019.07-rc1,
> > > > u-boot does fail to bo
Hello Heiko,
On Mon, 2019-04-29 at 16:11 +, Auer, Lukas wrote:
> Hello Heiko,
>
> On Mon, 2019-04-29 at 11:40 +0200, Heiko Schocher wrote:
> > Hello Simon,
> >
> > Am 22.04.2019 um 04:38 schrieb s...@google.com:
> > > On Wed, Apr 10, 2019 at 8:46 PM Luk
On Fri, 2019-05-03 at 14:05 -0300, Fabio Estevam wrote:
> Commit 3a7c45f6a772 ("simple-bus: add DM_FLAG_PRE_RELOC flag to
> simple-bus driver") causes some i.MX boards that were converted
> to DM, such as warp7, to fail to boot.
>
> As explained by Lukas Auer:
>
> "With the patch, U-Boot probes t
On Fri, 2019-05-03 at 09:25 -0300, Fabio Estevam wrote:
> Commit 3a7c45f6a772 ("simple-bus: add DM_FLAG_PRE_RELOC flag to
> simple-bus driver") causes some i.MX boards that were converted
> to DM, such as warp7, to fail to boot.
>
> As explained by Lukas Auer:
>
> "With the patch, U-Boot probes t
Hi Fabio,
On Fri, 2019-05-03 at 09:26 -0300, Fabio Estevam wrote:
> Hi Lukas,
>
> On Thu, May 2, 2019 at 1:59 PM Fabio Estevam wrote:
> > Hi Lukas,
> >
> > On Thu, May 2, 2019 at 1:58 PM Auer, Lukas
> > wrote:
> >
> > > Yes, I will send a p
Hi Fabio,
On Thu, 2019-05-02 at 11:08 -0300, Fabio Estevam wrote:
> Hi Lukas,
>
> On Thu, May 2, 2019 at 7:21 AM Auer, Lukas
> wrote:
>
> > I was able to reproduce the issue on my side. With the patch, U-Boot
> > probes the drivers for devices under simple-bus devic
Hi Stefano,
On Thu, 2019-05-02 at 10:55 +0200, Stefano Babic wrote:
> Hi Piere, Lukasz,
>
> On 01/05/19 20:49, Pierre-Jean Texier wrote:
> > Hi Fabio, Stefano,
> >
> > Just FYI, I just tested the U-Boot master branch (with u-boot-imx merges).
> > And I have some problems when the WaRP7 boot-up.
Hi Rick,
On Tue, 2019-04-30 at 13:49 +0800, Andes wrote:
> From: Rick Chen
>
> When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of
> CONFIG_OF_BOARD.
>
> Also remove unused code about prior_stage_fdt_address.
> And modify CONFIG_SYS_FDT_BASE as flash address.
>
> Signed-off-by: Rick
On Tue, 2019-04-30 at 13:49 +0800, Andes wrote:
> From: Rick Chen
>
> This patch will fix prior_stage_fdt_address write failure problem, when
> AE350 boots from flash.
>
> When AE350 boots from flash, prior_stage_fdt_address will be flash
> address, we shall avoid it to be written.
>
> Signed-o
Hello Heiko,
On Mon, 2019-04-29 at 11:40 +0200, Heiko Schocher wrote:
> Hello Simon,
>
> Am 22.04.2019 um 04:38 schrieb s...@google.com:
> > On Wed, Apr 10, 2019 at 8:46 PM Lukas Auer
> > wrote:
> > > Boards such as qemu-riscv, which receive their device tree at runtime,
> > > for example from Q
On Mon, 2019-04-29 at 15:44 +0800, Andes wrote:
> From: Rick Chen
>
> When U-Boot boots from flash, during the boot process,
> hart_lottery and available_harts_lock variable addresses
> point to flash which is not writable. This causes boot
> failures on AE350. Introduce a config option CONFIG_XI
Hi Rick,
On Mon, 2019-04-29 at 15:44 +0800, Andes wrote:
> From: Rick Chen
>
> This patch will fix prior_stage_fdt_address write failure problem, when
> AE350 boots from flash.
>
> When AE350 boots from flash, prior_stage_fdt_address will be flash
> address, we shall avoid it to be written.
>
On Thu, 2019-04-25 at 09:00 +0800, Rick Chen wrote:
> Bin Meng 於 2019年4月24日 週三 下午3:02寫道：
> > On Wed, Apr 24, 2019 at 2:38 PM Andes wrote:
> > > From: Rick Chen
> > >
> > > This patch will fix prior_stage_fdt_address write failure problem, when
> > > AE350 was booting from flash.
> >
> > was ->
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
> From: Rick Chen
>
> When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead
> of CONFIG_OF_BOARD.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> ---
> configs/ae350_rv32_defconfig | 2 +-
> configs/ae350_rv64_defconfig | 2 +-
>
Hi Rick,
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
> From: Rick Chen
>
> This patch will fix prior_stage_fdt_address write failure problem, when
> AE350 was booting from flash.
>
> When AE350 was booting from falsh, prior_stage_fdt_address will be in
nit: should be flash
> flash address
Hi Rick,
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
> From: Rick Chen
>
> Add two defconfigs to support AE350 SMP booting from flash.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> ---
> configs/ae350_rv32_xip_defconfig | 36
> configs/ae350_rv64_
Hi Rick,
Bin already included excellent feedback, I have just one more small nit
below.
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
> From: Rick Chen
>
> In smp flow these two features only can be enabled when U-Boot
> booting from ram. It shall be disabled when U-Boot booting from
> flash.
Hi Rick,
On Thu, 2019-04-25 at 08:55 +0800, Rick Chen wrote:
> Hi Lukas
>
> Auer, Lukas 於 2019年4月25日 週四 上午5:18寫道：
> > Hi Rick,
> >
> > On Wed, 2019-04-24 at 09:35 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > Auer, Lukas 於 2019年4月24日
Hi Rick,
On Wed, 2019-04-24 at 09:35 +0800, Rick Chen wrote:
> Hi Lukas
>
> Auer, Lukas 於 2019年4月24日 週三 上午3:58寫道：
> > Hi Rick,
> >
> > On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > > From: Rick Chen
> > >
> > > In curre
Hi Rick,
On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> From: Rick Chen
>
> In current RISC-V SMP flow, AE350 will encounter the the write
> failure problem since hart_lottery and available_harts_lock was
> not in ram address but in flash address when booing from flash.
>
> This patch can he
On Thu, 2019-04-11 at 14:51 +0200, David Abdurachmanov wrote:
> On Thu, Apr 11, 2019 at 2:41 PM Auer, Lukas
> wrote:
> > + Bin
> >
> > On Tue, 2019-04-09 at 12:42 +0200, David Abdurachmanov wrote:
> > > - Set fdt_addr variable, which is needed for extlinux to fi
On Thu, 2019-04-11 at 15:05 +0200, David Abdurachmanov wrote:
> On Thu, Apr 11, 2019 at 2:40 PM Auer, Lukas
> wrote:
> > + Bin
> > [Please use get_maintainer or patman to include all maintainers on CC]
>
> Thanks.
>
> Hm.. get_maintainer and patman are not mentione
On Thu, 2019-04-11 at 06:52 +, Anup Patel wrote:
> For 32bit system, the OpenSBI (or BBL) will jump to 0x8040 address
> in S-mode whereas for 64bit system it will jump to 0x8020 address
> in S-mode.
>
> Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x8020 for both
> 32bit and
+ Bin
On Tue, 2019-04-09 at 12:42 +0200, David Abdurachmanov wrote:
> - Set fdt_addr variable, which is needed for extlinux to find FDT.
> Otherwise booting kernel using extlinux results in missing FDT.
>
> - Also run fdt addr with FDT address so that fdt commands would
> work out of the box
+ Bin
[Please use get_maintainer or patman to include all maintainers on CC]
On Tue, 2019-04-09 at 12:42 +0200, David Abdurachmanov wrote:
> After updating Fedora/RISCV kernel to 5.1-rc3+ the size increased above
> the current threshold. Looking into HiKey, Dragonboards, etc. seems that
> SZ_64M i
Hi Rick,
On Wed, 2019-04-10 at 17:05 +0800, Rick Chen wrote:
> Hi Bin and Lukas
>
> Bin Meng 於 2019年3月21日 週四 下午5:17寫道：
> > Hi Rick,
> >
> > On Thu, Mar 21, 2019 at 5:00 PM Rick Chen wrote:
> > > Bin Meng 於 2019年3月21日 週四 下午4:49寫道：
> > > > Hi Rick,
> > > >
> > > > On Thu, Mar 21, 2019 at 4:27
On Wed, 2019-04-03 at 10:43 +0800, Andes wrote:
> From: Rick Chen
>
> It occurs since commit 27cb7300ffda
> ("Ensure device tree DTS is compiled").
>
> More details can refer to
> 89c2b5c02049aea746b1edee0b4e1d8519dec2f4
> ARM: fix arch/arm/dts/Makefile
>
> Signed-off-by: Rick Chen
> Cc: Green
On Tue, 2019-04-02 at 15:56 +0800, Andes wrote:
> From: Rick Chen
>
> The platform-Level Machine Timer (PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
>
> This driver implements the riscv_get_time() which
> is required by the generic RISC-V timer driver.
>
> Sign
On Tue, 2019-04-02 at 15:56 +0800, Andes wrote:
> From: Rick Chen
>
> The Platform-Level Interrupt Controller (PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt. It is required
> for handling IPI.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
Hi Rick,
On Tue, 2019-04-02 at 10:12 +0800, Rick Chen wrote:
> Hi Lukas
>
> > Auer, Lukas 於 2019年4月1日 週一 下午5:08寫道：
> >
> > Hi Rick,
> >
> > On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > > From: Rick Chen
> > >
> > > T
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Limit the cache configuration only can be supported in M mode.
> It can not be manipulated in S mode.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> arch/riscv/cpu/ax25/Kconfig | 1 +
> 1 f
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> board/AndesTech/ax25-ae350/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Lukas Auer
___
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Add ax25 RISC-V platform-specific Kconfig options, to include
> CPU and timer drivers.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> arch/riscv/cpu/ax25/Kconfig | 6 ++
> 1 file change
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> ---
> V3:
> - Fix some mis-alignments.
> - Recovery isa string of CPU1.
>
> arch/riscv/dts/ae350_32.dts | 81
> +
> arch/riscv/dts
Hi Rick,
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> The Platform-Level Interrupt Controller (PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt. It is required
> for handling IPI.
>
> Signed-off-by: Rick Chen
> Cc: Gree
Hi Rick,
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> The platform-Level Machine Timer (PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
>
> This driver implements the riscv_get_time() which
> is required by the generic RISC-V timer driver.
Hi Rick,
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Disable ATCPIT100 SoC timer and replace by PLMT.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> configs/ae350_rv32_defconfig | 1 -
> configs/ae350_rv64_defconfig | 1 -
> 2 files
On Wed, 2019-03-20 at 05:37 -0700, Palmer Dabbelt wrote:
> On Sun, 17 Mar 2019 11:28:31 PDT (-0700),
> lukas.a...@aisec.fraunhofer.de wrote:
> > This patch series adds SMP support for RISC-V to U-Boot. It allows
> > U-Boot to run on multi-hart systems (hart is the RISC-V terminology
> > for
> > ha
Hi Rick,
On Tue, 2019-03-12 at 09:15 +0800, Rick Chen wrote:
> Hi Lukas
>
> Auer, Lukas 於 2019年3月11日 週一
> 上午2:12寫道：
> > On Sun, 2019-03-10 at 20:24 +0530, Anup Patel wrote:
> > > On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas
> > > wrote:
> > > > Hi
On Sun, 2019-03-10 at 20:24 +0530, Anup Patel wrote:
> On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas
> wrote:
> > Hi Rick,
> >
> > On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > > From: Lukas Auer [mailt
On Wed, 2019-03-06 at 19:20 -0800, Atish Patra wrote:
> On 3/5/19 2:54 PM, Lukas Auer wrote:
> > Harts on RISC-V boot independently, U-Boot is responsible for
> > managing
> > them. Functions are called on other harts with smp_call_function(),
> > which sends inter-processor interrupts (IPIs) to al
Hi Rick,
On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Tuesday, February 12, 2019 6:14 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer
> > > Dabbelt;
On Sun, 2019-03-10 at 21:01 +0800, Bin Meng wrote:
> On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer
> wrote:
> > On RISC-V, all harts boot independently. To be able to run on a
> > multi-hart system, U-Boot must be extended with the functionality
> > to
> > manage all harts in the system. All harts ent
On Wed, 2019-03-06 at 10:07 +, Anup Patel wrote:
> > -Original Message-
> > From: Auer, Lukas
> > Sent: Wednesday, March 6, 2019 2:52 PM
> > To: u-boot@lists.denx.de; Anup Patel
> > Cc: paul.walms...@sifive.com; ag...@suse.de; a...@brainfa
> > > > > From: Andreas Schwab
> > > > > Sent: Wednesday, March 6, 2019 4:27 PM
> > > > > To: Anup Patel
> > > > > Cc: Auer, Lukas ;
> > > > > u-boot@lists.denx.de;
> > > > > paul.walms...@sifive.c
On Wed, 2019-03-06 at 04:00 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer
> > Sent: Wednesday, March 6, 2019 4:23 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer Dabbelt ;
> > Alexander Graf ; Lukas Auer
>
On Tue, 2019-02-19 at 13:46 +0530, Anup Patel wrote:
> On Mon, Feb 18, 2019 at 5:11 PM Auer, Lukas
> wrote:
> > On Mon, 2019-02-18 at 10:01 +, Auer, Lukas wrote:
> > > On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> > > > On Tue, Feb 12, 2019 at
On Mon, 2019-02-18 at 18:46 +0530, Anup Patel wrote:
> On Mon, Feb 18, 2019 at 5:11 PM Auer, Lukas
> wrote:
> > On Mon, 2019-02-18 at 10:01 +, Auer, Lukas wrote:
> > > On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> > > > On Tue, Feb 12, 2019 at
On Mon, 2019-02-18 at 10:01 +, Auer, Lukas wrote:
> On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> > On Tue, Feb 12, 2019 at 3:44 AM Lukas Auer
> > wrote:
> > > Harts on RISC-V boot independently and U-Boot is responsible for
> > > managing them. Fu
On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> On Tue, Feb 12, 2019 at 3:44 AM Lukas Auer
> wrote:
> > Harts on RISC-V boot independently and U-Boot is responsible for
> > managing them. Functions are called on other harts with
> > smp_call_function(), which sends inter-processor interrupt
On Mon, 2019-02-18 at 09:10 +0530, Anup Patel wrote:
> On Mon, Feb 18, 2019 at 8:53 AM Rick Chen
> wrote:
> > 於 2019年2月18日 週一 上午11:00寫道：
> > >
> > >
> > > > -----Original Message-
> > > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraun
On Tue, 2019-02-12 at 05:05 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 4:12 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer Da
Hi Rick,
On Fri, 2019-02-15 at 14:51 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Tuesday, February 12, 2019 6:14 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer
> > > Dabbelt;
On Tue, 2019-02-12 at 01:48 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 3:44 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer Da
Hi Bin,
On Tue, 2019-02-12 at 11:03 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Feb 12, 2019 at 6:14 AM Lukas Auer
> wrote:
> > Harts on RISC-V boot independently and U-Boot is responsible for
> > managing them. Functions are called on other harts with
> > smp_call_function(), which sends int
On Tue, 2019-02-12 at 01:44 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 3:44 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer Da
On Wed, 2019-02-13 at 01:31 +, Atish Patra wrote:
> > On Feb 12, 2019, at 4:18 PM, Kevin Hilman
> > wrote:
> >
> > Anup Patel writes:
> >
> > > From: Atish Patra
> > >
> > > The readme guide describes the procedure to build, flash and boot
> > > Linux
> > > using U-Boot on HiFive Unleashe
On Wed, 2019-02-13 at 10:35 +0100, Andreas Schwab wrote:
> On Feb 13 2019, Anup Patel wrote:
>
> > General practice (atlease what I have seen on few boards), is that
> > board
> > will have unique MAC address printed/labelled for each Ethernet
> > port. We
> > can just set-and-save "ethaddr" U-Bo
On Mon, 2019-02-11 at 23:16 +0100, Philipp Tomsich wrote:
> On 11.02.2019, at 23:13, Lukas Auer
> wrote:
> > This patch series adds SMP support for RISC-V to U-Boot. It allows
> > U-Boot to run on multi-hart systems and will boot images passed to
> > bootm
> > on all harts. The bootm command is cu
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