On Mon, 2019-03-11 at 22:35 +0100, Simon Goldschmidt wrote:
> Instead of fixing the SPL stack to 64 KiB in the board config header
> via
> CONFIG_SYS_SPL_MALLOC_SIZE, let's just use
> CONFIG_SPL_SYS_MALLOC_F_LEN
> in the defconfig.
>
> This also has the advandage that it removes sub-mach specific
On Sun, 2019-03-10 at 15:51 -0600, Simon Glass wrote:
> Hi Tien Fong,
>
> On Tue, 26 Feb 2019 at 05:37, Chee, Tien Fong om> wrote:
> >
> >
> > On Fri, 2019-02-15 at 14:35 +0800, tien.fong.c...@intel.com wrote:
> > >
> > > From: Tien F
On Thu, 2019-03-07 at 09:33 -0600, Dinh Nguyen wrote:
>
> On 3/7/19 2:24 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-03-05 at 22:52 -0600, Dinh Nguyen wrote:
> > >
> > >
> > > On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
&
On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote:
> The Kconfig checked for SoCFPGA Arria10 as a platform, instead of
> checking for specific board configuration, which works with one
> single platform in tree, but not with multiple. Fix it.
>
> Signed-off-by: Marek Vasut
> Cc: Chin Liang
On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote:
> This is not used anywhere, so drop it.
>
> Signed-off-by: Marek Vasut
> Cc: Chin Liang See
> Cc: Dinh Nguyen
> Cc: Simon Goldschmidt
> Cc: Tien Fong Chee
Reviewed-by: Tien Fong Chee
> ---
> include/configs/socfpga_common.h | 1 -
>
On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote:
> The bootrom seems to leave the D-cache in messed up state, make sure
> the SPL disables it so it can not interfere with operation.
>
> Signed-off-by: Marek Vasut
> Cc: Chin Liang See
> Cc: Dinh Nguyen
> Cc: Simon Goldschmidt
> Cc: Tien
On Thu, 2019-03-07 at 09:13 +0100, Simon Goldschmidt wrote:
> On Wed, Mar 6, 2019 at 10:05 PM Marek Vasut wrote:
> >
> >
> > The debug print is missing a newline, add it.
> >
> > Signed-off-by: Marek Vasut
> > Cc: Chin Liang See
> > Cc: Dinh Nguyen
> > Cc: Simon Goldschmidt
> > Cc: Tien
On Thu, 2019-03-07 at 09:14 +0100, Simon Goldschmidt wrote:
> On Wed, Mar 6, 2019 at 10:05 PM Marek Vasut wrote:
> >
> >
> > The Altera Arria10 DDR driver was using constants in a few places
> > instead of reading registers associated with those constants, fix
> > this.
> >
> > Signed-off-by:
On Thu, 2019-03-07 at 09:38 +0100, Marek Vasut wrote:
> On 3/7/19 9:30 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-03-07 at 09:18 +0100, Marek Vasut wrote:
> > >
> > > On 3/7/19 8:51 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-03-07 at 09:10 +0100, Simon Goldschmidt wrote:
> On Thu, Mar 7, 2019 at 8:08 AM Chee, Tien Fong com> wrote:
> >
> >
> > On Tue, 2019-03-05 at 21:05 +0100, Simon Goldschmidt wrote:
> > >
> > > Am 05.03.2019 um 17:23 schrieb tien.fong.c...
On Thu, 2019-03-07 at 09:18 +0100, Marek Vasut wrote:
> On 3/7/19 8:51 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
> > >
> > > Curious, you sent out 3 versions(2x v10, and v11) within ~2
> > > hours.
> &
On Tue, 2019-03-05 at 22:52 -0600, Dinh Nguyen wrote:
>
> On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > After some series of patches to maximise reusable of memory pool,
> > here come
> > to result of reasonable size required for whole SDMMC boot
On Tue, 2019-03-05 at 22:54 -0600, Dinh Nguyen wrote:
>
> On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Update the default configuration file to enable the necessary
> > functionality
> > the get the kit working.
> >
> > Signed-off-by: Tien Fong Chee
On Tue, 2019-03-05 at 22:11 -0600, Dinh Nguyen wrote:
>
> On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Update the default configuration file to enable the necessary
> > functionality
> > to get the SoCFPGA loadfs driver support. This would enable the
On Tue, 2019-03-05 at 22:35 -0600, Dinh Nguyen wrote:
> It looks like this patch was not in the previous 9 versions of this
> series? Please try to not add new functionality to a series that is
> already gone through so many reviews. It make reviewing the series
> really confusing!
This is split
On Tue, 2019-03-05 at 22:31 -0600, Dinh Nguyen wrote:
>
> On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Ensure the comment and debug messages are always consistent with
> > the rest.
> The rest of what? This patch seems unnecessary to me.
This patch
On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
> Curious, you sent out 3 versions(2x v10, and v11) within ~2 hours.
> What
> versions should we be reviewing?
2nd version of v10 was resent quickly after request from Dalon to
change the node names. I have comment on the 1st version v10 cover
On Tue, 2019-03-05 at 21:05 +0100, Simon Goldschmidt wrote:
> Am 05.03.2019 um 17:23 schrieb tien.fong.c...@intel.com:
> >
> > From: Tien Fong Chee
> >
> > After some series of patches to maximise reusable of memory pool,
> > here come
> > to result of reasonable size required for whole SDMMC
On Tue, 2019-03-05 at 21:05 +0100, Simon Goldschmidt wrote:
> Am 05.03.2019 um 17:23 schrieb tien.fong.c...@intel.com:
> >
> > From: Tien Fong Chee
> >
> > After some series of patches to maximise reusable of memory pool,
> > here come
> > to result of reasonable size required for whole SDMMC
On Tue, 2019-03-05 at 16:54 +0100, Marek Vasut wrote:
> On 3/5/19 4:53 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This version mainly resolved some comments from Simek in [v9].
> >
> > This series is working on top of u-boot.git http://git.denx.de/u-bo
> > ot.git
On Tue, 2019-03-05 at 23:19 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This version mainly resolved some comments from Simek in [v9].
>
> This series is working on top of u-boot.git http://git.denx.de/u-boot
> .git
>
> These patches are required before applying this
On Wed, 2019-02-27 at 10:13 +0100, Michal Simek wrote:
> On 27. 02. 19 7:37, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-26 at 07:58 -0800, Dalon L Westergreen wrote:
> > >
> > > On Tue, 2019-02-26 at 16:42 +0100, Michal Simek wrote:
> > > >
>
On Tue, 2019-02-26 at 07:58 -0800, Dalon L Westergreen wrote:
> On Tue, 2019-02-26 at 16:42 +0100, Michal Simek wrote:
> >
> > On 26. 02. 19 15:28, Chee, Tien Fong wrote:
> > >
> > > On Tue, 2019-02-26 at 15:06 +0100, Michal Simek wrote:
> > >
On Tue, 2019-02-26 at 16:46 +0100, Michal Simek wrote:
> On 26. 02. 19 15:53, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-26 at 15:20 +0100, Michal Simek wrote:
> > >
> > > On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Tue, 2019-02-26 at 16:46 +0100, Michal Simek wrote:
> On 26. 02. 19 15:53, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-26 at 15:20 +0100, Michal Simek wrote:
> > >
> > > On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Tue, 2019-02-26 at 16:43 +0100, Michal Simek wrote:
> On 26. 02. 19 15:30, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
> > >
> > > On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Tue, 2019-02-26 at 15:20 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> >
On Tue, 2019-02-26 at 15:20 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> >
On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v8
> > -
On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v8
> > -
On Tue, 2019-02-26 at 15:06 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This patch adds description on properties about file name used for
> > both
> > peripheral bitstream and core bitstream.
> >
> > Signed-off-by: Tien
On Fri, 2019-02-15 at 14:35 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> In previously label which will be expanded to the node's full path
> was
> used, and now replacing label with most commonly used DT phandle. The
> codes were changed accordingly to the use of DT phandle
On Tue, 2019-02-19 at 11:47 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This version mainly resolved comments from Marek in [v8].
>
> This series is working on top of u-boot.git - http://git.denx.de/u-b
> oot.git .
>
> These patches are required before applying this
On Fri, 2019-02-22 at 10:16 +0100, Michal Simek wrote:
> On 22. 02. 19 4:49, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-21 at 22:22 -0500, Tom Rini wrote:
> > >
> > > On Thu, Feb 21, 2019 at 08:45:37AM +0100, Michal Simek wrote:
> > > >
> &
On Thu, 2019-02-21 at 22:22 -0500, Tom Rini wrote:
> On Thu, Feb 21, 2019 at 08:45:37AM +0100, Michal Simek wrote:
> >
> > Hi Tom,
> >
> > On 20. 02. 19 2:58, Tom Rini wrote:
> > >
> > > On Mon, Feb 11, 2019 at 02:56:19PM +0800, tien.fong.c...@intel.co
> > > m wrote:
> > >
> > > >
> > > >
On Thu, 2019-02-21 at 09:29 +0100, Alexander Graf wrote:
>
> On 21.02.19 09:23, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-21 at 08:45 +0100, Michal Simek wrote:
> > >
> > > Hi Tom,
> > >
> > > On 20. 02. 19 2:58, Tom Rini wrote:
> &
On Thu, 2019-02-21 at 08:45 +0100, Michal Simek wrote:
> Hi Tom,
>
> On 20. 02. 19 2:58, Tom Rini wrote:
> >
> > On Mon, Feb 11, 2019 at 02:56:19PM +0800, tien.fong.c...@intel.com
> > wrote:
> >
> > >
> > > From: Tien Fong Chee
> > >
> > > Drop the statically allocated
On Mon, 2019-02-18 at 13:27 +0100, Michal Simek wrote:
> On 15. 02. 19 8:57, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Ensure the string for filename is always constant, otherwise it can
> > be
> > corrupted by the writing.
> Have you reach any issue with it?
Just to
On Thu, 2019-02-14 at 17:26 +0100, Marek Vasut wrote:
> On 2/14/19 4:47 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 17:26 +0100, Marek Vasut wrote:
> On 2/14/19 4:47 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 17:27 +0100, Marek Vasut wrote:
> On 2/14/19 4:37 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 16:21 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 4:15 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 16:33 +, Westergreen, Dalon wrote:
> On Thu, 2019-02-14 at 15:15 +0000, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> > > >
>
On Thu, 2019-02-14 at 16:33 +, Westergreen, Dalon wrote:
> On Thu, 2019-02-14 at 15:15 +0000, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> > > >
>
On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 16:21 +0100, Marek Vasut wrote:
> On 2/14/19 4:15 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 16:15 +0100, Marek Vasut wrote:
> On 2/14/19 4:14 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:42 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:50 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
> On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> On 2/14/19 12:51 PM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:11 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > >
On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
> On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Wed, 2019-02-13 at 17:11 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Adding some function declarations to the header file, so these
> > functions can be referred by other C files.
> >
> > Signed-off-by: Tien Fong Chee
On Thu, 2019-02-14 at 11:42 +0100, Marek Vasut wrote:
> On 2/14/19 7:50 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:25 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
> On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
> > > >
> > > >
On Thu, 2019-02-14 at 11:34 +0100, Marek Vasut wrote:
> On 2/14/19 6:55 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:07 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > >
On Wed, 2019-02-13 at 17:25 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add support for loading FPGA bitstream to get DDR up running before
> > U-Boot is loaded into DDR. Boot device initialization, generic
> > firmware
>
On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> >
On Wed, 2019-02-13 at 17:11 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Adding some function declarations to the header file, so these
> > functions can be referred by other C files.
> >
> > Signed-off-by: Tien Fong Chee
On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
> On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
> >
> > On Wed, 2019-02-13 at 17:10 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add
On Wed, 2019-02-13 at 17:07 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This patch adds description on properties about file name used for
> > both
> > peripheral bitstream and core bitstream.
> >
> > Signed-off-by: Tien
On Wed, 2019-02-13 at 13:00 +0100, Marek Vasut wrote:
> On 2/13/19 9:22 AM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 5:04 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> On 2/1/19 5:04 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-31 at 15:55 +0100, Marek Vasut wrote:
> > >
> > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Tue, 2019-02-12 at 05:49 -0800, Dalon L Westergreen wrote:
> On Tue, 2019-02-12 at 11:17 +0100, Marek Vasut wrote:
> >
> > On 2/12/19 11:13 AM, Chee, Tien Fong wrote:
> > >
> > > On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> > > >
>
On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
> [...]
>
> >
> > >
> > > my preference for the fit image would be
> > >
> > > ...
> > > images {
> > > fpga@1 {
> &g
On Mon, 2019-02-11 at 17:19 +, Westergreen, Dalon wrote:
> On Tue, 2019-02-12 at 01:01 +0800, Chee, Tien Fong wrote:
> >
> > On Mon, 2019-02-11 at 12:01 +0100, Marek Vasut wrote:
> > >
> > > On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> > > >
>
On Mon, 2019-02-11 at 12:01 +0100, Marek Vasut wrote:
> On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Mon, 2019-02-11 at 12:06 +0100, Marek Vasut wrote:
> On 2/11/19 7:23 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-05 at 09:51 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Tue, 2019-02-05 at 09:41 +0100, Marek Vasut wrote:
> On 2/2/19 4:27 AM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 12:12 -0800, Dalon L Westergreen wrote:
> > >
> > > On Thu, 2019-01-31 at 22:51 +0800, tien.fong.c...@intel.com
> > > wrote:
On Fri, 2019-02-01 at 23:06 -0700, Simon Glass wrote:
On Thu, 31 Jan 2019 at 04:34,
mailto:tien.fong.c...@intel.com>> wrote:
>
> From: Tien Fong Chee
> mailto:tien.fong.c...@intel.com>>
>
> Firmware loader would encounter problem if the block device is accessed
> before initializing it. This
On Tue, 2019-02-05 at 09:51 +0100, Marek Vasut wrote:
> On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Fri, 2019-02-01 at 12:12 -0800, Dalon L Westergreen wrote:
> On Thu, 2019-01-31 at 22:51 +0800, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on
On Fri, 2019-02-01 at 12:29 -0800, Dalon L Westergreen wrote:
> On Fri, 2019-02-01 at 12:02 -0800, Dalon L Westergreen wrote:
> >
> > On Sat, 2019-02-02 at 00:02 +0800, Chee, Tien Fong wrote:
> > >
> > > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
&
On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> On 2/1/19 5:04 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-31 at 15:55 +0100, Marek Vasut wrote:
> > >
> > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > >
> > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > >
> > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > >
On Fri, 2019-02-01 at 09:19 +0100, Marek Vasut wrote:
> On 2/1/19 9:11 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-31 at 15:22 +0100, Marek Vasut wrote:
> > >
> > > On 1/31/19 1:42 PM, tien.fong.c...@intel.com wrote:
> > > >
> > >
On Thu, 2019-01-31 at 15:22 +0100, Marek Vasut wrote:
> On 1/31/19 1:42 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Drop the statically allocated get_contents_vfatname_block and
> > dynamically allocate a buffer only if required. This saves
> > 64KiB of memory.
> >
On Thu, 2019-01-31 at 15:58 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > After some series of patches to maximise reusable of memory pool,
> > here come
> > to result of reasonable size required for whole SDMMC boot working
On Thu, 2019-01-31 at 15:57 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Update the default configuration file to enable the necessary
> > functionality
> > to get the SoCFPGA loadfs driver support. This would enable the
>
On Thu, 2019-01-31 at 15:55 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> >
On Thu, 2019-01-31 at 15:23 +0100, Marek Vasut wrote:
> On 1/31/19 1:42 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Release cluster block immediately when no longer use would help to
> > reduce
> > 64KiB memory allocated to the memory pool.
> >
> > Signed-off-by:
On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> >
On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This patch adds description on properties about file name used for
> > both
> > peripheral bitstream and core bitstream.
> >
> > Signed-off-by: Tien
On Thu, 2019-01-31 at 03:04 -0700, Simon Glass wrote:
> Hi,
>
> On Thu, 24 Jan 2019 at 03:24, wrote:
> >
> >
> > From: Tien Fong Chee
> >
> > Firmware loader would encounter problem if the block device is
> > accessed
> > before initializing it. This patch would adding the support of
> >
On Fri, 2019-01-18 at 07:23 +0100, Marek Vasut wrote:
> On 1/17/19 7:57 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This is minimum memory pool size required to get SPL booting to U-
> > Boot,
> > such as FPGA program and loading U-Boot image from FAT.
> Rather,
On Thu, 2019-01-17 at 14:52 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Release cluster block immediately when no longer use would help to
> reduce
> 64KiB memory allocated to the memory pool.
>
> Signed-off-by: Tien Fong Chee
> ---
> fs/fat/fat.c | 11 +--
> 1
On Fri, 2019-01-18 at 07:26 +0100, Marek Vasut wrote:
> On 1/17/19 7:52 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Stefan Agner
> >
> > Drop the statically allocated get_contents_vfatname_block and
> > dynamically allocate a buffer only if required. This saves
> > 64KiB of memory.
> >
>
On Thu, 2019-01-17 at 07:23 -0500, Tom Rini wrote:
> On Thu, Jan 17, 2019 at 03:01:49PM +0800, tien.fong.c...@intel.com
> wrote:
>
> >
> > From: Tien Fong Chee
> >
> > CONFIG_SPL_EXT_SUPPORT can be used to include/exclude the FS EXT4
> > from
> > SPL build. Excluding the FS EXT4 from SPL build
On Thu, 2019-01-17 at 07:25 -0500, Tom Rini wrote:
> On Thu, Jan 17, 2019 at 08:54:48AM +0100, Simon Goldschmidt wrote:
> >
> > On Thu, Jan 17, 2019 at 8:10 AM wrote:
> > >
> > >
> > > From: Tien Fong Chee
> > >
> > > Most of the time SPL only needs very simple FAT reading, so
> > > having
>
On Thu, 2019-01-03 at 21:15 +0100, Marek Vasut wrote:
> On 1/3/19 6:36 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-01-01 at 21:29 +0100, Marek Vasut wrote:
> > >
> > > On 1/1/19 4:32 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Wed, 2019-01-09 at 09:19 -0700, Simon Glass wrote:
> Hi Tien Fong,
>
> On Sat, 29 Dec 2018 at 18:36, wrote:
> >
> >
> > From: Tien Fong Chee
> >
> > Firmware loader would encounter problem if the MMC is accessed
> > before
> > initializing it. This patch would adding the support of
On Fri, 2019-01-04 at 03:24 +0100, Marek Vasut wrote:
> On 1/4/19 3:22 AM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-01-04 at 03:10 +0100, Marek Vasut wrote:
> > >
> > > On 1/4/
On Fri, 2019-01-04 at 03:10 +0100, Marek Vasut wrote:
> On 1/4/19 1:46 AM, Chee, Tien Fong wrote:
> [...]
>
> >
> > >
> > > >
> > > > 2. What you means with partial loading? partial loading for
> > > > periph.rbf
> > > > o
On Thu, 2019-01-03 at 21:14 +0100, Marek Vasut wrote:
> On 1/3/19 8:28 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-03 at 06:27 +0100, Marek Vasut wrote:
> > >
> > > On 1/3/19 6:07 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-01-03 at 21:15 +0100, Marek Vasut wrote:
> On 1/3/19 6:36 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-01-01 at 21:29 +0100, Marek Vasut wrote:
> > >
> > > On 1/1/19 4:32 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Thu, 2019-01-03 at 06:27 +0100, Marek Vasut wrote:
> On 1/3/19 6:07 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-01-01 at 21:27 +0100, Marek Vasut wrote:
> > >
> > > On 1/1/19 4:10 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Sun, 2018-12-30 at 09:36 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Firmware loader would encounter problem if the MMC is accessed before
> initializing it. This patch would adding the support of probing block
> device and initializing MMC before the MMC is accessed by
On Thu, 2019-01-03 at 06:27 +0100, Marek Vasut wrote:
> On 1/3/19 6:07 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-01-01 at 21:27 +0100, Marek Vasut wrote:
> > >
> > > On 1/1/19 4:10 AM, Chee, Tien Fong wrote:
> > > >
> > > >
>
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