Re: [U-Boot] [PATCH] ARM SOCFPGA: add resetmgr command so reset can be deasserted in bootcmd (for example on peripheral dma interfaces after fpga has been programmed).
Marek Vasut wrote: > Please always CC the list. Do NOT top-post. You do realize I was replying to an email you sent to my personal address and you didn't even send to the list? > What is your goal here ? To put things in context, my larger goal is to update u-boot from the old version altera integrates into Quartus to a reasonably recent version of mainline u-boot being provided by the distro we are using. My naive hope was the new version of u-boot would work at least as well as the old altera one. Experience so far: infinite reboot loop due to broken cadence driver: https://lists.denx.de/pipermail/u-boot/2017-December/313470.html No response except from author responsible for breaking the driver insisting his changes be kept. And now: DMA peripheral requests for FPGA are non-functional due to mainline u-boot ignoring the reset_config.h in the handoff files generated by Quartus. Apparently, the mainline uboot position is that it is inappropriate to provide any more support for initializing the resets than providing the ability to write to memory addresses with "mw". > > Going back to my initial question -- what is your usecase and your aim > here ? Usually you use FPGA manager in Linux to load the FPGA. > >> > >> But you can really just do mw to the correct address or create a U-Boot > >> script , so this command is not really needed, is it ? > Ok, I am running Linux on the board. I don't see how it would help to load the FPGA from Linux rather than u-boot. The dma peripheral requests would still be just as disabled. The only difference would be that I would be forced to deassert the resets from Linux rather than u-boot, which I guess would make it not your problem? In principle, the fpga manager provides a write_complete hook that the socfpga fpga manager could use to deassert resets (perhaps based on device tree settings), but looking at my 4.1.33 fpga/ socfpga.c it doesn't seem to. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM SOCFPGA: add resetmgr command so reset can be deasserted in bootcmd (for example on peripheral dma interfaces after fpga has been programmed).
---
arch/arm/mach-socfpga/reset_manager_gen5.c | 31 +
+
1 file changed, 31 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-
socfpga/reset_manager_gen5.c
index aa88adb414..6ad5d2a362 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -114,3 +114,34 @@ void socfpga_bridges_reset(int enable)
return;
}
#endif
+
+int resetmgr_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long bank;
+ unsigned long offset;
+ unsigned long assert;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ bank = simple_strtoul(argv[1], NULL, 0);
+ offset = simple_strtoul(argv[2], NULL, 0);
+ assert = simple_strtoul(argv[3], NULL, 0);
+ socfpga_per_reset(RSTMGR_DEFINE(bank, offset), assert);
+ return 0;
+}
+
+U_BOOT_CMD(
+ resetmgr, 4, 1, resetmgr_cmd,
+ "SoCFPGA HPS reset manager control",
+ "resetmgr bank offset assert\n"
+ "bank - Bank of reset to assert/deassert.\n"
+ "0 ... mpumodrst\n"
+ "1 ... permodrst\n"
+ "2 ... per2modrst\n"
+ "3 ... brgmodrst\n"
+ "4 ... miscmodrst\n"
+ "offset - Offset of reset to assert/deassert.\n"
+ "assert - 1 to assert reset, 0 to deassert.\n"
+ ""
+);
--
2.11.0
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[U-Boot] [PATCH] ARM SOCFPGA: add resetmgr command so reset can be deasserted in bootcmd (for example on peripheral dma interfaces after fpga has been programmed).
---
arch/arm/mach-socfpga/reset_manager_gen5.c | 31 ++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index aa88adb414..6ad5d2a362 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -114,3 +114,34 @@ void socfpga_bridges_reset(int enable)
return;
}
#endif
+
+int resetmgr_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long bank;
+ unsigned long offset;
+ unsigned long assert;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ bank = simple_strtoul(argv[1], NULL, 0);
+ offset = simple_strtoul(argv[2], NULL, 0);
+ assert = simple_strtoul(argv[3], NULL, 0);
+ socfpga_per_reset(RSTMGR_DEFINE(bank, offset), assert);
+ return 0;
+}
+
+U_BOOT_CMD(
+ resetmgr, 4, 1, resetmgr_cmd,
+ "SoCFPGA HPS reset manager control",
+ "resetmgr bank offset assert\n"
+ "bank - Bank of reset to assert/deassert.\n"
+ "0 ... mpumodrst\n"
+ "1 ... permodrst\n"
+ "2 ... per2modrst\n"
+ "3 ... brgmodrst\n"
+ "4 ... miscmodrst\n"
+ "offset - Offset of reset to assert/deassert.\n"
+ "assert - 1 to assert reset, 0 to deassert.\n"
+ ""
+);
--
2.11.0
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[U-Boot] tiny printf limits
Shouldn't tiny printf abort or something when it encounters a printf format string it doesn't support? Right now, it just silently skips it while leaving the associated argument in place, resulting in the arguments getting shifted onto the wrong format strings. -- Frank ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
Since your commit broke my platform to fix yours, shouldn't it be reverted and TI platforms use your pending patch queue? On Dec 3, 2017 23:14, "Vignesh R" <vigne...@ti.com> wrote: On Sunday 03 December 2017 09:29 PM, Frank Mori Hess wrote: > This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1. > > My u-boot spl crashes in a loop when I boot off a > cadence qspi flash. I narrowed it down to the changes from commit > dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes > CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to > successfully load the main u-boot. My board is an Altera HPS cyclone > V socfpga. It has an ahb base address of 0xffa0 and for some > reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots > when cadence_qspi_apb_indirect_read_execute tries to read from the ahb > base address. I'm was using version 2016.11 of u-boot. This breaks TI platforms where INDIRECTTRIGGER_ADDR is 32bit wide. Instead please try this patch series which adds cdns,trigger-address DT property: http://patchwork.ozlabs.org/patch/838589/ Regards Vignesh > > Signed-off-by: Frank Mori Hess <fmh...@gmail.com> > --- > drivers/spi/cadence_qspi_apb.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb .c > index e02f2217f4..b300f36607 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -47,6 +47,7 @@ > #define CQSPI_INST_TYPE_QUAD 2 > > #define CQSPI_STIG_DATA_LEN_MAX 8 > +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xF > > #define CQSPI_DUMMY_CLKS_PER_BYTE8 > #define CQSPI_DUMMY_BYTES_MAX4 > @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, > addr_bytes = cmdlen - 1; > > /* Setup the indirect trigger address */ > - writel((u32)plat->ahbbase, > + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), > plat->regbase + CQSPI_REG_INDIRECTTRIGGER); > > /* Configure the opcode */ > @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, > return -EINVAL; > } > /* Setup the indirect trigger address */ > - writel((u32)plat->ahbbase, > + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), > plat->regbase + CQSPI_REG_INDIRECTTRIGGER); > > /* Configure the opcode */ > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1. Signed-off-by: Frank Mori Hess <fmh...@gmail.com> --- drivers/spi/cadence_qspi_apb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e02f2217f4..b300f36607 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -47,6 +47,7 @@ #define CQSPI_INST_TYPE_QUAD 2 #define CQSPI_STIG_DATA_LEN_MAX8 +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK0xF #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
Oops, ignore that patch I didn't merge it correctly On Sun, Dec 3, 2017 at 10:36 AM, Frank Mori Hess <fmh...@gmail.com> wrote: > This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1. > > Signed-off-by: Frank Mori Hess <fmh...@gmail.com> > --- > drivers/spi/cadence_qspi_apb.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c > index e02f2217f4..b300f36607 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -47,6 +47,7 @@ > #define CQSPI_INST_TYPE_QUAD 2 > > #define CQSPI_STIG_DATA_LEN_MAX8 > +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK0xF > > #define CQSPI_DUMMY_CLKS_PER_BYTE 8 > #define CQSPI_DUMMY_BYTES_MAX 4 > @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct > cadence_spi_platdata *plat, > addr_bytes = cmdlen - 1; > > /* Setup the indirect trigger address */ > - writel((u32)plat->ahbbase, > + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), >plat->regbase + CQSPI_REG_INDIRECTTRIGGER); > > /* Configure the opcode */ > @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct > cadence_spi_platdata *plat, > return -EINVAL; > } > /* Setup the indirect trigger address */ > - writel((u32)plat->ahbbase, > + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), >plat->regbase + CQSPI_REG_INDIRECTTRIGGER); > > /* Configure the opcode */ > -- > 2.11.0 > > -- Frank ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
On Sun, Dec 3, 2017 at 10:49 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Sun, Dec 3, 2017 at 1:36 PM, Frank Mori Hess <fmh...@gmail.com> wrote: >> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1. > > Please explain the reasoning for the revert. It looks like my original post got stuck in moderation: -- Forwarded message -- From: Frank Mori Hess <fmh...@gmail.com> Date: Sat, Dec 2, 2017 at 7:50 PM Subject: commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 breaks cadence driver To: u-boot@lists.denx.de Hi, I've been debugging why u-boot spl crashes in a loop when I boot off a cadence qspi flash. I narrowed it down to the changes from commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to successfully load the main u-boot. My board is an Altera HPS cyclone V socfpga. It has an ahb base address of 0xffa0 and for some reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots when cadence_qspi_apb_indirect_read_execute tries to read from the ahb base address. I'm using version 2016.11 of u-boot. -- Frank -- Frank -- Frank ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1. My u-boot spl crashes in a loop when I boot off a cadence qspi flash. I narrowed it down to the changes from commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to successfully load the main u-boot. My board is an Altera HPS cyclone V socfpga. It has an ahb base address of 0xffa0 and for some reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots when cadence_qspi_apb_indirect_read_execute tries to read from the ahb base address. I'm was using version 2016.11 of u-boot. Signed-off-by: Frank Mori Hess <fmh...@gmail.com> --- drivers/spi/cadence_qspi_apb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e02f2217f4..b300f36607 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -47,6 +47,7 @@ #define CQSPI_INST_TYPE_QUAD 2 #define CQSPI_STIG_DATA_LEN_MAX8 +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK0xF #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
It looks like the change I'm trying to revert got rejected a couple years ago in another form: https://lists.denx.de/pipermail/u-boot/2015-August/224556.html In particular at the end Marek says: >> /* Indirect mode configurations */ >> writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); >> - writel((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK, >> + writel((u32)plat->trigger_base, >> plat->regbase + CQSPI_REG_INDIRECTTRIGGER); > >Here you actually changed to logic of the code, which breaks it for SoCFPGA. >plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK = 0x0 for SoCFPGA, but now >you changed it such that 0xffa0 is written into the register. Same does >apply for all your changes below. On Sun, Dec 3, 2017 at 10:54 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Sun, Dec 3, 2017 at 1:51 PM, Frank Mori Hess <fmh...@gmail.com> wrote: >> On Sun, Dec 3, 2017 at 10:49 AM, Fabio Estevam <feste...@gmail.com> wrote: >>> On Sun, Dec 3, 2017 at 1:36 PM, Frank Mori Hess <fmh...@gmail.com> wrote: >>>> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1. >>> >>> Please explain the reasoning for the revert. >> >> It looks like my original post got stuck in moderation: > > You should explain inside the commit log why you think it is a good > idea to do the revert. -- Frank ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 breaks cadence driver
Hi, I've been debugging why u-boot spl crashes in a loop when I boot off a cadence qspi flash. I narrowed it down to the changes from commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to successfully load the main u-boot. My board is an Altera HPS cyclone V socfpga. It has an ahb base address of 0xffa0 and for some reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots when cadence_qspi_apb_indirect_read_execute tries to read from the ahb base address. I'm using version 2016.11 of u-boot. -- Frank ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
On Mon, Dec 4, 2017 at 11:41 AM, Vignesh R <vigne...@ti.com> wrote: > Hi, > > On 04-Dec-17 6:41 PM, Frank Mori Hess wrote: >> Since your commit broke my platform to fix yours, shouldn't it be >> reverted and TI platforms use your pending patch queue? >> > > Socfpga DT defined ahb base as 0xffa0 while masked upper bits in the > code, which was confusing. And seems that my patch did work on some > socfgpa board looking at the original commit message. There is nothing in the original commit message that suggests it worked on any socfpga board, unless you mean "Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits." which is simply wrong. > If the patch is reverted then, applying pending patches alone will not > help because my patch would be needed anyway to make sure we don't mask > 31-20 bits on TI platforms. No it won't needed, see http://patchwork.ozlabs.org/patch/838592/ that patch series writes plat->trigger_address instead of ahbbase (masked or not). ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
