Re: [U-Boot] Auto-detecting touchscreen controller and dealing with hw configuration differences on q8 tablets

I'm also a user of an A33 Q8 tablet with GSL1680. However, I think a devicetree-per-device structure is not unacceptable... We can still have sun{5,8}i-q8.common.dtsi, and write most of the q8 codes there. Then the device dt can only contain wifi, touchscreen, accelerometer. (after including

Re: [U-Boot] [RFC PATCH 2/2] efi_loader: gop: add support to use cfb_console's framebuffer

2017年2月8日 10:44于 Bin Meng <bmeng...@gmail.com>写道： > > On Tue, Feb 7, 2017 at 8:58 PM, Icenowy Zheng <icen...@aosc.xyz> wrote: > > As cfb_console now can expose its GraphicDevice, use it in the > > implementation of EFI GOP protocol, so that the graphics framebu

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 08/11] sunxi: SPL: add FIT config selector for Pine64 boards

2017年1月24日 01:29于 Maxime Ripard 写道： > > On Sat, Jan 21, 2017 at 03:15:27PM +, André Przywara wrote: > > >>> On Fri, Jan 20, 2017 at 01:53:28AM +, Andre Przywara wrote:  > > For a board or platform to support FIT loading in the SPL, it has to > >

Re: [U-Boot] [linux-sunxi] Re: [PATCH v2 11/13] sunxi: introduce Allwinner H5 config option

2017年1月26日 18:45于 Maxime Ripard 写道： > > On Wed, Jan 25, 2017 at 02:22:45AM +, Andre Przywara wrote: > > The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores. > > As the peripherals and the pinmuxing are almost identical, we piggy > > back

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 08/11] sunxi: SPL: add FIT config selector for Pine64 boards

21.01.2017, 05:56, "André Przywara" : > On 20/01/17 21:35, Maxime Ripard wrote: > > Hi Maxime, > > thanks for having a look! > >>  On Fri, Jan 20, 2017 at 01:53:28AM +, Andre Przywara wrote: >>>  For a board or platform to support FIT loading in the SPL, it has to >>>

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 08/11] sunxi: SPL: add FIT config selector for Pine64 boards

21.01.2017, 05:56, "André Przywara" : > On 20/01/17 21:35, Maxime Ripard wrote: > > Hi Maxime, > > thanks for having a look! > >>  On Fri, Jan 20, 2017 at 01:53:28AM +, Andre Przywara wrote: >>>  For a board or platform to support FIT loading in the SPL, it has to >>>

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 4/6] sunxi: Add selective DRAM type and timing

2017年2月12日 00:59于 Jens Kuske <jensku...@gmail.com>写道： > > Hi. > > On 11.02.2017 16:08, Icenowy Zheng wrote: > [..] > > @@ -299,6 +190,13 @@ static void mctl_h3_zq_calibration_quirk(struct > > dram_para *para) > >  { > >  struct sunxi_

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 4/6] sunxi: Add selective DRAM type and timing

12.02.2017, 01:00, "Jens Kuske" <jensku...@gmail.com>: > Hi. > > On 11.02.2017 16:08, Icenowy Zheng wrote: > [..] >>  @@ -299,6 +190,13 @@ static void mctl_h3_zq_calibration_quirk(struct >> dram_para *para) >>   { >>

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 2/6] sunxi: Rename bus-width related macros in H3 DRAM code

12.02.2017, 01:00, "Jens Kuske" <jensku...@gmail.com>: > Hi, > > renaming is not quite enough, see the comments below. > > On 11.02.2017 16:08, Icenowy Zheng wrote: >>  The DesignWare DRAM controller used by H3 and newer SoCs use a bit to >>  identify w

[U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <i

[U-Boot] [PATCH v3 1/3] sunxi: add basic V3s support

Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <i

Re: [U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

2017年2月13日 15:17于 Maxime Ripard <maxime.rip...@free-electrons.com>写道： > > Hi, > > On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote: > > @@ -0,0 +1,13 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_SUNXI=y > > +# CONFIG_ARMV7_NONSEC is n

Re: [U-Boot] [linux-sunxi] Re: [PATCH 08/12] sunxi: prepare for sharing MACH_SUN8I_H3 config symbol

2017年1月16日 15:59于 Maxime Ripard 写道： > > On Fri, Jan 13, 2017 at 01:30:00AM +, Andre Przywara wrote: > > The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. > > To allow sharing the clocks, GPIO and driver code easily, create an > >

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 00/11] extend FIT loading support (plus Pine64/ATF support)

21.01.2017, 01:47, "Andre Przywara" : > Hi, > > On 20/01/17 17:35, Andrew F. Davis wrote: >>  On 01/20/2017 11:17 AM, Andre Przywara wrote: >>>  Hi Andrew, >>> >>>  thanks for the comments. >>> >>>  On 20/01/17 17:02, Andrew F. Davis wrote:  On 01/19/2017 07:53 PM,

Re: [U-Boot] [linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

2017年3月1日 23:51于 Maxime Ripard 写道： > > Hi Andre, > > On Wed, Mar 01, 2017 at 02:25:26AM +, Andre Przywara wrote: > > The Pine64 (and all other 64-bit Allwinner boards) need to load an > > ARM Trusted Firmware image beside the actual U-Boot proper. > >

Re: [U-Boot] [linux-sunxi] [PATCH 00/12] sunxi: Add support for R40 SoC

2017年3月1日 15:04于 Chen-Yu Tsai 写道： > > Hi everyone, > > This series adds support for the new R40 SoC. The R40 is marketed as the > successor to the A20. It is mostly pin compatible (in software) with the > A20. It has a somewhat similar memory layout, a hybrid of A20 and newer >

Re: [U-Boot] [linux-sunxi] [PATCH 1/8] sunxi: board: Print error after power initialization fails

01.03.2017, 20:52, "Olliver Schinagl" : > Currently during init, we enable all power, then enable the dram and > after that check if there was an error during power-up. > > This makes little sense, we should enable power and then check if power > was brought up properly

Re: [U-Boot] [linux-sunxi] Re: [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

01.03.2017, 21:45, "Olliver Schinagl" : > Hey Maxime, > > On 01-03-17 14:00, Maxime Ripard wrote: >>  Hi Oliver, >> >>  On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl wrote: >>>  Hi list, >>> >>>  When powering up an AXP209, the default value for LDO3 output

Re: [U-Boot] [linux-sunxi] Re: [PATCH 01/12] sunxi: Add initial support for R40

01.03.2017, 22:57, "Maxime Ripard" : > 1;4601;0c > On Wed, Mar 01, 2017 at 08:10:55PM +0800, Chen-Yu Tsai wrote: >>  On Wed, Mar 1, 2017 at 6:55 PM, Maxime Ripard >>   wrote: >>  > Hi Chen-Yu >>  > >>  > On Wed, Mar 01, 2017 at

Re: [U-Boot] [PATCH 1/2] sunxi: add proper device tree for iNet D978 rev2 boards

26.08.2016, 22:08, "Hans de Goede" <hdego...@redhat.com>: > Hi, > > On 26-08-16 15:20, Icenowy Zheng wrote: >>  26.08.2016, 20:23, "Hans de Goede" <hdego...@redhat.com>: >>>  Hi, >>> >>>  On 26-08-16 14:03, Icenowy Zhe

Re: [U-Boot] [PATCH 1/2] sunxi: add proper device tree for iNet D978 rev2 boards

26.08.2016, 20:23, "Hans de Goede" <hdego...@redhat.com>: > Hi, > > On 26-08-16 14:03, Icenowy Zheng wrote: >>  Add a proper dts for the iNet D978 rev2 based A33 tablets. > > Hmm, this dts file is not using the new sun8i-reference-design-tablet.dtsi > fil

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 0/3] sunxi: video: Add support for HDMI output on H3

14.12.2016, 04:29, "Simon Glass" : > Hi, > > On 12 December 2016 at 19:36, Jernej Skrabec wrote: >>  This patch series add support for HDMI output. Support for other, >>  newer, SoCs, which also uses DE2 and same or similar HDMI controller >>  and PHY

Re: [U-Boot] [linux-sunxi] [PATCH 0/2] sunxi: OrangePi Zero fixes

2017年1月14日 10:06于 Andre Przywara 写道： > > Hi, > > two small patches on top of sunxi/next to enable Ethernet and SPI flash. > Was there any reason the emac node was omitted from the DT patch (as > it is in the OrangePi One DT, which I belive the Zero has copied from)?

Re: [U-Boot] [PATCH 02/12] sunxi: simplify ACTLR.SMP bit set #ifdef

13.01.2017, 09:34, "Andre Przywara" : > Instead of enumerating all SoC families that need that bit set, let's > just express this more clearly: The SMP bits needs to be set on > SMP capable ARMv7 CPUs. It's much easier to Kconfig to express it the > other way round, so we

Re: [U-Boot] [PATCH 00/12] sunxi: Allwinner H5 and OrangePi PC2 support

13.01.2017, 09:34, "Andre Przywara" : > This series introduces support for the Allwinner H5 SoC with four > Cortex-A53 cores. The SoC's peripherals are very similar to the H3, > although the cores and the BROM/SRAM layout resembles the A64. > The first 6 patches contain

Re: [U-Boot] [PATCH v2 1/4] sunxi: add basic V3s support

11.01.2017, 03:25, "Maxime Ripard" <maxime.rip...@free-electrons.com>: > Hi, > > On Tue, Jan 10, 2017 at 05:18:22PM +0800, Icenowy Zheng wrote: >>  Basic U-Boot support is now present for V3s. >> >>  Some memory addresses are changed specially for V3s,

Re: [U-Boot] [linux-sunxi] Re: [PATCH 1/2] sunxi: power: add AXP803 support

2017年1月6日 05:59于 Maxime Ripard <maxime.rip...@free-electrons.com>写道： > > On Fri, Dec 23, 2016 at 04:31:32PM +0800, Icenowy Zheng wrote: > > The A64 uses the AXP803 as its PMIC. > > > > Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> > > ---

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 4/4] sunxi: low memory footprint for V3s

2017年1月6日 06:39于 Maxime Ripard <maxime.rip...@free-electrons.com>写道： > > On Thu, Dec 29, 2016 at 03:01:01AM +0800, Icenowy Zheng wrote: > > V3s devices won't have enough memory to load U-Boot binary at > > 0x4a00, and they do not have enough memory to reserve 64MiB f

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller

2017年1月6日 06:37于 Maxime Ripard <maxime.rip...@free-electrons.com>写道： > > On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote: > > H3-like DRAM controller needs some special code to operate a DDR2 DRAM > > chip. Add the logic to probe such a chip. > >

[U-Boot] [PATCH v2 1/6] sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <i

[U-Boot] [PATCH v2 3/6] sunxi: add basic V3s support

Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- Changes since v1: - squashed memory footprint patch into it. - disabled VIDEO f

[U-Boot] [PATCH v2 6/6] sunxi: do a CCM quirk on V3s for USB to work properly

initialization code. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- New patch in v2. arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + arch/arm/mach-sunxi/clock.c | 5 + arch/arm/mach-sunxi/clock_sun6i.c | 11 +++ 3 files changed, 17 inse

Re: [U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

2017年1月9日 下午7:06于 Maxime Ripard <maxime.rip...@free-electrons.com>写道： > > On Fri, Jan 06, 2017 at 07:13:17AM +0800, Icenowy Zheng wrote: > > > > > > 06.01.2017, 06:16, "Maxime Ripard" <maxime.rip...@free-electrons.com>: > > > On Thu

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller

2017年1月9日 下午6:30于 Andre Przywara <andre.przyw...@arm.com>写道： > > Hi, > > On 05/01/17 22:55, Icenowy Zheng wrote: > > > > 2017年1月6日 06:37于 Maxime Ripard <maxime.rip...@free-electrons.com>写道： > >> > >> On Thu, Dec 29, 2016 at 03:0

Re: [U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

06.01.2017, 06:16, "Maxime Ripard" <maxime.rip...@free-electrons.com>: > On Thu, Dec 29, 2016 at 02:50:48AM +0800, Icenowy Zheng wrote: >>  Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like >>  DesignWare DRAM controller, which do not have official fr

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller

09.01.2017, 18:01, "Maxime Ripard" <maxime.rip...@free-electrons.com>: > On Fri, Jan 06, 2017 at 06:55:05AM +0800, Icenowy Zheng wrote: >>  > > +    MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ | >>  > >>  > What's w

[U-Boot] [PATCH v2 2/4] sunxi: add DTSI file for V3s

As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/dts/sun8i-v3s.dtsi | 284 ++ include/dt-bi

Re: [U-Boot] Problems to Allwinner H3's eFUSE/SID

20.12.2016, 00:17, "Hans de Goede" <hdego...@redhat.com>: > Hi, > > On 19-12-16 17:06, Icenowy Zheng wrote: >>  19.12.2016, 23:30, "Hans de Goede" <hdego...@redhat.com>: >>>  Hi, >>> >>>  On 19-12-16 16:22, Icenowy

Re: [U-Boot] Problems to Allwinner H3's eFUSE/SID

19.12.2016, 23:30, "Hans de Goede" <hdego...@redhat.com>: > Hi, > > On 19-12-16 16:22, Icenowy Zheng wrote: >>  Hi everyone, >> >>  Today, I and KotCzarny on IRC of linux-sunxi found a problem in the SID >>  controller of H3 (incl. H2+). >>

Re: [U-Boot] [PATCH 1/2] sunxi: add proper device tree for Orange Pi Zero boards

16.12.2016, 22:52, "Jagan Teki" <ja...@openedev.com>: > On Fri, Dec 16, 2016 at 3:35 PM, Icenowy Zheng <icen...@aosc.xyz> wrote: >>  Add a proper device tree file for Orange Pi Zero boards from Xunlong, >>  which come with a Allwinner H2+ SoC (similar to H3)

[U-Boot] [PATCH 1/2] sunxi: power: add AXP803 support

The A64 uses the AXP803 as its PMIC. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/Makefile | 3 + arch/arm/mach-sunxi/pmic_bus.c | 6 +- arch/arm/mach-sunxi/rsb.c | 2 +- board/sunxi/board.c| 31 ++--- drivers/power/Kconfig

[U-Boot] [PATCH 1/2] sunxi: add proper device tree for Lichee Pi One

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun5i-a13-licheepi-one.dts | 224 2 files changed, 225 insertions(+) create mode 100644 arch/arm/dts/sun5i-a13-licheepi-one.dts diff --git

[U-Boot] [RFC PATCH 2/4] sunxi: add basic V3s support

Currently a working SPL for V3s can be built now. The U-Boot main binary still cannot work. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/board.c| 9 +++-- arch/arm/mach-sunxi/cpu_info.c

[U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <i

[U-Boot] [PATCH] sunxi: H3/A64: fix non-ODT setting

From: Andre Przywara According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this. Reported-by: Jens Kuske Signed-off-by: Andre Przywara ---

Re: [U-Boot] [linux-sunxi] [PATCH v2 0/7] sunxi: video: Add support for HDMI output on A64/H3/H5

; - patch 1 & 2 were removed because they were merged > - collect reviewed by and tested by tags > - TCON split out patch is splitted in two patches > - fixed lcdc_enable() calls in video driver for old SoCs > - defconfigs should disable video driver, not enable it > - minor con

Re: [U-Boot] [linux-sunxi] Re: [PATCH 2/6] sunxi: Rename bus-width related macros in H3 DRAM code

2017年3月15日 08:23于 André Przywara <andre.przyw...@arm.com>写道： > > On 13/03/17 17:50, Icenowy Zheng wrote: > > The DesignWare DRAM controller used by H3 and newer SoCs use a bit to > > identify whether the DRAM is half-width. > > > > As H3 itself come with 3

Re: [U-Boot] [linux-sunxi] Re: [PATCH 1/6] sunxi: makes an invisible option for H3-like DRAM controllers

2017年3月15日 08:23于 André Przywara <andre.przyw...@arm.com>写道： > > On 13/03/17 17:50, Icenowy Zheng wrote: > > Hi Icenowy, > > as mentioned before, I like this patch. > In general, can you rebase this series on top of sunxi/master? There are > some rather easy c

Re: [U-Boot] [linux-sunxi] Re: [PATCH 5/8] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

2017年3月13日 20:33于 Simon Glass 写道： > > Hi, > > On 8 March 2017 at 16:34, Jernej Skrabec wrote: > > This is needed for HDMI, which will be added later. > > > > Signed-off-by: Jernej Skrabec > > --- > > > > 

[U-Boot] [PATCH] sunxi: set up PLL1 on sun6i+ without use dividers

-by: Icenowy Zheng <icen...@aosc.io> --- This is a critical patch, and should be added to 2017.05. It has been verified by the Armbian. arch/arm/mach-sunxi/clock_sun6i.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach

Re: [U-Boot] [PATCH v2 14/18] sunxi: Pine64: defconfig: enable SPL FIT support

2017年3月29日 19:17于 Andre Przywara 写道： > > Hi, > > On 29/03/17 07:57, Maxime Ripard wrote: > > On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote: > >> The Pine64 (and all other 64-bit Allwinner boards) need to load an > >> ARM Trusted Firmware image beside

Re: [U-Boot] [PATCH v2 14/18] sunxi: Pine64: defconfig: enable SPL FIT support

2017年3月29日 14:57于 Maxime Ripard 写道： > > On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote: > > The Pine64 (and all other 64-bit Allwinner boards) need to load an > > ARM Trusted Firmware image beside the actual U-Boot proper. > > This can now be

[U-Boot] [PATCH] sunxi: assign default clock of H5 to 816MHz

to 816MHz, as it's a more reasonable and more safe value. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- board/sunxi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 609ce63b3e..5144c27535 100644 --- a/board/sunxi/Kconfig

[U-Boot] [PATCH 0/8] Allwinner DesignWare DRAM controller refactors and V3s SPL support

is still TODO, but current code can make it work. Icenowy Zheng (8): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related macros in H3 DRAM code sunxi: add option for 16-bit DW DRAM controller sunxi: add bank detection code to H3 DRAM initialization code

[U-Boot] [PATCH 3/8] sunxi: add option for 16-bit DW DRAM controller

Some Allwinner SoCs features a DesignWare-like controller with only 16 bit bus width. Add support for them. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 34 +- board/sunxi/Kconfig

[U-Boot] [PATCH 7/8] sunxi: add timing info for the DDR2 in V3s SoC

Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its timing param. Add the timing info for it, and make this chip selectable. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr2

[U-Boot] [PATCH 8/8] sunxi: add support for V3s DRAM controller

Allwinner V3s features a DRAM controller like the on in H3, but with a DDR2 DRAM. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 3 +++ board/sunxi/Kconfig | 9 - 2 files changed, 11 insertions(+), 1 de

[U-Boot] [PATCH 2/8] sunxi: Rename bus-width related macros in H3 DRAM code

and 16-bit. Rename the bit's macro, and also rename the variable name in dram_sun8i_h3.c. This commit do not add 16-bit DRAM controller support, but the support will be introduced in next commit. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/include/asm/arch-sunxi/dram_su

[U-Boot] [PATCH 1/8] sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <i

[U-Boot] [PATCH 5/8] sunxi: Add selective DRAM type and timing

DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++ arch/arm/mach

[U-Boot] [PATCH 4/8] sunxi: add bank detection code to H3 DRAM initialization code

Some DDR2 DRAM have only four banks, not eight. Add code to detect this situation. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sunx

[U-Boot] [PATCH 6/8] sunxi: add support for DDR2 DRAM for DesignWare-like DRAM controller

The DesignWare-like DRAM controllers in Allwinner chips have DDR2 DRAM support, add support for it in the driver. No real DDR2 chip info is added in this commit. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 ++ board/sunxi/K

Re: [U-Boot] [PATCH v4 1/3] sunxi: add basic V3s support

11.03.2017, 10:09, "Icenowy Zheng" <icen...@aosc.xyz>: > Basic U-Boot support is now present for V3s. > > Some memory addresses are changed specially for V3s, as the original > address map cannot fit into a so small DRAM. > > As the DRAM controller code nee

[U-Boot] [PATCH v4 1/3] sunxi: add basic V3s support

Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <i

[U-Boot] [PATCH v4 0/3] Allwinner V3s and Lichee Pi Zero support (w/o SPL)

, but the DRAM initialization code currently only support DDR3.) Icenowy Zheng (3): sunxi: add basic V3s support sunxi: add DTSI file for V3s sunxi: add support for Lichee Pi Zero arch/arm/dts/Makefile | 2 + arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83

[U-Boot] [PATCH v4 2/3] sunxi: add DTSI file for V3s

As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> --- Changes in v4: - Add Maxime's

[U-Boot] [PATCH v4 3/3] sunxi: add support for Lichee Pi Zero

-by: Icenowy Zheng <icen...@aosc.xyz> --- Changes in v4: - Removed NONSEC disabling for Lichee Pi Zero board. - Enriched commit message. arch/arm/dts/Makefile| 2 + arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83 board/sunxi/MAINT

[U-Boot] [PATCH v5 2/3] sunxi: add DTSI file for V3s

As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> --- Changes in v4: - Add Maxime's

[U-Boot] [PATCH v5 1/3] sunxi: add basic V3s support

Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <i

[U-Boot] [PATCH 3/6] sunxi: add option for 16-bit DW DRAM controller

Some Allwinner SoCs features a DesignWare-like controller with only 16 bit bus width. Add support for them. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 34 +- board/sunxi/Kconfig

[U-Boot] [PATCH v5 0/3] Allwinner V3s and Lichee Pi Zero support (w/o SPL)

, but the DRAM initialization code currently only support DDR3.) Icenowy Zheng (3): sunxi: add basic V3s support sunxi: add DTSI file for V3s sunxi: add support for Lichee Pi Zero arch/arm/dts/Makefile | 2 + arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83

[U-Boot] [PATCH 0/6] Allwinner DesignWare-like DRAM controllers refactor

needs this patchset. For V3s SPL support I will have another patchset, which depends on the not-yet-merged V3s support w/o SPL patchset. Icenowy Zheng (6): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related macros in H3 DRAM code sunxi: add option

[U-Boot] [PATCH 5/6] sunxi: Add selective DRAM type and timing

DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++ arch/arm/mach

[U-Boot] [PATCH 6/6] sunxi: enable dual rank detection in DesignWare-like DRAM code

on a Orange Pi One (H3, single rank), a Pine64+ 2GiB version (A64, single rank) , a Pinebook early prototype with DDR3 (A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins on one chip). Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 2

[U-Boot] [PATCH v5 3/3] sunxi: add support for Lichee Pi Zero

-by: Icenowy Zheng <icen...@aosc.xyz> --- Changes in v4: - Removed NONSEC disabling for Lichee Pi Zero board. - Enriched commit message. arch/arm/dts/Makefile| 2 + arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83 board/sunxi/MAINT

[U-Boot] [PATCH 1/6] sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <i

[U-Boot] [PATCH 2/6] sunxi: Rename bus-width related macros in H3 DRAM code

and 16-bit. Rename the bit's macro, and also rename the variable name in dram_sun8i_h3.c. This commit do not add 16-bit DRAM controller support, but the support will be introduced in next commit. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/include/asm/arch-sunxi/dram_su

[U-Boot] [PATCH 4/6] sunxi: add bank detection code to H3 DRAM initialization code

Some DDR2 DRAM have only four banks, not eight. Add code to detect this situation. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sunx

Re: [U-Boot] [linux-sunxi] [PATCH 8/8] [DO NOT MERGE] sunxi: power: add AXP803 support

2017年3月9日 07:34于 Jernej Skrabec <jernej.skra...@siol.net>写道： > > From: Icenowy Zheng <icen...@aosc.xyz> I'm making newer version of this patch. > > The A64 uses the AXP803 as its PMIC. > > Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> > >

Re: [U-Boot] [linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

2017年3月3日 17:55于 Andre Przywara <andre.przyw...@arm.com>写道： > > Hi, > > On 03/03/17 09:22, Maxime Ripard wrote: > > On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy Zheng wrote: > >> > >> 2017年3月1日 23:51于 Maxime Ripard <maxime.rip...@

Re: [U-Boot] [linux-sunxi] [PATCH 11/17] sunxi: SPL: add FIT config selector for Pine64 boards

01.03.2017, 10:26, "Andre Przywara" : > For a board or platform to support FIT loading in the SPL, it has to > provide a board_fit_config_name_match() routine, which helps to select > one of possibly multiple DTBs contained in a FIT image. > Provide a simple function

[U-Boot] [PATCH v5 0/3] Allwinner V3s and Lichee Pi Zero support (w/o SPL)

, but the DRAM initialization code currently only support DDR3.) Icenowy Zheng (3): sunxi: add basic V3s support sunxi: add DTSI file for V3s sunxi: add support for Lichee Pi Zero arch/arm/dts/Makefile | 5 +- arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83

[U-Boot] [PATCH v5 2/3] sunxi: add DTSI file for V3s

From: Icenowy Zheng <icen...@aosc.xyz> As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> Acked-by: Maxime Ripard <maxime.rip...@fre

[U-Boot] [PATCH v5 1/3] sunxi: add basic V3s support

From: Icenowy Zheng <icen...@aosc.xyz> Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this v

[U-Boot] [PATCH v5 3/3] sunxi: add support for Lichee Pi Zero

From: Icenowy Zheng <icen...@aosc.xyz> Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp

[U-Boot] [PATCH] sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I

onfig") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/serial/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a753367ee1..58320666b7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig

[U-Boot] [PATCH] sunxi: defaultly enable SPL for Lichee Pi Zero

As we have already DRAM initialization code for V3s SoC, we can defaultly enable SPL now on Lichee Pi Zero. Add CONFIG_SPL in Lichee Pi Zero defconfig. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- configs/LicheePi_Zero_defconfig | 4 1 file changed, 4 insertions(+) diff

[U-Boot] [PATCH 1/2] sunxi: add PRCM secure switch register definition

Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block. Add the definition of this register and its bits in the PRCM header file. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/include/asm/arch

[U-Boot] [PATCH 2/2] sunxi: switch PRCM to non-secure on H3/H5 SoCs

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/mach-sunxi/clock_sun6i.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index ec5b026ef5..870ff5b1e0 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++

Re: [U-Boot] [PATCH] sunxi: add MACPWR in Orange Pi PC2 defconfig

于 2017年7月4日 GMT+08:00 下午6:47:17, Andre Przywara <andre.przyw...@arm.com> 写到: >Hi, > >On 04/07/17 11:43, Icenowy Zheng wrote: >> The Ethernet function is enabled in the Orange Pi PC2 device tree and >> defconfig, however, CONFIG_MACPWR is not properly set, which lef

[U-Boot] [PATCH] sunxi: add MACPWR in Orange Pi PC2 defconfig

("sunxi: Add OrangePi PC 2 initial support") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- configs/orangepi_pc2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 5a64ad3f41..b72514d3b9 1006

Re: [U-Boot] [PATCH 3/4] sunxi: add stub EMAC device node in A83T device tree

于 2017年7月3日 GMT+08:00 下午2:52:00, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Sun, Jul 02, 2017 at 03:02:43PM +0800, Icenowy Zheng wrote: >> The Allwinner A83T SoC has an EMAC which is already supported by >> sun8i_emac driver in U-Boot now. >>

[U-Boot] [PATCH 0/4] Allwinner A83T and Banana Pi M3 EMAC support

BOOTP and I only tested pinging the router with fixed IP.) Icenowy Zheng (4): sun8i_emac: disable build of EPHY clock code on non-H3/H5 platforms sun8i_emac: add support for setting EMAC TX/RX delay sunxi: add stub EMAC device node in A83T device tree sunxi: enable EMAC for Banana Pi M3 board

[U-Boot] [PATCH 4/4] sunxi: enable EMAC for Banana Pi M3 board

Banana Pi M3 board comes with the A83T EMAC connected to a Realtek RTL8211E PHY, with a TX delay of 600ps. Add the necessary DT parts and enable sun8i_emac in the defconfig. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dt

[U-Boot] [PATCH 2/4] sun8i_emac: add support for setting EMAC TX/RX delay

for setting these delays. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/sun8i_emac.c | 31 +-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c071f5d3c3..4ba65c8a06

[U-Boot] [PATCH 3/4] sunxi: add stub EMAC device node in A83T device tree

The Allwinner A83T SoC has an EMAC which is already supported by sun8i_emac driver in U-Boot now. Add a stub device node for it. The device node cannot work for Linux, because it now lacks the proper clock definition; however, it can satisfy sun8i_emac driver in U-Boot. Signed-off-by: Icenowy

[U-Boot] [PATCH 1/4] sun8i_emac: disable build of EPHY clock code on non-H3/H5 platforms

Sometimes the EPHY clock macros are not defined for non-H3/H5 platforms (e.g. A83T), which makes the driver to fail to be built. Only build the EPHY clock code when the SoC is H3/H5 by wrap them into an #ifdef. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/sun8i_emac

Re: [U-Boot] [PATCH] sunxi: gpio: add missing compatible strings

于 2017年6月29日 GMT+08:00 下午6:10:31, Andre Przywara 写到: >The sunxi GPIO driver is missing some compatible strings for recent >SoCs. While most of the sunxi GPIO code seems to not rely on this (and >so works anyway), the sunxi_name_to_gpio() function does and fails at >the

[U-Boot] [PATCH 00/12] Big work on sunxi DW DRAM controllers and some new DDR type support

, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source) The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3. Icenowy Zheng (12): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related

[U-Boot] [PATCH 06/12] sunxi: enable dual rank detection in DesignWare-like DRAM code

From: Icenowy Zheng <icen...@aosc.xyz> The DesignWare-like DRAM code used to set the controller defaultly to single rank mode, which makes it not able to detect the second rank. Set the default value to dual rank, thus the rank detection code can work and finally the rank s

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