This adds a helper function to unlock the PCI configuration bit, so that
any extra PCI setup (such as outbound windows, etc.) can be done after
using the 83XX_GENERIC_PCI code to set up the PCI bus.
Signed-off-by: Ira W. Snyder [EMAIL PROTECTED]
---
cpu/mpc83xx/pci.c | 26
Add the ability for the MPC8349EMDS to run in PCI Agent mode, acting as a
PCI card rather than a host computer.
Signed-off-by: Ira W. Snyder [EMAIL PROTECTED]
---
board/freescale/mpc8349emds/mpc8349emds.c |9 +
board/freescale/mpc8349emds/pci.c | 49
Change the MPC8349EMDS board to use the generic PCI initialization code
for the mpc83xx cpu.
Signed-off-by: Ira W. Snyder [EMAIL PROTECTED]
---
board/freescale/mpc8349emds/pci.c | 377 ++---
include/configs/MPC8349EMDS.h |4 +-
2 files changed, 63
Hello u-boot-users,
This is my attempt at adding CONFIG_PCISLAVE support to the MPC8349EMDS
board. I noticed that there was some shared infrastructure for the PCI
controller in the 83xx-series CPU's, so I removed all of the old code,
and used the infrastructure instead.
I have boot tested the
due to a code change in upstream U-Boot to support the mx51 processor
family.
Reported-by: Jim Lentz jle...@zhone.com
Cc: Andy Fleming aflem...@freescale.com
Cc: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
I'm sending this as a new email
On Fri, Jan 06, 2012 at 12:35:28AM -0500, Peter Barada wrote:
On 01/06/2012 12:21 AM, qiao.hellowo...@gmail.com wrote:
2012/1/6 John Rigbyjohn.ri...@linaro.org
*u-boot/spl/u-boot-spl.lds:1: syntax error
make[1]: *** [/home/qian/Desktop/u-boot/spl/u-boot-spl] Error 1
make[1]: Leaving
On Fri, Feb 15, 2013 at 02:00:10PM -0500, Harvey Chapman wrote:
On Feb 15, 2013, at 7:38 AM, Albert ARIBAUD albert.u.b...@aribaud.net wrote:
On Thu, 14 Feb 2013 12:19:11 -0800
(PST), Sean Omalley omalle...@rocketmail.com wrote:
Is there anyway to break back into u-boot after trying to
On Fri, Mar 08, 2013 at 08:08:24PM +0100, Wolfgang Denk wrote:
The mtest command is of little practical use (if any), and
experience has shown that a large number of board configurations
define useless or even dangerous start and end addresses. If not even
the board maintainers are able to
From: Ira W. Snyder i...@ovro.caltech.edu
This series improves the hardware support for the Freescale MPC8308RDB board.
Optional support for the SPI pins routed to header J8 is added for testing SPI
flash chips. This was tested with a Spansion S25FL256S1. This is not enabled
by default, because
From: Ira W. Snyder i...@ovro.caltech.edu
Add support for the S25FL256S1 flash chip. It is a 256Mb (32MB) flash
comprised of 64KB pages.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
drivers/mtd/spi/spansion.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff
From: Ira W. Snyder i...@ovro.caltech.edu
This is very useful on a modern system.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
include/configs/MPC8308RDB.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/include/configs/MPC8308RDB.h b/include/configs
From: Ira W. Snyder i...@ovro.caltech.edu
Add support for the onboard eSDHC MMC controller. The hardware on the
MPC8308RDB has the following errata:
- ESDHC111: manual asynchronous CMD12 is broken
- DMA is broken (PIO works)
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
board
From: Ira W. Snyder i...@ovro.caltech.edu
The MPC8308RDB Reference Manual states that no bits in the SPMODE
register are allowed to change while the enable (EN) bit is set.
This driver changes the character length bits (LEN) while the enable
(EN) bit is set. Clearing the EN bit while changing
From: Ira W. Snyder i...@ovro.caltech.edu
The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.
This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some
support for eSDHC MMC controller (2012-09-17 17:47:12
-0500)
Ira W. Snyder (5):
mpc8xxx_spi: fix SPI support on MPC8308RDB
mpc8308rdb: add support for Spansion SPI flash on header J8
spansion: add
On Mon, Jan 14, 2013 at 06:59:59PM -0600, Kim Phillips wrote:
On Tue, 8 Jan 2013 18:25:11 -0800
Barry Grussling ba...@grussling.com wrote:
While trying to bring up a custom MPC8308 based board I found
that the clocking was wrong. The comment in
include/configs/mpc8308_p1m.h led me to
On Fri, Jul 24, 2009 at 09:41:21AM -0500, Peter Tyser wrote:
On Fri, 2009-07-24 at 15:46 +0200, Wolfgang Denk wrote:
Dear Peter,
In message 20090723190101.c8f8a832e...@gemini.denx.de I wrote:
In message 1247269570-11406-1-git-send-email-pty...@xes-inc.com you
wrote:
On Wed, Jul 08, 2009 at 02:28:39PM -0500, Peter Tyser wrote:
These changes bring the 83xx SDRAM ECC initialization in line
with the 85xx/86xx boards and also fixes a minor bug in fsl_dma.c.
I don't have any 83xx boards to test on, so it would be appreciated
if someone with 83xx hardware that
On Wed, Jul 08, 2009 at 03:31:29PM -0700, Ira W. Snyder wrote:
On Wed, Jul 08, 2009 at 02:28:39PM -0500, Peter Tyser wrote:
These changes bring the 83xx SDRAM ECC initialization in line
with the 85xx/86xx boards and also fixes a minor bug in fsl_dma.c.
I don't have any 83xx boards
On Wed, Jul 08, 2009 at 05:59:33PM -0500, Peter Tyser wrote:
On Wed, 2009-07-08 at 15:31 -0700, Ira W. Snyder wrote:
On Wed, Jul 08, 2009 at 02:28:39PM -0500, Peter Tyser wrote:
These changes bring the 83xx SDRAM ECC initialization in line
with the 85xx/86xx boards and also fixes a minor
On Wed, Jul 08, 2009 at 07:32:26PM -0500, Peter Tyser wrote:
On Thu, 2009-07-09 at 08:24 +0800, Liu Dave-R63238 wrote:
When SDRAM ECC is enabled and CONFIG_ECC_INIT_VIA_DDRCONTROLLER is not
defined use DMA to set SDRAM to a known state. Previously a
sequence of
64-bit stores was
On Wed, Jul 08, 2009 at 05:58:50PM -0700, Ira W. Snyder wrote:
On Wed, Jul 08, 2009 at 07:32:26PM -0500, Peter Tyser wrote:
On Thu, 2009-07-09 at 08:24 +0800, Liu Dave-R63238 wrote:
When SDRAM ECC is enabled and CONFIG_ECC_INIT_VIA_DDRCONTROLLER is not
defined use DMA to set SDRAM
The FIT image source files are missing the /dts-v1/; directive at the
beginning of the file. Add the directive to the examples.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Note that to make U-Boot's mkimage utility do anything at all, I had to
manually apply Remy's patch from Oct. 28
Hello,
I've just started testing U-Boot's FIT image support on a MPC8349EMDS
board. I'm using an .its file based on multi.its. It has a single
kernel, ramdisk, and fdt.
I've noticed that if I do not specify a load address for the ramdisk,
bootm will fail, with the messages:
Can't get ramdisk
On Mon, Nov 09, 2009 at 07:20:26PM -0600, Peter Tyser wrote:
On Tue, 2009-11-10 at 09:08 +0800, Liu Dave-R63238 wrote:
On Tue, 2009-11-10 at 08:42 +0800, Liu Dave-R63238 wrote:
IIRC, 85xx cache is enabled, so when we do the ecc error inject
test, What will happen before disable ecc
On Mon, Nov 09, 2009 at 09:07:25PM -0600, Peter Tyser wrote:
[ big snip ]
I haven't looked at your code. When I was running the old ecc command, I
had the 83xx reference manual open to decode the command's output, IIRC.
PS - I'm happy to test stuff on 83xx, I'll try and find time to
On Tue, Nov 10, 2009 at 11:36:44AM -0600, Peter Tyser wrote:
Ok, here are my results, this is on a 8349EMDS-derived board. My
8349EMDS eval board doesn't have ECC memory.
1) It might be nice to have something to print the current injection
registers. It is not a big deal, anyone using
On Wed, Mar 31, 2010 at 05:29:09PM -0400, Jason Hanna wrote:
Are you connected directly to the tftp server or is there switches in
between?
I'm running a Cisco/Linksys SLM2024 24-port switch. The embedded board
and TFTP server are on the same subnet and VLAN, however.
That's how I
On Tue, Apr 20, 2010 at 01:01:39PM -0600, Chris Rigg wrote:
Hello,
I have a general design question and I can't think of a better forum than
this one to ask it in. Let me know if this is not the right place to ask.
My environment:
I have an embedded system (u-boot/Embedded Linux) running
suggested that virtio would be a good choice here, since they have a
highly optimized network driver.
Ira
On Tue, Apr 20, 2010 at 3:37 PM, Scott McNutt smcn...@psyent.com wrote:
Hi Chris,
Ira W. Snyder wrote:
My problem:
If I have an in-memory filesystem on my board (the ramdisk
. Increase
the value of CONFIG_SYS_BOOTMAPSZ to accommodate the maximum value
allowed by Linux. This will allow very large kernels to boot.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Wolfgang,
I did both mpc83xx and mpc51xx (CONFIG_E300) at the same time. There
were fewer boards than I
On Fri, Sep 10, 2010 at 03:42:32PM -0700, Ira W. Snyder wrote:
Newer Linux kernels can overrun the initial memory window used for
booting with their BSS area. When this happens, they overwrite the FDT
and silently fail to boot.
On e300 CPUs, the Linux kernel uses an initial BAT covering
On Fri, Oct 15, 2010 at 03:51:48PM +0100, Gray Remlin wrote:
Signed-off-by: Gray Remlin g_rem...@rocketmail.com
---
arch/arm/lib/board.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 22bd2c9..c1b21f5 100644
---
On Sat, Nov 12, 2011 at 12:16:05PM -0600, Kumar Gala wrote:
This entire file is identical to board/freescale/p1_p2_rdb/ddr.c. In
fact, since this board only boots via the On-Chip ROM, the whole file is
useless: fixed_sdram() should just return the RAM size. We're running
from RAM when
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Unchanged from v1.
arch/powerpc/cpu/mpc85xx/cpu.c | 17 -
1 files
- v4:
- address review comments
- boot via L2 SRAM (just like P2020DS)
- use SPD EEPROM to configure DDR SDRAM
Changes v2 - v3:
- re-enable CCSR relocation
Changes v1 - v2:
- fix checkpatch warnings
- remove references to NAND (this board lacks NAND)
- disable CCSR relocation
Ira W. Snyder (3
the module_type field set to 0x08. This is an unknown value in
all documentation I can find online.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
Cc: York Sun york...@freescale.com
---
New in v4. Suggestions for other ways to solve this are welcome.
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c |7
-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Changes v3 - v4:
- address review comments (magic numbers, etc.)
- boot via L2 SRAM
- use SPD EEPROM to initialize DDR SDRAM
Changes v2 - v3:
- re-enable CCSR relocation
Changes v1 - v2:
- fix checkpatch warnings
- remove all references to NAND
On Mon, Nov 21, 2011 at 07:11:14PM +, sun york-R58495 wrote:
From: Ira W. Snyder [i...@ovro.caltech.edu]
Sent: Monday, November 21, 2011 10:59 AM
To: u-boot@lists.denx.de
Cc: sun york-R58495
Subject: [PATCH v4 2/3] mpc8xxx: assume unregistered
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Unchanged from v1.
arch/powerpc/cpu/mpc85xx/cpu.c | 17 -
1 files
)
- disable CCSR relocation
Ira W. Snyder (3):
mpc85xx: support board-specific reset function
mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
mpc85xx: support for Freescale COM Express P2020
MAINTAINERS |4 +
arch/powerpc/cpu/mpc85xx
Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
Cc: York Sun york...@freescale.com
---
New
-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Changes v4 - v5:
- unchanged
Changes v3 - v4:
- address review comments (magic numbers, etc.)
- boot via L2 SRAM
- use SPD EEPROM to initialize DDR SDRAM
Changes v2 - v3:
- re-enable CCSR relocation
Changes v1 - v2:
- fix checkpatch warnings
-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Changes v5 - v6:
- fix a build warning
- remove CONFIG_FSL_DDR_INTERACTIVE
Changes v4 - v5:
- unchanged
Changes v3 - v4:
- address review comments (magic numbers, etc.)
- boot via L2 SRAM
- use SPD EEPROM to initialize DDR SDRAM
Changes v2 - v3
On Mon, Nov 28, 2011 at 11:22:01PM +0100, Wojciech Zabolotny wrote:
Hi,
I'm trying to achieve starting of U-Boot from L2 cache memory after
downloading from SD card.
The board is P2020RDB-like, however it contains only 512MB of memory.
Because we suspect, that there may be problems with DDR
it was out of tree, another commit happened
(c67bee146 fsl_esdhc: add support for mx51 processor) which changed
how the mmc-priv variable is used.
From 91d7e1788b639602e62249f8db53412d913f4d35 Mon Sep 17 00:00:00 2001
From: Ira W. Snyder i...@ovro.caltech.edu
Date: Fri, 16 Dec 2011 09:48:19 -0800
On Tue, Mar 01, 2011 at 02:40:55PM -0800, Ira W. Snyder wrote:
Commit 359ec4931944adb885882deb9b781e4095eabc94 broke support for the
Freescale DMA engine on the 83xx parts. This is due to using registers
which do not exist on 83xx. Remove the attribute register accesses from
the 83xx build
Hi everyone,
Does anyone have a BDI2000 configuration for the P2020DS that they could
share with me?
The documentation Freescale sent me claims that U-Boot is in a 4MB SPI
flash, however, the U-Boot that came with the board is unable to
initialize the SPI subsystem per their instructions.
= sf
On Thu, Jul 14, 2011 at 09:45:37PM +0200, Wolfgang Denk wrote:
Dear Ira W. Snyder,
In message 20110714185958.ge19...@ovro.caltech.edu you wrote:
Does anyone have a BDI2000 configuration for the P2020DS that they could
share with me?
Abatron ships a p2020ds.cfg with their firmware
On Thu, Jul 14, 2011 at 08:16:13PM +, McClintock Matthew-B29882 wrote:
On Thu, Jul 14, 2011 at 1:59 PM, Ira W. Snyder i...@ovro.caltech.edu wrote:
The documentation Freescale sent me claims that U-Boot is in a 4MB SPI
flash, however, the U-Boot that came with the board is unable
On Wed, Jan 20, 2010 at 09:51:57AM +0530, Basavaraj Dengi wrote:
Hi,
I am trying to measure the time taken by uboot, from its init till
it jumps to zImage[kernel].
Any suggestions as to which API's to be used for that?
Thanks in advance.
I've used the attached ptx_ts script to
This is a cleaned up version of the U-Boot port provided with the BSP for
the Freescale COM Express P2020 evaluation kit.
Ira W. Snyder (2):
mpc85xx: support board-specific reset function
mpc85xx: support for Freescale COM Express P2020
arch/powerpc/cpu/mpc85xx/cpu.c| 17 +-
arch
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
arch/powerpc/cpu/mpc85xx/cpu.c | 17 -
1 files changed, 16 insertions
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.
Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.
Signed-off-by: Ira W
On Thu, Oct 06, 2011 at 11:18:48PM +0200, Wolfgang Denk wrote:
Dear Ira W. Snyder,
In message 1317159046-11886-3-git-send-email-...@ovro.caltech.edu you wrote:
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well
Hello Timur, Kumar, U-Boot List,
I'm working on porting U-Boot to the Freescale P2020 COM-Express board.
See the ML post from 2011-09-27 titled [PATCH 0/2] mpc85xx: support for
Freescale COM Express P2020.
When it was posted, the port was working on the top of tree U-Boot. This
included
On Thu, Nov 10, 2011 at 11:12:41AM -0600, Timur Tabi wrote:
Ira W. Snyder wrote:
Hello Timur, Kumar, U-Boot List,
I'm working on porting U-Boot to the Freescale P2020 COM-Express board.
See the ML post from 2011-09-27 titled [PATCH 0/2] mpc85xx: support for
Freescale COM Express P2020
On Thu, Nov 10, 2011 at 07:24:00PM +, McClintock Matthew-B29882 wrote:
On Thu, Nov 10, 2011 at 11:47 AM, Timur Tabi ti...@freescale.com wrote:
I boot off of SDCARD (P2020COME_SDCARD_config). To write the U-Boot
image to the microSD card, I use a tool provided with the BSP called
This is a cleaned up version of the U-Boot port provided with the BSP for
the Freescale COM Express P2020 evaluation kit.
Changes v1 - v2:
- fix checkpatch warnings
- remove references to NAND (this board lacks NAND)
- disable CCSR relocation
Ira W. Snyder (2):
mpc85xx: support board-specific
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Unchanged from v1.
arch/powerpc/cpu/mpc85xx/cpu.c | 17 -
1 files
-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Changes v1 - v2:
- fix checkpatch warnings
- remove all references to NAND
- update to top of tree U-Boot
- remove CCSR relocation (top of tree code doesn't work)
I wish I could debug the CCSR relocation issue on this board, but I don't
have a JTAG
On Thu, Nov 10, 2011 at 01:49:20PM -0600, Timur Tabi wrote:
Ira W. Snyder wrote:
I boot using the on-chip ROM, loading U-Boot from SD card to DDR.
The on-chip creates a 4GB TLB, which breaks the CCSR code. My five-patch
patchset fixes this.
Yep, that worked. I applied the patchset
On Thu, Nov 10, 2011 at 10:07:41PM +0200, Felix Radensky wrote:
Hi Ira,
On 11/10/2011 10:00 PM, Felix Radensky wrote:
Hello Timur, Kumar, U-Boot List,
I'm working on porting U-Boot to the Freescale P2020 COM-Express board.
See the ML post from 2011-09-27 titled [PATCH 0/2] mpc85xx:
This is a cleaned up version of the U-Boot port provided with the BSP for
the Freescale COM Express P2020 evaluation kit.
Changes v2 - v3:
- re-enable CCSR relocation
Changes v1 - v2:
- fix checkpatch warnings
- remove references to NAND (this board lacks NAND)
- disable CCSR relocation
Ira W
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
Unchanged from v1.
arch/powerpc/cpu/mpc85xx/cpu.c | 17 -
1 files
-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
The CCSR relocation issue is solved by Timur's 5 part patchset containing
the patch powerpc/85xx: resize the boot page TLB before relocating CCSR.
This patch is checkpatch clean using the checkpatch and configuration file
provided in the patch from
On Fri, Nov 11, 2011 at 07:22:14AM -0600, Kumar Gala wrote:
On Nov 10, 2011, at 3:11 PM, Ira W. Snyder wrote:
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.
Unlike all other
On Fri, Nov 11, 2011 at 04:58:17PM +, McClintock Matthew-B29882 wrote:
On Fri, Nov 11, 2011 at 10:53 AM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Does the board really support different DDR freq or is this copy / paste?
The memory is an SODIMM, but the RAM is configured before U
On Fri, Nov 11, 2011 at 08:36:47PM +, McClintock Matthew-B29882 wrote:
On Fri, Nov 11, 2011 at 11:12 AM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Yep, this is a P2020.
I'll check the Freescale documentation. Hopefully it provides an example
of how to configure the On-Chip ROM to use
On Fri, Nov 11, 2011 at 09:07:23PM +, McClintock Matthew-B29882 wrote:
On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Thanks. That config_sram.dat is exactly what I came up with.
I have my board booting via L2SRAM, but the DDR doesn't get configured
...
FSL-DDR go
That didn't work. Maybe I did something wrong? I'll try again.
Ira
York
On Fri, 2011-11-11 at 14:54 -0800, McClintock Matthew-B29882 wrote:
Adding York who might be able to help more...
-M
On Fri, Nov 11, 2011 at 4:18 PM, Ira W. Snyder i...@ovro.caltech.edu
On Fri, Nov 11, 2011 at 03:10:43PM -0800, Ira W. Snyder wrote:
On Fri, Nov 11, 2011 at 03:02:46PM -0800, York Sun wrote:
Looking good so far, what's the question? You can always override the
register values and try it since you got the interactive debug up.
Well, it doesn't work out
Commit 359ec4931944adb885882deb9b781e4095eabc94 broke support for the
Freescale DMA engine on the 83xx parts. This is due to using registers
which do not exist on 83xx. Remove the attribute register accesses from
the 83xx build.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
Cc: York Sun york
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