Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
Linux dts commit details:
commit <6ca2898df59f> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
C.TOUCH 2.0")
Add support for it.
Reviewed-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan T
support for it.
Reviewed-by: Patrick Delaunay
Signed-off-by: Jagan Teki
---
Changes for v3:
- include dts in MAINTAINERS
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F
arch/arm/dts/Makefile | 1 +
...mp157a
SPI Load isn't mandatory for STM32 builds.
Let's imply instead of select it to get rid of build
issues for non-SPI defconfigs.
Reviewed-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v3:
- add if SPL_SPI_SUPPORT
- collect Patrice r-b
Chan
Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
which has 32bits width 528000Khz frequency.
Add DDR configuration via dtsi.
Reviewed-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v3:
- fixed cosmetic s/Khz/kHz
- collect Patrice r-b
complete platform solutions.
Linux commit details:
commit <30f9a9da4ee1> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
SoM")
Add support for it.
Reviewed-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v3:
- collect Patrice r-
files in Makefile
- collect Patrice r-b
Any inputs?
Jagan.
Jagan Teki (8):
ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM
ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3
ARM: stm32: Imply SPL_SPI_LOAD
board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
board: stm32
Hi Patrick,
On Tue, Mar 16, 2021 at 7:16 PM Patrick DELAUNAY
wrote:
>
> Hi Jagan,
>
> On 3/15/21 6:32 PM, Jagan Teki wrote:
> > Engicam MicroGEA STM32MP1 Micro SOM has mounted 1x4Gb DDR3
> > which has 16bits width 533Mhz frequency.
> >
> > Add DDR configur
M2.2 Starter Kit")
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- add Linux commit details
arch/arm/dts/Makefile |1 +
.../imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi | 31 +
arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts | 97 +
arch/arm/dts
Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
Linux dts commit details:
commit ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
C.TOUCH 2.0")
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- add Linux commit details
arch/arm/dt
of Engicam baseboards
for creating complete platform solutions.
Linux dts commit details:
commit <470d6dad5ddd> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
SoM")
Add support for it.
Signed-off-by: Matteo Lisi
Signed-off-by: Jagan Teki
---
Changes for v2:
- add Linux commi
Move the redundant config item like SPL, memory-related
across all imx8mm config files in the common config header,
imx8mm-common.h
Verified the built files, seems almost the same as before.
Cc: Tim Harvey
Cc: Adam Ford
Cc: Peng Fan
Cc: Teresa Remmet
Cc: Igor Opaniuk
Signed-off-by: Jagan
/soc@0
aips1
aips2
aips3
clk
iomuxc
osc_24m
are common node enablements across imx8mm platform for
dm-spi, dm-pre-reloc stages.
Move them into common dtsi, imx8mm-u-boot.dtsi
Cc: Tim Harvey
Cc: Adam Ford
Cc: Peng Fan
Cc: Teresa Remmet
Cc: Igor Opaniuk
Signed-off-by: Jagan Teki
---
Changes
a1 in commit messages.
Any inputs?
Jagan.
Jagan Teki (5):
arm64: dts: imx8mm: Add common -u-boot.dtsi
configs: Add imx8mm-common header
arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
board: imx8mm: Add Engicam i.Core
t;)
Add support for it.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F
arch/arm/dts/Makefile | 1 +
...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi | 51 ++
...15
Micro SoM.
MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
Linux dts commit details:
commit ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 board")
Add support for it.
Signed-off-by:
Engicam MicroGEA STM32MP1 Micro SOM has mounted 1x4Gb DDR3
which has 16bits width 533Mhz frequency.
Add DDR configurations via dtsi.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
...m32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi | 121
<0be81dfaeaf8> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
SoM")
Add support for it.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F
.../dts/stm32mp157a-microgea-stm32m
Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
Linux dts commit details:
commit <6ca2898df59f> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
C.TOUCH 2.0")
Add support for it.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- col
for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F
arch/arm/dts/Makefile | 1 +
...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi | 51 ++
.../stm32mp157a-icore-stm32mp1-edimm
SPI Load isn't mandatory for STM32 builds.
Let's imply instead of select it to get rid of build
issues for non-SPI defconfigs.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
arch/arm/mach-stm32mp/Kconfig | 2 +-
1 file changed, 1
Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
which has 32bits width 528000Khz frequency.
Add DDR configuration via dtsi.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
.../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119
complete platform solutions.
Linux commit details:
commit <30f9a9da4ee1> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
SoM")
Add support for it.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
arch/arm
Patch series for Engicam i.Core and MicroGEA SoM and it's
associated carrier board dts(i) support.
Changes for v2:
- add Linux dts commit ids in commit messages
- drop CONFIG_BOARD_EARLY_INIT_F
- order dts files in Makefile
- collect Patrice r-b
Any inputs?
Jagan.
Jagan Teki (9):
ARM
On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec wrote:
>
> Now that proper DM clock and reset driver exists for Display Engine 2
> and 3, remove all clock and reset related code and use appropriate
> framework instead.
>
> Signed-off-by: Jernej Skrabec
> ---
Reviewed-by: Jagan Teki
On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec wrote:
>
> These clocks and resets are needed for video drivers.
>
> Cc: Lukasz Majewski
> Signed-off-by: Jernej Skrabec
> ---
Reviewed-by: Jagan Teki
z Majewski
> Signed-off-by: Jernej Skrabec
> ---
Reviewed-by: Jagan Teki
On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec wrote:
>
> This commit adds standalone driver for DW HDMI PHY. It deprecates code
> which is included in sunxi dw-hdmi platform driver.
>
> Signed-off-by: Jernej Skrabec
> ---
> arch/arm/mach-sunxi/Kconfig | 1 +
> drivers/video/sunxi/M
On Sat, Feb 27, 2021 at 6:21 PM Marek Vasut wrote:
>
> On 2/27/21 8:54 AM, Jagan Teki wrote:
> > Hi Marek,
> >
> > On Sat, Feb 27, 2021 at 3:44 AM Marek Vasut wrote:
> >>
> >> Add support for ethernet on the imx8mn-ddr4-evk.
> >>
> >>
needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.
Add support for it.
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
...rogea-stm32mp1-microdev
Engicam MicroGEA STM32MP1 Micro SOM has mounted 1x4Gb DDR3
which has 16bits width 533Mhz frequency.
Add DDR configurations via dtsi.
Signed-off-by: Jagan Teki
---
...m32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi | 121 ++
1 file changed, 121 insertions(+)
create mode 100644 arch
Micro SoM.
MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
Add support for it.
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
...-microgea-stm32mp1-microdev2.0-u-boot.dtsi
Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi | 51
.../stm32mp157a-icore-stm32mp1-ctouch2.dts| 47
is an EDIMM SoM based on STM32MP157A from Engicam.
i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
...mp157a-icore-stm
MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S
MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.
Add support for it.
Signed-off-by: Jagan
SPI Load isn't mandatory for STM32 builds.
Let's imply instead of select it to get rid of build
issues for non-SPI defconfigs.
Signed-off-by: Jagan Teki
---
arch/arm/mach-stm32mp/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/Kcon
Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
which has 32bits width 528000Khz frequency.
Add DDR configuration via dtsi.
Signed-off-by: Jagan Teki
---
.../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 ++
1 file changed, 119 insertions(+)
create mode 100644 arch
complete platform solutions.
Add support for it.
Signed-off-by: Jagan Teki
---
arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 +++
1 file changed, 196 insertions(+)
create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi
diff --git a/arch/arm/dts/stm32mp157a-icore
roGEA STM32MP1 Micro SoM dtsi
patch 7: MicroGEA DDR3 config
patch 8 - 9: MicroGEA STM32MP1 with MicroDev 2.0 and 7" OF carriers.
Note: dts(i) patches are Linux Mailing list.
Any inputs?
Jagan.
Jagan Teki (9):
ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM
ARM: dts: stm32: Add Engi
is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile |1 +
.../imx8mm-
Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
.../imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi| 31 ++
arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts | 97
of Engicam baseboards
for creating complete platform solutions.
Add support for it.
Signed-off-by: Matteo Lisi
Signed-off-by: Jagan Teki
---
arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 232 +++
1 file changed, 232 insertions(+)
create mode 100644 arch/arm/dts/imx8mm-icore
Move the redundant config item like SPL, memory-related
across all imx8mm config files in the common config header,
imx8mm-common.h
Verified the built files, seems almost the same as before.
Cc: Adam Ford
Cc: Peng Fan
Cc: Teresa Remmet
Cc: Igor Opaniuk
Signed-off-by: Jagan Teki
---
include
/soc@0
aips1
aips2
aips3
clk
iomuxc
osc_24m
are common node enablements across imx8mm platform for
dm-spi, dm-pre-reloc stages.
Move them into common dtsi, imx8mm-u-boot.dtsi
Cc: Adam Ford
Cc: Peng Fan
Cc: Teresa Remmet
Cc: Igor Opaniuk
Signed-off-by: Jagan Teki
---
arch/arm/dts/imx8mm
oards
Any inputs?
Jagan.
Jagan Teki (5):
arm64: dts: imx8mm: Add common -u-boot.dtsi
configs: Add imx8mm-common header
arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUC
Hi Marek,
On Sat, Feb 27, 2021 at 3:44 AM Marek Vasut wrote:
>
> Add support for ethernet on the imx8mn-ddr4-evk.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> ---
> arch/arm/dts/imx8mn-evk.dtsi| 1 +
> board/freescale/imx8mn_evk/imx8mn_
Hi Tom,
Please pull this PR.
Summary:
- new GigaDevice flash ids
- fixes for imx, nxp_spi drivers
GitLab CI:
https://gitlab.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/6528
The following changes since commit c28d5d704d3347fcbe5e49ab561973c00bf9337f:
Merge branch '2021-02-25-remove-platf
Hi Suniel,
On Mon, Feb 8, 2021 at 7:02 PM Andre Przywara wrote:
>
> At the moment nvme_read_completion_status() tries to invidate a single
> member of the cqes[] array, which is shady as just a single entry is
> not cache line aligned.
> The structure is dictated by hardware, and with 16 bytes is
On Fri, Feb 19, 2021 at 7:26 AM wrote:
>
> From: Takahiro Kuwano
>
> Some of Spansion/Cypress chips support volatile version of configuration
> registers and it is recommended to update volatile registers in the field
> application due to a risk of the non-volatile registers corruption by
> power
On Fri, Feb 19, 2021 at 7:26 AM wrote:
>
> From: Takahiro Kuwano
>
> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
>
> https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
> https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
>
> The
On Fri, Feb 5, 2021 at 9:41 AM Sean Anderson wrote:
>
> This series adds support for enhanced SPI modes. It was tested on a K210 (DWC
> SSI with QSPI flash).
>
> If anyone has a designware device with QSPI flash attached (especially a DW
> SSI
> APB device), I'd greatly appreciate them testing ou
On Fri, Feb 5, 2021 at 9:41 AM Sean Anderson wrote:
>
> This is useful for extending the default functionality. This mirrors the
> change in Linux commit 46109648052f ("spi: spi-mem: export
> spi_mem_default_supports_op()").
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Bin Meng
> Reviewed-by:
On Fri, Feb 5, 2021 at 9:41 AM Sean Anderson wrote:
>
> This prints some basic metadata about the SPI memory op. This information
> may be used to debug SPI drivers (e.g. determining the expected SPI mode).
> It is also helpful for verifying that the data on the wire matches the data
> intended to
On Thu, Jan 28, 2021 at 9:59 PM Bernhard Kirchen wrote:
>
> "sf protect lock" did only protect against accidental writes by
> software. it did not lock down the config or block-protection registers
> if the WP# pin was deasserted. hardware write protection was never
> enabled for these devices.
>
On Tue, Feb 23, 2021 at 6:29 PM Adam Ford wrote:
>
> On Tue, Jan 19, 2021 at 6:12 AM Pratyush Yadav wrote:
> >
> > On 18/01/21 03:32PM, Adam Ford wrote:
> > > On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
> > > rate the clock was able to set. When checking for errors, it
On Thu, Jan 28, 2021 at 9:59 PM Bernhard Kirchen wrote:
>
> prior to using the WBPR (write block protection register) command to
> write new block protection register values, the WREN command must be
> sent. otherwise the new values are not applied.
>
> Signed-off-by: Bernhard Kirchen
> ---
>
>
On Thu, Jan 28, 2021 at 9:49 PM Bernhard Kirchen wrote:
>
> it is not guaranteed that there is a human readable message when the
> lock or unlock operation failed. make sure there is a message emitted
> by the "sf protect" implementation if the subcommand failed.
>
> Signed-off-by: Bernhard Kirche
On Mon, Jan 25, 2021 at 8:29 AM Su Baocheng wrote:
>
> From: Su Baocheng
>
> The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents
> various models. From Winbond's website, I could only find 3 types of
> them:
>
> W25Q128JV-IQ/JQ
> datasheet:https://www.winbond.com/resour
On Wed, Jan 6, 2021 at 6:29 PM Bin Meng wrote:
>
> U-Boot coding convention prefers tabs over spaces.
>
> Signed-off-by: Bin Meng
> ---
Applied to u-boot-spi/master
On Sat, Oct 31, 2020 at 9:50 PM Alper Nebi Yasak
wrote:
>
> Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on
> rk3399-gru-kevin:
>
> => sf probe
> SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total
> 8 MiB
> => sf erase 0x60 0x20
>
On Wed, Feb 3, 2021 at 10:24 PM Marek Vasut wrote:
>
> The set_speed() callback should configure the bus speed, make it so.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Stefano Babic
> ---
> V2: Rename dev_get_platdata() to dev_get_plat()
> ---
Applied to u-boot-spi/master
ock before writing a bad block marker
Hongwei Zhang (1):
mtd: spi-nor-ids: add Micron MT25QL01G flash
Jagan Teki (3):
cl-som-imx7: Switch to DM_SPI/DM_SPI_FLASH
cm_fx6: Switch to full DM-aware
dh_imx6: Switch to full DM-aware
Lad Prabhakar (1):
mtd: spi-nor-ids: Add Winb
On Tue, Dec 8, 2020 at 2:42 PM Patrick DELAUNAY
wrote:
>
> Hi,
>
> it seems that the GPT partitionning is not regonized in SPL in part.c;
>
> see the trace:
>
> ## Unknown partition table type 0
>
> But you have correclty activate the GPT support in SPL
>
> CONFIG_SPL_EFI_PARTITION=y
er payloads can be
> transferred via FEL as well.
>
> Tested on A64, H5 and H6.
>
> Signed-off-by: Andre Przywara
> ---
Acked-by: Jagan Teki
On Fri, Nov 13, 2020 at 8:32 AM SkyLake Huang
wrote:
>
> From: "SkyLake.Huang"
>
> This patch adds support for MTK SPI NOR controller, which you
> can see on mt7622 & mt7629.
>
> This controller is designed only for SPI NOR. We can't adjust
> its bus clock dynamically. Set clock in dts instead.
>
set
CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
CONFIG_EFI_LOADER_HII=y
CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
CONFIG_EFI_UNICODE_CAPITALIZATION=y
# CONFIG_EFI_UNICODE_COLLATION_PROTOCOL is not set
CONFIG_EFI_PLATFORM_LANG_CODES="en-US"
CONFIG_EFI_GRUB_ARM32_WORKAROUND=y
CONFIG_EFI_RNG_PROTOCOL=y
#
Reviewed-by: Simon Glass
Reviewed-by: Jagan Teki
Hi Tom,
Please pull this PR.
Summary:
- PinePhone support (Samuel)
- V3/S3 support (Icenowy)
thanks,
Jagan.
The following changes since commit de865f7ee1d9b6dff6e265dee44509c8274ea606:
Merge tag 'efi-2021-01-rc3' of
https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-11-14 09:47:33 -
On Fri, Oct 30, 2020 at 3:05 PM Weijie Gao wrote:
>
> This patch adds USB PHY driver for MediaTek MT7620 SoC
>
> Signed-off-by: Weijie Gao
> ---
> v2 changes: none
> ---
> drivers/phy/Kconfig | 7 +++
> drivers/phy/Makefile | 1 +
> drivers/phy/mt7620-usb-phy.c | 113 +++
+
> + mt7620_wdt_ping(priv);
> +
> + clrbits_32(priv->regs + TIMER_CTL, TIMER_ENABLE);
> +
> + return 0;
> +}
> +
> +static int mt7620_wdt_reset(struct udevice *dev)
> +{
> + struct mt7620_wdt *priv = dev_get_priv(dev);
> +
> + mt7620_wdt_ping(priv);
> +
> + return 0;
> +}
> +
> +static int mt7620_wdt_expire_now(struct udevice *dev, ulong flags)
> +{
> + struct mt7620_wdt *priv = dev_get_priv(dev);
> +
> + mt7620_wdt_start(dev, 1, flags);
> +
> + /* 0 will disable the timer, so use 1 instead */
> + writel(1, priv->regs + TIMER_LOAD);
Better replace the magic number with macro.
Otherwise,
Reviewed-by: Jagan Teki
On Fri, Oct 30, 2020 at 3:05 PM Weijie Gao wrote:
>
> This patch adds spi controller support for MediaTek MT7620 SoC.
>
> The SPI controller supports two chip selects. These two chip selects are
> implemented as two separate register groups, but they share the same bus
> (DI/DO/CLK), only CS pins
On Mon, Oct 26, 2020 at 12:54 AM Sean Anderson wrote:
>
> On 10/24/20 10:58 AM, Jagan Teki wrote:
> > On Sat, Oct 24, 2020 at 12:14 AM Jagan Teki
> > wrote:
> >>
> >> On Sat, Oct 17, 2020 at 4:28 AM Sean Anderson wrote:
> >>>
> >>>
On Mon, Oct 26, 2020 at 7:46 PM Icenowy Zheng wrote:
>
> This patchset tries to add support for Allwinner V3/S3 and Pine64
> PineCube to U-Boot.
>
> First 3 patches adds support for Allwinner V3/S3 to U-Boot by expanding
> the code of V3s and add compatible strings to individual drivers.
>
> Then
On Mon, Oct 26, 2020 at 7:51 PM Icenowy Zheng wrote:
>
> PineCube is an IP camera development kit released by Pine64.
>
> It comes with the following compoents:
>
> - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC,
> a power-only microUSB connector, a USB Type-A connector, a 10/1
On Sat, Oct 24, 2020 at 8:52 PM Samuel Holland wrote:
>
> The PinePhone is a smartphone produced by Pine64, with an A64 SoC,
> 2 or 3 GiB LPDDR3 RAM, 16 or 32 GiB eMMC, 720x1440 MIPI-DSI panel,
> and Quectel EG25-G modem.
>
> There are two main board revisions: 1.1 for early adopters, and 1.2
> fo
: Jagan Teki
Signed-off-by: Suniel Mahesh
---
Changes for v4:
- none
arch/arm/dts/Makefile| 1 +
arch/arm/dts/px30-px30-core-ctouch2.dts | 22 +
arch/arm/mach-rockchip/px30/Kconfig | 7 ++
board/engicam/px30_core/MAINTAINERS | 6 ++
configs/px30-core-ctouch2
o mount on top of this Carrier board
for creating complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Michael Trimarchi
---
Changes for v4:
- none
arch/arm/dts/px30-engicam-ctouch2.dtsi | 8
1 file changed, 8 insertions(+)
create mode 10064
This would be useful and recommended boot flow for new boards
which has doesn't have the DDR support yet in mainline.
Sometimes it is very useful for debugging mainline DDR support.
Documen it for px30 boot flow.
Signed-off-by: Jagan Teki
---
Changes for v4:
- none
doc/board/roc
-off-by: Jagan Teki
Signed-off-by: Suniel Mahesh
---
Changes for v4:
- drop ram change
- on top of
https://patchwork.ozlabs.org/project/uboot/patch/20201001184003.3704604-1-he...@sntech.de/
arch/arm/dts/Makefile | 1 +
arch/arm/dts/px30-px30-core-edimm2.2.dts | 21
The existing common code for Engicam boards uses i.MX6,
so attach that into i.MX6 Engicam boards so-that adding
new SoC variants of Engicam boards become meaningful.
Add support for it.
Cc: Stefano Babic
Signed-off-by: Jagan Teki
---
Changes for v4:
- none
board/engicam/common/Kconfig | 8
PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Michael Trimarchi
Reviewed-by: Kever Yang
---
Changes for v4:
- none
arch/arm/dts/px30-engicam-common.d
baseboards are,
- EDIMM2.2
- C.TOUCH 2.0
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Michael Trimarchi
Reviewed-by: Kever Yang
---
Changes for v4:
- none
arch/arm/dts/px30-px30-core.dtsi | 232 +++
1 file changed, 232 insertions(+)
create mode 100644
TARGET_EVB_PX30 can be possible to use other px30 boards.
Add the help text for existing EVB, so-that the new boards
which are resuing this config option can mention their board
help text.
This would help to track which boards are using EVB_PX30 config.
Signed-off-by: Jagan Teki
Reviewed-by
master
- on top of Heiko, ram patch
https://patchwork.ozlabs.org/project/uboot/patch/20201001184003.3704604-1-he...@sntech.det/
thanks,
Jagan.
Jagan Teki (7):
arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit
rockchip: px30: Add EVB_PX30 Kconfig help
board: engicam: Attach i.MX6
DDR2/3 initialized would require a code modification.
>
> So add Kconfig options similar to RK3399 to allow selecting the DDR4
> and LPDDR2/3 options instead, while DDR3 stays the default as before.
>
> Signed-off-by: Heiko Stuebner
> ---
Reviewed-by: Jagan Teki
On Thu, Oct 22, 2020 at 1:22 PM Padmarao Begari
wrote:
>
> This doc describes the procedure to build, flash and
> boot Linux using U-boot on Microchip MPFS Icicle Kit.
>
> Signed-off-by: Padmarao Begari
> ---
> doc/board/index.rst | 1 +
> doc/board/microchip/index.rst |
On Fri, Jul 31, 2020 at 1:23 AM Alex Nemirovsky
wrote:
>
> From: Pengpeng Chen
>
> Add SPI Flash controller driver for Cortina Access
> CA SoCs
>
> Signed-off-by: Pengpeng Chen
> Signed-off-by: Alex Nemirovsky
> CC: Jagan Teki
> CC: Vignesh R
Applied to u-boot-spi/master
On Fri, Jul 31, 2020 at 1:23 AM Alex Nemirovsky
wrote:
>
> Add SPI NOR support for Cortina Access
> Presidio Engineering Board
>
> Signed-off-by: Alex Nemirovsky
> CC: Jagan Teki
> CC: Vignesh R
> CC: Tom Rini
>
> Add err processing while probe sf device
>
>
On Sat, Oct 24, 2020 at 12:14 AM Jagan Teki wrote:
>
> On Sat, Oct 17, 2020 at 4:28 AM Sean Anderson wrote:
> >
> > This series adds support for SPI on the Kendryte K210. This covers the MMC
> > slot and SPI flash on the Sipeed Maix Bit.
> >
> > This ser
On Thu, Sep 3, 2020 at 10:37 AM Samuel Holland wrote:
>
> All,
>
> This patch series implements a feature to automatically choose the
> right PinePhone device tree by probing the hardware. It then extends
> the functionality to pass the chosen DTB name to the boot command.
> Finally, I add device
Enable Console multiplexing in ROCKPi N8 which would is
required to video out the console buffer.
Enable it.
Signed-off-by: Jagan Teki
---
configs/rock-pi-n8-rk3288_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/rock-pi-n8-rk3288_defconfig
b/configs/rock-pi-n8
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.
This will help to get serial out messages.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
b/arch/arm/dts/rk3288
Like, rk3399 the rk3288 also supports 4K resolution.
So, enable it for rk3288 with HDMI platforms.
Right now, rockchip video drivers are supporting for rk3288,
rk3399 SoC families, so mark the 4K resolution by default
if it's an HDMI video out.
Signed-off-by: Jagan Teki
Cc: Anatolij Gust
Enable Console multiplexing in ROCKPi N10 which would is
required to video out the console buffer.
Enable it.
Signed-off-by: Jagan Teki
---
configs/rock-pi-n10-rk3399pro_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig
b/configs/rock-pi-n10
On Sat, Oct 24, 2020 at 12:17 AM Jagan Teki wrote:
>
> On Sun, Oct 18, 2020 at 5:39 PM Shuying Li wrote:
> >
> > From: Libunko
> >
> > Add initial support for Nanopi M4V2 board.
> >
> > Specification
> > - Rockchip RK3399
> > - Dual-C
> + regulator-always-on;
> + vin-supply = <&vdd_5v>;
> +};
> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
> b/board/rockchip/evb_rk3399/MAINTAINERS
> index 4c889e06a6..9967d68a88 100644
> --- a/board/rockchip/evb_rk3399/MAINTAINERS
> +++ b/board/rockch
t; spi: dw: Rename registers to match datasheet
> spi: dw: Remove spi_enable_chip
> spi: dw: Rearrange struct dw_spi_priv
> spi: dw: Add SoC-specific compatible strings
> spi: dw: Add support for multiple CTRLR0 layouts
> spi: dw: Document devicetree binding
> spi: dw: Add mem_ops
> riscv: Add device tree bindings for SPI
> riscv: Add support for SPI on Kendryte K210
Except for this patch with HUSH PARSER missing rest look fine for me.
Reviewed-by: Jagan Teki
On Thu, Oct 1, 2020 at 8:32 AM wrote:
>
> From: Takahiro Kuwano
>
> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
> The datasheet can be found in https://community.cypress.com/docs/DOC-15165
>
> This device family can be configured to non-uniform sector layout, while
> U-B
On Fri, Aug 7, 2020 at 10:43 PM Sean Anderson wrote:
>
> Preprocessing out large sections of the file is confusing and makes it
> difficult to follow the control flow. Presumably these were initially added
> to make porting easier, but this code has not been synced with Linux since
> it was introd
On Sat, Jul 11, 2020 at 10:23 PM Jagan Teki wrote:
>
> On Wed, Jul 8, 2020 at 6:25 PM Stefano Babic wrote:
> >
> > On 08.07.20 13:40, Jagan Teki wrote:
> > > On Sat, Jun 13, 2020 at 9:11 PM Tom Rini wrote:
> > >>
> > >> On Sat,
On Mon, Sep 14, 2020 at 7:04 PM Robert Marko wrote:
>
> According to the mx25l12805d datasheet it supports using 4K or 64K sectors.
> So lets add the SECT_4K to enable 4K sector usage.
>
> Datasheet:
> https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf
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