Commit 8a0eccb1056b313b45ab62e3aac400f339aa71b4 breaks netconsole. src_ip
must not be converted to host byte order, because nc_ip is already stored
in network byte order (see string_to_ip(), called by getenv_IPaddr()).
Signed-off-by: Michael Walle mich...@walle.cc
Cc: Joe Hershberger joe.hershber
Instead of using the serverip we get from the DHCP server, use the
broadcast address. That way it isn't necessary to use a special DHCP
configuration to set the netconsole peer.
Signed-off-by: Michael Walle mich...@walle.cc
Cc: Prafulla Wadaskar prafu...@marvell.com
---
Hi Prafulla,
although
On Thu, October 4, 2012 12:47, Prafulla Wadaskar wrote:
-Original Message-
From: Michael Walle [mailto:mich...@walle.cc]
Sent: 03 October 2012 21:15
To: u-boot@lists.denx.de
Cc: Michael Walle; Prafulla Wadaskar
Subject: [PATCH] lsxl: set ncip to broadcast address
Instead of using
Instead of using the serverip we get from the DHCP server, implicitly use
the broadcast address, which is automatically set when no ncip environment
variable is set. That way it isn't necessary to use a special DHCP
configuration to set the netconsole peer.
Signed-off-by: Michael Walle mich
Hi Prafulla,
Am Donnerstag 04 Oktober 2012, 18:54:25 schrieb Michael Walle:
Instead of using the serverip we get from the DHCP server, implicitly use
the broadcast address, which is automatically set when no ncip environment
variable is set. That way it isn't necessary to use a special DHCP
Hi Tom, Hi Prafulla,
Am Sonntag 04 November 2012, 19:49:59 schrieb Tom Rini:
Hey all,
With the official closing of the merge window just past us now, I've
tagged v2013.01-rc1.
Wow that was fast ;)
Prafulla, Tom, can someone of you take care of the following patch:
it into the 2015.04 release.
Michael Walle (3):
lsxl: use default load addresses for legacy boot
lsxl: place the dtb below the inital ramdisk
lsxl: switch from bootm to bootz for boot commands
include/configs/lsxl.h | 42 +-
1 file changed, 25 insertions(+), 17
by the distributions and thus cannot be easily changed. By using
the bootz command we can load the compressed image to a higher memory
address and the decompressor doesn't have to reloacte the image.
Signed-off-by: Michael Walle mich...@walle.cc
---
include/configs/lsxl.h | 34
-off-by: Michael Walle mich...@walle.cc
---
include/configs/lsxl.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index a14bfe3..6c8e369 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -127,9 +127,9
-by: Michael Walle mich...@walle.cc
---
include/configs/lsxl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 6c8e369..dff9025 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -125,7 +125,7 @@
hdpart
Hi there,
I stumbled across a situation where the SPI flash on my board was write
protected and i could not unlock it in the bootloader. This is
especially unfortunate because the recovery mechanism relies on the
bootloader to be able to erase the environment.
So any ideas how to fix this?
The README describes the recovery method which can be used if the NAS box
is not reachable anymore. Addionally, it describes the different boot
scripts.
Signed-off-by: Michael Walle mich...@walle.cc
---
board/buffalo/lsxl/README | 139 ++
1 file
Hi Luka,
Am 2015-02-16 11:48, schrieb Luka Perkov:
Do you have any other pending work for which you plan to send patches?
no, this was the last one. forgot it in the previous series, sorry.
-michael
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for the noise :(
Acked-By: Michael Walle mich...@walle.cc (for the lsxl board part)
-michael
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Hi Joe,
Am 2015-05-04 21:55, schrieb Joe Hershberger:
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index 487875c..45dd788 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -230,16 +230,6 @@ static void rescue_mode(void)
uchar enetaddr[6];
Am 2015-04-16 20:32, schrieb Jagan Teki:
On 9 February 2015 at 04:57, Michael Walle mich...@walle.cc wrote:
Hi there,
I stumbled across a situation where the SPI flash on my board was
write
protected and i could not unlock it in the bootloader. This is
especially
unfortunate because
Am 2016-08-05 14:06, schrieb Michael Walle:
there doesn't seem to be a dedicated filesystem maintainer, but I've
included the original committer for the ext4 write support.
I guess the ext4 write support does not work on big-endian machines.
As far as I see, almost no fields of the ext4
All fields were accessed directly instead of using the proper byte swap
functions. Thus, ext4 write support was only usable on little-endian
architectures. Fix this.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
Ok this patch is huge, please comment. I know, checkpatch fails b
le32_to_cpu() must only convert the revision_level and not the boolean
result.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 4eb4e18..b00b84f
Instead of __{be,le}{16,32}_to_cpu use {be,le}{16,32}_to_cpu.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_common.c | 90 +--
fs/ext4/ext4_write.c | 14
fs/ext4/ext4fs.c | 2 +-
include/ext_common.h | 4
Change all the types of ext2/4 fields to little endian types and all the
JBD fields to big endian types. Now we can use sparse (make C=1) to check
for statements where we need byteswaps.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_journal.h | 40 +++
i
Hi Tom, Uma and all,
there doesn't seem to be a dedicated filesystem maintainer, but I've
included the original committer for the ext4 write support.
I guess the ext4 write support does not work on big-endian machines. As
far as I see, almost no fields of the ext4 structures within the write
Am 2016-08-05 14:06, schrieb Michael Walle:
Hi Tom, Uma and all,
there doesn't seem to be a dedicated filesystem maintainer, but I've
included the original committer for the ext4 write support.
Hm, no Uma :(
<uma.shan...@samsung.com>: host mailin.samsung.com[203.254.224.12] said:
550
Hi Stefan,
Am 2016-08-14 03:50, schrieb Stefan Bruens:
On Freitag, 12. August 2016 15:16:20 CEST Michael Walle wrote:
All fields were accessed directly instead of using the proper byte
swap
functions. Thus, ext4 write support was only usable on little-endian
architectures. Fix this.
Signed
Am 2016-08-14 03:50, schrieb Stefan Bruens:
On Freitag, 12. August 2016 15:16:20 CEST Michael Walle wrote:
All fields were accessed directly instead of using the proper byte
swap
functions. Thus, ext4 write support was only usable on little-endian
architectures. Fix this.
Signed-off
All fields were accessed directly instead of using the proper byte swap
functions. Thus, ext4 write support was only usable on little-endian
architectures. Fix this.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
Changes:
v4:
- convert "unsigned int" to __le32 pointer in
Am 2016-08-29 10:46, schrieb Michael Walle:
[..snip..]
@@ -149,10 +169,10 @@ static void delete_double_indirect_block(struct
ext2_inode *inode)
int i;
short status;
static int prev_bg_bmap_idx = -1;
- long int blknr;
+ uint32_t blknr;
int remainder
Change all the types of ext2/4 fields to little endian types and all the
JBD fields to big endian types. Now we can use sparse (make C=1) to check
for statements where we need byteswaps.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_journal.h | 40 +++
i
Instead of __{be,le}{16,32}_to_cpu use {be,le}{16,32}_to_cpu.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_common.c | 90 +--
fs/ext4/ext4_write.c | 14
fs/ext4/ext4fs.c | 2 +-
include/ext_common.h | 4
All fields were accessed directly instead of using the proper byte swap
functions. Thus, ext4 write support was only usable on little-endian
architectures. Fix this.
Signed-off-by: Michael Walle <mich...@walle.cc>
Reviewed-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Tested-by:
le32_to_cpu() must only convert the revision_level and not the boolean
result.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 567350f..4a003cf
irentlen)" loops. Suggested by Stefan Brüns
(patch 0005)
Michael Walle (4):
ext4: change structure fields to __le/__be types
ext4: use kernel names for byte swaps
ext4: fix endianess problems in ext4 write support
ext4: fix wrong usage of le32_to_cpu()
fs/ext4/ext4_co
All fields were accessed directly instead of using the proper byte swap
functions. Thus, ext4 write support was only usable on little-endian
architectures. Fix this.
Signed-off-by: Michael Walle <mich...@walle.cc>
Reviewed-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
Tested-by:
Change all the types of ext2/4 fields to little endian types and all the
JBD fields to big endian types. Now we can use sparse (make C=1) to check
for statements where we need byteswaps.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_journal.h | 40 +++
i
Instead of __{be,le}{16,32}_to_cpu use {be,le}{16,32}_to_cpu.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_common.c | 90 +--
fs/ext4/ext4_write.c | 14
fs/ext4/ext4fs.c | 2 +-
include/ext_common.h | 4
le32_to_cpu() must only convert the revision_level and not the boolean
result.
Signed-off-by: Michael Walle <mich...@walle.cc>
---
fs/ext4/ext4_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 567350f..4a003cf
direntlen is always >= 8. Therefore, the loop condition is always true.
Signed-off-by: Michael Walle <mich...@walle.cc>
Suggested-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
fs/ext4/ext4_common.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
From: Michael Walle <michael.wa...@kontron.com>
This patch series fixes write support on big-endianness architectures.
Changes:
v2:
- instead of INC_X/DEC_X macros, use inline functions per structure
field. Suggested by Stefan Brüns. (patch 0003)
- optimize "while (dir
[CC Wolfgang because he's the ppc maintainer]
Hi,
I've build a powerpc64 cross compile toolchain with multilib support
(using http://crosstool-ng.org/). Eg. the default one is 64bit and you
can choose a 32 bit compile with "-m32". I can compile the bootloader
but linking fails with "libgcc
Am 2018-06-07 11:07, schrieb Bastian Germann:
Hello Michael,
I tried to use the MTD layer but that did not work even though I set
the
flash in the Linux device tree read-write. I cannot remember the output
exactly as it is some time ago that I tried (with Debian).
Cheers,
Bastian
+
://patchwork.ozlabs.org/patch/909973/
Signed-off-by: Michael Walle
Tested-by: Michael Walle
---
arch/arm/dts/kirkwood-lsxl.dtsi | 4
arch/arm/mach-kirkwood/include/mach/config.h | 1 -
configs/lschlv2_defconfig| 3 +++
configs/lsxhl_defconfig
Synchronize it with the LS-XHL board.
Signed-off-by: Michael Walle
---
configs/lschlv2_defconfig | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 23e68a00ea..f2763221a1 100644
--- a/configs
Am 6. Juni 2018 11:38:56 MESZ schrieb Bastian Germann
:
>Signed-off-by: Bastian Germann
>---
> board/buffalo/lsxl/README | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
>diff --git a/board/buffalo/lsxl/README b/board/buffalo/lsxl/README
>index ef5ed42880..3ede081776
Hi Chris,
thanks for your efforts. This basically works for me on my Kirkwood
LSCHLv2 board. So you may add
Tested-by: Michael Walle
But there are some issues. See below.
[snip]
-#if defined(CONFIG_PHYLIB)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
+#if defined(CONFIG_DM_ETH
Am 2018-05-08 00:54, schrieb Chris Packham:
This matches the compatible string used by the Linux kernel. This will
allow u-boot to use the same device tree files.
This patch is still missing to make SPI on kirkwoods work. Is there
anything missing which prevents it from being applied?
the phy-mode property to my dts ;) Will
post a patch for lsxl later.
Tested-by: Michael Walle
---
Changes in v3:
- select PHYLIB (thanks Michael)
- parse phy info from subnode
Changes in v2:
- create __mvgbe_phy_init and mvgbe_alloc_buffers helper functions
- move device tree reads
Am 2018-11-05 10:58, schrieb Jagan Teki:
On Mon, May 7, 2018 at 2:40 PM Jagan Teki
wrote:
kirkwood now support dt along with platform data,
respective boards need to switch into dm for the same.
Signed-off-by: Jagan Teki
---
Changes for v3:
- rebased master
- Move kconfig option if DM_SPI
Switch from legacy IDE driver to sata_mv driver.
Signed-off-by: Michael Walle
---
configs/lschlv2_defconfig | 4 ++--
configs/lsxhl_defconfig | 4 ++--
include/configs/lsxl.h| 23 ++-
3 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/configs
This fixes a compile error on kirkwood.
Signed-off-by: Michael Walle
---
drivers/ata/sata_mv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index d13695d79e..87ea95f75d 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata
Please note that this patchset depends on the following series:
https://patchwork.ozlabs.org/cover/1055937/
(ARM: kirkwood: migrate to DM_USB)
https://patchwork.ozlabs.org/patch/1054403/
(sata: sata_mv: Add DM support to enable CONFIG_BLK usage)
Michael Walle (4):
sata: sata_mv: use
The kirkwood devices are compatible with this driver.
Signed-off-by: Michael Walle
---
drivers/ata/sata_mv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index b691107dc0..2a630d46c1 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata
Fix the worng include and offset macros.
Signed-off-by: Michael Walle
---
drivers/ata/sata_mv.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 87ea95f75d..b691107dc0 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers
Add a command to control the watchdog devices. This is useful if the
watchdog is rather long running (eg. seconds) and it should be
controlled by scripts. It is also handy during debugging.
Signed-off-by: Michael Walle
---
cmd/Kconfig | 6 +++
cmd/Makefile | 1 +
cmd/wdt.c| 174
Both the network as well as the USB driver are not working with the
data cache enabled.
Signed-off-by: Michael Walle
---
include/configs/lsxl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 9d4be18413..728263910e 100644
--- a/include
Hi Chris,
Am 2019-03-13 08:47, schrieb Chris Packham:
Enable CONFIG_DM_USB and CONFIG_BLK.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Tested-by: Michael Walle
works at least after I switch off the dcache, but that another issue ;)
Thanks,
-michael
---
Changes in v3: None
From: Michael Walle
The boot commands have changed in the environment. Add a note about the
incompatible change and how resolve the issue in the board's README.
Signed-off-by: Michael Walle
---
Hi Stefan,
now that the patches are in the marvell tree and I guess they'll make it
into the next
The boot commands have changed in the environment. Add a note about the
incompatible change and how resolve the issue in the board's README.
Signed-off-by: Michael Walle
---
changes since v2:
- whoops wrong mail address for author and sob-tag, sorry about
that
Happy holidays
board
Signed-off-by: Michael Walle
---
Btw if anybody notices the compatible string difference to the rv3029
driver, ie mc,rv3029 vs microcrystal,rv8803. The "mc" prefix is actually
the legacy one.
drivers/rtc/Kconfig | 10 +++
drivers/rtc/Makefile | 1 +
drivers/rtc/rv88
Signed-off-by: Michael Walle
---
Btw if anybody notices the compatible string difference to the rv3029
driver, ie mc,rv3029 vs microcrystal,rv8803. The "mc" prefix is actually
the legacy one.
changes since v1:
- enable driver in sandbox_defconfig and sandbox64_defconfig
different values at startup.
Signed-off-by: Michael Walle
---
since v1:
- Removed the and-mask. Since there were no more comments I did some tests
and apparently there are no compiler warnings.
include/net.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/net.h b
different values at startup.
Signed-off-by: Michael Walle
---
include/net.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/net.h b/include/net.h
index a54d5eeac5..8215316bd3 100644
--- a/include/net.h
+++ b/include/net.h
@@ -816,7 +816,7 @@ static inline int
Am 2019-08-23 05:17, schrieb Bin Meng:
On Fri, Aug 23, 2019 at 6:08 AM Michael Walle wrote:
The net_random_ethaddr() tries to get some entropy from different
startup times of a board. The seed is initialized with get_timer()
which
has only a granularity of milliseconds. We can do better
Am 2019-05-15 16:58, schrieb Tom Rini:
On Fri, May 10, 2019 at 09:50:45PM +, Joe Hershberger wrote:
Hi Vladimir and Tom,
On Thu, May 9, 2019 at 7:51 AM Vladimir Oltean
wrote:
>
> On 09.05.2019 02:05, Vladimir Oltean wrote:
> > On 5/9/19 1:55 AM, Tom Rini wrote:
> >> On Wed, May 08, 2019
, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).
Signed-off-by: Michael Walle
Reviewed-by: Jagan Teki
---
changes since v1:
- fixed typo, thanks Jagan
drivers/spi/Kconfig
Also align the fspi node with the kernel one. There is actually no driver
which would match "nxp,dn-fspi".
Signed-off-by: Michael Walle
---
changes since v1:
- none
arch/arm/dts/fsl-ls1028a.dtsi | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/ar
Am 2019-11-02 16:05, schrieb Tom Rini:
[snip]
But again, I've given up. I say that the ABI meant that the wrong
value
was supposed to work since that's what happened and a new version of
the
binding needed to be used where the right value must be used. Others
disagree. I'm not holding
Am 2019-11-05 11:23, schrieb Priyanka Jain:
-Original Message-
From: U-Boot On Behalf Of Michael Walle
Sent: Tuesday, October 22, 2019 2:07 AM
To: u-boot@lists.denx.de
Cc: Tom Rini
Subject: [U-Boot] [PATCH] armv8: fsl-layerscape: fix hwconfig and
prefetching
If CONFIG_HWCONFIG
, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).
Signed-off-by: Michael Walle
Reviewed-by: Jagan Teki
---
changes since v1:
- fixed typo, thanks Jagan
changes since v2:
- none
-by: Michael Walle
---
changes since v1:
- n/a
changes since v2:
- new patch
arch/arm/dts/fsl-ls1028a.dtsi | 55 ---
1 file changed, 31 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 774e477542
Also align the fspi node with the kernel one.
Signed-off-by: Michael Walle
Reviewed-by: Kuldeep Singh
---
changes since v1:
- none
changes since v2:
- none
arch/arm/dts/fsl-ls1028a.dtsi | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl
processing.
Signed-off-by: Pankaj Bansal
Tested-by: Michael Walle
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Hi,
sorry for being so late..
We're going to try to get this binding accepted in Linux too.
shouldn't we try to get it accepted to linux first? To avoid any
incompatibilities?
-michael
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Am 2019-11-11 16:20, schrieb Priyanka Jain:
-Original Message-
From: U-Boot On Behalf Of Michael Walle
Sent: Monday, October 21, 2019 11:04 PM
To: u-boot@lists.denx.de
Cc: Tom Rini
Subject: [U-Boot] [PATCH] armv8: layerscape: set HWCONFIG_BUFFER_SIZE
Set the HWCONFIG_BUFFER_SIZE
Hi Singh,
Am 2019-11-05 07:40, schrieb Kuldeep Singh:
Hi Michael,
-Original Message-
From: U-Boot On Behalf Of Michael Walle
Sent: Saturday, November 2, 2019 11:56 PM
To: u-boot@lists.denx.de
Subject: [EXT] [U-Boot] [PATCH v2 2/2] arm: ls1028a: use the new
flexspi
driver
Caution
Am 2019-11-05 10:53, schrieb Kuldeep Singh:
Hi Kuldeep,
>> diff --git a/arch/arm/dts/fsl-ls1028a.dtsi
>> b/arch/arm/dts/fsl-ls1028a.dtsi index
>> 43a154e8e7..774e477542 100644
>> --- a/arch/arm/dts/fsl-ls1028a.dtsi
>> +++ b/arch/arm/dts/fsl-ls1028a.dtsi
>> @@ -49,14 +49,16 @@
>>
Am 2019-11-06 00:03, schrieb Michael Walle:
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.
The port was straightforward:
- remove the interrupt handling
Hi Tom, Hi Joe,
Am 2019-12-06 00:58, schrieb Tom Rini:
On Fri, Dec 06, 2019 at 12:27:39AM +0100, Michael Walle wrote:
Hi Joe, Hi Tom,
Am 2019-12-05 16:55, schrieb Joe Hershberger:
> Hi Michael,
>
> On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
> >
> > Prov
Am 2019-12-10 15:55, schrieb Alex Marginean:
Passes on the primary address used by u-boot to Linux. The code does a
DT
fix-up for ENETC PFs and sets the primary MAC address in IERB. The
address
in IERB is restored on ENETC PCI functions at FLR.
I don't get the reason why this is done in a
Also align the fspi node with the kernel one.
Signed-off-by: Michael Walle
Reviewed-by: Kuldeep Singh
---
changes since v1:
- none
changes since v2:
- none
changes since v3:
- none
arch/arm/dts/fsl-ls1028a.dtsi | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff
, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).
Signed-off-by: Michael Walle
Reviewed-by: Jagan Teki
Tested-by: Kuldeep Singh
---
changes since v1:
- fixed typo, thanks Jagan
-by: Michael Walle
---
changes since v1:
- n/a
changes since v2:
- new patch
changes since v3:
- none
arch/arm/dts/fsl-ls1028a.dtsi | 55 ---
1 file changed, 31 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl
Hi Vladimir,
Am 2019-12-11 13:46, schrieb Vladimir Oltean:
Hi Michael,
On Wed, 11 Dec 2019 at 00:48, Michael Walle wrote:
Am 2019-12-10 15:55, schrieb Alex Marginean:
> Passes on the primary address used by u-boot to Linux. The code does a
> DT
> fix-up for ENETC PFs and sets th
Am 2019-12-11 14:04, schrieb Alexandru Marginean:
On 12/10/2019 11:47 PM, Michael Walle wrote:
Am 2019-12-10 15:55, schrieb Alex Marginean:
Passes on the primary address used by u-boot to Linux. The code does
a DT
fix-up for ENETC PFs and sets the primary MAC address in IERB. The
address
Hi Alex,
Am 2019-12-11 22:01, schrieb Alexandru Marginean:
Hi Michael,
On 12/11/2019 6:03 PM, Michael Walle wrote:
Hi Alex,
Am 2019-12-11 16:37, schrieb Alexandru Marginean:
On 12/11/2019 2:16 PM, Michael Walle wrote:
Hi Vladimir,
Am 2019-12-11 13:46, schrieb Vladimir Oltean:
Hi Michael
Hi Alex,
Am 2019-12-11 16:37, schrieb Alexandru Marginean:
On 12/11/2019 2:16 PM, Michael Walle wrote:
Hi Vladimir,
Am 2019-12-11 13:46, schrieb Vladimir Oltean:
Hi Michael,
On Wed, 11 Dec 2019 at 00:48, Michael Walle wrote:
Am 2019-12-10 15:55, schrieb Alex Marginean:
> Pas
From: Vladimir Oltean
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or
From: Vladimir Oltean
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
---
drivers/net/phy/atheros.c | 69 +++
1 file changed, 41 insertions(+), 28 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index
From: Vladimir Oltean
Delete the extraneous write to debug reg 5 that enables Tx delay
When the driver was originally introduced in commit "6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.
Then during "2ec4d10b phy: atheros: add support for
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 57 ---
1 file changed, 41 insertions(+), 16 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 01953a1390..5ff5875d3d 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
From: Vladimir Oltean
Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
---
drivers/net/phy/atheros.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git
them
- fix the CLK_25M settings for the AR8035
- add two new patches "fix AR8021 PHY ID mask" and "use defines for PHY
IDs"
- use the new kernel device tree binding for the AR803x PHYs:
https://patchwork.ozlabs.org/patch/1188293/
- add debugging output
Michael Walle (7):
phy:
The upper bits are all the OUI.
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3cc162828c..01953a1390 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers
From: Vladimir Oltean
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 38 ++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 660dcd9491..22035c2496 100644
--- a/drivers/net/phy/atheros.c
+++ b
this output.
Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.
Signed-off-by: Michael Walle
---
doc/device-tree
. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <12500>" because that value was the hardcoded
value until this commit.
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 13 -
1 file changed, 13 de
The two functions are now exactly the same, remove one of them.
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 30 +++---
1 file changed, 3 insertions(+), 27 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 208b06d3c7
Am 2019-11-30 02:11, schrieb Joe Hershberger:
On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
Sorry this was superseeded by
https://patchwork.ozlabs.org/project
Am 2019-11-30 02:11, schrieb Joe Hershberger:
On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
Sorry this series superseeded by
https://patchwork.ozlabs.org
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