Re: [PATCH 2/2] xilinx: zynqmp: Add missing prototype for board_boot_order
On 2/21/23 08:03, Ashok Reddy Soma wrote: From: Algapally Santosh Sagar Add missing prototype to fix the sparse warning, warning: no previous prototype for 'board_boot_order' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 1 + common/spl/spl.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index c6733ed1bb..0f648c47a3 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -51,6 +51,7 @@ unsigned int zynqmp_get_silicon_version(void); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_mmio_read(const u32 address, u32 *value); +void board_boot_order(u32 *spl_boot_list); void initialize_tcm(bool mode); void mem_map_fill(void); #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) diff --git a/common/spl/spl.c b/common/spl/spl.c index a630e79866..6e5f326481 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -20,6 +20,7 @@ #include #include #include +#include This doesn't look right because then you expect all spl platforms will have this header which is not the case. It should go to include/spl.h #include #include #include M
Re: [PATCH v2] usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpio
On 2/22/23 02:06, Marek Vasut wrote: On 1/13/23 06:12, Venkatesh Yadav Abbarapu wrote: As the "reset-gpios" property is optional, don't return the error and just skip the gpio reset sequence. Signed-off-by: Venkatesh Yadav Abbarapu --- Changes in v2: - Replaced the gpio_request_by_name() the API with devm_gpiod_get_optional(). The PX30 seems to fail to build: https://source.denx.de/u-boot/custodians/u-boot-usb/-/jobs/580968 Doesn't look usb related. +Please report this bug. +make[4]: *** [scripts/Makefile.build:257: spl/drivers/mmc/mmc.o] Error 1 +make[3]: *** [scripts/Makefile.build:397: spl/drivers/mmc] Error 2 +make[2]: *** [scripts/Makefile.spl:533: spl/drivers] Error 2 Can you please double check it? Thanks, Michal
Re: [PATCH v2] usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpio
On 2/22/23 16:33, Marek Vasut wrote: On 2/22/23 08:01, Michal Simek wrote: On 2/22/23 02:06, Marek Vasut wrote: On 1/13/23 06:12, Venkatesh Yadav Abbarapu wrote: As the "reset-gpios" property is optional, don't return the error and just skip the gpio reset sequence. Signed-off-by: Venkatesh Yadav Abbarapu --- Changes in v2: - Replaced the gpio_request_by_name() the API with devm_gpiod_get_optional(). The PX30 seems to fail to build: https://source.denx.de/u-boot/custodians/u-boot-usb/-/jobs/580968 Doesn't look usb related. +Please report this bug. +make[4]: *** [scripts/Makefile.build:257: spl/drivers/mmc/mmc.o] Error 1 +make[3]: *** [scripts/Makefile.build:397: spl/drivers/mmc] Error 2 +make[2]: *** [scripts/Makefile.spl:533: spl/drivers] Error 2 Can you please double check it? u-boot/master without this patch built fine, usb/next just built fine too. I did retrigger the failing build to see if this is transient failure, but it would be good if someone at xilinx could build-test the px30 too . TBH. I actually was building it myself before I sent this email. M
Re: [PATCH v2 2/2] xilinx: zynqmp: Add missing prototype for board_boot_order
Hi, On 2/24/23 05:53, Ashok Reddy Soma wrote: From: Algapally Santosh Sagar Add missing prototype to fix the sparse warning, warning: no previous prototype for 'board_boot_order' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- Changes in v2: - Moved function prototype from sys_proto.h to include/spl.h include/spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/spl.h b/include/spl.h index 827bd25c88..bad12fb01f 100644 --- a/include/spl.h +++ b/include/spl.h @@ -884,5 +884,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image); */ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size); +void board_boot_order(u32 *spl_boot_list); void spl_save_restore_data(void); #endif The patch is fine but subject not. Should be something like spl: Add missing prototype for board_boot_order M
Re: [PATCH 1/2] cmd: smccc: Print results in hex instead of dec
On 2/15/23 09:45, Michal Simek wrote:
Printing return value in HEX instead of DEC. Return values are 64 bit
values which impossible to decode in DEC. For example getting CHIP ID in
dec is quite long.
Signed-off-by: Michal Simek
---
cmd/smccc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/smccc.c b/cmd/smccc.c
index 0539a42587e2..fb80431ad1d9 100644
--- a/cmd/smccc.c
+++ b/cmd/smccc.c
@@ -43,7 +43,7 @@ static int do_call(struct cmd_tbl *cmdtp, int flag, int argc,
else
arm_smccc_hvc(fid, a1, a2, a3, a4, a5, a6, a7, &res);
- printf("Res: %ld %ld %ld %ld\n", res.a0, res.a1, res.a2, res.a3);
+ printf("Res: 0x%lx 0x%lx 0x%lx 0x%lx\n", res.a0, res.a1, res.a2,
res.a3);
return 0;
}
Applied.
M
Re: [PATCH] arm64: zynqmp: Remove comment about gem spec in kv260
On 2/20/23 09:09, Michal Simek wrote:
The latest SOM specification doesn't enforce certain MIO lines allocated
for ethernet or ethernet controller itself. That's why remove comment about
it which is likely there from early version of specification.
Also removed the same comment from pinctrl node. It is clear that it has to
be defined for different carrier cards.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +-
arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +-
arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 4 ++--
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 83c65029c75f..c82e1dfac9da 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -229,7 +229,7 @@
/* gem2/gem3 via PL with phys u79@2 and u80@3 */
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index f41a2f830caf..9dd160c7a7c9 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -229,7 +229,7 @@
/* gem2/gem3 via PL with phys u79@2 and u80@3 */
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 0be5b29c0512..6f5a42606568 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -159,7 +159,7 @@
bus-width = <8>;
};
-&gem3 { /* required by spec */
+&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
@@ -185,7 +185,7 @@
};
};
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index fca57a6d91eb..7764adf1295f 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -146,7 +146,7 @@
bus-width = <8>;
};
-&gem3 { /* required by spec */
+&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
@@ -172,7 +172,7 @@
};
};
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
Applied.
M
Re: [PATCH] spi: xilinx_spi: Fix potential null pointer access
On 2/21/23 06:22, Jiajie Chen wrote:
It was incorrectly using an old priv->regs pointer, and may lead to null
pointer access.
I would describe it a little bit differently to describe what it happening.
priv structure is initiated by DM core to zeros that's why regs property is
pointing to 0 address + spi offsets. That's why likely spi resets never happened.
Signed-off-by: Jiajie Chen
---
drivers/spi/xilinx_spi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 4e9115dafe..e759b66000 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -112,9 +112,7 @@ struct xilinx_spi_priv {
static int xilinx_spi_probe(struct udevice *bus)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
- struct xilinx_spi_regs *regs = priv->regs;
-
- priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
+ struct xilinx_spi_regs *regs = priv->regs = (struct xilinx_spi_regs
*)dev_read_addr(bus);
The patch is good but I pretty much don't like this long line.
Can you please do it on 2 lines instead?
It would be easier to read.
Thanks,
Michal
Re: [PATCH 3/4] arm64: dts: zynqmp: Fix nand dt node
On 2/27/23 15:58, Dario Binacchi wrote:
Hi Ashok,
On Fri, Feb 24, 2023 at 6:07 AM Ashok Reddy Soma
wrote:
DC3 nand node is not correct, it is showing all partitions under
controller node directly. Create two sub nand nodes with partitions for
each.
Signed-off-by: Ashok Reddy Soma
---
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 117 ++-
1 file changed, 70 insertions(+), 47 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 13812470ae..8a06c2a90a 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -128,54 +128,77 @@
arasan,has-mdma;
num-cs = <2>;
- partition@0 { /* for testing purpose */
- label = "nand-fsbl-uboot";
- reg = <0x0 0x0 0x40>;
+ nand@0 {
+ reg = <0x0>;
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ nand-rb = <0>;
+ label = "main-storage-0";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x0 0x40>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x0 0x40 0x140>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x0 0x180 0x40>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x0 0x1C0 0x140>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x0 0x300 0x40>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand-misc";
+ reg = <0x0 0x340 0xFCC0>;
+ };
};
I don't see these partitions in the kernel dts. Can we take advantage
of this opportunity to align the dts to that of the kernel
by adding a new file -u-boot.dtsi where to put the partitions?
I don't want any -u-boot.dtsi file. Simon is trying to get rid of it by moving
u-boot specific configurations to dt binding.
But I think we should used fixed-partitions description instead.
Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
And yes the same change should be also pushed to Linux kernel.
Thanks,
Michal
Re: [PATCH v5 1/6] dt/bindings: fwu-mdata-mtd: drop changes outside FWU
On 2/28/23 01:52, jassisinghb...@gmail.com wrote:
From: Jassi Brar
Any requirement of FWU should not require changes to bindings
of other subsystems. For example, for mtd-backed storage we
can do without requiring 'fixed-partitions' children to also
carry 'uuid', a property which is non-standard and not in the
bindings.
There exists no code yet, so we can change the fwu-mtd bindings
to contain all properties within the fwu-mdata node.
Signed-off-by: Jassi Brar
---
.../firmware/fwu-mdata-mtd.yaml | 105 +++---
1 file changed, 91 insertions(+), 14 deletions(-)
diff --git a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
index 4f5404f999..4b87fb8624 100644
--- a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
+++ b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml
@@ -1,13 +1,13 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-sf.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
+$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-mtd.yaml#
+$schema: http://devicetree.org/meta-schemas/base.yaml#
title: FWU metadata on MTD device without GPT
maintainers:
- - Masami Hiramatsu
+ - Jassi Brar
properties:
compatible:
@@ -15,24 +15,101 @@ properties:
- const: u-boot,fwu-mdata-mtd
fwu-mdata-store:
-maxItems: 1
-description: Phandle of the MTD device which contains the FWU medatata.
+$ref: /schemas/types.yaml#/definitions/phandle
+description: Phandle of the MTD device which contains the FWU MetaData and
Banks.
- mdata-offsets:
+ mdata-parts:
+$ref: /schemas/types.yaml#/definitions/non-unique-string-array
minItems: 2
-description: Offsets of the primary and secondary FWU metadata in the NOR
flash.
+maxItems: 2
+description: labels of the primary and secondary FWU metadata partitions
in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node.
+
+ patternProperties:
+"fwu-bank@[0-9]":
+type: object
+description: List of FWU mtd-backed banks. Typically two banks.
+
+properties:
+ id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Index of the bank.
+
+ label:
+$ref: /schemas/types.yaml#/definitions/non-unique-string-array
+minItems: 1
+maxItems: 1
+description: label of the partition, in the 'fixed-partitions' subnode
of the 'jedec,spi-nor' flash device node, that holds this bank.
+
+ patternProperties:
+"fwu-image@[0-9]":
+type: object
+description: List of images in the FWU mtd-backed bank.
+
+properties:
+ id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Index of the bank.
+
+ offset:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Offset, from start of the bank, where the image is
located.
+
+ size:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Size reserved for the image.
+
+ uuid:
+$ref: /schemas/types.yaml#/definitions/non-unique-string-array
+minItems: 1
+maxItems: 1
+description: UUID of the image.
+
+required:
+ - id
+ - offset
+ - size
+ - uuid
+additionalProperties: false
+
+required:
+ - id
+ - label
+ - fwu-images
+additionalProperties: false
required:
- compatible
- fwu-mdata-store
- - mdata-offsets
-
+ - mdata-parts
+ - fwu-banks
additionalProperties: false
examples:
- |
-fwu-mdata {
-compatible = "u-boot,fwu-mdata-mtd";
-fwu-mdata-store = <&spi-flash>;
-mdata-offsets = <0x50 0x53>;
-};
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-mtd";
+ fwu-mdata-store = <&flash0>;
This is primary saying that both copies are in flash0.
Isn't it better to also via DT binding to support that it can be different
physical devices?
+ mdata-parts = "MDATA-Pri", "MDATA-Sec";
This is not clear to me what this is used for. Can you please explain what you
want to use this for?
+
+ fwu-bank@0 {
+ id = <0>;
I though that @X is all the time associated with reg property.
It means maybe you wanted to use fwu-bank0 instead or switch id to reg.
The same applies below to fwuimage.
+ label = "FIP-Bank0";
+ fwu-image@0 {
+ id = <0>;
+ offset = <0x0>;
+ size = <0x40>;
+ uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
+ };
+ };
+ fwu-bank@1 {
+
Re: [PATCH v2] spi: xilinx_spi: Fix spi reset
po 27. 2. 2023 v 18:17 odesílatel Jiajie Chen napsal:
>
> It was incorrectly using an old priv->regs pointer, which was
> initialized to zero. SPI resets won't happen on first call.
>
> Signed-off-by: Jiajie Chen
> ---
> drivers/spi/xilinx_spi.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
> index 4e9115dafe..9e6255a172 100644
> --- a/drivers/spi/xilinx_spi.c
> +++ b/drivers/spi/xilinx_spi.c
> @@ -112,10 +112,9 @@ struct xilinx_spi_priv {
> static int xilinx_spi_probe(struct udevice *bus)
> {
> struct xilinx_spi_priv *priv = dev_get_priv(bus);
> - struct xilinx_spi_regs *regs = priv->regs;
> -
> - priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
> + struct xilinx_spi_regs *regs;
>
> + regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
> priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
>
> writel(SPISSR_RESET_VALUE, ®s->srr);
> --
> 2.30.2
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 0/4] Fix arasan nand driver issues
On 2/24/23 06:07, Ashok Reddy Soma wrote: In this patch series - Remove hardcoding of NAND_BBT_USE_FLASH in nand->bbt_options - Find and update nand ofnode. - Fix nand node in zynqmp-zc1751-xm017-dc3.dts file - Enable nand-on-flash-bbt flag in zynqmp DT's by default Ashok Reddy Soma (4): mtd: nand: arasan: Remove hardcoded bbt option mtd: nand: arasan: Set ofnode value arm64: dts: zynqmp: Fix nand dt node arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 + arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 119 ++- drivers/mtd/nand/raw/arasan_nfc.c| 5 +- 3 files changed, 78 insertions(+), 48 deletions(-) Applied, M
Re: [PATCH 0/4] Fix arasan nand driver issues
Hi, On 3/7/23 15:02, Michael Nazzareno Trimarchi wrote: Hi On Tue, Mar 7, 2023 at 2:35 PM Michal Simek <mailto:michal.si...@amd.com>> wrote: On 2/24/23 06:07, Ashok Reddy Soma wrote: > In this patch series > - Remove hardcoding of NAND_BBT_USE_FLASH in nand->bbt_options > - Find and update nand ofnode. > - Fix nand node in zynqmp-zc1751-xm017-dc3.dts file > - Enable nand-on-flash-bbt flag in zynqmp DT's by default > If we are not fast to pick our part, please ping us Thank you to pick them anyway I am normally taking patches related to Xilinx/AMD SOCs and these 2 were quite simply. Anyway Ashok told me that nand core is kind of our sync from upstream kernel. Do you have any plan to sync changes from the kernel back to U-Boot? Thanks, Michal
Re: [PATCH v3 0/2] Fix sparse warnings
On 3/1/23 11:33, Ashok Reddy Soma wrote: Run and fix sparse warnings in below files -arch/arm/mach-zynqmp/include/mach/sys_proto.h -common/spl/spl.c -arch/arm/mach-versal-net/include/mach/sys_proto.h -arch/arm/mach-versal/include/mach/sys_proto.h -drivers/mmc/zynq_sdhci.c -drivers/spi/zynqmp_gqspi.c Changes in v3: - Replaced xilinx: zynqmp with just spl: from the commit header Changes in v2: - Moved function prototype from sys_proto.h to include/spl.h Algapally Santosh Sagar (2): xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write spl: Add missing prototype for board_boot_order arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +-- arch/arm/mach-versal/include/mach/sys_proto.h | 6 +- drivers/mmc/zynq_sdhci.c | 1 + drivers/spi/zynqmp_gqspi.c| 5 + include/spl.h | 1 + 5 files changed, 9 insertions(+), 11 deletions(-) Applied. M
Re: [PATCH 2/5] tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu()
On 3/5/23 18:49, Ovidiu Panait wrote:
Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in
both big-endian and little-endian formats.
Signed-off-by: Ovidiu Panait
---
tools/relocate-rela.c | 20
1 file changed, 20 insertions(+)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 689e2d4655..84531b23a6 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -45,6 +45,7 @@
#endif
static int ei_class;
+static int ei_data;
static uint64_t rela_start, rela_end, text_base, dyn_start;
@@ -61,6 +62,22 @@ static void debug(const char *fmt, ...)
}
}
+static uint16_t elf16_to_cpu(uint16_t data)
+{
+ if (ei_data == 0x01)
Can we used macros instead of hardcoding value?
/* e_ident[] data encoding */
#define ELFDATANONE 0 /* invalid */
#define ELFDATA2LSB 1 /* Little-Endian */
#define ELFDATA2MSB 2 /* Big-Endian */
#define ELFDATANUM 3 /* number of data encode defines */
M
Re: [PATCH 1/5] tools: relocate-rela: adjust le64_to_cpu -> le32_to_cpu in decode_elf32()
On 3/5/23 18:49, Ovidiu Panait wrote:
The sh_addr/sh_offset/sh_size fields in Elf32_Shdr are 32-bits wide, so
use le32_to_cpu() instead of the 64-bit variant.
Fixes: 5e0e1a86d327 ("tools: relocate-rela: Fix ELF decoding on big-endian
hosts")
Signed-off-by: Ovidiu Panait
---
tools/relocate-rela.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 2d2a2ed277..689e2d4655 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -316,9 +316,9 @@ static int decode_elf32(FILE *felf, char **argv)
debug("%s\n", sh_name);
- sh_addr = le64_to_cpu(sh_table[i].sh_addr);
- sh_offset = le64_to_cpu(sh_table[i].sh_offset);
- sh_size = le64_to_cpu(sh_table[i].sh_size);
+ sh_addr = le32_to_cpu(sh_table[i].sh_addr);
+ sh_offset = le32_to_cpu(sh_table[i].sh_offset);
+ sh_size = le32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
Reviewed-by: Michal Simek
Thanks,
Michal
Re: [PATCH 3/5] tools: relocate-rela: add support for handling 32-bit big endian files
On 3/5/23 18:49, Ovidiu Panait wrote:
Currently, a microblaze build with CONFIG_SYS_BIG_ENDIAN=y and
CONFIG_STATIC_RELA=y fails with:
tools/relocate-rela: Not supported machine type
ELF decoding failed
make[2]: *** [u-boot/Makefile:1306: u-boot-nodtb.bin] Error 1
To fix this, convert the 32-bit codepath to use the previously added
elf{16,32}_to_cpu() functions. The aarch64 codepath is left untouched.
This commit ensures that CI doesn't fail for the next patches which enable
runtime relocation by default for microblaze.
Signed-off-by: Ovidiu Panait
---
tools/relocate-rela.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 84531b23a6..2bc46a12d7 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -251,7 +251,7 @@ static int decode_elf32(FILE *felf, char **argv)
return 25;
}
- machine = le16_to_cpu(header.e_machine);
+ machine = elf16_to_cpu(header.e_machine);
debug("Machine %d\n", machine);
if (machine != EM_MICROBLAZE) {
@@ -259,10 +259,10 @@ static int decode_elf32(FILE *felf, char **argv)
return 30;
}
- text_base = le32_to_cpu(header.e_entry);
- section_header_base = le32_to_cpu(header.e_shoff);
- section_header_size = le16_to_cpu(header.e_shentsize) *
- le16_to_cpu(header.e_shnum);
+ text_base = elf32_to_cpu(header.e_entry);
+ section_header_base = elf32_to_cpu(header.e_shoff);
+ section_header_size = elf16_to_cpu(header.e_shentsize) *
+ elf16_to_cpu(header.e_shnum);
sh_table = malloc(section_header_size);
if (!sh_table) {
@@ -290,8 +290,8 @@ static int decode_elf32(FILE *felf, char **argv)
return 27;
}
- sh_index = le16_to_cpu(header.e_shstrndx);
- sh_size = le32_to_cpu(sh_table[sh_index].sh_size);
+ sh_index = elf16_to_cpu(header.e_shstrndx);
+ sh_size = elf32_to_cpu(sh_table[sh_index].sh_size);
debug("e_shstrndx %x, sh_size %lx\n", sh_index, sh_size);
sh_str = malloc(sh_size);
@@ -306,8 +306,8 @@ static int decode_elf32(FILE *felf, char **argv)
* Specifies the byte offset from the beginning of the file
* to the first byte in the section.
*/
- sh_offset = le32_to_cpu(sh_table[sh_index].sh_offset);
- sh_num = le16_to_cpu(header.e_shnum);
+ sh_offset = elf32_to_cpu(sh_table[sh_index].sh_offset);
+ sh_num = elf16_to_cpu(header.e_shnum);
ret = fseek(felf, sh_offset, SEEK_SET);
if (ret) {
@@ -329,13 +329,13 @@ static int decode_elf32(FILE *felf, char **argv)
}
for (i = 0; i < sh_num; i++) {
- char *sh_name = sh_str + le32_to_cpu(sh_table[i].sh_name);
+ char *sh_name = sh_str + elf32_to_cpu(sh_table[i].sh_name);
debug("%s\n", sh_name);
- sh_addr = le32_to_cpu(sh_table[i].sh_addr);
- sh_offset = le32_to_cpu(sh_table[i].sh_offset);
- sh_size = le32_to_cpu(sh_table[i].sh_size);
+ sh_addr = elf32_to_cpu(sh_table[i].sh_addr);
+ sh_offset = elf32_to_cpu(sh_table[i].sh_offset);
+ sh_size = elf32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
@@ -540,9 +540,9 @@ static int rela_elf32(char **argv, FILE *f)
PRIu32 " r_addend:\t%" PRIx32 "\n",
rela.r_offset, rela.r_info, rela.r_addend);
- swrela.r_offset = le32_to_cpu(rela.r_offset);
- swrela.r_info = le32_to_cpu(rela.r_info);
- swrela.r_addend = le32_to_cpu(rela.r_addend);
+ swrela.r_offset = elf32_to_cpu(rela.r_offset);
+ swrela.r_info = elf32_to_cpu(rela.r_info);
+ swrela.r_addend = elf32_to_cpu(rela.r_addend);
debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%"
PRIu32 " r_addend:\t%" PRIx32 "\n",
Reviewed-by: Michal Simek
Thanks,
Michal
Re: [PATCH 4/5] microblaze: drop CONFIG_NEEDS_MANUAL_RELOC
On 3/5/23 18:49, Ovidiu Panait wrote:
Microblaze and m68k are the only remaining architectures that still enable
CONFIG_NEEDS_MANUAL_RELOC by default.
Microblaze has had runtime relocation support using CONFIG_STATIC_RELA for
quite some time, since commit d58c007498 ("microblaze: Add support for run
time relocation"). Drop support for CONFIG_NEEDS_MANUAL_RELOC and make
runtime relocation the default, as the rest of the architectures do.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/Kconfig | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ce157a79cc..e38c9f6d71 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -4,19 +4,8 @@ menu "MicroBlaze architecture"
config SYS_ARCH
default "microblaze"
-config NEEDS_MANUAL_RELOC
- bool "Disable position-independent pre-relocation code"
- default y
- help
- U-Boot expects to be linked to a specific hard-coded address, and to
- be loaded to and run from that address. This option lifts that
- restriction, thus allowing the code to be loaded to and executed from
- almost any 4K aligned address. This logic relies on the relocation
- information that is embedded in the binary to support U-Boot
- relocating itself to the top-of-RAM later during execution.
-
config STATIC_RELA
- def_bool y if !NEEDS_MANUAL_RELOC
+ def_bool y
choice
prompt "Target select"
Reviewed-by: Michal Simek
Thanks,
Michal
Re: [PATCH 5/5] microblaze: drop remnants of manual reloc
On 3/5/23 18:49, Ovidiu Panait wrote: Runtime relocation has been made the default for microblaze, so do the following cleanups: - drop all manual reloc codepaths in start.S - drop all STATIC_RELA ifdefs, as it is now enabled unconditionally in Kconfig Signed-off-by: Ovidiu Panait --- arch/microblaze/config.mk| 4 arch/microblaze/cpu/Makefile | 3 +-- arch/microblaze/cpu/start.S | 28 3 files changed, 1 insertion(+), 34 deletions(-) diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 467c5ca1b1..64c3f31319 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -13,10 +13,6 @@ LDFLAGS_FINAL += --gc-sections ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC -endif - -ifeq ($(CONFIG_STATIC_RELA),y) -PLATFORM_CPPFLAGS += -fPIC LDFLAGS_u-boot += -pic endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 1c586a7de0..b8c1dcbe14 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,7 +5,6 @@ extra-y = start.o obj-y = irq.o -obj-y += interrupts.o cache.o exception.o cpuinfo.o -obj-$(CONFIG_STATIC_RELA) += relocate.o +obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 7079d9e170..c1e0fcda0a 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -10,16 +10,11 @@ #include #include -#if defined(CONFIG_STATIC_RELA) #define SYM_ADDR(reg, reg_add, symbol)\ mfs r20, rpc; \ addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \ lwi reg, r20, symbol@GOT; \ addkreg, reg reg_add; -#else -#define SYM_ADDR(reg, reg_add, symbol) \ - addireg, reg_add, symbol -#endif .text .global _start @@ -35,7 +30,6 @@ _start: addir1, r0, CONFIG_SPL_STACK #else add r1, r0, r20 -#if defined(CONFIG_STATIC_RELA) bri 1f /* Force alignment for easier ASM code below */ @@ -67,7 +61,6 @@ uboot_sym_start: brlid r15, mb_fix_rela nop -#endif #endif addi r1, r1, -4 /* Decrement SP to top of memory */ @@ -310,7 +303,6 @@ relocate_code: brlid r15, __setup_exceptions nop -#if defined(CONFIG_STATIC_RELA) /* reloc_offset is current location */ SYM_ADDR(r10, r0, _start) @@ -331,27 +323,7 @@ relocate_code: add r9, r9, r5 brlid r15, mb_fix_rela nop - /* end of code which does relocation */ -#else - /* Check if GOT exist */ - addik r21, r23, _got_start - addik r22, r23, _got_end - cmpur12, r21, r22 - beqir12, 2f /* No GOT table - jump over */ - - /* Skip last 3 entries plus 1 because of loop boundary below */ - addik r22, r22, -0x10 - -/* Relocate the GOT. */ -3: lw r12, r21, r0 /* Load entry */ - addkr12, r12, r23 /* Add reloc offset */ - sw r12, r21, r0 /* Save entry back */ - - cmpur12, r21, r22 /* Check if this cross boundary */ - bneid r12, 3b - addik r21. r21, 4 -#endif /* Flush caches to ensure consistency */ brlid r15, flush_cache_all Reviewed-by: Michal Simek Thanks, Michal
Re: [PATCH v2 2/5] tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu()
On 3/11/23 18:38, Ovidiu Panait wrote: Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in both big-endian and little-endian formats. Reviewed-by: Michal Simek I didn't give you this line in v1. But patch looks fine now. Applied the whole series. Thanks, Michal
[GIT PULL] xilinx patches for v2023.07-rc1
Hi Tom, please pull these patches to your next branch. CI loop doesn't report any issue. Thanks, Michal The following changes since commit 70ed05ce6c051e55e126e67e72ab20409134c953: Merge tag 'next-20230307' of https://source.denx.de/u-boot/custodians/u-boot-video into next (2023-03-07 12:54:01 -0500) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2023.07-rc1 for you to fetch changes up to 7ac50f88f8a9374e5cb4bc2a88c002d02ef3c570: microblaze: drop remnants of manual reloc (2023-03-13 11:46:17 +0100) Xilinx changes for v2023.07-rc1 cmd: - Print results in hex instead of dec in smc command firmware: - Cover missing ZYNQMP_FIRMWARE dependencies fpga: - fix loads for unencrypted use case relocation - Add support for BE systems spi: - Fix xilinx_spi init reset sequence arasan nand: - Remove hardcoded bbt option - Set ofnode value xilinx: - Enable SMC command - Fix some sparse issues zynqmp: - Remove cdns,zynq-gem compatible string - Add optee node - Some DT cleanups zynq: - Some DT cleanups microblaze - Remove MANUAL_RELOC option Algapally Santosh Sagar (3): arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write spl: Add missing prototype for board_boot_order Ashok Reddy Soma (4): mtd: nand: arasan: Remove hardcoded bbt option mtd: nand: arasan: Set ofnode value arm64: dts: zynqmp: Fix nand dt node arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default Ilias Apalodimas (1): arm64: zynqmp: Add an OP-TEE node to the device tree Jiajie Chen (1): spi: xilinx_spi: Fix spi reset Krzysztof Kozlowski (3): arm64: dts: xilinx: align LED node names with dtschema ARM: dts: xilinx: align gpio-key node names with dtschema ARM: dts: zynq-7000: drop useless 'dma-channels/requests' properties Michael Grzeschik (1): arm64: zynqmp: Enable hs termination flag for USB dwc3 controller Michal Simek (6): xilinx: dts: Remove cdns,zynq-gem ARM: zynq: Use recommended dma-controller name instead of dmac ARM: zynq: Comment interrupt names IRQs for pl330 cmd: smccc: Print results in hex instead of dec xilinx: Enable SMC command for arm64 targets arm64: zynqmp: Remove comment about gem spec in kv260 Neal Frager (1): fpga: zynqmppl: fix fpga loads command for unencrypted use case Ovidiu Panait (5): tools: relocate-rela: adjust le64_to_cpu -> le32_to_cpu in decode_elf32() tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu() tools: relocate-rela: add support for handling 32-bit big endian files microblaze: drop CONFIG_NEEDS_MANUAL_RELOC microblaze: drop remnants of manual reloc arch/arm/dts/zynq-7000.dtsi | 14 +-- arch/arm/dts/zynq-zc702.dts | 4 +- arch/arm/dts/zynq-zturn-common.dtsi | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 4 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 4 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 + arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 119 arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 15 ++- arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +- arch/arm/mach-versal/include/mach/sys_proto.h | 6 +- arch/microblaze/Kconfig | 13 +-- arch/microblaze/config.mk | 4 - arch/microblaze/cpu/Makefile | 3 +- arch/microblaze/cpu/start.S | 28 - board/xilinx/zynqmp/Kconfig | 1 + cmd/smccc.c | 2 +- configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + drivers/clk/Kconfig | 4 +- drivers/fpga/Kconfig | 2 +- drivers/fpga/zynqmppl.c | 12 +- drivers/mmc/zynq_sdhci.c | 5 +- drivers/mtd/nand/raw/arasan_nfc.c | 5 +- drivers/net/zynq_gem.c| 2 +- drivers/spi/xilinx_spi.c | 5 +- drivers/spi/zynqmp_gqspi.c| 5 + include/spl.h | 1 + tools/relocate-rela.c | 52 ++--- 32 files changed, 175 insertions(+), 155 deletions(-) -- Michal
Re: [QUESTION] Device tree for gmii-to-rgmii phy driver
Hi,
On 3/16/23 17:52, Stefan Herbrechtsmeier wrote:
Hi Siva Durga Prasad Paladugu,
we want to add rgmii-id support to the gmiitorgmii phy driver. How does the
correct device tree for the gmiitorgmii looks like? The converter sits between
the MAC and the external PHY (MAC <==> GMII2RGMII <==> RGMII_PHY) which would
mean that the phy-handle of the MAC should point to the GMII2RGMII and the
GMII2RGMII to RGMII_PHY:
&gem0 {
phy-handle = <&gmiitorgmii0>;
phy-mode = "gmii";
mdio {
ethphy0: ethernet-phy@1 {
};
gmiitorgmii0: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
phy-handle = <ðphy0>;
phy-mode = "rgmii-id";
};
};
};
This device tree snippet does not work in the kernel. The kernel gmii2rgmii
driver does not use a phy driver as base and manipulates the functions of the
external phy object instead. It requires the following device tree snippet:
&gem0 {
phy-handle = <ðphy0>;
phy-mode = "rgmii-id";
mdio {
ethphy0: ethernet-phy@1 {
};
gmiitorgmii0: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
phy-handle = <ðphy0>;
phy-mode = "rgmii-id";
};
};
};
This does not work in u-boot because the phy framework ignores the phy-handle of
the MAC for the gmii2rgmii but the gmii2rgmii driver itself checks the phy-mode
of the MAC.
What is the correct device tree and thereby proper implementation?
It is known issue for some time and U-Boot description is correct. Linux needs
to be fixed. I remember there were any issue with framework not supporting it
that's why unfortunately different description needs to be used.
I am CCing Harini. Here team should work on getting this fixed.
Thanks,
Michal
Re: [PATCH 1/2] lmb: Fix LMB_MEMORY_REGIONS flag usage
On 3/21/23 13:58, Patrick Delaunay wrote:
Remove test on CONFIG_LMB_MEMORY_REGIONS introduced by commit
7c1860fce4e3 ("lmb: Fix lmb property's defination under struct lmb").
This code in lmb_init() is strange, because if CONFIG_LMB_USE_MAX_REGIONS
and CONFIG_LMB_MEMORY_REGIONS are not defined, the implicit #else is empty
and the required initialization are not done:
lmb->memory.max = ?
lmb->reserved.max = ?
But this setting is not possible:
- CONFIG_LMB_USE_MAX_REGIONS not defined
- CONFIG_LMB_MEMORY_REGIONS not defined
because CONFIG_LMB_MEMORY_REGIONS and CONFIG_LMB_RESERVED_REGIONS are
defined as soon as the CONFIG_LMB_USE_MAX_REGIONS is not defined.
This patch removes this impossible case #elif and I add some
explanation in lmb.h to explain why in the struct lmb {} the lmb
property's should is defined if CONFIG_LMB_MEMORY_REGIONS is NOT defined.
Fixes: 5e2548c1d6e03 ("lmb: Fix LMB_MEMORY_REGIONS flag usage")
Reported-by: Mark Millard
Signed-off-by: Patrick Delaunay
---
include/lmb.h | 20 +++-
lib/lmb.c | 2 +-
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/include/lmb.h b/include/lmb.h
index 7298c2ccc403..f70463ac5440 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -35,6 +35,24 @@ struct lmb_property {
enum lmb_flags flags;
};
+/*
+ * For regions size management, see LMB configuration in KConfig
+ * all the #if test are done with CONFIG_LMB_USE_MAX_REGIONS (boolean)
+ *
+ * case 1. CONFIG_LMB_USE_MAX_REGIONS is defined (legacy mode)
+ * => CONFIG_LMB_MAX_REGIONS is used to configure the region size,
+ * direclty in the array lmb_region.region[], with the same
+ * configuration for memory reion and reseserved region.
+ *
+ * case 2. CONFIG_LMB_USE_MAX_REGIONS is not defined, the size of each
+ * region is configurated *independently* with
+ * => CONFIG_LMB_MEMORY_REGIONS: struct lmb.memory_regions
+ * => CONFIG_LMB_RESERVED_REGIONS: struct lmb.reserved_regions
+ * lmb_region.region is only a pointer to the correct buffer,
+ * initialized in lmb_init(). This configuration is useful to manage
+ * more reserved memory regions with CONFIG_LMB_RESERVED_REGIONS.
+ */
+
/**
* struct lmb_region - Description of a set of region.
*
@@ -68,7 +86,7 @@ struct lmb_region {
struct lmb {
struct lmb_region memory;
struct lmb_region reserved;
-#ifdef CONFIG_LMB_MEMORY_REGIONS
+#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS];
struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS];
#endif
diff --git a/lib/lmb.c b/lib/lmb.c
index 2444b2a62121..8fbe453dfa9d 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -110,7 +110,7 @@ void lmb_init(struct lmb *lmb)
#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
lmb->memory.max = CONFIG_LMB_MAX_REGIONS;
lmb->reserved.max = CONFIG_LMB_MAX_REGIONS;
-#elif defined(CONFIG_LMB_MEMORY_REGIONS)
+#else
lmb->memory.max = CONFIG_LMB_MEMORY_REGIONS;
lmb->reserved.max = CONFIG_LMB_RESERVED_REGIONS;
lmb->memory.region = lmb->memory_regions;
I just build this patch for our platforms and got this.
M
02: lmb: Fix LMB_MEMORY_REGIONS flag usage
aarch64: + xilinx_versal_mini xilinx_versal_mini_emmc0
xilinx_versal_mini_emmc1 xilinx_versal_mini_ospi xilinx_versal_mini_qspi
xilinx_versal_net_mini xilinx_zynqmp_mini xilinx_zynqmp_mini_emmc0
xilinx_zynqmp_mini_emmc1 xilinx_zynqmp_mini_nand xilinx_zynqmp_mini_nand_single
xilinx_zynqmp_mini_qspi
arm: + zynq_cse_nand zynq_cse_nor zynq_cse_qspi
+In file included from ../include/image.h:34:0,
+ from ../include/bootm.h:10,
+ from ../arch/arm/cpu/armv8/exception_level.c:12:
+../include/lmb.h:90:37: error: ‘CONFIG_LMB_MEMORY_REGIONS’ undeclared here (not
in a function)
+ struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS];
+ ^
+../include/lmb.h:91:39: error: ‘CONFIG_LMB_RESERVED_REGIONS’ undeclared here
(not in a function)
+ struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS];
+ ^~~
+make[2]: *** [../scripts/Makefile.build:257:
arch/arm/cpu/armv8/exception_level.o] Error 1
+make[1]: *** [Makefile:1847: arch/arm/cpu/armv8] Error 2
+make: *** [Makefile:177: sub-make] Error 2
+In file included from ../arch/arm/lib/stack.c:15:0:
+make[2]: *** [../scripts/Makefile.build:257: arch/arm/lib/stack.o] Error 1
+make[1]: *** [Makefile:1847: arch/arm/lib] Error 2
Re: [PATCH 01/41] net: phy: aquantia: Staticize PHY driver entries
Hi, On 3/19/23 18:02, Marek Vasut wrote: These struct phy_driver ... instances are local to this source code file, staticize them. No functional change. Signed-off-by: Marek Vasut --- Cc: "Ariel D'Alessandro" Cc: "Cédric Le Goater" Cc: "Marek Behún" Cc: Alex Nemirovsky Cc: Haolin Li Cc: Heinrich Schuchardt Cc: Joe Hershberger Cc: Joel Stanley Cc: Josua Mayer Cc: Marek Vasut Cc: Michael Trimarchi Cc: Michal Simek Cc: Nate Drude Cc: Neil Armstrong Cc: Radu Pirea Cc: Ramon Fried Cc: Samuel Mendoza-Jonas Cc: Stefan Roese Cc: T Karthik Reddy Cc: Tim Harvey Cc: Vladimir Oltean Cc: u-boot-amlo...@groups.io --- drivers/net/phy/aquantia.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) Would be good if you also create cover letter which I can reply. I have tested this series on Microblaze which is also using MANUAL relocation (but we are removing it from 2023.07 release) and it is working fine. I also went over all these patches and changes look good to me. That's why for all patches feel free to add Acked-by: Michal Simek Tested-by: Michal Simek #microblaze (MANUAL_RELOC) Thanks, Michal
Re: [PATCH] serial: zynqmp: Fetch baudrate from dtb and update
Hi Simon and Tom,
On 3/14/23 09:46, Venkatesh Yadav Abbarapu wrote:
From: Algapally Santosh Sagar
The baudrate configured in .config is taken by default by serial. If
change of baudrate is required then the .config needs to changed and
u-boot recompilation is required or the u-boot environment needs to be
updated.
To avoid this, support is added to fetch the baudrate directly from the
device tree file and update.
The serial, prints the log with the configured baudrate in the dtb.
The commit c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for
$fdtfile env variable") is taken as reference for changing the default
environment variable.
The default environment stores the default baudrate value, When default
baudrate and dtb baudrate are not same glitches are seen on the serial.
So, the environment also needs to be updated with the dtb baudrate to
avoid the glitches on the serial.
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Venkatesh Yadav Abbarapu
I reviewed this patch internally and would like to get your opinion about it.
The problematic part is around ENV_RW_FILLER that's why I want to make sure that
the patch is going in the right direction.
Thanks,
Michal
Re: [PATCH] net: phy: gmii2rgmii: Support external rgmii-id phy
On 3/20/23 16:55, Stefan Herbrechtsmeier wrote: From: Stefan Herbrechtsmeier Read the phy mode of the external phy from the device tree if available. Signed-off-by: Stefan Herbrechtsmeier --- drivers/net/phy/xilinx_gmii2rgmii.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index 7376283956..12519a8d57 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -48,7 +48,10 @@ static int xilinxgmiitorgmii_config(struct phy_device *phydev) return -EINVAL; } - ext_phydev->interface = PHY_INTERFACE_MODE_RGMII; + ext_phydev->interface = ofnode_read_phy_mode(node); + if (ext_phydev->interface == PHY_INTERFACE_MODE_NA) + ext_phydev->interface = PHY_INTERFACE_MODE_RGMII; + This is open a way to pretty much define any mode which doesn't look right. I think it would be good to also check that mode is setup based on what IP itself supports. It means check that rgmii or rgmii-id are selected. If in DT someone put sgmii it should error out. Thanks, Michal
[PATCH] mtd: Add missing MTD dependency for cfi_mtd
cfi_mtd requires add_mtd_device() which is available only when MTD is enabled that's why record this dependency. Signed-off-by: Michal Simek --- drivers/mtd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 5fa88dae5f33..c56840c84975 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -128,7 +128,7 @@ config FLASH_SPANSION_S29WS_N config FLASH_CFI_MTD bool "Enable CFI MTD driver" - depends on FLASH_CFI_DRIVER + depends on FLASH_CFI_DRIVER && MTD help This option enables the building of the cfi_mtd driver in the drivers directory. The driver exports CFI flash -- 2.36.1
[PATCH] sysreset: Change Kconfig GPIO dependency
DM_GPIO depends on GPIO to be enabled but select will cause that DM_GPIO is selected without GPIO which ends up in compilation error: undefined reference to `dm_gpio_set_value' undefined reference to `dm_gpio_get_value' undefined reference to `dm_gpio_free' undefined reference to `gpio_request_by_name' Signed-off-by: Michal Simek --- drivers/sysreset/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 03f7fdd59785..bdbe2a95364d 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -61,14 +61,14 @@ endif config POWEROFF_GPIO bool "Enable support for GPIO poweroff driver" - select DM_GPIO + depends on DM_GPIO help Support for system poweroff using a GPIO pin. This can be used for systems having a single GPIO to trigger a system poweroff. config SYSRESET_GPIO bool "Enable support for GPIO reset driver" - select DM_GPIO + depends on DM_GPIO help Reset support via GPIO pin connected reset logic. This is used for example on Microblaze where reset logic can be controlled via GPIO -- 2.36.1
Re: [PATCH] zynqmp: config: Add proper dependency for CONFIG_DFU_MMC
Grrr. Patch subject prefix should be fixed. The rest looks good to me. M On 7/7/23 08:59, Ashok Reddy Soma wrote: When CONFIG_CMD_MMC and CONFIG_MMC are disabled, still some compilation errors are seen as below due to unresolved symbols. drivers/dfu/dfu_mmc.o: in function `mmc_block_op': drivers/dfu/dfu_mmc.c:32: undefined reference to `find_mmc_device' drivers/dfu/dfu_mmc.c:54: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.c:67: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.c:70: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.o: in function `dfu_fill_entity_mmc': drivers/dfu/dfu_mmc.c:369: undefined reference to `find_mmc_device' drivers/dfu/dfu_mmc.c:376: undefined reference to `mmc_init' drivers/dfu/dfu_mmc.c:403: undefined reference to `mmc_get_blk_desc' gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-ld.bfd: line 4: 31661 Segmentation fault (core dumped) $CC --sysroot=$LIBC --no-warn-rwx-segment "$@" Makefile:1760: recipe for target 'u-boot' failed make: *** [u-boot] Error 139 make: *** Deleting file 'u-boot' Add dependency of CONFIG_MMC for CONFIG_DFU_MMC config to fix the errors. Signed-off-by: Ashok Reddy Soma --- drivers/dfu/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 8d7f13dcb0..8e9e8eb4fe 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -35,6 +35,7 @@ config DFU_TIMEOUT config DFU_MMC bool "MMC back end for DFU" + depends on MMC help This option enables using DFU to read and write to MMC based storage.
Re: [PATCH] xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h
pá 23. 6. 2023 v 14:52 odesílatel Michal Simek napsal:
>
> zynqmp_mmio_read/write() are firmware provided hooks that's why use only
> zynqmp_firmware.h for function declaration.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/mach-versal-net/include/mach/sys_proto.h | 2 --
> arch/arm/mach-versal/include/mach/sys_proto.h | 2 --
> arch/arm/mach-zynqmp/include/mach/sys_proto.h | 3 ---
> arch/arm/mach-zynqmp/mp.c | 1 +
> drivers/clk/clk_zynqmp.c | 1 +
> include/zynqmp_firmware.h | 1 +
> 6 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h
> b/arch/arm/mach-versal-net/include/mach/sys_proto.h
> index a20cf02712bd..23374d10a6b4 100644
> --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
> +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
> @@ -7,5 +7,3 @@
> #include
>
> void mem_map_fill(void);
> -
> -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
> diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h
> b/arch/arm/mach-versal/include/mach/sys_proto.h
> index 433f9ba07c77..757bd873fbee 100644
> --- a/arch/arm/mach-versal/include/mach/sys_proto.h
> +++ b/arch/arm/mach-versal/include/mach/sys_proto.h
> @@ -13,5 +13,3 @@ enum {
> void initialize_tcm(bool mode);
> void tcm_init(u8 mode);
> void mem_map_fill(void);
> -
> -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
> diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
> b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
> index c6733ed1bbe7..ede00d73fe0c 100644
> --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
> +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
> @@ -48,9 +48,6 @@ enum {
>
> unsigned int zynqmp_get_silicon_version(void);
>
> -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
> -int zynqmp_mmio_read(const u32 address, u32 *value);
> -
> void initialize_tcm(bool mode);
> void mem_map_fill(void);
> #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) ||
> defined(CONFIG_DEFINE_TCM_OCM_MMAP)
> diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
> index b06c867e57f6..4c514258ba69 100644
> --- a/arch/arm/mach-zynqmp/mp.c
> +++ b/arch/arm/mach-zynqmp/mp.c
> @@ -7,6 +7,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
> index be0ee50e0e4f..8320d4918462 100644
> --- a/drivers/clk/clk_zynqmp.c
> +++ b/drivers/clk/clk_zynqmp.c
> @@ -12,6 +12,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
> index c56ad3f92067..18a87d274954 100644
> --- a/include/zynqmp_firmware.h
> +++ b/include/zynqmp_firmware.h
> @@ -454,6 +454,7 @@ int zynqmp_pm_set_sd_config(u32 node, enum
> pm_sd_config_type config, u32 value);
> int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
> u32 value);
> int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
> +int zynqmp_mmio_read(const u32 address, u32 *value);
> int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
>
> /* Type of Config Object */
> --
> 2.36.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] spl: Add function called after fpga image upload
On 6/27/23 11:04, christian.taedcke-...@weidmueller.com wrote: From: Christian Taedcke This way custom logic can be implemented per board after the fpga image is uploaded. What do you want to do there? I expect Simon won't like that it is another weak function. Signed-off-by: Christian Taedcke --- common/spl/spl_fit.c | 13 + 1 file changed, 13 insertions(+) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 730639f756..3a1e3382ba 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -560,6 +560,16 @@ __weak void *spl_load_simple_fit_fix_load(const void *fit) return (void *)fit; } +/* + * Weak default function to allow implementing logic after fpga image is + * uploaded. + */ +__weak void board_spl_fit_post_upload_fpga(const void *fit, int node, + struct spl_image_info *fpga_image, + int ret) Would be good to have kernel-doc and curious about ret parameter. Also function like this could fail and you should propagate error. M
Re: [PATCH] xilinx: zynqmp: Extract aes operation into new file
On 6/27/23 10:29, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This moves the aes operation that is perfomed by the pmu into a
typo
separate file. This way it can be called not just from the shell
command, but also e.g. from board initialization code.
Signed-off-by: Christian Taedcke
---
arch/arm/mach-zynqmp/Makefile | 3 +-
arch/arm/mach-zynqmp/aes.c| 58 +++
.../arm/mach-zynqmp/include/mach/zynqmp_aes.h | 31 ++
board/xilinx/zynqmp/cmds.c| 44 ++
4 files changed, 96 insertions(+), 40 deletions(-)
create mode 100644 arch/arm/mach-zynqmp/aes.c
create mode 100644 arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index bb1830c846..1a76493bef 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek
-obj-y += clk.o
-obj-y += cpu.o
+obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c
new file mode 100644
index 00..f508862e57
--- /dev/null
+++ b/arch/arm/mach-zynqmp/aes.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu
+ *
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG
+ * Christian Taedcke
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+int zynqmp_aes_operation(struct zynqmp_aes *aes)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
switch them. It should be reverse christmas tree.
+
+ if (zynqmp_firmware_version() <= PMUFW_V1_0)
+ return -ENOENT;
+
+ if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
+ flush_dcache_range(aes->srcaddr,
+ (aes->srcaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN)));
+ flush_dcache_range(aes->ivaddr,
+ (aes->ivaddr +
+ roundup(IV_SIZE, ARCH_DMA_MINALIGN)));
+ flush_dcache_range(aes->dstaddr,
+ (aes->dstaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN)));
+ }
+
+ if (aes->keysrc == 0) {
+ if (aes->keyaddr == 0)
+ return -EINVAL;
+
+ flush_dcache_range(aes->keyaddr, (aes->keyaddr +
+ roundup(KEY_PTR_LEN,
ARCH_DMA_MINALIGN)));
+ }
+
+ flush_dcache_range((ulong)aes, (ulong)(aes) +
+ roundup(sizeof(struct zynqmp_aes),
ARCH_DMA_MINALIGN));
+
+ ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
+ lower_32_bits((ulong)aes), 0, 0, ret_payload);
+ if (ret || ret_payload[1]) {
+ printf("Failed: AES op status:0x%x, errcode:0x%x\n",
+ ret, ret_payload[1]);
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
new file mode 100644
index 00..7c28e377a1
--- /dev/null
+++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
It was taken from 2.0 that's why please keep 2.0 not 2.0+
+/*
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG
+ * Christian Taedcke
+ *
+ * Declaration of AES operation functionality for ZynqMP.
+ */
+
+#ifndef ZYNQMP_AES_H
+#define ZYNQMP_AES_H
+
+struct zynqmp_aes {
+ u64 srcaddr;
+ u64 ivaddr;
+ u64 keyaddr;
+ u64 dstaddr;
+ u64 len;
+ u64 op;
+ u64 keysrc;
+};
+
+/*
+ * Performs an aes operation using the pmu firmware
+ *
+ * @param aes The aes operation buffer that must have been allocated using
+ *ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1).
+ * @return 0 in case of success, in case of an errer any other value.
+ */
kernel-doc format please.
+int zynqmp_aes_operation(struct zynqmp_aes *aes);
+
+#endif /* ZYNQMP_AES_H */
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index e20030ecda..76be17e7ae 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -14,16 +14,7 @@
#include
#include
#include
-
-struct aes {
- u64 srcaddr;
- u64 ivaddr;
- u64 keyaddr;
- u64 dstaddr;
- u64 len;
- u64 op;
- u64 keysrc;
-};
+#include
static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int a
[PATCH] xilinx: zynq: Enable fdt apply utility for zynq
From: Raju Kumar Pothuraju Enables the FDT library (libfdt) overlay support for zynq platforms to be able to use fdt apply command. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Michal Simek --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 474abc7f6b0b..990057734595 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -7,6 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_ENV_OFFSET=0xE0 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_STACK_R_ADDR=0x20 CONFIG_SPL_STACK=0xfe00 CONFIG_SPL=y -- 2.36.1
[PATCH] mmc: zynq_sdhci: Dll reset only for ZynqMP platform
From: Ashok Reddy Soma Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e779251ce34f..935540d17194 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); @@ -468,7 +469,9 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) } udelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); /* Enable only interrupts served by the SD controller */ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, -- 2.36.1
[PATCH] arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek --- The same changes have been done in Linux. Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.si...@amd.com --- arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/versal-mini-emmc0.dts| 4 ++-- arch/arm/dts/versal-mini-emmc1.dts| 4 ++-- arch/arm/dts/versal-mini-ospi.dtsi| 4 ++-- arch/arm/dts/versal-mini-qspi.dtsi| 4 ++-- arch/arm/dts/versal-mini.dts | 2 +- arch/arm/dts/zynq-dlc20-rev1.0.dts| 2 +- arch/arm/dts/zynq-minized.dts | 2 +- arch/arm/dts/zynqmp-a2197-revA.dts| 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp-dlc21-revA.dts| 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc0.dts| 2 +- arch/arm/dts/zynqmp-mini-emmc1.dts| 2 +- arch/arm/dts/zynqmp-mini-nand.dts | 4 ++-- arch/arm/dts/zynqmp-mini-qspi.dts | 4 ++-- arch/arm/dts/zynqmp-mini.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-r5.dts| 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 4 ++-- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.1.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1275-revB.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1285-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- arch/arm/mach-tegra/arm64-mmu.c | 2 +- arch/arm/mach-versal/Makefile | 2 +- arch/arm/mach-versal/clk.c| 2 +- arch/arm/mach-versal/cpu.c| 2 +- arch/arm/mach-versal/mp.c | 2 +- arch/arm/mach-zynqmp/Makefile | 2 +- arch/arm/mach-zynqmp/clk.c| 2 +- arch/arm/mach-zynqmp/cpu.c| 2 +- arch/arm/mach-zynqmp/handoff.c| 2 +- arch/arm/mach-zynqmp/include/mach/clk.h | 2 +- arch/arm/mach-zynqmp/include/mach/hardware.h | 2 +- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 2 +- arch/arm/mach-zynqmp/mp.c | 2 +- arch/arm/mach-zynqmp/psu_spl_init.c | 2 +- arch/arm/mach-zynqmp/spl.c| 2 +- arch/microblaze/cpu/spl.c | 2 +- arch/microblaze/cpu/u-boot-spl.lds| 2 +- arch/microblaze/include/asm/spl.h | 2 +- board/xilinx/common/Makefile | 2 +- board/xilinx/common/board.h | 2 +- board/xilinx/common/cpu-info.c| 2 +- board/xilinx/common/fru.h | 2 +- board/xilinx/versal/Makefile | 2 +- board/xilinx/versal/board.c | 2 +- board/xilinx/versal/cmds.c| 2 +- board/xilinx/zynqmp/Makefile | 2 +- board/xilinx/zynqmp/cmds.c| 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- common/spl/spl_ram.c | 2 +- drivers/ata/sata_ceva.c | 2 +- drivers/clk/clk_versal.c | 2 +- drivers/fpga/versalpl.c | 2 +- drivers/fpga/zynqmppl.c | 4 ++-- drivers/net/xilinx_axi_mrmac.c| 2 +- drivers/net/xilinx_axi_mrmac.h| 2 +- drivers/pinctrl/pinctrl
[PATCH 00/17] Hi,
sending couple of DT patches to be in sync with Linux repository. There are still some changes but we are working on it to get them fully in sync for SystemReady IR certification. Thanks, Michal Harini Katakam (3): arm64: zynqmp: Assign TSU clock frequency for KR260 arm64: zynqmp: Increase reset assert time for TI SGMII PHY arm64: zynqmp: Assign TSU clock frequency for KV and KD boards Manikanta Guntupalli (1): xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal Michal Simek (8): arm64: zynqmp: Fix gpio comment about No of gpios arm64: zynqmp: Record compatible string for kv260 rev2 arm64: zynqmp: Cover K24 revB/1 SOM arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 arm64: zynqmp: Sync node name address with reg (mailbox) arm64: zynqmp: Remove interrupt/reg-names for AMS arm64: zynqmp: Rename ams_ps/pl node names arm64: zynqmp: Remove clock-names from pcap node Parth Gajjar (1): arm64: zynqmp: Update MALI 400 interrupt and clock names Piyush Mehta (1): arm64: zynqmp: remove snps,enable_guctl1_resume_quirk quirk for usb Radhey Shyam Pandey (2): arm64: zynqmp: Add L2 cache nodes arm64: zynqmp: add pmu interrupt-affinity Varalaxmi Bingi (1): arm: xilinx: Setting default i2c clock frequency to 400kHz arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynq-zc702.dts | 5 ++-- arch/arm/dts/zynqmp-clk-ccf.dtsi | 10 +++ arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 6 ++--- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts| 8 +++--- arch/arm/dts/zynqmp-sck-kr-g-revB.dts| 8 +++--- arch/arm/dts/zynqmp-sck-kv-g-revA.dts| 5 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts| 8 +++--- arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 6 ++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 +++--- arch/arm/dts/zynqmp-zcu100-revC.dts | 6 +++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 +-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 +-- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu208-revA.dts | 10 +++ arch/arm/dts/zynqmp-zcu216-revA.dts | 10 +++ arch/arm/dts/zynqmp.dtsi | 33 28 files changed, 103 insertions(+), 79 deletions(-) -- 2.36.1
[PATCH 01/17] arm: xilinx: Setting default i2c clock frequency to 400kHz
From: Varalaxmi Bingi Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynqmp.dtsi| 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 97a9e49a19c3..8c6eafec1d4e 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -153,6 +153,7 @@ clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <40>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -164,6 +165,7 @@ clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <40>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index c9640c44451f..5f1e163e87f2 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -611,6 +611,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; + clock-frequency = <40>; reg = <0x0 0xff02 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -622,6 +623,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; + clock-frequency = <40>; reg = <0x0 0xff03 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; -- 2.36.1
[PATCH 03/17] arm64: zynqmp: Update MALI 400 interrupt and clock names
From: Parth Gajjar
Motivation for the commit is to utilize the upstream community
device tree so that the either modified ARM Mali 400 driver
or upstream lima driver can be used.
Signed-off-by: Parth Gajjar
Signed-off-by: Vishal Sagar
Link:
https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gaj...@amd.com
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +-
arch/arm/dts/zynqmp.dtsi | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 173e4bc5f1d8..4d44924f6633 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -126,7 +126,7 @@
};
&gpu {
- clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk
GPU_PP1_REF>;
+ clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
};
&lpd_dma_chan1 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 5f1e163e87f2..38114d55386b 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -396,12 +396,12 @@
gpu: gpu@fd4b {
status = "disabled";
- compatible = "arm,mali-400", "arm,mali-utgard";
+ compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b 0x0 0x1>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132
4>, <0 132 4>, <0 132 4>;
- interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0",
"IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
- clock-names = "gpu", "gpu_pp0", "gpu_pp1";
+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0",
"pp1", "ppmmu1";
+ clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
};
--
2.36.1
[PATCH 02/17] xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
From: Manikanta Guntupalli
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by
Linux.
"enforced open drain please flag it properly in DT/ACPI DSDT/board
file."
Signed-off-by: Manikanta Guntupalli
Signed-off-by: Michal Simek
---
arch/arm/dts/zynq-zc702.dts | 5 +++--
arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 4 ++--
arch/arm/dts/zynqmp-sck-kr-g-revA.dts| 4 ++--
arch/arm/dts/zynqmp-sck-kr-g-revB.dts| 4 ++--
arch/arm/dts/zynqmp-sck-kv-g-revA.dts| 4 ++--
arch/arm/dts/zynqmp-sck-kv-g-revB.dts| 4 ++--
arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++--
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 ++--
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 ++--
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8
arch/arm/dts/zynqmp-zcu100-revC.dts | 4 ++--
arch/arm/dts/zynqmp-zcu102-revA.dts | 8
arch/arm/dts/zynqmp-zcu104-revA.dts | 4 ++--
arch/arm/dts/zynqmp-zcu104-revC.dts | 4 ++--
arch/arm/dts/zynqmp-zcu106-revA.dts | 8
arch/arm/dts/zynqmp-zcu111-revA.dts | 8
arch/arm/dts/zynqmp-zcu208-revA.dts | 8
arch/arm/dts/zynqmp-zcu216-revA.dts | 8
18 files changed, 49 insertions(+), 48 deletions(-)
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 27fb194fc9e2..8d47f24b757b 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "zynq-7000.dtsi"
+#include
/ {
model = "Xilinx ZC702 board";
@@ -102,8 +103,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
- scl-gpios = <&gpio0 50 0>;
- sda-gpios = <&gpio0 51 0>;
+ scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 {
compatible = "nxp,pca9548";
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index b185669b9c5e..11142401151f 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -131,8 +131,8 @@
&i2c0 { /* MIO 34-35 - can't stay here */
status = "okay";
clock-frequency = <40>;
- scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { /* u94 */
compatible = "nxp,pca9548";
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 95347604a27b..5ac66bc1ec5f 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -68,8 +68,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index 26ac540e7b0e..401de9efb913 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -68,8 +68,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 2b6c3946e858..8229244d241a 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -34,8 +34,8 @@
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio 24 (GPIO_ACT
[PATCH 04/17] arm64: zynqmp: Assign TSU clock frequency for KR260
From: Harini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KR260 CC to allow PTP functionality.
Signed-off-by: Harini Katakam
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 4
arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 ++
arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 ++
3 files changed, 8 insertions(+)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 4d44924f6633..a21dca87d248 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -169,24 +169,28 @@
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gpio {
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 5ac66bc1ec5f..caaf71d729e4 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -188,6 +188,7 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
+ assigned-clock-rates = <25000>;
};
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@@ -196,6 +197,7 @@
pinctrl-0 = <&pinctrl_gem1_default>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
+ assigned-clock-rates = <25000>;
mdio: mdio {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index 401de9efb913..f9d87559a719 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -188,6 +188,7 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
+ assigned-clock-rates = <25000>;
};
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@@ -196,6 +197,7 @@
pinctrl-0 = <&pinctrl_gem1_default>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
+ assigned-clock-rates = <25000>;
mdio: mdio {
#address-cells = <1>;
--
2.36.1
[PATCH 05/17] arm64: zynqmp: Fix gpio comment about No of gpios
There are total 174 gpios but from 0 - 173 that's why fix comment to
reflect it.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +-
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +-
arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +-
arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +-
arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +-
arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +-
arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +-
arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +-
arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +-
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts
b/arch/arm/dts/zynqmp-dlc21-revA.dts
index e287a9b6591c..1b247bfa8944 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -131,7 +131,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
- "", "", "", ""; /* 170 - 174 */
+ "", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO34/35 */
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index e24d070adb69..bf6ffb778b6a 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -201,7 +201,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
- "", "", "", ""; /* 170 - 174 */
+ "", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index 11142401151f..d5cfc61faf71 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -125,7 +125,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
- "", "", "", ""; /* 170 - 174 */
+ "", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index aa4f7c23ede5..97500b132876 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -154,7 +154,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
- "", "", "", ""; /* 170 - 174 */
+ "", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 7aa8c2b4d1f6..3bdcf052a555 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -149,7 +149,7 @@
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
- "", "", "", ""; /* 170 - 174 */
+ "", "", "", ""; /* 170 - 173 */
};
&i2c0 { /* MIO 34-35 - can't stay here */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 459736abe6bc..9a693a57a932 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -149,7 +149,7 @@
"", "", "", "", "", /* 155 - 159 */
"", ""
[PATCH 06/17] arm64: zynqmp: Increase reset assert time for TI SGMII PHY
From: Harini Katakam Increase reset assert time for TI SGMII PHY on KR260 CC starting 6.1 kernel. This PHY does not come out of reset with the existing 100us pulse width as per testing on multiple carrier cards. The reset is driven via a PCA9570 I2C expander. The expander driver was updated to an upstream version in 6.1 where gpio_chip _set was optimized. Delays in earlier kernels may have masked this issue. This is a safe workaround value for assert pulse width before the discussions are resolved with TI. Signed-off-by: Harini Katakam Reviewed-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index caaf71d729e4..d318773bd9d6 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -210,7 +210,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index f9d87559a719..69dba0761b37 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -210,7 +210,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; -- 2.36.1
[PATCH 07/17] arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
From: Harini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KV and KD carrier cards to allow PTP functionality.
Signed-off-by: Harini Katakam
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 1 +
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 8229244d241a..a81b3f6f51ad 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -165,6 +165,7 @@
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ assigned-clock-rates = <25000>;
mdio: mdio {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 96a51219f425..0ac20869b37d 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -152,6 +152,7 @@
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ assigned-clock-rates = <25000>;
mdio: mdio {
#address-cells = <1>;
--
2.36.1
[PATCH 08/17] arm64: zynqmp: Record compatible string for kv260 rev2
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335
autofocus feature). PS side is completely unchanged.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 0ac20869b37d..f935f25c887f 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -16,7 +16,8 @@
/plugin/;
&{/} {
- compatible = "xlnx,zynqmp-sk-kv260-rev1",
+ compatible = "xlnx,zynqmp-sk-kv260-rev2",
+"xlnx,zynqmp-sk-kv260-rev1",
"xlnx,zynqmp-sk-kv260-revB",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
model = "ZynqMP KV260 revB";
--
2.36.1
[PATCH 09/17] arm64: zynqmp: Cover K24 revB/1 SOM
Extend compatible versions for K24 SOM.
Changes are not affecting SW behavior that's why all versions are
compatible to each other.
Describing all revisions is done by purpose because user space SW is
reading compatible string for logic around DT overlays and bitstreams.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts
b/arch/arm/dts/zynqmp-sm-k24-revA.dts
index 24514409cb9e..653bd9362264 100644
--- a/arch/arm/dts/zynqmp-sm-k24-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -11,8 +11,9 @@
#include "zynqmp-sm-k26-revA.dts"
/ {
- model = "ZynqMP SM-K24 RevA";
- compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
+ model = "ZynqMP SM-K24 RevA/B/1";
+ compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB",
+"xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
"xlnx,zynqmp";
memory@0 {
--
2.36.1
[PATCH 10/17] arm64: zynqmp: Fix usb reset over bootmode pins on zcu100
The commit a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT
node") added usb phy reset over bootmode pins by default on usb0 only.
zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset
line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744
hub which is used only in host mode. Especially this chip requires reset to
operate properly that's why better assign gpio reset to usb1 instead of
usb0.
Without this change usb start crashed when runs.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu100-revC.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts
b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 78c325076006..a84cd86694e2 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -569,6 +569,7 @@
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
+ /delete-property/ reset-gpios;
};
&dwc3_0 {
@@ -584,6 +585,7 @@
pinctrl-0 = <&pinctrl_usb1_default>;
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
+ reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
};
&dwc3_1 {
--
2.36.1
[PATCH 11/17] arm64: zynqmp: Add L2 cache nodes
From: Radhey Shyam Pandey
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.
Reported-by: John Toomey
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 38114d55386b..59b52919f130 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -33,6 +33,7 @@
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -42,6 +43,7 @@
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -51,6 +53,7 @@
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -60,6 +63,13 @@
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
idle-states {
--
2.36.1
[PATCH 12/17] arm64: zynqmp: Sync node name address with reg (mailbox)
Address in node name should match with the first reg property in DT.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 59b52919f130..b9cfd562c913 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -121,7 +121,7 @@
#size-cells = <2>;
ranges;
- ipi_mailbox_pmu1: mailbox@ff990400 {
+ ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
--
2.36.1
[PATCH 13/17] arm64: zynqmp: add pmu interrupt-affinity
From: Radhey Shyam Pandey
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
guessing.
Reported-by: John Toomey
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b9cfd562c913..11eaf4b6a193 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -149,6 +149,10 @@
<0 144 4>,
<0 145 4>,
<0 146 4>;
+ interrupt-affinity = <&cpu0>,
+<&cpu1>,
+<&cpu2>,
+<&cpu3>;
};
psci {
--
2.36.1
[PATCH 14/17] arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usb
From: Piyush Mehta To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk' quirk for usb. This quirk is no more available in linux after the xilinx release 2022.2. This functionality is taken care of by the 'snps,resume-hs-terminations' quirk. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 11eaf4b6a193..223cdab5f93d 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -892,7 +892,6 @@ iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations; @@ -924,7 +923,6 @@ iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations; -- 2.36.1
[PATCH 15/17] arm64: zynqmp: Remove interrupt/reg-names for AMS
These two properties are not described in DT binding and also not used by driver that's why remove them. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 223cdab5f93d..299ad1e7c039 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -954,9 +954,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; - interrupt-names = "ams-irq"; reg = <0x0 0xffa5 0x0 0x800>; - reg-names = "ams-base"; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; -- 2.36.1
[PATCH 16/17] arm64: zynqmp: Rename ams_ps/pl node names
Fix child node names to be aligned with dt-binding available in the Linux
kernel which requires names as ams-ps@ and ams-pl@.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 299ad1e7c039..6228149b886e 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -960,13 +960,13 @@
#io-channel-cells = <1>;
ranges = <0 0 0xffa50800 0x800>;
- ams_ps: ams_ps@0 {
+ ams_ps: ams-ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
status = "disabled";
reg = <0x0 0x400>;
};
- ams_pl: ams_pl@400 {
+ ams_pl: ams-pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;
--
2.36.1
[PATCH 17/17] arm64: zynqmp: Remove clock-names from pcap node
Clock is not used in driver and also not described in binding.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 4
arch/arm/dts/zynqmp.dtsi | 1 -
2 files changed, 5 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index a21dca87d248..1ae8ea2e43f7 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -289,10 +289,6 @@
clocks = <&zynqmp_clk AMS_REF>;
};
-&zynqmp_pcap {
- clocks = <&zynqmp_clk PCAP>;
-};
-
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 6228149b886e..1632be843b15 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -193,7 +193,6 @@
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
- clock-names = "ref_clk";
};
xlnx_aes: zynqmp-aes {
--
2.36.1
Re: [PATCH] mmc: zynq_sdhci: Dll reset only for ZynqMP platform
Hi, On 7/11/23 07:00, Jaehoon Chung wrote: Hi, -Original Message- From: Michal Simek Sent: Monday, July 10, 2023 9:12 PM To: u-boot@lists.denx.de; g...@xilinx.com Cc: Ashok Reddy Soma ; Jaehoon Chung ; Peng Fan Subject: [PATCH] mmc: zynq_sdhci: Dll reset only for ZynqMP platform From: Ashok Reddy Soma Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e779251ce34f..935540d17194 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); How about using local variable to check whether it needs to reset or not? It's not efficient to call device_is_compatible() everytime. (I'm not sure that it will be added more in future.) e.g) bool reset = device_is_compatible(mmc->dev, "xlx,zynmp-8.8a"); if (reset) arasan_zynqmp_dll_reset(host, priv->node_id); .. If (reset) arasan_zynqmp_dll_reset(host, priv->node_id); This is very valid request and TBH I have already added this to our TODO list to convert all device_is_compatible() to flags because over time the driver was extended and this construct is used more than it should be. This is going to be the last device_is_compatible() patch. Is it fine for you? Thanks, Michal
Re: [PATCH] spl: Add function called after fpga image upload
On 7/10/23 17:50, Marek Vasut wrote:
On 7/10/23 17:47, Simon Glass wrote:
Hi,
On Mon, 10 Jul 2023 at 09:15, Taedcke, Christian
wrote:
Am 10.07.2023 um 15:44 schrieb Marek Vasut:
On 7/10/23 15:02, Taedcke, Christian wrote:
Am 10.07.2023 um 13:41 schrieb Michal Simek:
On 6/27/23 11:04, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This way custom logic can be implemented per board after the fpga
image is uploaded.
What do you want to do there?
I have 2 use-cases for this:
1. Clear the RAM which contained the bitstream (memset to zero). This
should happen independed of the result of the upload operation.
Is this some "secure-boot" related item ?
Not directly. This only helps reducing the time the decrypted bitstream
is stored in RAM.
2. Control a LED based on the upload result. So in case the upload
failed, i want to enable some error LED.
One issue is that the return values of spl_fit_load_fpga() or
spl_fit_upload_fpga() are not evaluated in common/spl
/spl_fit.c. So this error is not propagated to higher layers.
I my use-case uploading the bitstream is mandatory before starting
u-boot.
I expect Simon won't like that it is another weak function.
I did not find another way to implement the above use-cases. Maybe i
missed something.
Based on the above, probably make a weak wrapper around the fpga_load()
call, make it call fpga_load() by default and override it in some board
specific manner if needed.
So instead of the implemented function in this patch, i add
__weak int fpga_load_wrapper(int devnum, const void *buf, size_t bsize,
bitstream_type bstype, int flags) {
return fpga_load(devnum, buf, bsize, bstype, flags);
}
in the file common/spl/spl_fit.c and call this instead of fpga_load()?
This way only the logic for loading the fpga bitstream in the spl from a
fit image would change, but not anywhere else (which is ok for me).
Firstly we should not be using devnum but a struct udevice. Really the
FPGA subsystem needs to be converted to use drivel model properly.
Maybe Xilinx can help here as they are the maintainer of the FPGA framework ?
:-) I will add it to our list. And maybe USB maintainer can keep DWC3 and other
parts taken from Linux kernel aligned with latest version too.
M
Re: [ANN] U-Boot v2023.07 released
On 7/11/23 02:47, Tom Rini wrote: On Mon, Jul 10, 2023 at 02:14:58PM -0400, Tom Rini wrote: Hey all, It's a week after our planned release date, but, we've gotten the issues that had delayed the release sorted out and understood. I want to thank everyone that's contributed to this release, not just in terms of code, but documentation, testing and otherwise ensuring things go as smoothly as they can. In terms of a changelog, git log --merges v2023.07-rc6..v2023.07 contains what I've pulled since the last RC or: git log --merges v2023.04..v2023.07 for changes since the last full release. As always, more details in pull requests (or the tags referenced by them) will result in more details here. The merge window is formally open again, and I'll be merging in next shortly. v2023.10 is scheduled for October 2nd, 2023 and the merge window will close and -rc1 will be released on the 24th of July, and then the next window will open with -rc2, two weeks later. I know this means the merge window is slightly shorter than normal but with the next window having been open, I think that's fine. And I forgot to update the Makefile to drop -rc6. As I've also merged next to master and pushed that out, re-doing the tag seems sub-optimal. If it's important to distribution folks I can make v2023.07.01 which will really _just_ be correcting the Makefile. Or I'm open to other suggestions. Linus did this in past but on RC version. https://lwn.net/Articles/848265/ I think you can rename incorrect tag first and remove origin one. And creating new tag (with -rc6 removed from Makefile) make sense to me. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
Re: [PATCH] clk: Dont return error when assigned-clocks is empty or missing
Hi Sean, On 7/11/23 15:40, Sean Anderson wrote: On 7/11/23 05:51, Ashok Reddy Soma wrote: There is a chance that assigned-clock-rates is given and assigned-clocks could be empty. Dont return error in that case, because the probe of the corresponding driver will not be called at all if this fails. Better to continue to look for it and return 0. No, this is an error in the device tree. assigned-clock-rates depends on assigned-clocks, so you must provide the latter if the former is present. We were also checking it and in the Linux kernel it is handle like this. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-conf.c#n95 It means you can have rate assigned but not assigned-clocks property. And yes in working case both should be present to work properly. Thanks, Michal
Re: [PATCH] clk: Dont return error when assigned-clocks is empty or missing
On 7/11/23 16:28, Sean Anderson wrote: On 7/11/23 10:20, Michal Simek wrote: Hi Sean, On 7/11/23 15:40, Sean Anderson wrote: On 7/11/23 05:51, Ashok Reddy Soma wrote: There is a chance that assigned-clock-rates is given and assigned-clocks could be empty. Dont return error in that case, because the probe of the corresponding driver will not be called at all if this fails. Better to continue to look for it and return 0. No, this is an error in the device tree. assigned-clock-rates depends on assigned-clocks, so you must provide the latter if the former is present. We were also checking it and in the Linux kernel it is handle like this. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-conf.c#n95 It means you can have rate assigned but not assigned-clocks property. And yes in working case both should be present to work properly. What is the use-case for this? It will not pass schema checking [1] anyway. --Sean [1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml If you check your DT against schema. No doubt how correct behavior should be. It is just aligning behavior with Linux kernel if user messes up DT. Thanks, Michal
[PATCH v2] xilinx: board: Add support to pick bootscr address from DT
From: Algapally Santosh Sagar
The bootscript is expected at a default address specific to each
platform.
When high speed memory like Programmable Logic Double Data Rate RAM
(PL DDR RAM) or Higher Bandwidth Memory RAM (HBM) is used the boot.scr
may be loaded at a different offset. The offset needs to be set through
setenv. Due to the default values in some cases the boot.scr is falling
in between the kernel partition.
The bootscript address or the bootscript offset is fetched directly from
the DT and updated in the environment making it easier for automated
flows.
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Michal Simek
---
Changes in v2:
- s/bootscr-offset-from-ram-start/bootscr-ram-offset/
- Aligned with https://github.com/devicetree-org/dt-schema/pull/105
board/xilinx/common/board.c | 43 ++---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 0328d68e7512..53c4264e794c 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -405,6 +405,31 @@ static int env_set_by_index(const char *name, int index,
char *data)
return env_set(var, data);
}
+static int get_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset)
+{
+ int ret;
+ ofnode uboot;
+
+ *bootscr_address = 0;
+ *bootscr_offset = 0;
+
+ uboot = ofnode_path("/options/u-boot");
+ if (!ofnode_valid(uboot)) {
+ printf("%s: Missing /u-boot node\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u64(uboot, "bootscr-address", bootscr_address);
+ if (ret) {
+ ret = ofnode_read_u64(uboot, "bootscr-ram-offset",
+ bootscr_offset);
+ if (ret)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int board_late_init_xilinx(void)
{
u32 ret = 0;
@@ -414,9 +439,21 @@ int board_late_init_xilinx(void)
if (!IS_ENABLED(CONFIG_MICROBLAZE)) {
ulong scriptaddr;
-
- scriptaddr = env_get_hex("scriptaddr", 0);
- ret |= env_set_hex("scriptaddr", gd->ram_base + scriptaddr);
+ u64 bootscr_address;
+ u64 bootscr_offset;
+
+ /* Fetch bootscr_address/bootscr_offset from DT and update */
+ if (!get_bootscript_address(&bootscr_address, &bootscr_offset))
{
+ if (bootscr_offset)
+ ret |= env_set_hex("scriptaddr",
+ gd->ram_base +
bootscr_offset);
+ else
+ ret |= env_set_hex("scriptaddr",
bootscr_address);
+ } else {
+ /* Update scriptaddr(bootscr offset) from env */
+ scriptaddr = env_get_hex("scriptaddr", 0);
+ ret |= env_set_hex("scriptaddr", gd->ram_base +
scriptaddr);
+ }
}
if (IS_ENABLED(CONFIG_ARCH_ZYNQ) || IS_ENABLED(CONFIG_MICROBLAZE))
--
2.36.1
[PATCH] fwu: Allow code to properly decode trial state
Current code after capsule update (mtd write) is not changing active_index in mdata to previous_active_index. On the reboot this is shown but showing message "Boot idx 1 is not matching active idx 0, changing active_idx" which is changing active_idx and writing mdata to flash. But when this message is visible it is not checking which state that images are. If they have acceptance bit setup to yes everything is fine and valid images are booted (doesn't mean the latest one). But if acceptance bit is no and images are in trial state in_trial variable is never setup. Which means that from new flashed image stable image can be rewritten because in_trial is not setup properly. Signed-off-by: Michal Simek --- lib/fwu_updates/fwu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index cd5c3b64773b..38b50cb7628c 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -666,8 +666,6 @@ static int fwu_boottime_checks(void *ctx, struct event *event) ret = fwu_set_active_index(boot_idx); if (!ret) boottime_check = 1; - - return 0; } if (efi_init_obj_list() != EFI_SUCCESS) -- 2.36.1
[PATCH] efi_loader: Allow also empty capsule to be process
Empty capsule are also allowed to be process. Without it updated images
can't change their Image Acceptance state from no to yes.
Signed-off-by: Michal Simek
---
lib/efi_loader/efi_capsule.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 7a6f195cbc02..93e83e5f04c3 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -752,7 +752,8 @@ efi_status_t EFIAPI efi_update_capsule(
log_debug("Capsule[%d] (guid:%pUs)\n",
i, &capsule->capsule_guid);
if (!guidcmp(&capsule->capsule_guid,
-&efi_guid_firmware_management_capsule_id)) {
+&efi_guid_firmware_management_capsule_id) ||
+ fwu_empty_capsule(capsule)) {
ret = efi_capsule_update_firmware(capsule);
} else {
log_err("Unsupported capsule type: %pUs\n",
--
2.36.1
[PATCH] fwu: mtd: Fix dfu_alt_info generation for 2 images per bank
Code rewrites the last char of size with adding &. It is visible from
dfu_alt_info print before this patch:
Make dfu_alt_info: 'mtd nor0=bank0 raw 232 8;bank1 raw 27a
8000&mtd nor0=bank0 raw 23a 400;bank1 raw 282 400'
And after it:
Make dfu_alt_info: 'mtd nor0=bank0 raw 232 8;bank1 raw 27a
8&mtd nor0=bank0 raw 23a 400;bank1 raw 282 400'
Size for bank0 and bank1 must be the same because it is the same image.
Signed-off-by: Michal Simek
---
lib/fwu_updates/fwu_mtd.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c
index b73111ae24da..69cd3d7001f9 100644
--- a/lib/fwu_updates/fwu_mtd.c
+++ b/lib/fwu_updates/fwu_mtd.c
@@ -175,8 +175,10 @@ int fwu_gen_alt_info_from_mtd(char *buf, size_t len,
struct mtd_info *mtd)
l = strlen(buf);
/* Replace the last ';' with '&' if there is another image. */
- if (i != CONFIG_FWU_NUM_IMAGES_PER_BANK - 1 && l)
- buf[l - 1] = '&';
+ if (i != CONFIG_FWU_NUM_IMAGES_PER_BANK - 1 && l) {
+ buf[l] = '&';
+ buf++;
+ }
len -= l;
buf += l;
}
--
2.36.1
Re: [PATCH v2] xilinx: board: Add support to pick bootscr address from DT
On 7/13/23 22:51, Simon Glass wrote: Hi Michal, On Thu, 13 Jul 2023 at 06:54, Michal Simek wrote: From: Algapally Santosh Sagar The bootscript is expected at a default address specific to each platform. When high speed memory like Programmable Logic Double Data Rate RAM (PL DDR RAM) or Higher Bandwidth Memory RAM (HBM) is used the boot.scr may be loaded at a different offset. The offset needs to be set through setenv. Due to the default values in some cases the boot.scr is falling in between the kernel partition. The bootscript address or the bootscript offset is fetched directly from the DT and updated in the environment making it easier for automated flows. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Michal Simek --- Changes in v2: - s/bootscr-offset-from-ram-start/bootscr-ram-offset/ - Aligned with https://github.com/devicetree-org/dt-schema/pull/105 board/xilinx/common/board.c | 43 ++--- 1 file changed, 40 insertions(+), 3 deletions(-) How about we start a new 'options' API in /common to read things from /options? You could have opt_bootscript_addr() as the first member? Actually I was thinking if make sense to pretty much move this code to generic common location that it can be reused by others. Not sure if make sense to create new functions for all DT options properties because they should be read only once not multiple times. Or do you see the reason to call them multiple times? Thanks, Michal
[PATCH] fwu: Show number of attempts in Trial State
It is not visible anywhere in Trial State if this is the first, second, etc
attempt that's why show a message to be aware about status.
Signed-off-by: Michal Simek
---
lib/fwu_updates/fwu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index 38b50cb7628c..4d0c8b84b9d0 100644
--- a/lib/fwu_updates/fwu.c
+++ b/lib/fwu_updates/fwu.c
@@ -95,6 +95,8 @@ static int fwu_trial_count_update(void)
log_err("Unable to revert active_index\n");
ret = 1;
} else {
+ log_info("Trial State count: attempt %d out of %d\n",
+trial_state_ctr, CONFIG_FWU_TRIAL_STATE_CNT);
ret = trial_counter_update(&trial_state_ctr);
if (ret)
log_err("Unable to increment TrialStateCtr variable\n");
--
2.36.1
Re: [PATCH v2 5/8] tools: mkeficapsule: Add support for parsing capsule params from config file
On 6/24/23 15:41, Sughosh Ganu wrote: Add support for specifying the parameters needed for capsule generation through a config file, instead of passing them through command-line. Parameters for more than a single capsule file can be specified, resulting in generation of multiple capsules through a single invocation of the command. This path is to be used for generating capsules through a make target, with the parameters being parsed from the config file. Can you please also add support for adding comment to config file? Pretty much just ignore lines which starts with /* or so. Thanks, Michal
Re: [PATCH v2 5/8] tools: mkeficapsule: Add support for parsing capsule params from config file
On 7/15/23 14:30, Sughosh Ganu wrote: On Fri, 14 Jul 2023 at 16:14, Michal Simek wrote: On 6/24/23 15:41, Sughosh Ganu wrote: Add support for specifying the parameters needed for capsule generation through a config file, instead of passing them through command-line. Parameters for more than a single capsule file can be specified, resulting in generation of multiple capsules through a single invocation of the command. This path is to be used for generating capsules through a make target, with the parameters being parsed from the config file. Can you please also add support for adding comment to config file? Pretty much just ignore lines which starts with /* or so. Comments are currently supported with the '#' character, so that lines starting with # are considered as comments. Good thanks. M
Re: [PATCH] .mailmap: Correct entires for Masahiro Yamada
On 7/15/23 17:02, Tom Rini wrote:
His entries had the correct email address listed last rather than first,
correct this.
Fixes 4fa4227cdd14 (".mailmap: Record all address for main U-Boot contributor")
Signed-off-by: Tom Rini
---
.mailmap | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/.mailmap b/.mailmap
index 312a428dc9f6..05cb310e416f 100644
--- a/.mailmap
+++ b/.mailmap
@@ -65,8 +65,8 @@ Marek Vasut
Marek Vasut
Marek Vasut
Markus Klotzbuecher
-Masahiro Yamada
-Masahiro Yamada
+Masahiro Yamada
+Masahiro Yamada
Michal Simek
Michal Simek
Michal Simek
Acked-by: Michal Simek
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
Re: [PATCH] xilinx: zynq: Enable fdt apply utility for zynq
On 7/10/23 13:56, Michal Simek wrote: From: Raju Kumar Pothuraju Enables the FDT library (libfdt) overlay support for zynq platforms to be able to use fdt apply command. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Michal Simek --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 474abc7f6b0b..990057734595 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -7,6 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_ENV_OFFSET=0xE0 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_STACK_R_ADDR=0x20 CONFIG_SPL_STACK=0xfe00 CONFIG_SPL=y Applied. M
Re: [PATCH] arm64: zynqmp: Switch to amd.com emails
On 7/10/23 14:35, Michal Simek wrote: Update my and DPs email address to match current setup. Signed-off-by: Michal Simek --- The same changes have been done in Linux. Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.si...@amd.com --- arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/versal-mini-emmc0.dts| 4 ++-- arch/arm/dts/versal-mini-emmc1.dts| 4 ++-- arch/arm/dts/versal-mini-ospi.dtsi| 4 ++-- arch/arm/dts/versal-mini-qspi.dtsi| 4 ++-- arch/arm/dts/versal-mini.dts | 2 +- arch/arm/dts/zynq-dlc20-rev1.0.dts| 2 +- arch/arm/dts/zynq-minized.dts | 2 +- arch/arm/dts/zynqmp-a2197-revA.dts| 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp-dlc21-revA.dts| 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc0.dts| 2 +- arch/arm/dts/zynqmp-mini-emmc1.dts| 2 +- arch/arm/dts/zynqmp-mini-nand.dts | 4 ++-- arch/arm/dts/zynqmp-mini-qspi.dts | 4 ++-- arch/arm/dts/zynqmp-mini.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-r5.dts| 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 4 ++-- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.1.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1275-revB.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1285-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- arch/arm/mach-tegra/arm64-mmu.c | 2 +- arch/arm/mach-versal/Makefile | 2 +- arch/arm/mach-versal/clk.c| 2 +- arch/arm/mach-versal/cpu.c| 2 +- arch/arm/mach-versal/mp.c | 2 +- arch/arm/mach-zynqmp/Makefile | 2 +- arch/arm/mach-zynqmp/clk.c| 2 +- arch/arm/mach-zynqmp/cpu.c| 2 +- arch/arm/mach-zynqmp/handoff.c| 2 +- arch/arm/mach-zynqmp/include/mach/clk.h | 2 +- arch/arm/mach-zynqmp/include/mach/hardware.h | 2 +- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 2 +- arch/arm/mach-zynqmp/mp.c | 2 +- arch/arm/mach-zynqmp/psu_spl_init.c | 2 +- arch/arm/mach-zynqmp/spl.c| 2 +- arch/microblaze/cpu/spl.c | 2 +- arch/microblaze/cpu/u-boot-spl.lds| 2 +- arch/microblaze/include/asm/spl.h | 2 +- board/xilinx/common/Makefile | 2 +- board/xilinx/common/board.h | 2 +- board/xilinx/common/cpu-info.c| 2 +- board/xilinx/common/fru.h | 2 +- board/xilinx/versal/Makefile | 2 +- board/xilinx/versal/board.c | 2 +- board/xilinx/versal/cmds.c| 2 +- board/xilinx/zynqmp/Makefile | 2 +- board/xilinx/zynqmp/cmds.c| 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- common/spl/spl_ram.c | 2 +- drivers/ata/sata_ceva.c | 2 +- drivers/clk/clk_versal.c | 2 +- drivers/fpga/versalpl.c | 2 +- drivers/fpga/zynqmppl.c | 4
Re: [PATCH v2] xilinx: zynqmp: Extract aes operation into new file
On 7/10/23 16:09, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This moves the aes operation that is performed by the pmu into a
separate file. This way it can be called not just from the shell
command, but also e.g. from board initialization code.
Signed-off-by: Christian Taedcke
---
Changes in v2:
- convert doxygen comments to kernel-doc
- fix typos
- fix header license
- fix do_zynqmp_aes() return value
arch/arm/mach-zynqmp/Makefile | 3 +-
arch/arm/mach-zynqmp/aes.c| 58 +++
.../arm/mach-zynqmp/include/mach/zynqmp_aes.h | 32 ++
board/xilinx/zynqmp/cmds.c| 43 +-
4 files changed, 94 insertions(+), 42 deletions(-)
create mode 100644 arch/arm/mach-zynqmp/aes.c
create mode 100644 arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index bb1830c846..1a76493bef 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek
-obj-y += clk.o
-obj-y += cpu.o
+obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c
new file mode 100644
index 00..115bca8338
--- /dev/null
+++ b/arch/arm/mach-zynqmp/aes.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu
+ *
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG
+ * Christian Taedcke
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+int zynqmp_aes_operation(struct zynqmp_aes *aes)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (zynqmp_firmware_version() <= PMUFW_V1_0)
+ return -ENOENT;
+
+ if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
+ flush_dcache_range(aes->srcaddr,
+ (aes->srcaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN)));
+ flush_dcache_range(aes->ivaddr,
+ (aes->ivaddr +
+ roundup(IV_SIZE, ARCH_DMA_MINALIGN)));
+ flush_dcache_range(aes->dstaddr,
+ (aes->dstaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN)));
+ }
+
+ if (aes->keysrc == 0) {
+ if (aes->keyaddr == 0)
+ return -EINVAL;
+
+ flush_dcache_range(aes->keyaddr, (aes->keyaddr +
+ roundup(KEY_PTR_LEN,
ARCH_DMA_MINALIGN)));
+ }
+
+ flush_dcache_range((ulong)aes, (ulong)(aes) +
+ roundup(sizeof(struct zynqmp_aes),
ARCH_DMA_MINALIGN));
+
+ ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
+ lower_32_bits((ulong)aes), 0, 0, ret_payload);
+ if (ret || ret_payload[1]) {
+ printf("Failed: AES op status:0x%x, errcode:0x%x\n",
+ ret, ret_payload[1]);
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
new file mode 100644
index 00..5bffb6b64c
--- /dev/null
+++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG
+ * Christian Taedcke
+ *
+ * Declaration of AES operation functionality for ZynqMP.
+ */
+
+#ifndef ZYNQMP_AES_H
+#define ZYNQMP_AES_H
+
+struct zynqmp_aes {
+ u64 srcaddr;
+ u64 ivaddr;
+ u64 keyaddr;
+ u64 dstaddr;
+ u64 len;
+ u64 op;
+ u64 keysrc;
+};
+
+/*
Should start with /**
+ * Performs an aes operation using the pmu firmware
+ *
+ * @aes The aes operation buffer that must have been allocated using
+ * ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1).
+ *
+ * Return: 0 in case of success, in case of an error any other value
+ */
Not a kernel-doc format.
./scripts/kernel-doc -man -v 2>/dev/null
arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
The rest looks good.
M
Re: [PATCH] mtd: spi-nor: Add support for w25q256jwm
On 6/26/23 05:32, Venkatesh Yadav Abbarapu wrote:
Add support for Winbond 256M-bit flash w25q256jwm.
Performed basic erase/write/readback operations on
ZynqMP zc1751+dc1 board.
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-ids.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 3f8b796789..53a743a038 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -446,6 +446,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("w25q256jwm", 0xef8019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
{
INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
Applied.
M
Re: [PATCH] mmc: zynq_sdhci: Dll reset only for ZynqMP platform
On 7/10/23 14:11, Michal Simek wrote: From: Ashok Reddy Soma Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e779251ce34f..935540d17194 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); @@ -468,7 +469,9 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) } udelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); /* Enable only interrupts served by the SD controller */ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, Applied. M
Re: [PATCH] mtd: Add missing MTD dependency for cfi_mtd
On 7/4/23 14:04, Michal Simek wrote: cfi_mtd requires add_mtd_device() which is available only when MTD is enabled that's why record this dependency. Signed-off-by: Michal Simek --- drivers/mtd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 5fa88dae5f33..c56840c84975 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -128,7 +128,7 @@ config FLASH_SPANSION_S29WS_N config FLASH_CFI_MTD bool "Enable CFI MTD driver" - depends on FLASH_CFI_DRIVER + depends on FLASH_CFI_DRIVER && MTD help This option enables the building of the cfi_mtd driver in the drivers directory. The driver exports CFI flash Applied. M
Re: [PATCH 00/17] arm64: zynqmp: Sync DTs was [Hi,]
On 7/10/23 14:37, Michal Simek wrote: sending couple of DT patches to be in sync with Linux repository. There are still some changes but we are working on it to get them fully in sync for SystemReady IR certification. Thanks, Michal Harini Katakam (3): arm64: zynqmp: Assign TSU clock frequency for KR260 arm64: zynqmp: Increase reset assert time for TI SGMII PHY arm64: zynqmp: Assign TSU clock frequency for KV and KD boards Manikanta Guntupalli (1): xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal Michal Simek (8): arm64: zynqmp: Fix gpio comment about No of gpios arm64: zynqmp: Record compatible string for kv260 rev2 arm64: zynqmp: Cover K24 revB/1 SOM arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 arm64: zynqmp: Sync node name address with reg (mailbox) arm64: zynqmp: Remove interrupt/reg-names for AMS arm64: zynqmp: Rename ams_ps/pl node names arm64: zynqmp: Remove clock-names from pcap node Parth Gajjar (1): arm64: zynqmp: Update MALI 400 interrupt and clock names Piyush Mehta (1): arm64: zynqmp: remove snps,enable_guctl1_resume_quirk quirk for usb Radhey Shyam Pandey (2): arm64: zynqmp: Add L2 cache nodes arm64: zynqmp: add pmu interrupt-affinity Varalaxmi Bingi (1): arm: xilinx: Setting default i2c clock frequency to 400kHz arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynq-zc702.dts | 5 ++-- arch/arm/dts/zynqmp-clk-ccf.dtsi | 10 +++ arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 6 ++--- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts| 8 +++--- arch/arm/dts/zynqmp-sck-kr-g-revB.dts| 8 +++--- arch/arm/dts/zynqmp-sck-kv-g-revA.dts| 5 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts| 8 +++--- arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 6 ++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 +++--- arch/arm/dts/zynqmp-zcu100-revC.dts | 6 +++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 +-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 +-- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu208-revA.dts | 10 +++ arch/arm/dts/zynqmp-zcu216-revA.dts | 10 +++ arch/arm/dts/zynqmp.dtsi | 33 28 files changed, 103 insertions(+), 79 deletions(-) Applied and also fix subject for this cover letter just in reply. M
Re: [PATCH v3] event: Add fpga load event
On 7/12/23 13:39, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This enables implementing custom logic after a bitstream was loaded
into the fpga.
Signed-off-by: Christian Taedcke
---
Changes in v3:
- replace #if with if
- remove previously added printf
- return notification error from fpga_load()
- fix static_assert checking event name list
Changes in v2:
- replace __weak function with a new event
common/event.c | 3 +++
drivers/fpga/fpga.c | 20
include/event.h | 16
3 files changed, 39 insertions(+)
diff --git a/common/event.c b/common/event.c
index 164c95f8f5..20720c5283 100644
--- a/common/event.c
+++ b/common/event.c
@@ -36,6 +36,9 @@ const char *const type_name[] = {
/* init hooks */
"misc_init_f",
+ /* Fpga load hook */
+ "fpga_load",
+
/* fdt hooks */
"ft_fixup",
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 7f6b6bc73a..81e6d8ffc0 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size,
}
#endif
+static int fpga_load_event_notify(const void *buf, size_t bsize, int result)
+{
+ if (CONFIG_IS_ENABLED(EVENT)) {
+ struct event_fpga_load load = {
+ .buf = buf,
+ .bsize = bsize,
+ .result = result
+ };
+
+ return event_notify(EVT_FPGA_LOAD, &load, sizeof(load));
+ }
+
+ return 0;
+}
+
/*
* Generic multiplexing code
*/
@@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype,
int flags)
{
int ret_val = FPGA_FAIL; /* assume failure */
+ int ret_notify;
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
(char *)__func__);
@@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
}
}
+ ret_notify = fpga_load_event_notify(buf, bsize, ret_val);
+ if (ret_notify)
+ return ret_notify;
+
return ret_val;
}
diff --git a/include/event.h b/include/event.h
index fe41080fa6..77124c2e73 100644
--- a/include/event.h
+++ b/include/event.h
@@ -31,6 +31,9 @@ enum event_t {
/* Init hooks */
EVT_MISC_INIT_F,
+ /* Fpga load hook */
+ EVT_FPGA_LOAD,
+
/* Device tree fixups before booting */
EVT_FT_FIXUP,
@@ -59,6 +62,19 @@ union event_data {
struct udevice *dev;
} dm;
+ /**
+* struct event_fpga_load - fpga load event
+*
+* @buf: The buffer that was loaded into the fpga
+* @bsize: The size of the buffer that was loaded into the fpga
+* @result: Result of the load operation
+*/
+ struct event_fpga_load {
+ const void *buf;
+ size_t bsize;
+ int result;
+ } fpga_load;
+
/**
* struct event_ft_fixup - FDT fixup before booting
*
There is the error generated for kmcent2_defconfig.
Please fix.
For more information please take a look at
https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/jobs/657127
+In file included from board/keymile/kmcent2/kmcent2.c:9:
+include/event.h:74:17: error: unknown type name 'size_t'
+ 74 | size_t bsize;
+ | ^~
+make[2]: *** [scripts/Makefile.build:257: board/keymile/kmcent2/kmcent2.o]
Error 1
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
Re: [PATCH] env: Fix default environment saving issue
On 7/4/23 08:16, Ashok Reddy Soma wrote:
When CONFIG_SYS_REDUNDAND_ENVIRONMENT is enabled, by default env is
getting saved to redundant environment irrespective of primary env is
present or not.
It means even if primary and redundant environment are not present, by
default, env is getting stored to redundant environment. Even if primary
env is present, it is choosing to store in redudndant env.
Ideally it should look for primary env and choose to store in primary env
if it is present. If both primary and redundant env are not present then
it should save in to primary env area.
Fix the issue by making env_valid = ENV_INVALID when both the
environments are not present.
Signed-off-by: Ashok Reddy Soma
---
env/common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/env/common.c b/env/common.c
index 8beb8e6aa4..0ecdb248a0 100644
--- a/env/common.c
+++ b/env/common.c
@@ -353,6 +353,7 @@ int env_check_redund(const char *buf1, int buf1_read_fail,
tmp_env2->crc;
if (!crc1_ok && !crc2_ok) {
+ gd->env_valid = ENV_INVALID;
return -ENOMSG; /* needed for env_load() */
} else if (crc1_ok && !crc2_ok) {
gd->env_valid = ENV_VALID;
Applied.
M
Re: [PATCH] efi_loader: Allow also empty capsule to be process
On 7/18/23 17:41, Heinrich Schuchardt wrote: On 13.07.23 16:35, Michal Simek wrote: Empty capsule are also allowed to be process. Without it updated images can't change their Image Acceptance state from no to yes. Is there any documentation describing the usage of empty capsule to set the image acceptance state? I actually don't know about documentation. I was talking to Ilias to make sure that documentation is up2date because there are missing couple of things there. I am testing A/B update and if you setup oemflags to 0x8000 then capsules are not automatically accepted and waiting for acceptance capsule to be passed. When I tested it I found out that they are not process that's why I created this patch. But definitely someone should check that logic that the patch is right based on intention how these empty capsules should be used. I am actually not quite sure how revert capsules should be used and how to revert only certain image if you use multiple images in the same bank. Thanks, Michal
Re: [PATCH v3] event: Add fpga load event
On 7/18/23 13:22, Taedcke, Christian wrote:
Hello Michal,
On 17.07.2023 12:36, Michal Simek wrote:
On 7/12/23 13:39, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This enables implementing custom logic after a bitstream was loaded
into the fpga.
Signed-off-by: Christian Taedcke
---
Changes in v3:
- replace #if with if
- remove previously added printf
- return notification error from fpga_load()
- fix static_assert checking event name list
Changes in v2:
- replace __weak function with a new event
common/event.c | 3 +++
drivers/fpga/fpga.c | 20
include/event.h | 16
3 files changed, 39 insertions(+)
diff --git a/common/event.c b/common/event.c
index 164c95f8f5..20720c5283 100644
--- a/common/event.c
+++ b/common/event.c
@@ -36,6 +36,9 @@ const char *const type_name[] = {
/* init hooks */
"misc_init_f",
+ /* Fpga load hook */
+ "fpga_load",
+
/* fdt hooks */
"ft_fixup",
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 7f6b6bc73a..81e6d8ffc0 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size,
}
#endif
+static int fpga_load_event_notify(const void *buf, size_t bsize, int result)
+{
+ if (CONFIG_IS_ENABLED(EVENT)) {
+ struct event_fpga_load load = {
+ .buf = buf,
+ .bsize = bsize,
+ .result = result
+ };
+
+ return event_notify(EVT_FPGA_LOAD, &load, sizeof(load));
+ }
+
+ return 0;
+}
+
/*
* Generic multiplexing code
*/
@@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype,
int flags)
{
int ret_val = FPGA_FAIL; /* assume failure */
+ int ret_notify;
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
(char *)__func__);
@@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype,
}
}
+ ret_notify = fpga_load_event_notify(buf, bsize, ret_val);
+ if (ret_notify)
+ return ret_notify;
+
return ret_val;
}
diff --git a/include/event.h b/include/event.h
index fe41080fa6..77124c2e73 100644
--- a/include/event.h
+++ b/include/event.h
@@ -31,6 +31,9 @@ enum event_t {
/* Init hooks */
EVT_MISC_INIT_F,
+ /* Fpga load hook */
+ EVT_FPGA_LOAD,
+
/* Device tree fixups before booting */
EVT_FT_FIXUP,
@@ -59,6 +62,19 @@ union event_data {
struct udevice *dev;
} dm;
+ /**
+ * struct event_fpga_load - fpga load event
+ *
+ * @buf: The buffer that was loaded into the fpga
+ * @bsize: The size of the buffer that was loaded into the fpga
+ * @result: Result of the load operation
+ */
+ struct event_fpga_load {
+ const void *buf;
+ size_t bsize;
+ int result;
+ } fpga_load;
+
/**
* struct event_ft_fixup - FDT fixup before booting
*
There is the error generated for kmcent2_defconfig.
Please fix.
For more information please take a look at
https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/jobs/657127
+In file included from board/keymile/kmcent2/kmcent2.c:9:
+include/event.h:74:17: error: unknown type name 'size_t'
+ 74 | size_t bsize;
+ | ^~
+make[2]: *** [scripts/Makefile.build:257: board/keymile/kmcent2/kmcent2.o]
Error 1
Thanks for pasting the error message here, since i cannot access your link.
Which header should i inlucde before event.h in kmcent2.c (to fix the error)?
1. common.h seems to be used often, but i only need size_t, or
2. stddef.h seems to be used sometimes, but never in the board folder, or
3. linux/stddef.h seems to be used sometimes, but never in the board folder
I think priority is from top to down.
Just try to build that target to see that error first and then try to add
missing header to fix it.
Thanks,
Michal
Re: [PATCH] net: axi_emac: Change return value to -EAGAIN if RX is not ready
On 7/19/23 08:53, Maksim Kiselev wrote:
If there is no incoming package than axiemac_recv will return -1 which
in turn leads to printing `eth_rx: recv() returned error -1` error
message in eth_rx function. But missing a package is not an fatal error,
so return -EAGAIN in that case would be more suitable.
Signed-off-by: Maksim Kiselev
---
drivers/net/xilinx_axi_emac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 3e9919993d..39cb3cc260 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -748,7 +748,7 @@ static int axiemac_recv(struct udevice *dev, int flags,
uchar **packetp)
/* Wait for an incoming packet */
if (!isrxready(priv))
- return -1;
+ return -EAGAIN;
debug("axiemac: RX data ready\n");
Make sense. Applied.
M
Re: [PATCH] efi_loader: Allow also empty capsule to be process
Hi, On 7/20/23 07:49, AKASHI Takahiro wrote: Hi, On Wed, Jul 19, 2023 at 08:28:41AM +0200, Michal Simek wrote: On 7/18/23 17:41, Heinrich Schuchardt wrote: On 13.07.23 16:35, Michal Simek wrote: Empty capsule are also allowed to be process. Without it updated images can't change their Image Acceptance state from no to yes. Is there any documentation describing the usage of empty capsule to set the image acceptance state? I actually don't know about documentation. I was talking to Ilias to make sure that documentation is up2date because there are missing couple of things there. Sughosh should have more to say here about A/B update. I am testing A/B update and if you setup oemflags to 0x8000 then capsules are not automatically accepted and waiting for acceptance capsule to be passed. When I tested it I found out that they are not process that's why I created this patch. The path you tried to modify is only executed by "efidebug capsule update" or more specifically via the runtime service, UPDATE_CAPSULE. But this API is NOT officially supported in the current capsule implementation (at least, in my initial intention). The only way to invoke capsule updates is to reboot the system. If you want to test A/B update, please do the reboot. I realized that to get full flow you need to use capsule update on disk to get all functionalities. But it is very impractical. Actually I would expect via efidebug you should be able to perform all steps as capsule update performs when you do reboot. I would also understand that via efidebug you are not able to apply any capsule but I don't think it is right that you can apply just update capsules but not empty capsules. I would understand none or all but not something in the middle. Thanks, Michal
Re: [PATCH] efi_loader: Allow also empty capsule to be process
On 7/20/23 08:36, Sughosh Ganu wrote: On Thu, 20 Jul 2023 at 11:37, Michal Simek wrote: Hi, On 7/20/23 07:49, AKASHI Takahiro wrote: Hi, On Wed, Jul 19, 2023 at 08:28:41AM +0200, Michal Simek wrote: On 7/18/23 17:41, Heinrich Schuchardt wrote: On 13.07.23 16:35, Michal Simek wrote: Empty capsule are also allowed to be process. Without it updated images can't change their Image Acceptance state from no to yes. Is there any documentation describing the usage of empty capsule to set the image acceptance state? I actually don't know about documentation. I was talking to Ilias to make sure that documentation is up2date because there are missing couple of things there. Sughosh should have more to say here about A/B update. I am testing A/B update and if you setup oemflags to 0x8000 then capsules are not automatically accepted and waiting for acceptance capsule to be passed. When I tested it I found out that they are not process that's why I created this patch. The path you tried to modify is only executed by "efidebug capsule update" or more specifically via the runtime service, UPDATE_CAPSULE. But this API is NOT officially supported in the current capsule implementation (at least, in my initial intention). The only way to invoke capsule updates is to reboot the system. If you want to test A/B update, please do the reboot. I realized that to get full flow you need to use capsule update on disk to get all functionalities. But it is very impractical. Actually I would expect via efidebug you should be able to perform all steps as capsule update performs when you do reboot. I would also understand that via efidebug you are not able to apply any capsule but I don't think it is right that you can apply just update capsules but not empty capsules. I would understand none or all but not something in the middle. The A/B update functionality requires using the capsule-on-disk functionality for performing the updates. This is also mentioned in the fwu_updates.rst document. You should be able to apply empty capsules even with the 'efidebug disk-update' command. Yes this is working fine. ZynqMP> efidebug capsule disk-update # Applying capsule capsule1.bin succeeded. # Applying capsule capsule2.bin succeeded. Reboot after firmware update. I tested it also with empty capsules which are also process properly. I have never used the 'efidebug capsule update' command, so I'm not sure if that is supported. Like Takahiro mentioned, if you place the capsules(genuine or empty) under the /EFI/UpdateCapsule/ directory, the update should happen automatically, since the fwu update feature also enables the EFI_CAPSULE_ON_DISK_EARLY config. Yes that's work fine on production systems. But from my point of view there shouldn't be really a problem to also apply empty capsule via efidebug capsule update to be able to see that steps and changes in mdata structure without performing reset. Again I have no issue with code which is using capsule-on-disk feature but I think that pretty much all these steps which are done automatically should be possible to do through steps to see them. That's what you can do with bootm start and simply stepping through it. I am testing 2 images per bank and I can simply load other partition by simple commands tftpboot 0x10 192.168.0.105:capsule1.bin && efidebug capsule update -v 0x10 tftpboot 0x10 192.168.0.105:capsule2.bin && efidebug capsule update -v 0x10 And then perform reset to them. I would expect that the same should work also for empty capsules. I am not able to get in this to trial state but I expect this is simply because I am not creating TrialStateCtr variable by hand. Take a look at log below. Thanks, Michal U-Boot 2023.07-00693-g41137e2e3970 (Jul 20 2023 - 08:46:56 +0200) CPU: ZynqMP Silicon: v3 Chip: xck26 Detected name: zynqmp-sm-k26-xcl2gc-ed-revB-sck-kv-g-revB Model: ZynqMP KV260 revB Board: Xilinx ZynqMP DRAM: 2 GiB (effective 4 GiB) PMUFW: v1.1 Xilinx I2C FRU format at nvmem0: Manufacturer Name: XILINX Product Name: SM-K26-XCL2GC-ED Serial No: 50572B111F2H Part Number: 5057-02ED File ID: 0x0 Revision Number: B Xilinx I2C FRU format at nvmem1: Manufacturer Name: XILINX Product Name: SCK-KV-G Serial No: 50582B112M07 Part Number: 5058-02 File ID: 0x0 Revision Number: B EL Level: EL2 Secure Boot:not authenticated, not encrypted Core: 90 devices, 33 uclasses, devicetree: fit NAND: 0 MiB MMC: mmc@ff16: 0, mmc@ff17: 1 Loading Environment from SPIFlash... SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB OK In:serial Out: serial Err: serial Net: PHY reset timed out ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 1, interface rgmii-id eth0: ethernet@ff0e fwu_plat_get_bootidx: boot_idx: 1, active_idx: 1 tpm_tis_spi_probe: mi
Re: [PATCH] efi_loader: Allow also empty capsule to be process
On 7/20/23 10:45, Sughosh Ganu wrote: On Thu, 20 Jul 2023 at 13:26, Michal Simek wrote: On 7/20/23 08:36, Sughosh Ganu wrote: On Thu, 20 Jul 2023 at 11:37, Michal Simek wrote: Hi, On 7/20/23 07:49, AKASHI Takahiro wrote: Hi, On Wed, Jul 19, 2023 at 08:28:41AM +0200, Michal Simek wrote: On 7/18/23 17:41, Heinrich Schuchardt wrote: On 13.07.23 16:35, Michal Simek wrote: Empty capsule are also allowed to be process. Without it updated images can't change their Image Acceptance state from no to yes. Is there any documentation describing the usage of empty capsule to set the image acceptance state? I actually don't know about documentation. I was talking to Ilias to make sure that documentation is up2date because there are missing couple of things there. Sughosh should have more to say here about A/B update. I am testing A/B update and if you setup oemflags to 0x8000 then capsules are not automatically accepted and waiting for acceptance capsule to be passed. When I tested it I found out that they are not process that's why I created this patch. The path you tried to modify is only executed by "efidebug capsule update" or more specifically via the runtime service, UPDATE_CAPSULE. But this API is NOT officially supported in the current capsule implementation (at least, in my initial intention). The only way to invoke capsule updates is to reboot the system. If you want to test A/B update, please do the reboot. I realized that to get full flow you need to use capsule update on disk to get all functionalities. But it is very impractical. Actually I would expect via efidebug you should be able to perform all steps as capsule update performs when you do reboot. I would also understand that via efidebug you are not able to apply any capsule but I don't think it is right that you can apply just update capsules but not empty capsules. I would understand none or all but not something in the middle. The A/B update functionality requires using the capsule-on-disk functionality for performing the updates. This is also mentioned in the fwu_updates.rst document. You should be able to apply empty capsules even with the 'efidebug disk-update' command. Yes this is working fine. ZynqMP> efidebug capsule disk-update # Applying capsule capsule1.bin succeeded. # Applying capsule capsule2.bin succeeded. Reboot after firmware update. I tested it also with empty capsules which are also process properly. I have never used the 'efidebug capsule update' command, so I'm not sure if that is supported. Like Takahiro mentioned, if you place the capsules(genuine or empty) under the /EFI/UpdateCapsule/ directory, the update should happen automatically, since the fwu update feature also enables the EFI_CAPSULE_ON_DISK_EARLY config. Yes that's work fine on production systems. But from my point of view there shouldn't be really a problem to also apply empty capsule via efidebug capsule update to be able to see that steps and changes in mdata structure without performing reset. The 'efidebug capsule update' command calls the efi_update_capsule function, which implements the UpdateCapsule runtime service call. The initial versions of my fwu patches were indeed adding support for this path, but one of the review comments was to restrict support only for the capsule-on-disk path when performing the update in u-boot, since we are not using the runtime call in u-boot. I don't think this is a valid argument. As I said I would understand if there is no interface for any capsule. It means having support for both or none is IMHO the way we should support. Can you please point me to that discussion? Thanks, Michal
Re: [PATCH] clk: Dont return error when assigned-clocks is empty or missing
Hi Sean, On 7/11/23 16:55, Michal Simek wrote: On 7/11/23 16:28, Sean Anderson wrote: On 7/11/23 10:20, Michal Simek wrote: Hi Sean, On 7/11/23 15:40, Sean Anderson wrote: On 7/11/23 05:51, Ashok Reddy Soma wrote: There is a chance that assigned-clock-rates is given and assigned-clocks could be empty. Dont return error in that case, because the probe of the corresponding driver will not be called at all if this fails. Better to continue to look for it and return 0. No, this is an error in the device tree. assigned-clock-rates depends on assigned-clocks, so you must provide the latter if the former is present. We were also checking it and in the Linux kernel it is handle like this. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-conf.c#n95 It means you can have rate assigned but not assigned-clocks property. And yes in working case both should be present to work properly. What is the use-case for this? It will not pass schema checking [1] anyway. --Sean [1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml If you check your DT against schema. No doubt how correct behavior should be. It is just aligning behavior with Linux kernel if user messes up DT. I see that you are listed as clock maintainer. Are you fine with this alignment patch or do you want to change something or reject it? Thanks, Michal
Re: [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks
On 7/19/23 10:49, Ashok Reddy Soma wrote:
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma
---
drivers/clk/clk_zynqmp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index be0ee50e0e..27479391e1 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -718,6 +718,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong
rate)
switch (id) {
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
+ case gem0_rx ... gem3_rx:
+ case gem_tsu:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,
Applied.
M
Re: [PATCH] clk: zynqmp: Add gem rx and tsu clocks to return register
On 7/20/23 09:28, Ashok Reddy Soma wrote: Add gem_tsu and gem0_rx till gem3_rx to return proper register from zynqmp_clk_get_register. Otherwise firmware won't be able to set clock for these due to incorrect register address. Signed-off-by: Ashok Reddy Soma --- drivers/clk/clk_zynqmp.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 27479391e1..b0843fe546 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -269,17 +269,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) case usb3_dual_ref: return CRL_APB_USB3_DUAL_REF_CTRL; case gem_tsu_ref: + case gem_tsu: return CRL_APB_GEM_TSU_REF_CTRL; case gem0_tx: + case gem0_rx: case gem0_ref: return CRL_APB_GEM0_REF_CTRL; case gem1_tx: + case gem1_rx: case gem1_ref: return CRL_APB_GEM1_REF_CTRL; case gem2_tx: + case gem2_rx: case gem2_ref: return CRL_APB_GEM2_REF_CTRL; case gem3_tx: + case gem3_rx: case gem3_ref: return CRL_APB_GEM3_REF_CTRL; case usb0_bus_ref: Applied. M
[GIT PULL] xilinx patches for v2023.10-rc1 v2
Hi Tom, please pull these patches to your tree. CI is not reporting any issue. The biggest part is adding support for versal-net mini configuration for non volatile memories programming and also DT changes based on our effort to be aligned with dt-schema validation. Thanks, Michal The following changes since commit 7fe5accb4516144b7abb8f183640cdf50423121e: Merge branch '2023-07-20-assorted-CI-updates' (2023-07-20 21:28:59 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2023.10-rc1-v2 for you to fetch changes up to a1190b4d6a9bf3a45038e3eba4a11de4be2b1cca: event: Add fpga load event (2023-07-21 09:00:39 +0200) Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs Algapally Santosh Sagar (6): spi: xilinx_spi: Add missing prototype for xilinx_qspi_mem_exec_op xilinx: zynq: Add missing prototype for zynqmp_mmio_write spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_op mtd: nand: zynq_nand: Change datatype of status and ecc_status to int arm: zynq: Pass the missing argument type in function definition xilinx: zynq: Add the missing function prototypes Ashok Reddy Soma (8): arm64: versal-net: spi: Update boot sequence dynamically cadence_qspi: Enable flash reset for Versal NET platform xilinx: versal-net: Add mini qspi configuration xilinx: versal-net: Add mini ospi configuration xilinx: versal-net: Add mini eMMC 5.1 configuration mmc: zynq_sdhci: Dll reset only for ZynqMP platform clk: zynqmp: Add set_rate support for gem rx and tsu clks clk: zynqmp: Add gem rx and tsu clocks to return register Christian Taedcke (1): event: Add fpga load event Harini Katakam (3): arm64: zynqmp: Assign TSU clock frequency for KR260 arm64: zynqmp: Increase reset assert time for TI SGMII PHY arm64: zynqmp: Assign TSU clock frequency for KV and KD boards Maksim Kiselev (1): net: axi_emac: Change return value to -EAGAIN if RX is not ready Manikanta Guntupalli (1): xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal Michal Simek (12): watchdog: versal: Use new compatible xlnx,versal-wwdt xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h arm64: zynqmp: Switch to amd.com emails mtd: Add missing MTD dependency for cfi_mtd arm64: zynqmp: Fix gpio comment about No of gpios arm64: zynqmp: Record compatible string for kv260 rev2 arm64: zynqmp: Cover K24 revB/1 SOM arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 arm64: zynqmp: Sync node name address with reg (mailbox) arm64: zynqmp: Remove interrupt/reg-names for AMS arm64: zynqmp: Rename ams_ps/pl node names arm64: zynqmp: Remove clock-names from pcap node Parth Gajjar (1): arm64: zynqmp: Update MALI 400 interrupt and clock names Piyush Mehta (1): arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usb Radhey Shyam Pandey (2): arm64: zynqmp: Add L2 cache nodes arm64: zynqmp: add pmu interrupt-affinity Raju Kumar Pothuraju (1): xilinx: zynq: Enable fdt apply utility for zynq Sharath Kumar Dasari (1): arm64: zynqmp: Fix the memory node for k26/k24 kria som boards Varalaxmi Bingi (1): arm: xilinx: Setting default i2c clock frequency to 400kHz Venkatesh Yadav Abbarapu (1): net: zynq_gem: Don't hardcode the MDC clock divisor arch/arm/dts/Makefile | 3 + arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/versal-mini-emmc0.dts| 4 +- arch/arm/dts/versal-mini-emmc1.dts| 4 +- arch/arm/dts/versal-mini-ospi.dtsi| 4 +- arch/arm/dts/versal-mini-qspi.dtsi| 4 +- arch/arm/dts/versal-mini.dts | 2 +- arch/arm/dts/versal-net-mini-emmc.dts | 64 arch/arm/dts/versal-net-mini-ospi-single.dts | 19 + arch/arm/dts/versal-net
Re: [PATCH v3 09/11] binman: btool: Add Xilinx Bootgen btool
On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote: From: Lukas Funke Add the Xilinx Bootgen as bintool. Xilinx Bootgen is used to create bootable SPL (FSBL in Xilinx terms) images for Zynq/ZynqMP devices. The btool creates a signed version of the SPL. Additionally to signing the key source for the decryption engine can be passend to the boot image. Signed-off-by: Lukas Funke --- Changes in v3: - Fixed an issue where the build result was not found - Fixed an issue where the version string was not reported correctly Changes in v2: - Pass additional 'keysrc_enc' parameter to Bootgen - Added more information and terms to documentation tools/binman/bintools.rst | 2 +- tools/binman/btool/bootgen.py | 136 ++ 2 files changed, 137 insertions(+), 1 deletion(-) create mode 100644 tools/binman/btool/bootgen.py diff --git a/tools/binman/bintools.rst b/tools/binman/bintools.rst index c6c9a88c21..8f58aaebf7 100644 --- a/tools/binman/bintools.rst +++ b/tools/binman/bintools.rst @@ -197,7 +197,7 @@ Using `fdt_add_pubkey` the key can be injected to the SPL independent of Bintool: bootgen: Sign ZynqMP FSBL image -- + This bintool supports running `bootgen` in order to sign a SPL for ZynqMP devices. diff --git a/tools/binman/btool/bootgen.py b/tools/binman/btool/bootgen.py new file mode 100644 index 00..83bbe124dc --- /dev/null +++ b/tools/binman/btool/bootgen.py @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2023 Weidmüller Interface GmbH & Co. KG +# Lukas Funke +# +"""Bintool implementation for bootgen + +bootgen allows creating bootable SPL for Zynq(MP) + +Documentation is available via:: +https://www.xilinx.com/support/documents/sw_manuals/xilinx2022_1/ug1283-bootgen-user-guide.pdf + +Source code is available at: + +https://github.com/Xilinx/bootgen + +""" +import tempfile + +from binman import bintool +from u_boot_pylib import tools + +# pylint: disable=C0103 +class Bintoolbootgen(bintool.Bintool): +"""Generate bootable fsbl image for zynq/zynqmp + +This bintools supports running Xilinx "bootgen" in order +to generate a bootable, authenticated image form an SPL. + +""" +def __init__(self, name): +super().__init__(name, 'Xilinx Bootgen', + version_regex=r'^\*\*\*\*\*\* *Xilinx Bootgen *(.*)', + version_args='-help') + +# pylint: disable=R0913 +def sign(self, arch, spl_elf_fname, pmufw_elf_fname, + psk_fname, ssk_fname, fsbl_config, auth_params, keysrc_enc, + output_fname): +""" Sign SPL elf file and bundle it PMU firmware into an image + +The method bundels the SPL together with a 'Platform Management Unit' +(PMU)[1] firmware into a single bootable image. The image in turn is +signed with the provided 'secondary secret key' (ssk), which in turn is +signed with the 'primary secret key' (ppk). In order to verify the +authenticity of the ppk, it's hash has to be fused into the device +itself. + +In Xilinx terms the SPL is usually called 'FSBL' +(First Stage Boot Loder). The jobs of the SPL and the FSBL are mostly +the same: load bitstream, bootstrap u-boot. + +Args: +arch (str): Xilinx SoC architecture. Currently only 'zynqmp' is +supported. +spl_elf_fname (str): Filename of SPL ELF file. The filename must end +with '.elf' in order for bootgen to recognized it as an ELF +file. Otherwise the start address field is missinterpreted. +pmufw_elf_fname (str): Filename PMU ELF firmware. +psk_fname (str): Filename of the primary secret key (psk). The psk +is a .pem file which holds the RSA private key used for signing +the secondardy secret key. typo +ssk_fname (str): Filename of the secondary secret key. The ssk +is a .pem file which holds the RSA private key used for signing +the aktual boot firmware. actual +fsbl_config (str): FSBL config options. A string list of fsbl config +options. Valid values according to [2] are: +"bh_auth_enable": Boot Header Authentication Enable: RSA +authentication of the bootimage is done +excluding the verification of PPK hash and SPK ID. This is +useful for debugging before bricking a device. +"auth_only": Boot image is only RSA signed. FSBL should not be +decrypted. See the +Zynq UltraScale+ Device Technical Reference Manual (UG1085) +for more information. +There are more options which relate to PUF (physical unclonable +
Re: [PATCH v3 00/11] Sign Xilinx ZynqMP SPL/FSBL boot images using binman
On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
This series adds two etypes to create a verified boot chain for
Xilinx ZynqMP devices. The first etype 'xilinx-fsbl-auth' is used to
create a bootable, signed image for ZynqMP boards using the Xilinx
Bootgen tool. The second etype 'u-boot-spl-pubkey-dtb' is used to add
a '/signature' node to the SPL. The public key in the signature is read
from a certificate file and added using the 'fdt_add_pubkey' tool. The
series also contains the corresponding btool for calling 'bootgen' and
'fdt_add_pubkey'.
The following block shows an example on how to use this functionality:
spl {
filename = "boot.signed.bin";
xilinx-fsbl-auth {
psk-key-name-hint = "psk0";
ssk-key-name-hint = "ssk0";
auth-params = "ppk_select=0", "spk_id=0x";
u-boot-spl-nodtb {
};
u-boot-spl-pubkey-dtb {
algo = "sha384,rsa4096";
required = "conf";
key-name-hint = "dev";
};
};
};
I was looking at binman couple of times in past but never had time to do any
development with it. Maybe it is good opportunity to look at it now with this
series.
Is there a way to see more verbose output?
I expect that keys should be generated as is described here.
https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/Key-Generation?tocId=yf_PWbWVciRyrDMi2g1H1w
Anyway I tried to use u-boot-spl-nodtb like this.
&binman {
spl {
filename = "boot.signed.bin";
xilinx-fsbl-auth {
psk-key-name-hint = "/tmp/ddd/psk0";
ssk-key-name-hint = "/tmp/ddd/ssk0";
auth-params = "ppk_select=0", "spk_id=0x";
pmufw-filename =
"/mnt/disk/u-boot-bins/zynqmp/zynqmp-zcu102-revA/pmufw.elf";
u-boot-spl-nodtb {
};
};
};
};
but getting error
BINMAN .binman_stamp
Using input directories ['.', '.', './board/xilinx/zynqmp', 'arch/arm/dts']
Using output directory '.'
Processing entry args:
of-list = avnet-ultra96-rev1 zynqmp-a2197-revA
zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA
zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA
zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1
zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4
zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1
zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA
zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA
zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA
zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA
zynqmp-smk-k26-revA zynqmp-dlc21-revA
atf-bl31-path = /tftpboot/bl31.bin
tee-os-path = /tftpboot/tee.bin
opensbi-path =
default-dt = zynqmp-zcu100-revC
scp-path =
rockchip-tpl-path =
spl-bss-pad =
tpl-bss-pad = 1
spl-dtb = y
tpl-dtb =
pre-load-key-path =
Processing entry args done
Node '/binman/spl/xilinx-fsbl-auth/u-boot-spl-nodtb': Packing: offset=None,
size=None, content_size=240d8
Node '/binman/spl/xilinx-fsbl-auth/u-boot-spl-nodtb':- packed: offset=0x0,
size=0x240d8, content_size=0x240d8, next_offset=240d8
Node '/binman/spl/xilinx-fsbl-auth/u-boot-spl-nodtb': GetData: size 0x240d8
Node '/binman/spl/xilinx-fsbl-auth': GetPaddedDataForEntry: size None
Node '/binman/spl/xilinx-fsbl-auth': GetData: 1 entries, total size 0x240d8
bintool: bootgen -arch zynqmp -image ./bootgen-in.sign.bif -w -o
./boot.spl.xilinx-fsbl-auth.bin
** Xilinx Bootgen v2022.2.0
Build date : Oct 13 2022-12:22:43
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
[WARNING]: Authentication padding scheme will be as per silicon 2.0(ES2) and
above. The image generated will NOT work for 1.0(ES1).
Use '-zynqmpes1' to generate image for 1.0(ES1)
[INFO] : Bootimage generated successfully
Node '/binman/spl': GetPaddedDataForEntry: size None
Node '/binman/spl/xilinx-fsbl-auth': Packing: offset=None, size=0x47280,
content_size=47280
Node '/binman/spl/xilinx-fsbl-auth':- packed: offset=0x0, size=0x47280,
content_size=0x47280, next_offset=47280
Node '/binman/spl/xilinx-fsbl-auth/u-boot-spl-nodtb': GetData: size 0x240d8
Node '/binman/spl/xilinx-fsbl-auth': GetPaddedDataForEntry: size 0x47280
Node '/binman/spl/xilinx-fsbl-auth': GetData: 1 entries, total size 0x240d8
bintool: bootgen -arch zynqmp -image ./bootgen-in.sign.bif -w -o
./boot.spl.xilinx-fsbl-auth.bin
** Xilinx Bootgen v2022.2.0
Build date : Oct 13 2022-12:22:43
** Copyrig
Re: [PATCH v5] event: Add fpga load event
On 7/20/23 09:27, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This enables implementing custom logic after a bitstream was loaded
into the fpga.
Signed-off-by: Christian Taedcke
Reviewed-by: Simon Glass
---
Changes in v5:
- remove changes from kmcent2 board file
- add missing include to event.h
Changes in v4:
- add include common.h to kmcent2 board file
Changes in v3:
- replace #if with if
- remove previously added printf
- return notification error from fpga_load()
- fix static_assert checking event name list
Changes in v2:
- replace __weak function with a new event
common/event.c | 3 +++
drivers/fpga/fpga.c | 20
include/event.h | 17 +
3 files changed, 40 insertions(+)
diff --git a/common/event.c b/common/event.c
index 164c95f8f5..20720c5283 100644
--- a/common/event.c
+++ b/common/event.c
@@ -36,6 +36,9 @@ const char *const type_name[] = {
/* init hooks */
"misc_init_f",
+ /* Fpga load hook */
+ "fpga_load",
+
/* fdt hooks */
"ft_fixup",
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 7f6b6bc73a..81e6d8ffc0 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size,
}
#endif
+static int fpga_load_event_notify(const void *buf, size_t bsize, int result)
+{
+ if (CONFIG_IS_ENABLED(EVENT)) {
+ struct event_fpga_load load = {
+ .buf = buf,
+ .bsize = bsize,
+ .result = result
+ };
+
+ return event_notify(EVT_FPGA_LOAD, &load, sizeof(load));
+ }
+
+ return 0;
+}
+
/*
* Generic multiplexing code
*/
@@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype,
int flags)
{
int ret_val = FPGA_FAIL; /* assume failure */
+ int ret_notify;
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
(char *)__func__);
@@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
}
}
+ ret_notify = fpga_load_event_notify(buf, bsize, ret_val);
+ if (ret_notify)
+ return ret_notify;
+
return ret_val;
}
diff --git a/include/event.h b/include/event.h
index fe41080fa6..daf44bf8a8 100644
--- a/include/event.h
+++ b/include/event.h
@@ -11,6 +11,7 @@
#define __event_h
#include
+#include
/**
* enum event_t - Types of events supported by U-Boot
@@ -31,6 +32,9 @@ enum event_t {
/* Init hooks */
EVT_MISC_INIT_F,
+ /* Fpga load hook */
+ EVT_FPGA_LOAD,
+
/* Device tree fixups before booting */
EVT_FT_FIXUP,
@@ -59,6 +63,19 @@ union event_data {
struct udevice *dev;
} dm;
+ /**
+* struct event_fpga_load - fpga load event
+*
+* @buf: The buffer that was loaded into the fpga
+* @bsize: The size of the buffer that was loaded into the fpga
+* @result: Result of the load operation
+*/
+ struct event_fpga_load {
+ const void *buf;
+ size_t bsize;
+ int result;
+ } fpga_load;
+
/**
* struct event_ft_fixup - FDT fixup before booting
*
I forget to reply that I applied this patch.
Already merged to main repo as a1190b4d6a9bf3a45038e3eba4a11de4be2b1cca.
Thanks,
Michal
Re: [PATCH v3] xilinx: zynqmp: Extract aes operation into new file
On 7/18/23 12:30, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This moves the aes operation that is performed by the pmu into a
separate file. This way it can be called not just from the shell
command, but also e.g. from board initialization code.
Signed-off-by: Christian Taedcke
---
Changes in v3:
- fix function doc format
Changes in v2:
- convert doxygen comments to kernel-doc
- fix typos
- fix header license
- fix do_zynqmp_aes() return value
arch/arm/mach-zynqmp/Makefile | 3 +-
arch/arm/mach-zynqmp/aes.c| 58 +++
.../arm/mach-zynqmp/include/mach/zynqmp_aes.h | 32 ++
board/xilinx/zynqmp/cmds.c| 43 +-
4 files changed, 94 insertions(+), 42 deletions(-)
create mode 100644 arch/arm/mach-zynqmp/aes.c
create mode 100644 arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index bb1830c846..1a76493bef 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek
-obj-y += clk.o
-obj-y += cpu.o
+obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c
new file mode 100644
index 00..115bca8338
--- /dev/null
+++ b/arch/arm/mach-zynqmp/aes.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu
+ *
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG
+ * Christian Taedcke
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+int zynqmp_aes_operation(struct zynqmp_aes *aes)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (zynqmp_firmware_version() <= PMUFW_V1_0)
+ return -ENOENT;
+
+ if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
+ flush_dcache_range(aes->srcaddr,
+ (aes->srcaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN)));
Can you please get rid of () around the second parameter?
+ flush_dcache_range(aes->ivaddr,
+ (aes->ivaddr +
+ roundup(IV_SIZE, ARCH_DMA_MINALIGN)));
same here
+ flush_dcache_range(aes->dstaddr,
+ (aes->dstaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN)));
same here.
+ }
+
+ if (aes->keysrc == 0) {
+ if (aes->keyaddr == 0)
+ return -EINVAL;
+
+ flush_dcache_range(aes->keyaddr, (aes->keyaddr +
+ roundup(KEY_PTR_LEN,
ARCH_DMA_MINALIGN)));
And here. And here you also have incorrect indentation on second line.
+ }
+
+ flush_dcache_range((ulong)aes, (ulong)(aes) +
+ roundup(sizeof(struct zynqmp_aes),
ARCH_DMA_MINALIGN));
+
+ ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
+ lower_32_bits((ulong)aes), 0, 0, ret_payload);
+ if (ret || ret_payload[1]) {
+ printf("Failed: AES op status:0x%x, errcode:0x%x\n",
+ ret, ret_payload[1]);
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
new file mode 100644
index 00..2a9cffbd0f
--- /dev/null
+++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG
+ * Christian Taedcke
+ *
+ * Declaration of AES operation functionality for ZynqMP.
+ */
+
+#ifndef ZYNQMP_AES_H
+#define ZYNQMP_AES_H
+
+struct zynqmp_aes {
+ u64 srcaddr;
+ u64 ivaddr;
+ u64 keyaddr;
+ u64 dstaddr;
+ u64 len;
+ u64 op;
+ u64 keysrc;
+};
+
+/**
+ * zynqmp_aes_operation() - Performs an aes operation using the pmu firmware
+ *
+ * @aes: The aes operation buffer that must have been allocated using
+ * ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1)
+ *
+ * Return: 0 in case of success, in case of an error any other value
+ */
+int zynqmp_aes_operation(struct zynqmp_aes *aes);
+
+#endif /* ZYNQMP_AES_H */
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index dd1ad66f90..60c7bfca02 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -14,16 +14,7 @@
#include
#include
#include
-
-struct aes {
- u64 srcaddr;
- u64
[PATCH] arm64: zynqmp: Remove fclk driver
fclk will never go upstream that's why removing this node from DT.
All PL (programmable logic) based IPs should handle clocks self without
using this workaround.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 5f1b0b23c124..dd4569e7bd95 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -10,12 +10,6 @@
#include
/ {
- fclk0: fclk0 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL0_REF>;
- };
-
pss_ref_clk: pss_ref_clk {
bootph-all;
compatible = "fixed-clock";
--
2.36.1
[PATCH 0/5] arm64: xilinx: DT sync
Hi, I have found 5 more patches internally which should be also upstreamed to get DT in sync and descrease amount of differences. Thanks, Michal Michal Simek (4): arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revA arm64: zynqmp: Remove xlnx,zynqmp-aes node Revert "arm64: zynqmp: Add power domain description for PL" arm64: zynqmp: Remove address/size-cells from ams node Piyush Mehta (1): arm64: zynqmp: remove snps,xhci-stream-quirk property for usb arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 10 +++--- arch/arm/dts/zynqmp-vpk120-revA.dts| 10 +++--- arch/arm/dts/zynqmp.dtsi | 9 - 3 files changed, 14 insertions(+), 15 deletions(-) -- 2.36.1
[PATCH 3/5] Revert "arm64: zynqmp: Add power domain description for PL"
This reverts commit d59fac2f3f247470708a1aed1af96802a05e0e61.
This power domain shouldn't be enabled by default. Power domain behavior
should be handled on case by case basis. Adding this property to
zynqmp.dtsi is breaking some suspend/resume cases that's why remove it
from this file.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 463ac14f4b59..366b50a104be 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -257,7 +257,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- power-domains = <&zynqmp_firmware PD_PL>;
};
remoteproc {
--
2.36.1
[PATCH 2/5] arm64: zynqmp: Remove xlnx,zynqmp-aes node
AES can be discovered via firmware interface that's why remove node for it.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index f03c201caee9..463ac14f4b59 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -220,10 +220,6 @@
compatible = "xlnx,zynqmp-pcap-fpga";
};
- xlnx_aes: zynqmp-aes {
- compatible = "xlnx,zynqmp-aes";
- };
-
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
--
2.36.1
[PATCH 1/5] arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revA
All boards have been converted to use mdio node that's why move ethernet
phys under mdio node too.
Signed-off-by: Michal Simek
---
Same change was done by:
https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.si...@amd.com
---
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 10 +++---
arch/arm/dts/zynqmp-vpk120-revA.dts| 10 +++---
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
index 2f88aa4a0d28..9ab8f5bfffe4 100644
--- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -119,9 +119,13 @@
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
- /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
- phy0: ethernet-phy@0 { /* u131 - M88e1512 */
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 { /* u131 - M88e1512 */
+ reg = <0>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts
b/arch/arm/dts/zynqmp-vpk120-revA.dts
index 66919f578e02..ce76e0b3db36 100644
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -120,9 +120,13 @@
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
- /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
--
2.36.1
[PATCH 5/5] arm64: zynqmp: remove snps, xhci-stream-quirk property for usb
From: Piyush Mehta To sync up with the upstream bulk-stream feature, removed 'snps,xhci-stream-quirk' DT property for usb. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index de60233fd061..2253e773d386 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -955,7 +955,6 @@ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; - snps,xhci-stream-quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -988,7 +987,6 @@ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; - snps,xhci-stream-quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; -- 2.36.1
[PATCH 4/5] arm64: zynqmp: Remove address/size-cells from ams node
Remove unused address/size-cells which is also done upstream that's why this is pretty much sync patch with upstream. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 366b50a104be..de60233fd061 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1034,8 +1034,6 @@ compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; - #address-cells = <1>; - #size-cells = <0>; }; }; -- 2.36.1
[PATCH] arm64: zynqmp: Disable the lock option for mini qspi
From: Venkatesh Yadav Abbarapu As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek --- Depends on https://lore.kernel.org/all/20230928034940.2220-2-venkatesh.abbar...@amd.com/ --- configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index a1adfb9e5d14..4a74ca76a281 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -77,6 +77,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y -- 2.36.1
[PATCH] ARM: zynq: Disable the config CONFIG_SPI_FLASH_USE_4K_SECTORS
From: Venkatesh Yadav Abbarapu Lock size for the flashes will be in terms of sector size, so disable the CONFIG_SPI_FLASH_USE_4K_SECTORS and read it from the flash itself. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 817fb4142d18..6145af62b511 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -126,6 +126,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -- 2.36.1
[PATCH] arm64: dts: zynqmp: make hw-ecc as the default ecc mode
From: Amit Kumar Mahapatra Except for Linux no other component (i.e., u-boot, fsbl or BootRom) of the software stack supports software ecc engine. So, make hw-ecc as the default ecc mode. Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 23a3ff2fed98..160c6c58b36d 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -141,8 +141,7 @@ reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; @@ -178,8 +177,7 @@ reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; -- 2.36.1
Re: [PATCH] usb: xhci: Workaround to fix the USB halted endpoint issues
On 9/12/23 05:59, Venkatesh Yadav Abbarapu wrote:
The xhci host controller driver trying to queue the URB's and it is
getting halted at the endpoint, thereby hitting the BUG_ON's.
Mostly these kind of random issues are seen on faulty boards.
Removing these BUG_ON's from the U-Boot xhci code, as in Linux kernel
xhci code BUG_ON/BUG's are removed entirely.
Please also note, that BUG_ON() is not recommended any more in the Linux
kernel.
Similar issue has been observed on TI AM437x board and they created a patch
in Linux kernel as below
https://patches.linaro.org/project/linux-usb/patch/1390250711-25840-1-git-send-email-ba...@ti.com/
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/usb/host/xhci-mem.c | 17 -
drivers/usb/host/xhci-ring.c | 31 +++
drivers/usb/host/xhci.c | 6 --
include/usb/xhci.h | 2 +-
4 files changed, 8 insertions(+), 48 deletions(-)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 72b7530626..0efb4bd7ba 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -36,8 +36,6 @@
*/
void xhci_flush_cache(uintptr_t addr, u32 len)
{
- BUG_ON((void *)addr == NULL || len == 0);
-
flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
ALIGN(addr + len, CACHELINE_SIZE));
}
@@ -51,8 +49,6 @@ void xhci_flush_cache(uintptr_t addr, u32 len)
*/
void xhci_inval_cache(uintptr_t addr, u32 len)
{
- BUG_ON((void *)addr == NULL || len == 0);
-
invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
ALIGN(addr + len, CACHELINE_SIZE));
}
@@ -84,8 +80,6 @@ static void xhci_ring_free(struct xhci_ctrl *ctrl, struct
xhci_ring *ring)
struct xhci_segment *seg;
struct xhci_segment *first_seg;
- BUG_ON(!ring);
-
first_seg = ring->first_seg;
seg = first_seg->next;
while (seg != first_seg) {
@@ -210,7 +204,6 @@ static void *xhci_malloc(unsigned int size)
size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
- BUG_ON(!ptr);
memset(ptr, '\0', size);
xhci_flush_cache((uintptr_t)ptr, size);
@@ -291,7 +284,6 @@ static struct xhci_segment *xhci_segment_alloc(struct
xhci_ctrl *ctrl)
struct xhci_segment *seg;
seg = malloc(sizeof(struct xhci_segment));
- BUG_ON(!seg);
seg->trbs = xhci_malloc(SEGMENT_SIZE);
seg->dma = xhci_dma_map(ctrl, seg->trbs, SEGMENT_SIZE);
@@ -323,13 +315,11 @@ struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl,
unsigned int num_segs,
struct xhci_segment *prev;
ring = malloc(sizeof(struct xhci_ring));
- BUG_ON(!ring);
if (num_segs == 0)
return ring;
ring->first_seg = xhci_segment_alloc(ctrl);
- BUG_ON(!ring->first_seg);
num_segs--;
@@ -338,7 +328,6 @@ struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs,
struct xhci_segment *next;
next = xhci_segment_alloc(ctrl);
- BUG_ON(!next);
xhci_link_segments(ctrl, prev, next, link_trbs);
@@ -399,7 +388,6 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
break;
page_size = page_size >> 1;
}
- BUG_ON(i == 16);
ctrl->page_size = 1 << (i + 12);
buf = memalign(ctrl->page_size, num_sp * ctrl->page_size);
@@ -444,9 +432,7 @@ static struct xhci_container_ctx
struct xhci_container_ctx *ctx;
ctx = malloc(sizeof(struct xhci_container_ctx));
- BUG_ON(!ctx);
- BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
ctx->type = type;
ctx->size = (MAX_EP_CTX_NUM + 1) *
CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams));
@@ -638,7 +624,6 @@ int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr
*hccr,
struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
{
- BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
return (struct xhci_input_control_ctx *)ctx->bytes;
}
@@ -760,8 +745,6 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
virt_dev = ctrl->devs[slot_id];
- BUG_ON(!virt_dev);
-
/* Extract the EP0 and Slot Ctrl */
ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index c8260cbdf9..1bde0b9793 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -244,6 +244,7 @@ static int prepare_ring(struct xhci_ctrl *ctrl, struct
xhci_ring *ep_ring,
return -EINVAL;
case EP_STATE_HALTED:
puts("WARN halted endpoint, queueing URB anyway.\n");
+ return -EPIPE;
