Re: [PATCH v2 RESEND 2/2] nvme: Update nvme_scan_namespace to keep trying on busy

[Moritz Fischer]

On Tue, Jan 9, 2024 at 9:05 PM Moritz Fischer  wrote:
>
> A busy controller shouldn't be game-over for all controllers,
> so keep trying on hitting -EBUSY.
>
> This change brings the actual behavior of the routine in line
> with what the descriptions says.
>
> Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
> Reviewed-by: Simon Glass 
> Signed-off-by: Moritz Fischer 
> ---
>  drivers/nvme/nvme.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
> index ec45f831a3..59a139baa0 100644
> --- a/drivers/nvme/nvme.c
> +++ b/drivers/nvme/nvme.c
> @@ -695,7 +695,9 @@ int nvme_scan_namespace(void)
> if (ret) {
> log_err("Failed to probe '%s': err=%dE\n", dev->name,
> ret);
> -   return ret;
> +   /* Bail if we ran out of memory, else keep trying */
> +   if (ret != -EBUSY)
> +   return ret;
> }
> }
>
> --
> 2.43.0.472.g3155946c3a-goog
>

Gently ping on this. Is anything wrong with this series or why does it
keep falling through the cracks?

- Moritz

[PATCH v2 RESEND 2/2] nvme: Update nvme_scan_namespace to keep trying on busy

[Moritz Fischer]

A busy controller shouldn't be game-over for all controllers,
so keep trying on hitting -EBUSY.

This change brings the actual behavior of the routine in line
with what the descriptions says.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass 
Signed-off-by: Moritz Fischer 
---
 drivers/nvme/nvme.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index ec45f831a3..59a139baa0 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -695,7 +695,9 @@ int nvme_scan_namespace(void)
if (ret) {
log_err("Failed to probe '%s': err=%dE\n", dev->name,
ret);
-   return ret;
+   /* Bail if we ran out of memory, else keep trying */
+   if (ret != -EBUSY)
+   return ret;
}
}
 
-- 
2.43.0.472.g3155946c3a-goog

[PATCH v2 RESEND 1/2] nvme: Fix error code and log to indicate busy

[Moritz Fischer]

Return -EBUSY if controller is found busy rather than -ENOMEM
and update the error message accordingly.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass 
Signed-off-by: Moritz Fischer 
---
 drivers/nvme/nvme.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index c39cd41aa3..ec45f831a3 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -835,8 +835,8 @@ int nvme_init(struct udevice *udev)
ndev->udev = udev;
INIT_LIST_HEAD(>namespaces);
if (readl(>bar->csts) == -1) {
-   ret = -ENODEV;
-   printf("Error: %s: Out of memory!\n", udev->name);
+   ret = -EBUSY;
+   printf("Error: %s: Controller not ready!\n", udev->name);
goto free_nvme;
}
 
-- 
2.43.0.472.g3155946c3a-goog

[PATCH v4] drivers: pci: Fix dm_pci_map_bar() to support 64b BARs

[Moritz Fischer]

This enables 64b BARs if CONFIG_SYS_PCI_64BIT is enabled.

Reviewed-by: Philip Oberfichtner 
Reviewed-by: Simon Glass 
Signed-off-by: Moritz Fischer 
---

Changes from V3:
- Rebased onto v2024.01

Changes from V2:

- Turned IS_ENABLED() into #if defined to allow
  building on platforms that don't define
  CONFIG_SYS_PCI_64BIT

Changes from V1:

- Reworded commit message / typo

---
 drivers/pci/pci-uclass.c | 11 +++
 include/pci.h|  1 +
 2 files changed, 12 insertions(+)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index e0d01f6a85..1a48256de0 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1611,6 +1611,17 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, 
size_t offset, size_t len,
dm_pci_read_config32(udev, bar, _response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 
+   /* This has a lot of baked in assumptions, but essentially tries
+* to mirror the behavior of BAR assignment for 64 Bit enabled
+* hosts and 64 bit placeable BARs in the auto assign code.
+*/
+#if defined(CONFIG_SYS_PCI_64BIT)
+   if (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+   dm_pci_read_config32(udev, bar + 4, _response);
+   pci_bus_addr |= (pci_addr_t)bar_response << 32;
+   }
+#endif /* CONFIG_SYS_PCI_64BIT */
+
if (~((pci_addr_t)0) - pci_bus_addr < offset)
return NULL;
 
diff --git a/include/pci.h b/include/pci.h
index 2f5eb30b83..aad233769a 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1354,6 +1354,7 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, 
phys_addr_t addr, size_t len,
  * type 1 functions.
  * Can also be used on type 0 functions that support Enhanced Allocation for
  * 32b/64b BARs.  Note that duplicate BEI entries are not supported.
+ * Can also be used on 64b bars on type 0 functions.
  *
  * @dev:   Device to check
  * @bar:   Bar register offset (PCI_BASE_ADDRESS_...)
-- 
2.43.0.472.g3155946c3a-goog

[PATCH v3] pci: Enable dm_pci_map_bar() for 64-bit BARs

[Moritz Fischer]

Allow dm_pci_map_bar() usage on systems with CONFIG_SYS_PCI_64BIT.

Reviewed-by: Philip Oberfichtner 
Reviewed-by: Simon Glass 
Signed-off-by: Moritz Fischer 
---

Changes from V2:

- Turned IS_ENABLED() into #if defined to allow
  building on platforms that don't define 
  CONFIG_SYS_PCI_64BIT

Changes from V1:

- Reworded commit message / typo

---
 drivers/pci/pci-uclass.c | 12 
 include/pci.h|  4 ++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index e0d01f6a85..04c82d3884 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1611,6 +1611,18 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, 
size_t offset, size_t len,
dm_pci_read_config32(udev, bar, _response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 
+#if defined(CONFIG_SYS_PCI_64BIT)
+   /*
+* This assumes that dm_pciauto_setup_device() will allocate
+* a 64-bit address if CONFIG_SYS_PCI_64BIT is enabled and
+* the device advertises that it supports it.
+*/
+   if (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+   dm_pci_read_config32(udev, bar + 4, _response);
+   pci_bus_addr |= (pci_addr_t)bar_response << 32;
+   }
+#endif /* CONFIG_SYS_PCI_64BIT */
+
if (~((pci_addr_t)0) - pci_bus_addr < offset)
return NULL;
 
diff --git a/include/pci.h b/include/pci.h
index 2f5eb30b83..0d1ac7b015 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1350,8 +1350,8 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, 
phys_addr_t addr, size_t len,
  *
  * Looks up a base address register and finds the physical memory address
  * that corresponds to it.
- * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
- * type 1 functions.
+ * Can be used for 32b/64b BARs 0-5 on type 0 functions and for 32b BARs 0-1
+ * on type 1 functions.
  * Can also be used on type 0 functions that support Enhanced Allocation for
  * 32b/64b BARs.  Note that duplicate BEI entries are not supported.
  *
-- 
2.43.0.472.g3155946c3a-goog

Re: [PATCH v2 RESEND] pci: Enable dm_pci_map_bar() for 64-bit BARs

[Moritz Fischer]

Tom,

On Thu, Dec 21, 2023 at 9:53 AM Tom Rini  wrote:
>
> On Sun, Dec 17, 2023 at 12:52:09AM +, Moritz Fischer wrote:
>
> > Allow dm_pci_map_bar() usage on systems with CONFIG_SYS_PCI_64BIT.
> >
> > Reviewed-by: Philip Oberfichtner 
> > Reviewed-by: Simon Glass 
> > Signed-off-by: Moritz Fischer 
>
> This causes a failure to build on qemu_arm and a number of other
> platforms, thanks.

Argh, yes, I got got by the IS_ENABLED(). Switching it to #if
defined(CONFIG_SYS_PCI_64BIT) makes it work.

Sorry, let me resend this.

- Moritz

[PATCH v2 RESEND] pci: Enable dm_pci_map_bar() for 64-bit BARs

[Moritz Fischer]

Allow dm_pci_map_bar() usage on systems with CONFIG_SYS_PCI_64BIT.

Reviewed-by: Philip Oberfichtner 
Reviewed-by: Simon Glass 
Signed-off-by: Moritz Fischer 
---
 drivers/pci/pci-uclass.c | 11 +++
 include/pci.h|  4 ++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index e0d01f6a85..82308c7477 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1611,6 +1611,17 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, 
size_t offset, size_t len,
dm_pci_read_config32(udev, bar, _response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 
+   /*
+* This assumes that dm_pciauto_setup_device() will allocate
+* a 64-bit address if CONFIG_SYS_PCI_64BIT is enabled and
+* the device advertises that it supports it.
+*/
+   if (IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+   (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+   dm_pci_read_config32(udev, bar + 4, _response);
+   pci_bus_addr |= (pci_addr_t)bar_response << 32;
+   }
+
if (~((pci_addr_t)0) - pci_bus_addr < offset)
return NULL;
 
diff --git a/include/pci.h b/include/pci.h
index 2f5eb30b83..0d1ac7b015 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1350,8 +1350,8 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, 
phys_addr_t addr, size_t len,
  *
  * Looks up a base address register and finds the physical memory address
  * that corresponds to it.
- * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
- * type 1 functions.
+ * Can be used for 32b/64b BARs 0-5 on type 0 functions and for 32b BARs 0-1
+ * on type 1 functions.
  * Can also be used on type 0 functions that support Enhanced Allocation for
  * 32b/64b BARs.  Note that duplicate BEI entries are not supported.
  *
-- 
2.43.0.472.g3155946c3a-goog

[PATCH v2 2/2] nvme: Update scan namespace to keep trying on busy

[Moritz Fischer]

A busy controller shouldn't be game-over for all controllers,
so keep trying on hitting -EBUSY.

This change brings the actual behavior of the routine in line
with what the descriptions says.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass 
Signed-off-by: Moritz Fischer 
---
Changes from V1:
- Added Simon's Reviewed-by
---

 drivers/nvme/nvme.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index ec45f831a3..59a139baa0 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -695,7 +695,9 @@ int nvme_scan_namespace(void)
if (ret) {
log_err("Failed to probe '%s': err=%dE\n", dev->name,
ret);
-   return ret;
+   /* Bail if we ran out of memory, else keep trying */
+   if (ret != -EBUSY)
+   return ret;
}
}
 
-- 
2.43.0.472.g3155946c3a-goog

[PATCH v2 1/2] nvme: Fix error code and log to indicate busy

[Moritz Fischer]

Return -EBUSY if controller is found busy rather than -ENOMEM
and update the error message accordingly.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass 
Signed-off-by: Moritz Fischer 
---
Changes from V1:
- Added Simon's Reviewed-by
---
 drivers/nvme/nvme.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index c39cd41aa3..ec45f831a3 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -835,8 +835,8 @@ int nvme_init(struct udevice *udev)
ndev->udev = udev;
INIT_LIST_HEAD(>namespaces);
if (readl(>bar->csts) == -1) {
-   ret = -ENODEV;
-   printf("Error: %s: Out of memory!\n", udev->name);
+   ret = -EBUSY;
+   printf("Error: %s: Controller not ready!\n", udev->name);
goto free_nvme;
}
 
-- 
2.43.0.472.g3155946c3a-goog

[PATCH RESEND 2/2] nvme: Update nvme_scan_namespace to keep trying on busy

[Moritz Fischer]

A busy controller shouldn't be game-over for all controllers,
so keep trying on hitting -EBUSY.

This change brings the actual behavior of the routine in line
with what the descriptions says.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Signed-off-by: Moritz Fischer 
---
 drivers/nvme/nvme.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index ec45f831a3..59a139baa0 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -695,7 +695,9 @@ int nvme_scan_namespace(void)
if (ret) {
log_err("Failed to probe '%s': err=%dE\n", dev->name,
ret);
-   return ret;
+   /* Bail if we ran out of memory, else keep trying */
+   if (ret != -EBUSY)
+   return ret;
}
}
 
-- 
2.43.0.rc2.451.g8631bc7472-goog

[PATCH RESEND 1/2] nvme: Fix error code and log to indicate busy

[Moritz Fischer]

Return -EBUSY if controller is found busy rather than -ENOMEM
and update the error message accordingly.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Signed-off-by: Moritz Fischer 
---
 drivers/nvme/nvme.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index c39cd41aa3..ec45f831a3 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -835,8 +835,8 @@ int nvme_init(struct udevice *udev)
ndev->udev = udev;
INIT_LIST_HEAD(>namespaces);
if (readl(>bar->csts) == -1) {
-   ret = -ENODEV;
-   printf("Error: %s: Out of memory!\n", udev->name);
+   ret = -EBUSY;
+   printf("Error: %s: Controller not ready!\n", udev->name);
goto free_nvme;
}
 
-- 
2.43.0.rc2.451.g8631bc7472-goog

Re: Setting up boot chain ACPI on ARM with STM32MPU

[Moritz Fischer]

Hi,

On Wed, Nov 29, 2023 at 11:28 AM Simon Glass  wrote:
>
> +Heinrich Schuchardt
>
> Hi,
>
> On Wed, 29 Nov 2023 at 08:29, Ba Gia Bao Phan
>  wrote:
> >
> > Hello everyone,
> >
> > I am a trainee at STMicroelectronics France. I am working on a project 
> > "Setting up a boot chain ACPI" for STM32MPU, which is based on ARM Cortex-A 
> > . The objective of my project is to add a way of booting (with ACPI) 
> > besides Device Tree available on STM32MPU.
> >
> > I found that ACPI was enabled on some x86 platforms but I don't know 
> > whether it was set up on ARM or not. I found a PATCH that discussed 
> > Enabling ACPI booting on ARM with Raspberry Pi 4 but I don't know if it 
> > functioned or not. Did anyone here succeed in setting up ACPI on ARM by 
> > U-boot?
>
> Sort-of...the refactoring to allow ACPI tables on ARM is completed,
> but I don't think any U-Boot board uses this.
>
> >
> > What are the differences between x86 and ARM platforms when enabling ACPI? 
> > The architecture of my board STM32PMU is ARM so can I apply the technique 
> > used on platform x86 for my board?
>
> Firstly I wonder why you want ACPI?

I think STM32MPU is as good as any platform to get the pipe flushed
with enabling ACPI on ARM platforms.

Overall I think it's a worthwhile endeavour to get this sorted for at
least one ARM platform as a starting point.

> Secondly, if you have the tables somewhere it should be easy enough to
> build them, building on the series you pointed to. Heinrich is
> interested in this, I think. I can help with advice. I have been
> toying with going back to that rpi series but have not done so yet.

I've started to mess around with this over the holidays. Feel free to
CC me on future work in that direction.

- Moritz

[PATCH v2] pci: Enable dm_pci_map_bar() for 64-bit BARs

[Moritz Fischer]

Allow dm_pci_map_bar() usage on systems with CONFIG_SYS_PCI_64BIT.

Reviewed-by: Philip Oberfichtner 
Signed-off-by: Moritz Fischer 
---
Changes from v1:
- Fixed commit message
---
 drivers/pci/pci-uclass.c | 11 +++
 include/pci.h|  4 ++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index e0d01f6a85..82308c7477 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1611,6 +1611,17 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, 
size_t offset, size_t len,
dm_pci_read_config32(udev, bar, _response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 
+   /*
+* This assumes that dm_pciauto_setup_device() will allocate
+* a 64-bit address if CONFIG_SYS_PCI_64BIT is enabled and
+* the device advertises that it supports it.
+*/
+   if (IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+   (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+   dm_pci_read_config32(udev, bar + 4, _response);
+   pci_bus_addr |= (pci_addr_t)bar_response << 32;
+   }
+
if (~((pci_addr_t)0) - pci_bus_addr < offset)
return NULL;
 
diff --git a/include/pci.h b/include/pci.h
index 2f5eb30b83..0d1ac7b015 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1350,8 +1350,8 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, 
phys_addr_t addr, size_t len,
  *
  * Looks up a base address register and finds the physical memory address
  * that corresponds to it.
- * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
- * type 1 functions.
+ * Can be used for 32b/64b BARs 0-5 on type 0 functions and for 32b BARs 0-1
+ * on type 1 functions.
  * Can also be used on type 0 functions that support Enhanced Allocation for
  * 32b/64b BARs.  Note that duplicate BEI entries are not supported.
  *
-- 
2.43.0.rc1.413.gea7ed67945-goog

[PATCH] pci: Enable dm_pci_map_bar() for 64-bit BARs

[Moritz Fischer]

Allow dm_pci_map_bar() usage on systems with CONFIG_PCI_SYS_64BIT.

Signed-off-by: Moritz Fischer 
---
 drivers/pci/pci-uclass.c | 11 +++
 include/pci.h|  4 ++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index e0d01f6a85..82308c7477 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1611,6 +1611,17 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, 
size_t offset, size_t len,
dm_pci_read_config32(udev, bar, _response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 
+   /*
+* This assumes that dm_pciauto_setup_device() will allocate
+* a 64-bit address if CONFIG_SYS_PCI_64BIT is enabled and
+* the device advertises that it supports it.
+*/
+   if (IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+   (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+   dm_pci_read_config32(udev, bar + 4, _response);
+   pci_bus_addr |= (pci_addr_t)bar_response << 32;
+   }
+
if (~((pci_addr_t)0) - pci_bus_addr < offset)
return NULL;
 
diff --git a/include/pci.h b/include/pci.h
index 2f5eb30b83..0d1ac7b015 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1350,8 +1350,8 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, 
phys_addr_t addr, size_t len,
  *
  * Looks up a base address register and finds the physical memory address
  * that corresponds to it.
- * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
- * type 1 functions.
+ * Can be used for 32b/64b BARs 0-5 on type 0 functions and for 32b BARs 0-1
+ * on type 1 functions.
  * Can also be used on type 0 functions that support Enhanced Allocation for
  * 32b/64b BARs.  Note that duplicate BEI entries are not supported.
  *
-- 
2.43.0.rc1.413.gea7ed67945-goog

[PATCH 2/2] nvme: Update scan namespace to keep trying on busy

[Moritz Fischer]

A busy controller shouldn't be game-over for all controllers,
so keep trying on hitting -EBUSY.

This change brings the actual behavior of the routine in line
with what the descriptions says.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Signed-off-by: Moritz Fischer 
---
 drivers/nvme/nvme.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index ec45f831a3..59a139baa0 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -695,7 +695,9 @@ int nvme_scan_namespace(void)
if (ret) {
log_err("Failed to probe '%s': err=%dE\n", dev->name,
ret);
-   return ret;
+   /* Bail if we ran out of memory, else keep trying */
+   if (ret != -EBUSY)
+   return ret;
}
}
 
-- 
2.43.0.rc1.413.gea7ed67945-goog

[PATCH 1/2] nvme: Fix error code and log to indicate busy

[Moritz Fischer]

Return -EBUSY if controller is found busy rather than -ENOMEM
and update the error message accordingly.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Signed-off-by: Moritz Fischer 
---
 drivers/nvme/nvme.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index c39cd41aa3..ec45f831a3 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -835,8 +835,8 @@ int nvme_init(struct udevice *udev)
ndev->udev = udev;
INIT_LIST_HEAD(>namespaces);
if (readl(>bar->csts) == -1) {
-   ret = -ENODEV;
-   printf("Error: %s: Out of memory!\n", udev->name);
+   ret = -EBUSY;
+   printf("Error: %s: Controller not ready!\n", udev->name);
goto free_nvme;
}
 
-- 
2.43.0.rc1.413.gea7ed67945-goog

[PATCH] MAINTAINERS: Fix ARCH_APPLE file paths

[Moritz Fischer]

Fixes a filepath in MAINTAINERS file that wasn't updated when
renaming the files to match the new SoC name.

Fixes: a4bd5e4120d6 ('arm: apple: Change SoC name from "m1" into "apple"')
Signed-off-by: Moritz Fischer 
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7c1cb2dc4d..833f7beb9a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -117,7 +117,7 @@ F:  drivers/mmc/snps_dw_mmc.c
 APPLE M1 SOC SUPPORT
 M: Mark Kettenis 
 S: Maintained
-F: arch/arm/include/asm/arch-m1/
+F: arch/arm/include/asm/arch-apple/
 F: arch/arm/mach-apple/
 F: configs/apple_m1_defconfig
 F: drivers/iommu/apple_dart.c
-- 
2.43.0.rc1.413.gea7ed67945-goog

Re: [PATCH 2/2] acpi: Move MCFG implementation to common lib

[Moritz Fischer]

Hi Simon,

On Mon, Feb 7, 2022 at 12:22 PM Simon Glass  wrote:
>
> Hi Moritz,
>
> On Sat, 5 Feb 2022 at 13:17, Moritz Fischer  wrote:
> >
> > MCFG tables are used on multiple arches. Move to common ACPI lib.
> >
> > Cc: Simon Glass 
> > Signed-off-by: Moritz Fischer 
> > ---
> >
> >  arch/x86/cpu/intel_common/acpi.c  | 15 +---
> >  arch/x86/cpu/tangier/acpi.c   | 11 --
> >  arch/x86/include/asm/acpi_table.h |  1 -
> >  arch/x86/lib/acpi_table.c | 54 --
> >  lib/acpi/Makefile |  1 +
> >  lib/acpi/mcfg.c   | 64 +++
> >  6 files changed, 81 insertions(+), 65 deletions(-)
> >  create mode 100644 lib/acpi/mcfg.c
> >
> > diff --git a/arch/x86/cpu/intel_common/acpi.c 
> > b/arch/x86/cpu/intel_common/acpi.c
> > index 15f19da206..d94ec208f6 100644
> > --- a/arch/x86/cpu/intel_common/acpi.c
> > +++ b/arch/x86/cpu/intel_common/acpi.c
> > @@ -31,14 +31,17 @@
> >  #include 
> >  #include 
> >
> > -u32 acpi_fill_mcfg(u32 current)
> > +int acpi_fill_mcfg(struct acpi_ctx *ctx)
> >  {
> > +   size_t size;
> > +
> > /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
> > -   current += acpi_create_mcfg_mmconfig((void *)current,
> > -CONFIG_MMCONF_BASE_ADDRESS, 0, 
> > 0,
> > -(CONFIG_SA_PCIEX_LENGTH >> 20)
> > -- 1);
> > -   return current;
> > +   size = acpi_create_mcfg_mmconfig((void *)ctx->current,
> > +CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
> > +(CONFIG_SA_PCIEX_LENGTH >> 20) - 
> > 1);
> > +   acpi_inc(ctx, size);
> > +
> > +   return 0;
> >  }
> >
> >  static int acpi_sci_irq(void)
> > diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
> > index 12f9289612..e3a2fcea76 100644
> > --- a/arch/x86/cpu/tangier/acpi.c
> > +++ b/arch/x86/cpu/tangier/acpi.c
> > @@ -68,14 +68,17 @@ u32 acpi_fill_madt(u32 current)
> > return current;
> >  }
> >
> > -u32 acpi_fill_mcfg(u32 current)
> > +int acpi_fill_mcfg(struct acpi_ctx *ctx)
> >  {
> > +   size_t size;
> > +
> > /* TODO: Derive parameters from SFI MCFG table */
> > -   current += acpi_create_mcfg_mmconfig
> > -   ((struct acpi_mcfg_mmconfig *)current,
> > +   size = acpi_create_mcfg_mmconfig
> > +   ((struct acpi_mcfg_mmconfig *)ctx->current,
> > MCFG_BASE_ADDRESS, 0x0, 0x0, 0x0);
> > +   acpi_inc(ctx, size);
> >
> > -   return current;
> > +   return 0;
> >  }
> >
> >  static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp)
> > diff --git a/arch/x86/include/asm/acpi_table.h 
> > b/arch/x86/include/asm/acpi_table.h
> > index 0d07f7cad8..39547de0d4 100644
> > --- a/arch/x86/include/asm/acpi_table.h
> > +++ b/arch/x86/include/asm/acpi_table.h
> > @@ -34,7 +34,6 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi 
> > *lapic_nmi,
> >  u32 acpi_fill_madt(u32 current);
> >  int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 
> > base,
> >   u16 seg_nr, u8 start, u8 end);
> > -u32 acpi_fill_mcfg(u32 current);
> >
> >  /**
> >   * acpi_write_hpet() - Write out a HPET table
> > diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
> > index 753bf39619..c5b33dc65d 100644
> > --- a/arch/x86/lib/acpi_table.c
> > +++ b/arch/x86/lib/acpi_table.c
> > @@ -161,28 +161,6 @@ int acpi_write_madt(struct acpi_ctx *ctx, const struct 
> > acpi_writer *entry)
> >  }
> >  ACPI_WRITER(5x86, NULL, acpi_write_madt, 0);
> >
> > -int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 
> > base,
> > - u16 seg_nr, u8 start, u8 end)
> > -{
> > -   memset(mmconfig, 0, sizeof(*mmconfig));
> > -   mmconfig->base_address_l = base;
> > -   mmconfig->base_address_h = 0;
> > -   mmconfig->pci_segment_group_number = seg_nr;
> > -   mmconfig->start_bus_number = start;
> > -   mmconfig->end_bus_number = end;
> > -
> > -   return sizeof(struct acpi_mcfg_mmconfig);
> > -}
> > -
> > -__weak u32 acpi_fill_mcfg(u32 curre

Re: [U-Boot] [OE-core] [PATCH] u-boot: Upgrade to 2017.09

[Moritz Fischer]

Hi Marek,

On Fri, Sep 22, 2017 at 3:19 PM, Marek Vasut  wrote:
> On 09/21/2017 11:35 PM, Philip Balister wrote:
>> On 09/19/2017 04:15 AM, Marek Vasut wrote:
>>> On 09/18/2017 06:06 PM, Tom Rini wrote:
 On Mon, Sep 18, 2017 at 04:51:31PM +0100, Burton, Ross wrote:
> On 18 September 2017 at 16:46, Otavio Salvador <
> otavio.salva...@ossystems.com.br> wrote:
>
>> What is the policy on doing u-boot version upgrades this late in the
>>
>> release cycle? SHouldn't this wait until after the release?
>>
>>
>> Why?
>>
>> It is just another recipe and we are upgrading to the final release.
>>
>> As Martin said, it was already broken.
>>
>> I'll take the responsibility to fix it. But as other packages, upgrades
>> has risk and we have more than enough time to proper fix it.
>>
>
> Why?  Because it was merged to master after the freeze.
>
> Personally I'm of the opinion that u-boot is one of those special recipes
> that if an upgrade appears just after freeze, we consider it.  If we don't
> keep it up to date BSPs won't use the recipe, and we'll be back to every
> BSP layer containing its own special copy of the u-boot recipe.

 Also please note that U-Boot has a rather regular and public release
 schedule: http://www.denx.de/wiki/U-Boot/ReleaseCycle so you can have a
 good idea beforehand if you want to grab something for a release or not.

 Personally, I would like to see this in.  But the security issue that's
 been disclosed now is "resolved" just by not enabling functionality that
 no one was enabling in mainline, and will be removed in the next
 release, so don't feel you need to pull it in on those grounds.
>>>
>>> I agree that the 2017.09 upgrade is a good idea.
>>>
>>
>> OK, I just wanted to make sure everyone was on the same page about
>> timing of the update. We certainly don't want very many recipes to
>> decide they are special and take version bumps right up to release.
>
> Agreed. So what is the conclusion here about this , are we updating to
> 2017.09 or not ?

+1 for upgrade.

- morats
>
>> Philip
>>
>>
>
>
> --
> Best regards,
> Marek Vasut
> --
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[U-Boot] [PATCH v3] i2c: muxes: pca954x: Add support for GPIO reset line

[Moritz Fischer]

This commit adds support for GPIO reset lines matching the
common linux "reset-gpios" devicetree binding.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Reviewed-by: Heiko Schocher <h...@denx.de>
Reviewed-by: Simon Glass <s...@chromium.org>
---

Changes from v2:
-  Removed ifdef that would break build as suggested by Simon
-  Added Simon's and Heko's Reviewed-by

Changes from v1:
- Simon's feedback on ifdef vs IS_ENABLED()

Cheers,
Moritz

---
 drivers/i2c/muxes/pca954x.c | 40 +++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index 383f72f552..01ca1ff48d 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Copyright (C) 2017 National Instruments Corp
  * Written by Michal Simek
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -9,7 +10,8 @@
 #include 
 #include 
 #include 
-#include 
+
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -30,6 +32,7 @@ struct chip_desc {
 struct pca954x_priv {
u32 addr; /* I2C mux address */
u32 width; /* I2C mux width - number of busses */
+   struct gpio_desc gpio_mux_reset;
 };
 
 static const struct chip_desc chips[] = {
@@ -105,10 +108,45 @@ static int pca954x_ofdata_to_platdata(struct udevice *dev)
return 0;
 }
 
+static int pca954x_probe(struct udevice *dev)
+{
+   if (IS_ENABLED(CONFIG_DM_GPIO)) {
+   struct pca954x_priv *priv = dev_get_priv(dev);
+   int err;
+
+   err = gpio_request_by_name(dev, "reset-gpios", 0,
+   >gpio_mux_reset, GPIOD_IS_OUT);
+
+   /* it's optional so only bail if we get a real error */
+   if (err && (err != -ENOENT))
+   return err;
+
+   /* dm will take care of polarity */
+   if (dm_gpio_is_valid(>gpio_mux_reset))
+   dm_gpio_set_value(>gpio_mux_reset, 0);
+   }
+
+   return 0;
+}
+
+static int pca954x_remove(struct udevice *dev)
+{
+   if (IS_ENABLED(CONFIG_DM_GPIO)) {
+   struct pca954x_priv *priv = dev_get_priv(dev);
+
+   if (dm_gpio_is_valid(>gpio_mux_reset))
+   dm_gpio_free(dev, >gpio_mux_reset);
+   }
+
+   return 0;
+}
+
 U_BOOT_DRIVER(pca954x) = {
.name = "pca954x",
.id = UCLASS_I2C_MUX,
.of_match = pca954x_ids,
+   .probe = pca954x_probe,
+   .remove = pca954x_remove,
.ops = _ops,
.ofdata_to_platdata = pca954x_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct pca954x_priv),
-- 
2.14.1

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[U-Boot] [PATCH v2] i2c: muxes: pca954x: Add support for GPIO reset line

[Moritz Fischer]

This commit adds support for GPIO reset lines matching the
common linux "reset-gpios" devicetree binding.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---

Changes from v1:
- Simon's feedback on ifdef vs IS_ENABLED()

---
 drivers/i2c/muxes/pca954x.c | 42 +-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index 383f72f552..7dee12166d 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Copyright (C) 2017 National Instruments Corp
  * Written by Michal Simek
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -9,7 +10,8 @@
 #include 
 #include 
 #include 
-#include 
+
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -30,6 +32,9 @@ struct chip_desc {
 struct pca954x_priv {
u32 addr; /* I2C mux address */
u32 width; /* I2C mux width - number of busses */
+#ifdef CONFIG_DM_GPIO
+   struct gpio_desc gpio_mux_reset;
+#endif /* CONFIG_DM_GPIO */
 };
 
 static const struct chip_desc chips[] = {
@@ -105,10 +110,45 @@ static int pca954x_ofdata_to_platdata(struct udevice *dev)
return 0;
 }
 
+static int pca954x_probe(struct udevice *dev)
+{
+   if (IS_ENABLED(CONFIG_DM_GPIO)) {
+   struct pca954x_priv *priv = dev_get_priv(dev);
+   int err;
+
+   err = gpio_request_by_name(dev, "reset-gpios", 0,
+   >gpio_mux_reset, GPIOD_IS_OUT);
+
+   /* it's optional so only bail if we get a real error */
+   if (err && (err != -ENOENT))
+   return err;
+
+   /* dm will take care of polarity */
+   if (dm_gpio_is_valid(>gpio_mux_reset))
+   dm_gpio_set_value(>gpio_mux_reset, 0);
+   }
+
+   return 0;
+}
+
+static int pca954x_remove(struct udevice *dev)
+{
+   if (IS_ENABLED(CONFIG_DM_GPIO)) {
+   struct pca954x_priv *priv = dev_get_priv(dev);
+
+   if (dm_gpio_is_valid(>gpio_mux_reset))
+   dm_gpio_free(dev, >gpio_mux_reset);
+   }
+
+   return 0;
+}
+
 U_BOOT_DRIVER(pca954x) = {
.name = "pca954x",
.id = UCLASS_I2C_MUX,
.of_match = pca954x_ids,
+   .probe = pca954x_probe,
+   .remove = pca954x_remove,
.ops = _ops,
.ofdata_to_platdata = pca954x_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct pca954x_priv),
-- 
2.14.1

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Re: [U-Boot] [PATCH] i2c: muxes: pca954x: Add support for GPIO reset line

[Moritz Fischer]

Hi Simon,

On Fri, Sep 8, 2017 at 9:55 PM, Simon Glass <s...@chromium.org> wrote:
> On 5 September 2017 at 12:24, Moritz Fischer <moritz.fisc...@ettus.com> wrote:
>> This commit adds support for GPIO reset lines matching the
>> common linux "reset-gpios" devicetree binding.
>>
>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>> Cc: Heiko Schocher <h...@denx.de>
>> Cc: Stefan Roese <s...@denx.de>
>> Cc: Marek Behún <marek.be...@nic.cz>
>> Cc: Simon Glass <s...@chromium.org>
>> Cc: Michal Simek <mon...@monstr.eu>
>>
>> ---
>>  drivers/i2c/muxes/pca954x.c | 44 
>> +++-
>>  1 file changed, 43 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
>> index 383f72f552..dd28ff057b 100644
>> --- a/drivers/i2c/muxes/pca954x.c
>> +++ b/drivers/i2c/muxes/pca954x.c
>> @@ -1,5 +1,6 @@
>>  /*
>>   * Copyright (C) 2015 - 2016 Xilinx, Inc.
>> + * Copyright (C) 2017 National Instruments Corp
>>   * Written by Michal Simek
>>   *
>>   * SPDX-License-Identifier:GPL-2.0+
>> @@ -9,7 +10,10 @@
>>  #include 
>>  #include 
>>  #include 
>> -#include 
>> +
>> +#if CONFIG_DM_GPIO
>> +# include 
>> +#endif /* CONFIG_DM_GPIO */
>
> Can we drop the #ifdef?

Yeah, will do.
>
>>
>>  DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -30,6 +34,9 @@ struct chip_desc {
>>  struct pca954x_priv {
>> u32 addr; /* I2C mux address */
>> u32 width; /* I2C mux width - number of busses */
>> +#ifdef CONFIG_DM_GPIO
>> +   struct gpio_desc gpio_mux_reset;
>> +#endif /* CONFIG_DM_GPIO */
>>  };
>>
>>  static const struct chip_desc chips[] = {
>> @@ -105,10 +112,45 @@ static int pca954x_ofdata_to_platdata(struct udevice 
>> *dev)
>> return 0;
>>  }
>>
>> +static int pca954x_probe(struct udevice *dev)
>> +{
>> +#ifdef CONFIG_DM_GPIO
>
> Can we use if (IS_ENABLED(CONFIG_DM_GPIO)) ?

I suppose. I was wondering. Is this in general preferable?
>
>> +   struct pca954x_priv *priv = dev_get_priv(dev);
>> +   int err;
>> +
>> +   err = gpio_request_by_name(dev, "reset-gpios", 0,
>> +   >gpio_mux_reset, GPIOD_IS_OUT);
>> +
>> +   /* it's optional so only bail if we get a real error */
>> +   if (err && (err != -ENOENT))
>> +   return err;
>> +
>> +   /* dm will take care of polarity */
>> +   if (dm_gpio_is_valid(>gpio_mux_reset))
>> +   dm_gpio_set_value(>gpio_mux_reset, 0);
>> +
>> +#endif /* CONFIG_DM_GPIO */
>> +   return 0;
>> +}
>> +
>> +static int pca954x_remove(struct udevice *dev)
>> +{
>> +#ifdef CONFIG_DM_GPIO
>> +   struct pca954x_priv *priv = dev_get_priv(dev);
>> +
>> +   if (dm_gpio_is_valid(>gpio_mux_reset))
>> +   dm_gpio_free(dev, >gpio_mux_reset);
>> +
>> +#endif /* CONFIG_DM_GPIO */
>> +   return 0;
>> +}
>> +
>>  U_BOOT_DRIVER(pca954x) = {
>> .name = "pca954x",
>> .id = UCLASS_I2C_MUX,
>> .of_match = pca954x_ids,
>> +   .probe = pca954x_probe,
>> +   .remove = pca954x_remove,
>> .ops = _ops,
>> .ofdata_to_platdata = pca954x_ofdata_to_platdata,
>> .priv_auto_alloc_size = sizeof(struct pca954x_priv),
>> --
>> 2.14.1
>>

Thanks for the review,

Moritz
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[U-Boot] [PATCH] i2c: muxes: pca954x: Add support for GPIO reset line

[Moritz Fischer]

This commit adds support for GPIO reset lines matching the
common linux "reset-gpios" devicetree binding.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Stefan Roese <s...@denx.de>
Cc: Marek Behún <marek.be...@nic.cz>
Cc: Simon Glass <s...@chromium.org>
Cc: Michal Simek <mon...@monstr.eu>

---
 drivers/i2c/muxes/pca954x.c | 44 +++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index 383f72f552..dd28ff057b 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Copyright (C) 2017 National Instruments Corp
  * Written by Michal Simek
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -9,7 +10,10 @@
 #include 
 #include 
 #include 
-#include 
+
+#if CONFIG_DM_GPIO
+# include 
+#endif /* CONFIG_DM_GPIO */
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -30,6 +34,9 @@ struct chip_desc {
 struct pca954x_priv {
u32 addr; /* I2C mux address */
u32 width; /* I2C mux width - number of busses */
+#ifdef CONFIG_DM_GPIO
+   struct gpio_desc gpio_mux_reset;
+#endif /* CONFIG_DM_GPIO */
 };
 
 static const struct chip_desc chips[] = {
@@ -105,10 +112,45 @@ static int pca954x_ofdata_to_platdata(struct udevice *dev)
return 0;
 }
 
+static int pca954x_probe(struct udevice *dev)
+{
+#ifdef CONFIG_DM_GPIO
+   struct pca954x_priv *priv = dev_get_priv(dev);
+   int err;
+
+   err = gpio_request_by_name(dev, "reset-gpios", 0,
+   >gpio_mux_reset, GPIOD_IS_OUT);
+
+   /* it's optional so only bail if we get a real error */
+   if (err && (err != -ENOENT))
+   return err;
+
+   /* dm will take care of polarity */
+   if (dm_gpio_is_valid(>gpio_mux_reset))
+   dm_gpio_set_value(>gpio_mux_reset, 0);
+
+#endif /* CONFIG_DM_GPIO */
+   return 0;
+}
+
+static int pca954x_remove(struct udevice *dev)
+{
+#ifdef CONFIG_DM_GPIO
+   struct pca954x_priv *priv = dev_get_priv(dev);
+
+   if (dm_gpio_is_valid(>gpio_mux_reset))
+   dm_gpio_free(dev, >gpio_mux_reset);
+
+#endif /* CONFIG_DM_GPIO */
+   return 0;
+}
+
 U_BOOT_DRIVER(pca954x) = {
.name = "pca954x",
.id = UCLASS_I2C_MUX,
.of_match = pca954x_ids,
+   .probe = pca954x_probe,
+   .remove = pca954x_remove,
.ops = _ops,
.ofdata_to_platdata = pca954x_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct pca954x_priv),
-- 
2.14.1

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Re: [U-Boot] [PATCH 4/5] test: overlay: Add unit test for stacked overlay

[Moritz Fischer]

Hi Pantelis,

nit inline

On Fri, Jun 30, 2017 at 9:23 AM, Pantelis Antoniou
<pantelis.anton...@konsulko.com> wrote:
> Verify that stacked overlays work.
>
> Signed-off-by: Pantelis Antoniou <pantelis.anton...@konsulko.com>

Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>
> ---
>  test/overlay/Makefile |  1 +
>  test/overlay/cmd_ut_overlay.c | 34 
> ++-
>  test/overlay/test-fdt-overlay-stacked.dts | 21 +++
>  3 files changed, 55 insertions(+), 1 deletion(-)
>  create mode 100644 test/overlay/test-fdt-overlay-stacked.dts
>
> diff --git a/test/overlay/Makefile b/test/overlay/Makefile
> index 907f085..416645c 100644
> --- a/test/overlay/Makefile
> +++ b/test/overlay/Makefile
> @@ -13,3 +13,4 @@ DTC_FLAGS += -@
>  # DT overlays
>  obj-y += test-fdt-base.dtb.o
>  obj-y += test-fdt-overlay.dtb.o
> +obj-y += test-fdt-overlay-stacked.dtb.o
> diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c
> index cbef720..d8f5c8f 100644
> --- a/test/overlay/cmd_ut_overlay.c
> +++ b/test/overlay/cmd_ut_overlay.c
> @@ -20,6 +20,7 @@
>
>  extern u32 __dtb_test_fdt_base_begin;
>  extern u32 __dtb_test_fdt_overlay_begin;
> +extern u32 __dtb_test_fdt_overlay_stacked_begin;
>
>  static int fdt_getprop_u32_by_index(void *fdt, const char *path,
> const char *name, int index,
> @@ -201,6 +202,19 @@ static int fdt_overlay_local_phandles(struct 
> unit_test_state *uts)
>  }
>  OVERLAY_TEST(fdt_overlay_local_phandles, 0);
>
> +static int fdt_overlay_stacked(struct unit_test_state *uts)
> +{
> +   void *fdt = uts->priv;
> +   u32 val = 0;
> +
> +   ut_assertok(fdt_getprop_u32(fdt, "/new-local-node", 
> "stacked-test-int-property",
> +   ));
> +   ut_asserteq(43, val);
> +
> +   return CMD_RET_SUCCESS;
> +}
> +OVERLAY_TEST(fdt_overlay_stacked, 0);
> +
>  int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  {
> struct unit_test *tests = ll_entry_start(struct unit_test,
> @@ -210,7 +224,8 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
> char * const argv[])
> struct unit_test *test;
> void *fdt_base = &__dtb_test_fdt_base_begin;
> void *fdt_overlay = &__dtb_test_fdt_overlay_begin;
> -   void *fdt_base_copy, *fdt_overlay_copy;
> +   void *fdt_overlay_stacked = &__dtb_test_fdt_overlay_stacked_begin;
> +   void *fdt_base_copy, *fdt_overlay_copy, *fdt_overlay_stacked_copy;
>
> uts = calloc(1, sizeof(*uts));
> if (!uts)
> @@ -228,6 +243,10 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
> char * const argv[])
> if (!fdt_overlay_copy)
> return -ENOMEM;
>
> +   fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE);
> +   if (!fdt_overlay_stacked_copy)
> +   return -ENOMEM;
> +
> /*
>  * Resize the FDT to 4k so that we have room to operate on
>  *
> @@ -245,9 +264,21 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
> char * const argv[])
> ut_assertok(fdt_open_into(fdt_overlay, fdt_overlay_copy,
>   FDT_COPY_SIZE));
>
> +   /*
> +* Resize the stacked overlay to 4k so that we have room to operate on
> +*
> +* (and relocate it since the memory might be mapped
> +* read-only)
> +*/
> +   ut_assertok(fdt_open_into(fdt_overlay_stacked, 
> fdt_overlay_stacked_copy,
> + FDT_COPY_SIZE));
> +
> /* Apply the overlay */
> ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_copy));
>
> +   /* Apply the stacked overlay */
> +   ut_assertok(fdt_overlay_apply(fdt_base_copy, 
> fdt_overlay_stacked_copy));
> +
> if (argc == 1)
> printf("Running %d environment tests\n", n_ents);
>
> @@ -263,6 +294,7 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
> char * const argv[])
>
> printf("Failures: %d\n", uts->fail_count);
>
> +   free(fdt_overlay_stacked_copy);
> free(fdt_overlay_copy);
> free(fdt_base_copy);
> free(uts);
> diff --git a/test/overlay/test-fdt-overlay-stacked.dts 
> b/test/overlay/test-fdt-overlay-stacked.dts
> new file mode 100644
> index 000..9fb7c7b
> --- /dev/null
> +++ b/test/overlay/test-fdt-overlay-stacked.dts
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright (c) 2016 NextThing Co
> + * Copyri

Re: [U-Boot] [RFC/PATCH 1/2] ni: zynq: Add support for NI Ettus Research Project Sulfur Rev2 SDR

[Moritz Fischer]

On Thu, Jun 29, 2017 at 3:22 AM, Michal Simek <mon...@monstr.eu> wrote:
> On 23.6.2017 22:57, Moritz Fischer wrote:
>> Add support for second revision of NI Ettus Research Project Sulfur
>> Revision 2 SDR board.
>>
>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>> ---
>>  arch/arm/dts/Makefile|   1 +
>>  arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi  |  16 ++
>>  arch/arm/dts/zynq-ni-sulfur-rev2.dts | 275 
>>  board/ni/zynq/MAINTAINERS|   6 +
>>  board/ni/zynq/Makefile   |  10 +
>>  board/ni/zynq/board.c| 204 +++
>>  board/ni/zynq/ps7_init_common.c  | 119 +
>>  board/ni/zynq/ps7_init_gpl.h |  34 +++
>>  board/ni/zynq/zynq-ni-sulfur-rev2/ps7_init_gpl.c | 313 
>> +++
>>  configs/ni_sulfur_rev2_defconfig |  74 ++
>>  include/configs/ni_sulfur_rev2.h |  65 +
>>  11 files changed, 1117 insertions(+)
>>  create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi
>>  create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev2.dts
>>  create mode 100644 board/ni/zynq/MAINTAINERS
>>  create mode 100644 board/ni/zynq/Makefile
>>  create mode 100644 board/ni/zynq/board.c
>>  create mode 100644 board/ni/zynq/ps7_init_common.c
>>  create mode 100644 board/ni/zynq/ps7_init_gpl.h
>>  create mode 100644 board/ni/zynq/zynq-ni-sulfur-rev2/ps7_init_gpl.c
>>  create mode 100644 configs/ni_sulfur_rev2_defconfig
>>  create mode 100644 include/configs/ni_sulfur_rev2.h
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index a01c9b6..c3be80f 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
>>   zynq-zybo.dtb \
>>   zynq-microzed.dtb \
>>   zynq-picozed.dtb \
>> + zynq-ni-sulfur-rev2.dtb \
>>   zynq-topic-miami.dtb \
>>   zynq-topic-miamilite.dtb \
>>   zynq-topic-miamiplus.dtb \
>> diff --git a/arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi 
>> b/arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi
>> new file mode 100644
>> index 000..28344c5
>> --- /dev/null
>> +++ b/arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi
>> @@ -0,0 +1,16 @@
>> +/*
>> + * U-Boot addition to handle Sulfur Rev2 pins
>> + *
>> + * (C) Copyright 2016 National Instruments Corp
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + */
>> +
>> +#include 
>> +
>> + {
>> + sys_pwron_33 {
>> + u-boot,dm-pre-reloc;
>> + gpios = < 4 GPIO_ACTIVE_HIGH>;
>> + };
>> +};
>> diff --git a/arch/arm/dts/zynq-ni-sulfur-rev2.dts 
>> b/arch/arm/dts/zynq-ni-sulfur-rev2.dts
>> new file mode 100644
>> index 000..86f2b1c
>> --- /dev/null
>> +++ b/arch/arm/dts/zynq-ni-sulfur-rev2.dts
>> @@ -0,0 +1,275 @@
>> +/*
>> + * National Instruments Ettus Research Project Sulfur SDR Revision 2
>> + * devicetree source.
>> + *
>> + * Copyright (c) 2016 National Instruments Corp.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + *  Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software i

Re: [U-Boot] [PATCH] arm: zynq: Label whole PL part as fpga_full region

[Moritz Fischer]

Hi Michal,

can you / did you send this to the kernel ML, too?

On Thu, Jun 29, 2017 at 3:14 AM, Michal Simek <michal.si...@xilinx.com> wrote:
> This will simplify dt overlay structure for the whole PL.
>
> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>
> ---
>
>  arch/arm/dts/zynq-7000.dtsi | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
> index 34fc6e5f8936..f993e19ef280 100644
> --- a/arch/arm/dts/zynq-7000.dtsi
> +++ b/arch/arm/dts/zynq-7000.dtsi
> @@ -38,6 +38,14 @@
> };
> };
>
> +   fpga_full: fpga-full {
> +   compatible = "fpga-region";
> +   fpga-mgr = <>;
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   ranges;
> +   };
> +
> pmu@f8891000 {
> compatible = "arm,cortex-a9-pmu";
> interrupts = <0 5 4>, <0 6 4>;
> --
> 1.9.1
>
Thanks,

Moritz
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[U-Boot] [RFC/PATCH 2/2] ni: zynq: Add support for NI Ettus Research Project Sulfur Rev3 SDR

[Moritz Fischer]

Add support for second revision of NI Ettus Research Project Sulfur
Revision 3 SDR board.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/zynq-ni-sulfur-rev3-uboot.dtsi  |  26 ++
 arch/arm/dts/zynq-ni-sulfur-rev3.dts | 325 +++
 board/ni/zynq/board.c|  38 +++
 board/ni/zynq/sulfur-eeprom.h|  66 +
 board/ni/zynq/zynq-ni-sulfur-rev3/ps7_init_gpl.c | 307 +
 configs/ni_sulfur_rev3_defconfig |  69 +
 include/configs/ni_sulfur_rev3.h |  42 +++
 8 files changed, 874 insertions(+)
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev3-uboot.dtsi
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev3.dts
 create mode 100644 board/ni/zynq/sulfur-eeprom.h
 create mode 100644 board/ni/zynq/zynq-ni-sulfur-rev3/ps7_init_gpl.c
 create mode 100644 configs/ni_sulfur_rev3_defconfig
 create mode 100644 include/configs/ni_sulfur_rev3.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c3be80f..2a29b9c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -127,6 +127,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
zynq-ni-sulfur-rev2.dtb \
+   zynq-ni-sulfur-rev3.dtb \
zynq-topic-miami.dtb \
zynq-topic-miamilite.dtb \
zynq-topic-miamiplus.dtb \
diff --git a/arch/arm/dts/zynq-ni-sulfur-rev3-uboot.dtsi 
b/arch/arm/dts/zynq-ni-sulfur-rev3-uboot.dtsi
new file mode 100644
index 000..9a8b4e7
--- /dev/null
+++ b/arch/arm/dts/zynq-ni-sulfur-rev3-uboot.dtsi
@@ -0,0 +1,26 @@
+/*
+ * U-Boot addition to handle Sulfur Rev3 pins
+ *
+ * (C) Copyright 2017 National Instruments Corp
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+ {
+   u-boot,dm-pre-reloc;
+
+   sys_pwron_33 {
+   u-boot,dm-pre-reloc;
+   gpios = < 3 GPIO_ACTIVE_HIGH>;
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/zynq-ni-sulfur-rev3.dts 
b/arch/arm/dts/zynq-ni-sulfur-rev3.dts
new file mode 100644
index 000..3e2c69e
--- /dev/null
+++ b/arch/arm/dts/zynq-ni-sulfur-rev3.dts
@@ -0,0 +1,325 @@
+/*
+ * National Instruments Ettus Research Project Sulfur SDR Revision 2
+ * devicetree source.
+ *
+ * Copyright (c) 2016 National Instruments Corp.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "zynq-7000.dtsi"
+
+/ {
+   model = "NI Ettus Research Project Sulfur SDR Rev3";
+   compatible = "ettus,zynq-sulfur-rev3", "xlnx,zynq-7000";
+
+   aliases {
+   ethernet0 = 
+   serial0 = 
+   serial1 = 
+   spi0 = 
+   spi1 = 
+   gpio0 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2

[U-Boot] [RFC/PATCH 1/2] ni: zynq: Add support for NI Ettus Research Project Sulfur Rev2 SDR

[Moritz Fischer]

Add support for second revision of NI Ettus Research Project Sulfur
Revision 2 SDR board.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi  |  16 ++
 arch/arm/dts/zynq-ni-sulfur-rev2.dts | 275 
 board/ni/zynq/MAINTAINERS|   6 +
 board/ni/zynq/Makefile   |  10 +
 board/ni/zynq/board.c| 204 +++
 board/ni/zynq/ps7_init_common.c  | 119 +
 board/ni/zynq/ps7_init_gpl.h |  34 +++
 board/ni/zynq/zynq-ni-sulfur-rev2/ps7_init_gpl.c | 313 +++
 configs/ni_sulfur_rev2_defconfig |  74 ++
 include/configs/ni_sulfur_rev2.h |  65 +
 11 files changed, 1117 insertions(+)
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev2.dts
 create mode 100644 board/ni/zynq/MAINTAINERS
 create mode 100644 board/ni/zynq/Makefile
 create mode 100644 board/ni/zynq/board.c
 create mode 100644 board/ni/zynq/ps7_init_common.c
 create mode 100644 board/ni/zynq/ps7_init_gpl.h
 create mode 100644 board/ni/zynq/zynq-ni-sulfur-rev2/ps7_init_gpl.c
 create mode 100644 configs/ni_sulfur_rev2_defconfig
 create mode 100644 include/configs/ni_sulfur_rev2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a01c9b6..c3be80f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zybo.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
+   zynq-ni-sulfur-rev2.dtb \
zynq-topic-miami.dtb \
zynq-topic-miamilite.dtb \
zynq-topic-miamiplus.dtb \
diff --git a/arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi 
b/arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi
new file mode 100644
index 000..28344c5
--- /dev/null
+++ b/arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi
@@ -0,0 +1,16 @@
+/*
+ * U-Boot addition to handle Sulfur Rev2 pins
+ *
+ * (C) Copyright 2016 National Instruments Corp
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+ {
+   sys_pwron_33 {
+   u-boot,dm-pre-reloc;
+   gpios = < 4 GPIO_ACTIVE_HIGH>;
+   };
+};
diff --git a/arch/arm/dts/zynq-ni-sulfur-rev2.dts 
b/arch/arm/dts/zynq-ni-sulfur-rev2.dts
new file mode 100644
index 000..86f2b1c
--- /dev/null
+++ b/arch/arm/dts/zynq-ni-sulfur-rev2.dts
@@ -0,0 +1,275 @@
+/*
+ * National Instruments Ettus Research Project Sulfur SDR Revision 2
+ * devicetree source.
+ *
+ * Copyright (c) 2016 National Instruments Corp.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "zynq-7000.dtsi"
+
+/ {
+   model = "NI Ettus Research Project Sulfur SDR Rev2";
+   compatible = "ettus,zynq-sulfur-rev2", "xlnx,zynq-7000";

[U-Boot] [RFC/PATCH 0/2] Support for NI Ettus Research Project Sulfur

[Moritz Fischer]

Hi Michal,

this series adds (basic) support for the NI Ettus Research Project Sulfur SDR.

I have a bunch of follow up patches that still need cleanup, so maybe we
can start with this.

I'm not entirely happy with duplicating a large amount of code from
the board/xilinx/zynq/board.c file so suggestions are welcome.

My reasoning was that future modifications might be easier if I don't have
to mess with the common file via #if defined() for stuff that is NI/Ettus
specific in the board/xilinx/zynq directory.

Thanks,

Moritz

Moritz Fischer (2):
  ni: zynq: Add support for NI Ettus Research Project Sulfur Rev2 SDR
  ni: zynq: Add support for NI Ettus Research Project Sulfur Rev3 SDR

 arch/arm/dts/Makefile|   2 +
 arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi  |  16 ++
 arch/arm/dts/zynq-ni-sulfur-rev2.dts | 275 +++
 arch/arm/dts/zynq-ni-sulfur-rev3-uboot.dtsi  |  26 ++
 arch/arm/dts/zynq-ni-sulfur-rev3.dts | 325 +++
 board/ni/zynq/MAINTAINERS|   6 +
 board/ni/zynq/Makefile   |  10 +
 board/ni/zynq/board.c| 242 +
 board/ni/zynq/ps7_init_common.c  | 119 +
 board/ni/zynq/ps7_init_gpl.h |  34 +++
 board/ni/zynq/sulfur-eeprom.h|  66 +
 board/ni/zynq/zynq-ni-sulfur-rev2/ps7_init_gpl.c | 313 ++
 board/ni/zynq/zynq-ni-sulfur-rev3/ps7_init_gpl.c | 307 +
 configs/ni_sulfur_rev2_defconfig |  74 ++
 configs/ni_sulfur_rev3_defconfig |  69 +
 include/configs/ni_sulfur_rev2.h |  65 +
 include/configs/ni_sulfur_rev3.h |  42 +++
 17 files changed, 1991 insertions(+)
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev2-uboot.dtsi
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev2.dts
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev3-uboot.dtsi
 create mode 100644 arch/arm/dts/zynq-ni-sulfur-rev3.dts
 create mode 100644 board/ni/zynq/MAINTAINERS
 create mode 100644 board/ni/zynq/Makefile
 create mode 100644 board/ni/zynq/board.c
 create mode 100644 board/ni/zynq/ps7_init_common.c
 create mode 100644 board/ni/zynq/ps7_init_gpl.h
 create mode 100644 board/ni/zynq/sulfur-eeprom.h
 create mode 100644 board/ni/zynq/zynq-ni-sulfur-rev2/ps7_init_gpl.c
 create mode 100644 board/ni/zynq/zynq-ni-sulfur-rev3/ps7_init_gpl.c
 create mode 100644 configs/ni_sulfur_rev2_defconfig
 create mode 100644 configs/ni_sulfur_rev3_defconfig
 create mode 100644 include/configs/ni_sulfur_rev2.h
 create mode 100644 include/configs/ni_sulfur_rev3.h

-- 
2.7.4

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Re: [U-Boot] [PATCH 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Moritz Fischer]

Hi all,

On Mon, Feb 20, 2017 at 6:59 AM, Michal Simek  wrote:

> Definitely I am open to improve this subsystem to make it more flexible.

Over at linux-fpga ([1]) we're currently discussing the idea of coming
up with a header
format (vendor neutral) that we stitch onto the fpga image to allow the fpga-mgr
to derive certain features of the image from the image itself (i.e. is
the image encrypted,
compressed, ...).

We're trying to come up with an extensible format that would allow us
to add stuff like
encryption keys etc.

Cheers,

Moritz


[1] https://patchwork.kernel.org/patch/9574399/
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Re: [U-Boot] ZYNQ direct MAC connection

[Moritz Fischer]

Hi Hannes,

On Mon, Feb 13, 2017 at 4:56 AM, Hannes Schmelzer
<han...@schmelzer.or.at> wrote:
> Hello,
>
> did anybody setup successfully setup a direct MAC connection using RGMII
> with a zynq ?
> For example to a switch.
>
> The zynq_gem driver wants to probe for phy by itself.
> I already made a connection with very bad hacks in various files.
>
> In linux such things are working with "fixed-link". Also the i.mx6 FEC
> driver (not using DM) can operate in direct-connection mode.

For linux I have a patch that I've meant to submit since quite a while that
makes fixed-link work for the cadence gem. Maybe you can use that as a
starting point. It definitely does work.

I'll submit the linux one eventually, feel free to comment or improve.

Cheers,
Moritz
From 2526c6b641c5fb87b7469cd3fdef59de3d870b5e Mon Sep 17 00:00:00 2001
From: Moritz Fischer <moritz.fisc...@ettus.com>
Date: Mon, 13 Feb 2017 14:01:29 -0800
Subject: [PATCH] net: ethernet: cadence: Add fixed-link functionality

This allows 'fixed-link' direct MAC connections to be declared
in devicetree.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 drivers/net/ethernet/cadence/macb.c | 61 ++---
 drivers/net/ethernet/cadence/macb.h |  1 +
 2 files changed, 57 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 538544a..d3d4067 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -432,6 +432,34 @@ static int macb_mii_probe(struct net_device *dev)
 	return 0;
 }
 
+static int macb_fixed_init(struct macb *bp)
+{
+	struct phy_device *phydev;
+
+	phydev = of_phy_connect(bp->dev, bp->phy_node,
+_handle_link_change, 0,
+bp->phy_interface);
+	if (!phydev)
+		return -ENODEV;
+
+	/* mask with MAC supported features */
+	if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
+		phydev->supported &= PHY_GBIT_FEATURES;
+	else
+		phydev->supported &= PHY_BASIC_FEATURES;
+
+	if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
+		phydev->supported &= ~SUPPORTED_1000baseT_Half;
+
+	phydev->advertising = phydev->supported;
+
+	bp->link = 0;
+	bp->speed = 0;
+	bp->duplex = -1;
+
+	return 0;
+}
+
 static int macb_mii_init(struct macb *bp)
 {
 	struct macb_platform_data *pdata;
@@ -3127,6 +3155,7 @@ static int macb_probe(struct platform_device *pdev)
 	const char *mac;
 	struct macb *bp;
 	int err;
+	bool fixed_link = false;
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	mem = devm_ioremap_resource(>dev, regs);
@@ -3221,8 +3250,18 @@ static int macb_probe(struct platform_device *pdev)
 		macb_get_hwaddr(bp);
 
 	/* Power up the PHY if there is a GPIO reset */
-	phy_node =  of_get_next_available_child(np, NULL);
-	if (phy_node) {
+	phy_node = of_parse_phandle(np, "phy-handle", 0);
+	if (!phy_node && of_phy_is_fixed_link(np)) {
+		err = of_phy_register_fixed_link(np);
+		if (err < 0) {
+			dev_err(>dev, "broken fixed-link specification");
+			goto failed_phy;
+		}
+		/* in case of a fixed PHY, the DT node is the ethernet MAC */
+		phy_node = of_node_get(np);
+		bp->phy_node = phy_node;
+		fixed_link = true;
+	} else {
 		int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
 
 		if (gpio_is_valid(gpio)) {
@@ -3248,7 +3287,10 @@ static int macb_probe(struct platform_device *pdev)
 	if (err)
 		goto err_out_free_netdev;
 
-	err = macb_mii_init(bp);
+	if (!fixed_link)
+		err = macb_mii_init(bp);
+	else
+		err = macb_fixed_init(bp);
 	if (err)
 		goto err_out_free_netdev;
 
@@ -3279,6 +3321,9 @@ static int macb_probe(struct platform_device *pdev)
 	if (bp->reset_gpio)
 		gpiod_set_value(bp->reset_gpio, 0);
 
+failed_phy:
+	of_node_put(phy_node);
+
 err_out_free_netdev:
 	free_netdev(dev);
 
@@ -3302,9 +3347,14 @@ static int macb_remove(struct platform_device *pdev)
 		bp = netdev_priv(dev);
 		if (dev->phydev)
 			phy_disconnect(dev->phydev);
-		mdiobus_unregister(bp->mii_bus);
+
+		if (!bp->phy_node)
+			mdiobus_unregister(bp->mii_bus);
+
 		dev->phydev = NULL;
-		mdiobus_free(bp->mii_bus);
+
+		if (!bp->phy_node)
+			mdiobus_free(bp->mii_bus);
 
 		/* Shutdown the PHY if there is a GPIO reset */
 		if (bp->reset_gpio)
@@ -3314,6 +3364,7 @@ static int macb_remove(struct platform_device *pdev)
 		clk_disable_unprepare(bp->tx_clk);
 		clk_disable_unprepare(bp->hclk);
 		clk_disable_unprepare(bp->pclk);
+		of_node_put(bp->phy_node);
 		clk_disable_unprepare(bp->rx_clk);
 		free_netdev(dev);
 	}
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d67adad..282a569 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -852,6 +852,7 @@ struct macb {
 	struct macb_or_gem_ops	macbgem_ops;
 
 	struc

Re: [U-Boot] [PATCH] cros_ec: i2c: Add support for version 3 of the EC protocol

[Moritz Fischer]

Hi Simon,

On Thu, Jan 26, 2017 at 3:23 PM, Simon Glass  wrote:

> Unfortunately due to travel I'm not going to be able to try this
> out/review it for two more weeks.

No problem, I'm travelling too at the moment.

Moritz
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[U-Boot] [PATCH v2] cros_ec: i2c: Add support for version 3 of the EC protocol

[Moritz Fischer]

Add support for version 3 of the ec protocol. It basically works by
stitching some additional header in front (special command code),
and having a result and packet_length stitched on for the reply.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: u-boot@lists.denx.de
---

Changes from v1:
- Early return in case i2c xfer fails

Thanks,
Moritz

---
 drivers/misc/cros_ec_i2c.c | 84 ++
 1 file changed, 84 insertions(+)

diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c
index f2f6961..6e09340 100644
--- a/drivers/misc/cros_ec_i2c.c
+++ b/drivers/misc/cros_ec_i2c.c
@@ -24,6 +24,89 @@
 #define debug_trace(fmt, b...)
 #endif
 
+/**
+ * Request format for protocol v3
+ * byte 0  0xda (EC_COMMAND_PROTOCOL_3)
+ * byte 1-8struct ec_host_request
+ * byte 10-response data
+ */
+struct ec_host_request_i2c {
+   /* Always 0xda to backward compatible with v2 struct */
+   uint8_t  command_protocol;
+   struct ec_host_request ec_request;
+} __packed;
+
+/*
+ * Response format for protocol v3
+ * byte 0  result code
+ * byte 1  packet_length
+ * byte 2-9struct ec_host_response
+ * byte 10-response data
+ */
+struct ec_host_response_i2c {
+   uint8_t result;
+   uint8_t packet_length;
+   struct ec_host_response ec_response;
+} __packed;
+
+static int cros_ec_i2c_packet(struct udevice *udev, int out_bytes, int 
in_bytes)
+{
+   struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
+   struct dm_i2c_chip *chip = dev_get_parent_platdata(udev);
+   struct ec_host_request_i2c *ec_request_i2c =
+   (struct ec_host_request_i2c *)dev->dout;
+   struct ec_host_response_i2c *ec_response_i2c =
+   (struct ec_host_response_i2c *)dev->din;
+   struct i2c_msg i2c_msg[2];
+   int ret;
+
+   i2c_msg[0].addr = chip->chip_addr;
+   i2c_msg[0].flags = 0;
+   i2c_msg[1].addr = chip->chip_addr;
+   i2c_msg[1].flags = I2C_M_RD;
+
+   /* one extra byte, to indicate v3 */
+   i2c_msg[0].len = out_bytes + 1;
+   i2c_msg[0].buf = dev->dout;
+
+   /* stitch on EC_COMMAND_PROTOCOL_3 */
+   memmove(_request_i2c->ec_request, dev->dout, out_bytes);
+   ec_request_i2c->command_protocol = EC_COMMAND_PROTOCOL_3;
+
+   /* two extra bytes for v3 */
+   i2c_msg[1].len = in_bytes + 2;
+   i2c_msg[1].buf = dev->din;
+
+   ret = dm_i2c_xfer(udev, _msg[0], 2);
+   if (ret) {
+   printf("%s: Could not execute transfer: %d\n", __func__, ret);
+   return ret;
+   }
+
+   /* When we send a v3 request to v2 ec, ec won't recognize the 0xda
+* (EC_COMMAND_PROTOCOL_3) and will return with status
+* EC_RES_INVALID_COMMAND with zero data length
+*
+* In case of invalid command for v3 protocol the data length
+* will be at least sizeof(struct ec_host_response)
+*/
+   if (ec_response_i2c->result == EC_RES_INVALID_COMMAND &&
+   ec_response_i2c->packet_length == 0)
+   return -EPROTONOSUPPORT;
+
+   if (ec_response_i2c->packet_length < sizeof(struct ec_host_response)) {
+   printf("%s: response of %u bytes too short; not a full hdr\n",
+  __func__, ec_response_i2c->packet_length);
+   return -EBADMSG;
+   }
+
+
+   /* drop result and packet_len */
+   memmove(dev->din, _response_i2c->ec_response, in_bytes);
+
+   return in_bytes;
+}
+
 static int cros_ec_i2c_command(struct udevice *udev, uint8_t cmd,
   int cmd_version, const uint8_t *dout,
   int dout_len, uint8_t **dinp, int din_len)
@@ -140,6 +223,7 @@ static int cros_ec_probe(struct udevice *dev)
 
 static struct dm_cros_ec_ops cros_ec_ops = {
.command = cros_ec_i2c_command,
+   .packet = cros_ec_i2c_packet,
 };
 
 static const struct udevice_id cros_ec_ids[] = {
-- 
2.7.4

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[U-Boot] [PATCH RESEND v2 3/4] i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a quirk where if during a long read transfer
the transfer_size register will go to 0, the master will send a NACK to
the slave prematurely.
The way to work around this is to reprogram the transfer_size register
mid-transfer when the only the receive fifo is known full, i.e. the I2C
bus is known non-active.
The workaround is based on the implementation in the linux-kernel.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- Fixed the removal/addition of printf/debug
---
 drivers/i2c/i2c-cdns.c | 119 -
 1 file changed, 89 insertions(+), 30 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 1c9fda8..89d429b 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,6 +68,8 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
+
 #define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
@@ -247,15 +250,21 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
   u32 len)
 {
u8 *cur_data = data;
-
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
+   /* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
-
-
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
+   /* Check message size against FIFO depth, and set hold bus bit
+* if it is greater than FIFO depth
+*/
+   if (len > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
+   /* Clear the interrupts in status register */
writel(0xFF, >interrupt_status);
+
writel(addr, >address);
 
while (len--) {
@@ -280,48 +289,98 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
return 0;
 }
 
+static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+{
+   return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+}
+
 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len)
+ u32 recv_count)
 {
-   u32 status;
-   u32 i = 0;
u8 *cur_data = data;
-
-   /* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
+   int curr_recv_count;
+   int updatetx, hold_quirk;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0))
+   if ((recv_count < 0))
return -EINVAL;
 
+   curr_recv_count = recv_count;
+
+   /* Check for the message size against the FIFO depth */
+   if (recv_count > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
 
+   if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+   curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+   writel(curr_recv_count, >transfer_size);
+   } else {
+   writel(recv_count, >transfer_size);
+   }
+
/* Start reading data */
writel(addr, >address);
-   writel(len, >transfer_size);
-
-   /* Wait for data */
-   do {
-   status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_DATA);
-   if (!status) {
-   /* Release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   return -ETIMEDOUT;
+
+   updatetx = recv_count > curr_recv_count;
+
+   hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
+
+   while (recv_count) {
+   while (readl(>status) & CDNS_I2C_STATUS_RXDV) {
+   if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+   !i2c_bus->hold_flag) {
+   clrbits_le32(>control,
+CDNS_I2C_CONTROL_HOLD);
+   }
+   *(cur_data)++ = readl(>data);
+   recv_count--;
+   curr_recv_count--;
+
+   if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+   break;
}
-   debug("Read %d bytes\n",
- len - readl(>transfer_size));
-   for (; i < len - rea

[U-Boot] [PATCH RESEND v2 4/4] i2c: i2c-cdns: No need for dedicated probe function

[Moritz Fischer]

The generic probe code in dm works, so get rid of the leftover cruft.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- None
---
 drivers/i2c/i2c-cdns.c | 21 -
 1 file changed, 21 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 89d429b..dec1820 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -226,26 +226,6 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
return 0;
 }
 
-/* Probe to see if a chip is present. */
-static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
-   uint chip_flags)
-{
-   struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
-   struct cdns_i2c_regs *regs = i2c_bus->regs;
-
-   /* Attempt to read a byte */
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_RW);
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   writel(0xFF, >interrupt_status);
-   writel(chip_addr, >address);
-   writel(1, >transfer_size);
-
-   return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_NACK) &
-   CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
-}
-
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
   u32 len)
 {
@@ -453,7 +433,6 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 
 static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
-   .probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
 };
 
-- 
2.7.4

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[U-Boot] [PATCH RESEND v2 2/4] i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

[Moritz Fischer]

Reorder the timeout loop such that we first check if the
condition is already true, and then call udelay() so if
the condition is already true, break early.

Reviewed-by: Michal Simek <michal.si...@xilinx.com>
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- None

---
 drivers/i2c/i2c-cdns.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index c1d6427..1c9fda8 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -130,10 +130,10 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, 
u32 mask)
int timeout, int_status;
 
for (timeout = 0; timeout < 100; timeout++) {
-   udelay(100);
int_status = readl(_i2c->interrupt_status);
if (int_status & mask)
break;
+   udelay(100);
}
 
/* Clear interrupt status flags */
-- 
2.7.4

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[U-Boot] [PATCH RESEND v2 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a couple of issues, such as not supporting
repeated start conditions for read transfers.

So scan through the list of i2c messages for these conditions
and report an error if they are attempted.

This has been fixed for revision 1.4 of the IP, so only report the error
when the IP can really not do it.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- Removed additional blank lines
- No longer modify printout paths
- Rebased on top of prior patches for r1p14 support
---
 drivers/i2c/i2c-cdns.c | 66 +++---
 1 file changed, 52 insertions(+), 14 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index ef85a70..c1d6427 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -67,6 +67,7 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
@@ -114,6 +115,13 @@ struct i2c_cdns_bus {
int id;
unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
+
+   int hold_flag;
+   u32 quirks;
+};
+
+struct cdns_i2c_platform_data {
+   u32 quirks;
 };
 
 /* Wait for an interrupt */
@@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, uint 
chip_addr,
 }
 
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
-  u32 len, bool next_is_read)
+  u32 len)
 {
u8 *cur_data = data;
 
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_HOLD);
+   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
 
-   /* if next is a read, we need to clear HOLD, doesn't work */
-   if (next_is_read)
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
@@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
}
 
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
/* Wait for the address and data to be sent */
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
@@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
+   if ((len < 0))
return -EINVAL;
 
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
@@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
*(cur_data++) = readl(>data);
} while (readl(>transfer_size) != 0);
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
 #ifdef DEBUG
cdns_i2c_debug_status(regs);
@@ -322,19 +329,41 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
i2c_msg *msg,
 int nmsgs)
 {
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
-   int ret;
+   int ret, count;
+   bool hold_quirk;
+
+   hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
+
+   if (nmsgs > 1) {
+   /*
+* This controller does not give completion interrupt after a
+* master receive message if HOLD bit is set (repeated start),
+* resulting in SW timeout. Hence, if a receive message is
+* followed by any other message, an error is returned
+* indicating that this sequence is not supported.
+*/
+   for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
+   if (msg[count].flags & I2C_M_RD) {
+   printf("Can't do repeated start after a receive 
message\n");
+   return -EOPNOTSUPP;
+   }
+   }
+
+   i2c_bus->hold_flag = 1;
+   setbits_le32(_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
+   } else {
+   i2c_bus->hold_flag = 0;
+   }
 
debug("i2c_xfer: %d messages\n&quo

[U-Boot] [PATCH v2] i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent

[Moritz Fischer]

For mux check if the parent is already a device of UCLASS_I2C and if yes
just use that. Otherwise see if someone specified an i2c-parent phandle.
This mimics the behavior found in the Kernel, as it removes the
requirement to explicitly specify a i2c-parent phandle.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Bin Meng <bmeng...@gmail.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- Fixed comment style (Michal)
---
 drivers/i2c/muxes/i2c-mux-uclass.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c 
b/drivers/i2c/muxes/i2c-mux-uclass.c
index 7a698b6..db086ef 100644
--- a/drivers/i2c/muxes/i2c-mux-uclass.c
+++ b/drivers/i2c/muxes/i2c-mux-uclass.c
@@ -86,6 +86,16 @@ static int i2c_mux_post_probe(struct udevice *mux)
debug("%s: %s\n", __func__, mux->name);
priv->selected = -1;
 
+   /* if parent is of i2c uclass already, we'll take that, otherwise
+* look if we find an i2c-parent phandle
+*/
+   if (UCLASS_I2C == device_get_uclass_id(mux->parent)) {
+   priv->i2c_bus = dev_get_parent(mux);
+   debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus,
+ priv->i2c_bus->name);
+   return 0;
+   }
+
ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
   >i2c_bus);
if (ret)
-- 
2.7.4

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[U-Boot] [PATCH] cros_ec: i2c: Add support for version 3 of the EC protocol

[Moritz Fischer]

Add support for version 3 of the ec protocol. It basically works by
stitching some additional header in front (special command code),
and having a result and packet_length stitched on for the reply.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: u-boot@lists.denx.de
---
Hi Simon,

I tested this on a v3 EC, but again as for the previous patch,
I do not have a v2 EC to test with. I'm not perfectly happy with the memmove
back and forth, so if you have a better solution for that I'm all ears.

Thanks,
Moritz

---
 drivers/misc/cros_ec_i2c.c | 84 ++
 1 file changed, 84 insertions(+)

diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c
index f2f6961..c46215b 100644
--- a/drivers/misc/cros_ec_i2c.c
+++ b/drivers/misc/cros_ec_i2c.c
@@ -24,6 +24,89 @@
 #define debug_trace(fmt, b...)
 #endif
 
+/**
+ * Request format for protocol v3
+ * byte 0  0xda (EC_COMMAND_PROTOCOL_3)
+ * byte 1-8struct ec_host_request
+ * byte 10-response data
+ */
+struct ec_host_request_i2c {
+   /* Always 0xda to backward compatible with v2 struct */
+   uint8_t  command_protocol;
+   struct ec_host_request ec_request;
+} __packed;
+
+/*
+ * Response format for protocol v3
+ * byte 0  result code
+ * byte 1  packet_length
+ * byte 2-9struct ec_host_response
+ * byte 10-response data
+ */
+struct ec_host_response_i2c {
+   uint8_t result;
+   uint8_t packet_length;
+   struct ec_host_response ec_response;
+} __packed;
+
+static int cros_ec_i2c_packet(struct udevice *udev, int out_bytes, int 
in_bytes)
+{
+   struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
+   struct dm_i2c_chip *chip = dev_get_parent_platdata(udev);
+   struct ec_host_request_i2c *ec_request_i2c =
+   (struct ec_host_request_i2c *)dev->dout;
+   struct ec_host_response_i2c *ec_response_i2c =
+   (struct ec_host_response_i2c *)dev->din;
+   struct i2c_msg i2c_msg[2];
+   int ret;
+
+   i2c_msg[0].addr = chip->chip_addr;
+   i2c_msg[0].flags = 0;
+   i2c_msg[1].addr = chip->chip_addr;
+   i2c_msg[1].flags = I2C_M_RD;
+
+   /* one extra byte, to indicate v3 */
+   i2c_msg[0].len = out_bytes + 1;
+   i2c_msg[0].buf = dev->dout;
+
+   /* stitch on EC_COMMAND_PROTOCOL_3 */
+   memmove(_request_i2c->ec_request, dev->dout, out_bytes);
+   ec_request_i2c->command_protocol = EC_COMMAND_PROTOCOL_3;
+
+   /* two extra bytes for v3 */
+   i2c_msg[1].len = in_bytes + 2;
+   i2c_msg[1].buf = dev->din;
+
+   ret = dm_i2c_xfer(udev, _msg[0], 2);
+   if (ret) {
+   printf("%s: Could not execute transfer: %d\n", __func__, ret);
+   ret = -1;
+   }
+
+   /* When we send a v3 request to v2 ec, ec won't recognize the 0xda
+* (EC_COMMAND_PROTOCOL_3) and will return with status
+* EC_RES_INVALID_COMMAND with zero data length
+*
+* In case of invalid command for v3 protocol the data length
+* will be at least sizeof(struct ec_host_response)
+*/
+   if (ec_response_i2c->result == EC_RES_INVALID_COMMAND &&
+   ec_response_i2c->packet_length == 0)
+   return -EPROTONOSUPPORT;
+
+   if (ec_response_i2c->packet_length < sizeof(struct ec_host_response)) {
+   printf("%s: response of %u bytes too short; not a full hdr\n",
+  __func__, ec_response_i2c->packet_length);
+   return -EBADMSG;
+   }
+
+
+   /* drop result and packet_len */
+   memmove(dev->din, _response_i2c->ec_response, in_bytes);
+
+   return in_bytes;
+}
+
 static int cros_ec_i2c_command(struct udevice *udev, uint8_t cmd,
   int cmd_version, const uint8_t *dout,
   int dout_len, uint8_t **dinp, int din_len)
@@ -140,6 +223,7 @@ static int cros_ec_probe(struct udevice *dev)
 
 static struct dm_cros_ec_ops cros_ec_ops = {
.command = cros_ec_i2c_command,
+   .packet = cros_ec_i2c_packet,
 };
 
 static const struct udevice_id cros_ec_ids[] = {
-- 
2.7.4

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[U-Boot] [RFC/PATCH] cros_ec: i2c: Group i2c write / read into single transaction

[Moritz Fischer]

Replace dm_i2c_write() / dm_i2c_read() with transaction using
struct i2c_msg[2] in order to allow for i2c controller to detect
write/read cycle to emit a repeated start condition.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: u-boot@lists.denx.de
---
Hi Simon,

since I don't have a v2 protocol EC I couldn't test this,
but I noticed when playing around with a v3 one, that it would simply ignore
the packets if they don't have a repeated start condition (which from my 
understanding)
you can *only* get if you use struct i2c_msg, since otherwise the driver has no 
way of
knowing your intention.

Do you have a v2 board around to test this?

Cheers,

Moritz
---
 drivers/misc/cros_ec_i2c.c | 26 +++---
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c
index 3de18b2..f2f6961 100644
--- a/drivers/misc/cros_ec_i2c.c
+++ b/drivers/misc/cros_ec_i2c.c
@@ -29,6 +29,8 @@ static int cros_ec_i2c_command(struct udevice *udev, uint8_t 
cmd,
   int dout_len, uint8_t **dinp, int din_len)
 {
struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
+   struct dm_i2c_chip *chip = dev_get_parent_platdata(udev);
+   struct i2c_msg i2c_msg[2];
/* version8, cmd8, arglen8, out8[dout_len], csum8 */
int out_bytes = dout_len + 4;
/* response8, arglen8, in8[din_len], checksum8 */
@@ -53,6 +55,11 @@ static int cros_ec_i2c_command(struct udevice *udev, uint8_t 
cmd,
assert(dout_len >= 0);
assert(dinp);
 
+   i2c_msg[0].addr = chip->chip_addr;
+   i2c_msg[0].len = out_bytes;
+   i2c_msg[0].buf = dev->dout;
+   i2c_msg[0].flags = 0;
+
/*
 * Copy command and data into output buffer so we can do a single I2C
 * burst transaction.
@@ -85,24 +92,21 @@ static int cros_ec_i2c_command(struct udevice *udev, 
uint8_t cmd,
*ptr++ = (uint8_t)
cros_ec_calc_checksum(dev->dout, dout_len + 3);
 
+   i2c_msg[1].addr = chip->chip_addr;
+   i2c_msg[1].len = in_bytes;
+   i2c_msg[1].buf = in_ptr;
+   i2c_msg[1].flags = I2C_M_RD;
+
/* Send output data */
cros_ec_dump_data("out", -1, dev->dout, out_bytes);
-   ret = dm_i2c_write(udev, 0, dev->dout, out_bytes);
+
+   ret = dm_i2c_xfer(udev, _msg[0], 2);
if (ret) {
-   debug("%s: Cannot complete I2C write to %s\n", __func__,
+   debug("%s: Could not execute transfer to %s\n", __func__,
  udev->name);
ret = -1;
}
 
-   if (!ret) {
-   ret = dm_i2c_read(udev, 0, in_ptr, in_bytes);
-   if (ret) {
-   debug("%s: Cannot complete I2C read from %s\n",
- __func__, udev->name);
-   ret = -1;
-   }
-   }
-
if (*in_ptr != EC_RES_SUCCESS) {
debug("%s: Received bad result code %d\n", __func__, *in_ptr);
return -(int)*in_ptr;
-- 
2.7.4

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[U-Boot] [PATCH v2 2/4] i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

[Moritz Fischer]

Reorder the timeout loop such that we first check if the
condition is already true, and then call udelay() so if
the condition is already true, break early.

Reviewed-by: Michal Simek <michal.si...@xilinx.com>
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- None

---
 drivers/i2c/i2c-cdns.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index c1d6427..1c9fda8 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -130,10 +130,10 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, 
u32 mask)
int timeout, int_status;
 
for (timeout = 0; timeout < 100; timeout++) {
-   udelay(100);
int_status = readl(_i2c->interrupt_status);
if (int_status & mask)
break;
+   udelay(100);
}
 
/* Clear interrupt status flags */
-- 
2.7.4

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[U-Boot] [PATCH v2 4/4] i2c: i2c-cdns: No need for dedicated probe function

[Moritz Fischer]

The generic probe code in dm works, so get rid of the leftover cruft.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- None
---
 drivers/i2c/i2c-cdns.c | 21 -
 1 file changed, 21 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 89d429b..dec1820 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -226,26 +226,6 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
return 0;
 }
 
-/* Probe to see if a chip is present. */
-static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
-   uint chip_flags)
-{
-   struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
-   struct cdns_i2c_regs *regs = i2c_bus->regs;
-
-   /* Attempt to read a byte */
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_RW);
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   writel(0xFF, >interrupt_status);
-   writel(chip_addr, >address);
-   writel(1, >transfer_size);
-
-   return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_NACK) &
-   CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
-}
-
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
   u32 len)
 {
@@ -453,7 +433,6 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 
 static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
-   .probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
 };
 
-- 
2.7.4

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[U-Boot] [PATCH v2 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a couple of issues, such as not supporting
repeated start conditions for read transfers.

So scan through the list of i2c messages for these conditions
and report an error if they are attempted.

This has been fixed for revision 1.4 of the IP, so only report the error
when the IP can really not do it.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- Removed additional blank lines
- No longer modify printout paths
- Rebased on top of prior patches for r1p14 support
---
 drivers/i2c/i2c-cdns.c | 66 +++---
 1 file changed, 52 insertions(+), 14 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index ef85a70..c1d6427 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -67,6 +67,7 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
@@ -114,6 +115,13 @@ struct i2c_cdns_bus {
int id;
unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
+
+   int hold_flag;
+   u32 quirks;
+};
+
+struct cdns_i2c_platform_data {
+   u32 quirks;
 };
 
 /* Wait for an interrupt */
@@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, uint 
chip_addr,
 }
 
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
-  u32 len, bool next_is_read)
+  u32 len)
 {
u8 *cur_data = data;
 
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_HOLD);
+   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
 
-   /* if next is a read, we need to clear HOLD, doesn't work */
-   if (next_is_read)
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
@@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
}
 
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
/* Wait for the address and data to be sent */
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
@@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
+   if ((len < 0))
return -EINVAL;
 
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
@@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
*(cur_data++) = readl(>data);
} while (readl(>transfer_size) != 0);
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
 #ifdef DEBUG
cdns_i2c_debug_status(regs);
@@ -322,19 +329,41 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
i2c_msg *msg,
 int nmsgs)
 {
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
-   int ret;
+   int ret, count;
+   bool hold_quirk;
+
+   hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
+
+   if (nmsgs > 1) {
+   /*
+* This controller does not give completion interrupt after a
+* master receive message if HOLD bit is set (repeated start),
+* resulting in SW timeout. Hence, if a receive message is
+* followed by any other message, an error is returned
+* indicating that this sequence is not supported.
+*/
+   for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
+   if (msg[count].flags & I2C_M_RD) {
+   printf("Can't do repeated start after a receive 
message\n");
+   return -EOPNOTSUPP;
+   }
+   }
+
+   i2c_bus->hold_flag = 1;
+   setbits_le32(_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
+   } else {
+   i2c_bus->hold_flag = 0;
+   }
 
debug("i2c_xfer: %d messages\n&quo

[U-Boot] [PATCH v2 3/4] i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a quirk where if during a long read transfer
the transfer_size register will go to 0, the master will send a NACK to
the slave prematurely.
The way to work around this is to reprogram the transfer_size register
mid-transfer when the only the receive fifo is known full, i.e. the I2C
bus is known non-active.
The workaround is based on the implementation in the linux-kernel.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
Changes from v1:
- Fixed the removal/addition of printf/debug
---
 drivers/i2c/i2c-cdns.c | 119 -
 1 file changed, 89 insertions(+), 30 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 1c9fda8..89d429b 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,6 +68,8 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
+
 #define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
@@ -247,15 +250,21 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
   u32 len)
 {
u8 *cur_data = data;
-
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
+   /* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
-
-
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
+   /* Check message size against FIFO depth, and set hold bus bit
+* if it is greater than FIFO depth
+*/
+   if (len > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
+   /* Clear the interrupts in status register */
writel(0xFF, >interrupt_status);
+
writel(addr, >address);
 
while (len--) {
@@ -280,48 +289,98 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
return 0;
 }
 
+static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+{
+   return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+}
+
 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len)
+ u32 recv_count)
 {
-   u32 status;
-   u32 i = 0;
u8 *cur_data = data;
-
-   /* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
+   int curr_recv_count;
+   int updatetx, hold_quirk;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0))
+   if ((recv_count < 0))
return -EINVAL;
 
+   curr_recv_count = recv_count;
+
+   /* Check for the message size against the FIFO depth */
+   if (recv_count > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
 
+   if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+   curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+   writel(curr_recv_count, >transfer_size);
+   } else {
+   writel(recv_count, >transfer_size);
+   }
+
/* Start reading data */
writel(addr, >address);
-   writel(len, >transfer_size);
-
-   /* Wait for data */
-   do {
-   status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_DATA);
-   if (!status) {
-   /* Release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   return -ETIMEDOUT;
+
+   updatetx = recv_count > curr_recv_count;
+
+   hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
+
+   while (recv_count) {
+   while (readl(>status) & CDNS_I2C_STATUS_RXDV) {
+   if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+   !i2c_bus->hold_flag) {
+   clrbits_le32(>control,
+CDNS_I2C_CONTROL_HOLD);
+   }
+   *(cur_data)++ = readl(>data);
+   recv_count--;
+   curr_recv_count--;
+
+   if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+   break;
}
-   debug("Read %d bytes\n",
- len - readl(>transfer_size));
-   for (; i < len - rea

Re: [U-Boot] [PATCH] i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent

[Moritz Fischer]

Hi Michal,

On Tue, Jan 3, 2017 at 1:22 AM, Michal Simek <michal.si...@xilinx.com> wrote:
> On 2.1.2017 20:20, Moritz Fischer wrote:
>> Hi Michal,
>>
>> On Mon, Jan 2, 2017 at 6:24 AM, Michal Simek <michal.si...@xilinx.com> wrote:
>>> On 29.12.2016 23:50, Moritz Fischer wrote:
>>>> For mux check if the parent is already a device of UCLASS_I2C and if yes
>>>> just use that. Otherwise see if someone specified an i2c-parent phandle.
>>>> This mimics the behavior found in the Kernel, as it removes the
>>>> requirement to explicitly specify a i2c-parent phandle.
>>>>
>>>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>>>> Cc: Heiko Schocher <h...@denx.de>
>>>> Cc: Bin Meng <bmeng...@gmail.com>
>>>> Cc: Simon Glass <s...@chromium.org>
>>>> Cc: Michal Simek <michal.si...@xilinx.com>
>>>> Cc: u-boot@lists.denx.de
>>>> ---
>>>>  drivers/i2c/muxes/i2c-mux-uclass.c | 9 +
>>>>  1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c 
>>>> b/drivers/i2c/muxes/i2c-mux-uclass.c
>>>> index 7a698b6..e01b773 100644
>>>> --- a/drivers/i2c/muxes/i2c-mux-uclass.c
>>>> +++ b/drivers/i2c/muxes/i2c-mux-uclass.c
>>>> @@ -86,6 +86,15 @@ static int i2c_mux_post_probe(struct udevice *mux)
>>>>   debug("%s: %s\n", __func__, mux->name);
>>>>   priv->selected = -1;
>>>>
>>>> + /* if parent is of i2c uclass already, we'll take that, otherwise
>>>> +  * look if we find an i2c-parent phandle */
>>>
>>> Incorrect comment style.
>>
>> Yeah, wasn't flagged by checkpatch  will fix.
>>>
>>>> + if (UCLASS_I2C == device_get_uclass_id(mux->parent)) {
>>>> + priv->i2c_bus = dev_get_parent(mux);
>>>> + debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus,
>>>> +   priv->i2c_bus->name);
>>>> + return 0;
>>>> + }
>>>> +
>>>>   ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
>>>>  >i2c_bus);
>>>>   if (ret)
>>>>
>>>
>>> The part of this will be good to also handle
>>> req_seq for mux busses. But at least this should solved part of the
>>> problems.
>>
>> I'm not sure I understand this comment.
>
> AFAIK using i2c muxes requires two changes in DTS file.
> First change is this to setup i2c-parent in DTS file which is something
> what Linux doesn't need.

Yeah this part is addressed in this patch.

> The next change is that you have to extend i2c aliases to point to i2c
> mux sub busses which is the second thing what Linux doesn't need.
> I expect that this change you have in your dts file.

Yeah, thanks for clarifying. In my dts I have aliases for each of the
mux channels,
which, I don't have a good idea on how to solve differently. In Linux
I think I don't need that.

> I think that if you detect mux with 8 ports you can simply use unique
> busid to be able to address them.

In Linux? I'll have to take another look at that. Currently I get
busses like 700,701,702 etc (which are aliases I defined).
Each of them points to a mux channel.


aliases { ...
i2c0 = 
i2c0700 = _70_0;
i2c0701 = _70_1;
i2c0702 = _70_2;
i2c0703 = _70_3;
};

...
i2cswitch@70 {
compatible = "ti,pca9548", "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
status = "okay";

i2c0_70_0: i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;

status = "okay";
};
...
  };



I Will resubmit a v2 for the other changes above

If you or Simon have ideas on how to correctly solve the alias issue,
I can take another stab at that.

Thanks,

Moritz
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Re: [U-Boot] [PATCH 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Moritz Fischer]

Hi Michal,

On Mon, Jan 2, 2017 at 6:29 AM, Michal Simek <michal.si...@xilinx.com> wrote:
> +Siva: please test it.
>
> On 27.12.2016 23:46, Moritz Fischer wrote:
>> Revision 1.0 of this IP has a couple of issues, such as not supporting
>> repeated start conditions for read transfers.
>>
>> So scan through the list of i2c messages for these conditions
>> and report an error if they are attempted.
>>
>> This has been fixed for revision 1.4 of the IP, so only report the error
>> when the IP can really not do it.
>>
>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>> Cc: Heiko Schocher <h...@denx.de>
>> Cc: Michal Simek <michal.si...@xilinx.com>
>> Cc: u-boot@lists.denx.de
>> ---
>>  drivers/i2c/i2c-cdns.c | 69 
>> --
>>  1 file changed, 55 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
>> index f49f60b..c69e7e8 100644
>> --- a/drivers/i2c/i2c-cdns.c
>> +++ b/drivers/i2c/i2c-cdns.c
>> @@ -67,6 +67,7 @@ struct cdns_i2c_regs {
>>
>>  #define CDNS_I2C_FIFO_DEPTH  16
>>  #define CDNS_I2C_TRANSFER_SIZE_MAX   255 /* Controller transfer limit */
>> +#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
>>
>>  #ifdef DEBUG
>>  static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
>> @@ -114,6 +115,13 @@ struct i2c_cdns_bus {
>>   int id;
>>   unsigned int input_freq;
>>   struct cdns_i2c_regs __iomem *regs; /* register base */
>> +
>
> no reason.
>
>> + int hold_flag;
>> + u32 quirks;
>> +};
>> +
>> +struct cdns_i2c_platform_data {
>> + u32 quirks;
>>  };
>>
>>  /* Wait for an interrupt */
>> @@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, 
>> uint chip_addr,
>>  }
>>
>>  static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
>> *data,
>> -u32 len, bool next_is_read)
>> +u32 len)
>>  {
>>   u8 *cur_data = data;
>>
>>   struct cdns_i2c_regs *regs = i2c_bus->regs;
>>
>> - setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
>> - CDNS_I2C_CONTROL_HOLD);
>> + setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
>>
>> - /* if next is a read, we need to clear HOLD, doesn't work */
>> - if (next_is_read)
>> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>>
>
> two blank line after removing this code.

Whoops...
>
>>   clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
>>
>> @@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
>> *i2c_bus, u32 addr, u8 *data,
>>   }
>>
>>   /* All done... release the bus */
>> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>> + if (!i2c_bus->hold_flag)
>> + clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>> +
>>   /* Wait for the address and data to be sent */
>>   if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
>>   return -ETIMEDOUT;
>> @@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus 
>> *i2c_bus, u32 addr, u8 *data,
>>   struct cdns_i2c_regs *regs = i2c_bus->regs;
>>
>>   /* Check the hardware can handle the requested bytes */
>> - if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
>> + if ((len < 0))
>>   return -EINVAL;
>>
>>   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
>> @@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus 
>> *i2c_bus, u32 addr, u8 *data,
>>   *(cur_data++) = readl(>data);
>>   } while (readl(>transfer_size) != 0);
>>   /* All done... release the bus */
>> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>> + if (!i2c_bus->hold_flag)
>> + clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>>
>>  #ifdef DEBUG
>>   cdns_i2c_debug_status(regs);
>> @@ -322,19 +329,43 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
>> i2c_msg *msg,
>>int nmsgs)
>>  {
>>   struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
>> - int ret;
>> + int ret, count;
>> + bool hold_quirk;
>> +
>> +
>
> ditto.
>
>> + printf("i2c_xfer: %d messages\n", 

Re: [U-Boot] [PATCH] i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent

[Moritz Fischer]

Hi Michal,

On Mon, Jan 2, 2017 at 6:24 AM, Michal Simek <michal.si...@xilinx.com> wrote:
> On 29.12.2016 23:50, Moritz Fischer wrote:
>> For mux check if the parent is already a device of UCLASS_I2C and if yes
>> just use that. Otherwise see if someone specified an i2c-parent phandle.
>> This mimics the behavior found in the Kernel, as it removes the
>> requirement to explicitly specify a i2c-parent phandle.
>>
>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>> Cc: Heiko Schocher <h...@denx.de>
>> Cc: Bin Meng <bmeng...@gmail.com>
>> Cc: Simon Glass <s...@chromium.org>
>> Cc: Michal Simek <michal.si...@xilinx.com>
>> Cc: u-boot@lists.denx.de
>> ---
>>  drivers/i2c/muxes/i2c-mux-uclass.c | 9 +
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c 
>> b/drivers/i2c/muxes/i2c-mux-uclass.c
>> index 7a698b6..e01b773 100644
>> --- a/drivers/i2c/muxes/i2c-mux-uclass.c
>> +++ b/drivers/i2c/muxes/i2c-mux-uclass.c
>> @@ -86,6 +86,15 @@ static int i2c_mux_post_probe(struct udevice *mux)
>>   debug("%s: %s\n", __func__, mux->name);
>>   priv->selected = -1;
>>
>> + /* if parent is of i2c uclass already, we'll take that, otherwise
>> +  * look if we find an i2c-parent phandle */
>
> Incorrect comment style.

Yeah, wasn't flagged by checkpatch  will fix.
>
>> + if (UCLASS_I2C == device_get_uclass_id(mux->parent)) {
>> + priv->i2c_bus = dev_get_parent(mux);
>> + debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus,
>> +   priv->i2c_bus->name);
>> + return 0;
>> + }
>> +
>>   ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
>>  >i2c_bus);
>>   if (ret)
>>
>
> The part of this will be good to also handle
> req_seq for mux busses. But at least this should solved part of the
> problems.

I'm not sure I understand this comment.

Thanks for the review, will resubmit

Moritz
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[U-Boot] [PATCH] i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent

[Moritz Fischer]

For mux check if the parent is already a device of UCLASS_I2C and if yes
just use that. Otherwise see if someone specified an i2c-parent phandle.
This mimics the behavior found in the Kernel, as it removes the
requirement to explicitly specify a i2c-parent phandle.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Bin Meng <bmeng...@gmail.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
 drivers/i2c/muxes/i2c-mux-uclass.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c 
b/drivers/i2c/muxes/i2c-mux-uclass.c
index 7a698b6..e01b773 100644
--- a/drivers/i2c/muxes/i2c-mux-uclass.c
+++ b/drivers/i2c/muxes/i2c-mux-uclass.c
@@ -86,6 +86,15 @@ static int i2c_mux_post_probe(struct udevice *mux)
debug("%s: %s\n", __func__, mux->name);
priv->selected = -1;
 
+   /* if parent is of i2c uclass already, we'll take that, otherwise
+* look if we find an i2c-parent phandle */
+   if (UCLASS_I2C == device_get_uclass_id(mux->parent)) {
+   priv->i2c_bus = dev_get_parent(mux);
+   debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus,
+ priv->i2c_bus->name);
+   return 0;
+   }
+
ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
   >i2c_bus);
if (ret)
-- 
2.7.4

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[U-Boot] [PATCH 4/4] i2c: i2c-cdns: No need for dedicated probe function

[Moritz Fischer]

The generic probe code in dm works, so get rid of the leftover cruft.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 21 -
 1 file changed, 21 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 4a46dbf..cd5cce0 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -226,26 +226,6 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
return 0;
 }
 
-/* Probe to see if a chip is present. */
-static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
-   uint chip_flags)
-{
-   struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
-   struct cdns_i2c_regs *regs = i2c_bus->regs;
-
-   /* Attempt to read a byte */
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_RW);
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   writel(0xFF, >interrupt_status);
-   writel(chip_addr, >address);
-   writel(1, >transfer_size);
-
-   return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_NACK) &
-   CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
-}
-
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
   u32 len)
 {
@@ -453,7 +433,6 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 
 static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
-   .probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
 };
 
-- 
2.7.4

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[U-Boot] [PATCH 3/4] i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a quirk where if during a long read transfer
the transfer_size register will go to 0, the master will send a NACK to
the slave prematurely.
The way to work around this is to reprogram the transfer_size register
mid-transfer when the only the receive fifo is known full, i.e. the I2C
bus is known non-active.
The workaround is based on the implementation in the linux-kernel.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 121 -
 1 file changed, 89 insertions(+), 32 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 9a1b520..4a46dbf 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,6 +68,8 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
+
 #define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
@@ -247,15 +250,20 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
   u32 len)
 {
u8 *cur_data = data;
-
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
+   /* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
-
-
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
+   /* Check message size against FIFO depth, and set hold bus bit
+* if it is greater than FIFO depth */
+   if (len > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
+   /* Clear the interrupts in status register */
writel(0xFF, >interrupt_status);
+
writel(addr, >address);
 
while (len--) {
@@ -280,48 +288,98 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
return 0;
 }
 
+static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+{
+   return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+}
+
 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len)
+ u32 recv_count)
 {
-   u32 status;
-   u32 i = 0;
u8 *cur_data = data;
-
-   /* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
+   int curr_recv_count;
+   int updatetx, hold_quirk;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0))
+   if ((recv_count < 0))
return -EINVAL;
 
+   curr_recv_count = recv_count;
+
+   /* Check for the message size against the FIFO depth */
+   if (recv_count > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
 
+   if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+   curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+   writel(curr_recv_count, >transfer_size);
+   } else {
+   writel(recv_count, >transfer_size);
+   }
+
/* Start reading data */
writel(addr, >address);
-   writel(len, >transfer_size);
-
-   /* Wait for data */
-   do {
-   status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_DATA);
-   if (!status) {
-   /* Release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   return -ETIMEDOUT;
+
+   updatetx = recv_count > curr_recv_count;
+
+   hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
+
+   while (recv_count) {
+   while (readl(>status) & CDNS_I2C_STATUS_RXDV) {
+   if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+   !i2c_bus->hold_flag) {
+   clrbits_le32(>control,
+CDNS_I2C_CONTROL_HOLD);
+   }
+   *(cur_data)++ = readl(>data);
+   recv_count--;
+   curr_recv_count--;
+
+   if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+   break;
}
-   debug("Read %d bytes\n",
- len - readl(>transfer_size));
-   for (; i < len - readl(>transfer_size); i++)
-   *(

[U-Boot] [PATCH 2/4] i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

[Moritz Fischer]

Reorder the timeout loop such that we first check if the
condition is already true, and then call udelay() so if
the condition is already true, break early.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index c69e7e8..9a1b520 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -130,10 +130,10 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, 
u32 mask)
int timeout, int_status;
 
for (timeout = 0; timeout < 100; timeout++) {
-   udelay(100);
int_status = readl(_i2c->interrupt_status);
if (int_status & mask)
break;
+   udelay(100);
}
 
/* Clear interrupt status flags */
-- 
2.7.4

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[U-Boot] [PATCH 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a couple of issues, such as not supporting
repeated start conditions for read transfers.

So scan through the list of i2c messages for these conditions
and report an error if they are attempted.

This has been fixed for revision 1.4 of the IP, so only report the error
when the IP can really not do it.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Heiko Schocher <h...@denx.de>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 69 --
 1 file changed, 55 insertions(+), 14 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index f49f60b..c69e7e8 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -67,6 +67,7 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
@@ -114,6 +115,13 @@ struct i2c_cdns_bus {
int id;
unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
+
+   int hold_flag;
+   u32 quirks;
+};
+
+struct cdns_i2c_platform_data {
+   u32 quirks;
 };
 
 /* Wait for an interrupt */
@@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, uint 
chip_addr,
 }
 
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
-  u32 len, bool next_is_read)
+  u32 len)
 {
u8 *cur_data = data;
 
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_HOLD);
+   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
 
-   /* if next is a read, we need to clear HOLD, doesn't work */
-   if (next_is_read)
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
@@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
}
 
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
/* Wait for the address and data to be sent */
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
@@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
+   if ((len < 0))
return -EINVAL;
 
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
@@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
*(cur_data++) = readl(>data);
} while (readl(>transfer_size) != 0);
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
 #ifdef DEBUG
cdns_i2c_debug_status(regs);
@@ -322,19 +329,43 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
i2c_msg *msg,
 int nmsgs)
 {
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
-   int ret;
+   int ret, count;
+   bool hold_quirk;
+
+
+   printf("i2c_xfer: %d messages\n", nmsgs);
+   hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
+
+   if (nmsgs > 1) {
+   /*
+* This controller does not give completion interrupt after a
+* master receive message if HOLD bit is set (repeated start),
+* resulting in SW timeout. Hence, if a receive message is
+* followed by any other message, an error is returned
+* indicating that this sequence is not supported.
+*/
+   for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
+   if (msg[count].flags & I2C_M_RD) {
+   printf("Can't do repeated start after a receive 
message\n");
+   return -EOPNOTSUPP;
+   }
+   }
+
+   i2c_bus->hold_flag = 1;
+   setbits_le32(_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
+   } else {
+   i2c_bus->hold_flag = 0;
+   }
 
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
-   

Re: [U-Boot] [PATCH] ARM64: zynqmp: Fix i2c node's compatible string

[Moritz Fischer]

Hi Michal,

On Wed, Dec 21, 2016 at 11:35 PM, Michal Simek  wrote:

> compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";

I keep getting that wrong .. .damn ... :) Will resubmit.

> The same of course for u-boot where also p14 should be added to the driver.

Yeah, I realized that part after submitting...

Thanks
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[U-Boot] [PATCH 2/2] ARM64: zynqmp: Fix i2c node's compatible string

[Moritz Fischer]

The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core
which fixes some silicon bugs that needed software workarounds
in Version 1.0 that was used on Zynq systems.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: Heiko Schocher <h...@denx.de>
---
 arch/arm/dts/zynqmp.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index ab5c243..20c5efc 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -619,7 +619,7 @@
};
 
i2c0: i2c@ff02 {
-   compatible = "cdns,i2c-r1p10";
+   compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
status = "disabled";
interrupt-parent = <>;
interrupts = <0 17 4>;
@@ -630,7 +630,7 @@
};
 
i2c1: i2c@ff03 {
-   compatible = "cdns,i2c-r1p10";
+   compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
status = "disabled";
interrupt-parent = <>;
interrupts = <0 18 4>;
-- 
2.7.4

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[U-Boot] [PATCH 1/2] i2c: cdns: Add additional compatible string for r1p14 of the IP.

[Moritz Fischer]

Adding additional compatible string for version 1.4 of the IP block.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: Heiko Schocher <h...@denx.de>
---
 drivers/i2c/i2c-cdns.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index f49f60b..ef85a70 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -366,6 +366,7 @@ static const struct dm_i2c_ops cdns_i2c_ops = {
 
 static const struct udevice_id cdns_i2c_of_match[] = {
{ .compatible = "cdns,i2c-r1p10" },
+   { .compatible = "cdns,i2c-r1p14" },
{ /* end of table */ }
 };
 
-- 
2.7.4

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[U-Boot] [PATCH] ARM64: zynqmp: Fix i2c node's compatible string

[Moritz Fischer]

From: Moritz Fischer <m...@kernel.org>

The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core
which fixes some silicon bugs that needed software workarounds
in Version 1.0 that was used on Zynq systems.

Signed-off-by: Moritz Fischer <m...@kernel.org>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: Sören Brinkmann <soren.brinkm...@xilinx.com>
Cc: U-Boot List <u-boot@lists.denx.de>
Cc: Rob Herring <robh...@kernel.org>
---

Hi Michal,

I think this is a slip up and should be r1p14 for
Ultrascale ZynqMP. drivers/i2c/i2c-cadence.c already uses this.
I Cc'd the u-boot list, because the same change would be required there.

Cheers,

Moritz

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi 
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 68a90833..a5a5f91 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -175,7 +175,7 @@
};
 
i2c0: i2c@ff02 {
-   compatible = "cdns,i2c-r1p10";
+   compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <>;
interrupts = <0 17 4>;
@@ -185,7 +185,7 @@
};
 
i2c1: i2c@ff03 {
-   compatible = "cdns,i2c-r1p10";
+   compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <>;
interrupts = <0 18 4>;
-- 
2.4.11

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Re: [U-Boot] [PATCH 2/4] ARM: zynq: Remove spi-max-frequency

[Moritz Fischer]

Hi Michal,

On Fri, Dec 16, 2016 at 5:38 AM, Michal Simek  wrote:
> spi-max-frequency for spi bus depends on devices which are
> connected to it. Remove this parameter from dtsi file.
>
> Signed-off-by: Michal Simek 
> ---
>
>  arch/arm/dts/zynq-7000.dtsi | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
> index 668f54ec219d..fa9ee276cb59 100644
> --- a/arch/arm/dts/zynq-7000.dtsi
> +++ b/arch/arm/dts/zynq-7000.dtsi
> @@ -177,7 +177,6 @@
> interrupts = <0 26 4>;
> clocks = < 25>, < 34>;
> clock-names = "ref_clk", "pclk";
> -   spi-max-frequency = <16700>;
> #address-cells = <1>;
> #size-cells = <0>;
> };
> @@ -190,7 +189,6 @@
> interrupts = <0 49 4>;
> clocks = < 26>, < 35>;
> clock-names = "ref_clk", "pclk";
> -   spi-max-frequency = <16700>;
> #address-cells = <1>;
> #size-cells = <0>;
> };
> --
> 1.9.1
>

While I agree with the patch, doesn't the drivers/spi/zynq_spi.c in u-boot
(wrongly) use this to determine it's peripheral clock speed?


plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  25000);


and later in zynq_spi_set_speed() to calculate divisors?

Cheers,

Moritz
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Re: [U-Boot] [PATCH] zynq: spi: Honour the activation / deactivation delay

[Moritz Fischer]

Michal,

On Wed, Dec 14, 2016 at 11:23 PM, Michal Simek <michal.si...@xilinx.com> wrote:
> On 14.12.2016 20:13, Moritz Fischer wrote:
>> Whoops,
>>
>> On Thu, Dec 8, 2016 at 12:11 PM, Moritz Fischer
>> <moritz.fisc...@ettus.com> wrote:
>>> This is not currently implemented. Add support for this so that the
>>> Chrome OS EC can be used reliably.
>>>
>>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>>> Cc: Jagan Teki <ja...@openedev.com>
>>> Cc: Simon Glass <s...@chromium.org>
>>> Cc: u-boot@lists.denx.de
>> Cc: Michal Simek <michal.si...@xilinx.com>
>
> Jagan is the guy who should apply this.

Ok. Can you re-delegate in patchwork? Not entirely sure how workflow
in u-boot is :)

> Anyway are you running chrome OS on Zynq or ZynqMP?

The EC (Embedded Controller) is a MCU running firmware hooked up over SPI.
I do have a board with a Zynq and a Chromium EC and it only works with
this patch.

Thanks,

Moritz
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Re: [U-Boot] [PATCH] zynq: spi: Honour the activation / deactivation delay

[Moritz Fischer]

Whoops,

On Thu, Dec 8, 2016 at 12:11 PM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> This is not currently implemented. Add support for this so that the
> Chrome OS EC can be used reliably.
>
> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
> Cc: Jagan Teki <ja...@openedev.com>
> Cc: Simon Glass <s...@chromium.org>
> Cc: u-boot@lists.denx.de
Cc: Michal Simek <michal.si...@xilinx.com>

> ---
>  drivers/spi/zynq_spi.c | 24 
>  1 file changed, 24 insertions(+)
>
> diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
> index 15ca271..5e7954c 100644
> --- a/drivers/spi/zynq_spi.c
> +++ b/drivers/spi/zynq_spi.c
> @@ -56,6 +56,8 @@ struct zynq_spi_platdata {
> struct zynq_spi_regs *regs;
> u32 frequency;  /* input frequency */
> u32 speed_hz;
> +   uint deactivate_delay_us;   /* Delay to wait after deactivate */
> +   uint activate_delay_us; /* Delay to wait after activate */
>  };
>
>  /* zynq spi priv */
> @@ -63,6 +65,7 @@ struct zynq_spi_priv {
> struct zynq_spi_regs *regs;
> u8 cs;
> u8 mode;
> +   ulong last_transaction_us;  /* Time of last transaction end */
> u8 fifo_depth;
> u32 freq;   /* required frequency */
>  };
> @@ -78,6 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
> /* FIXME: Use 250MHz as a suitable default */
> plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
> 25000);
> +   plat->deactivate_delay_us = fdtdec_get_int(blob, node,
> +   "spi-deactivate-delay", 0);
> +   plat->activate_delay_us = fdtdec_get_int(blob, node,
> +"spi-activate-delay", 0);
> plat->speed_hz = plat->frequency / 2;
>
> debug("%s: regs=%p max-frequency=%d\n", __func__,
> @@ -133,10 +140,19 @@ static int zynq_spi_probe(struct udevice *bus)
>  static void spi_cs_activate(struct udevice *dev)
>  {
> struct udevice *bus = dev->parent;
> +   struct zynq_spi_platdata *plat = bus->platdata;
> struct zynq_spi_priv *priv = dev_get_priv(bus);
> struct zynq_spi_regs *regs = priv->regs;
> u32 cr;
>
> +   /* If it's too soon to do another transaction, wait */
> +   if (plat->deactivate_delay_us && priv->last_transaction_us) {
> +   ulong delay_us; /* The delay completed so far */
> +   delay_us = timer_get_us() - priv->last_transaction_us;
> +   if (delay_us < plat->deactivate_delay_us)
> +   udelay(plat->deactivate_delay_us - delay_us);
> +   }
> +
> clrbits_le32(>cr, ZYNQ_SPI_CR_CS_MASK);
> cr = readl(>cr);
> /*
> @@ -147,15 +163,23 @@ static void spi_cs_activate(struct udevice *dev)
>  */
> cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & 
> ZYNQ_SPI_CR_CS_MASK;
> writel(cr, >cr);
> +
> +   if (plat->activate_delay_us)
> +   udelay(plat->activate_delay_us);
>  }
>
>  static void spi_cs_deactivate(struct udevice *dev)
>  {
> struct udevice *bus = dev->parent;
> +   struct zynq_spi_platdata *plat = bus->platdata;
> struct zynq_spi_priv *priv = dev_get_priv(bus);
> struct zynq_spi_regs *regs = priv->regs;
>
> setbits_le32(>cr, ZYNQ_SPI_CR_CS_MASK);
> +
> +   /* Remember time of this transaction so we can honour the bus delay */
> +   if (plat->deactivate_delay_us)
> +   priv->last_transaction_us = timer_get_us();
>  }
>
>  static int zynq_spi_claim_bus(struct udevice *dev)
> --
> 2.7.4
>

Thanks,

Moritz
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[U-Boot] [PATCH v2] ARM: dt: zynq: Add labels to cpu nodes to allow overriding OPPs.

[Moritz Fischer]

By adding labels to the cpu nodes in the dtsi, a dts that
includes it can change the OPPs by referencing the cpu0
through the label.

[Based on linux (400b6a0cbef55d1ae32808eaa1ef1c28820bf6ac)]
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---

Ok, since I fatfingered v1 ... this one with right subject
prefix, and only one patch in 'series'.

Changes from v1: None

Sorry 'bout the noise,

Moritz

---
 arch/arm/dts/zynq-7000.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 6df0329..668f54e 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -16,7 +16,7 @@
#address-cells = <1>;
#size-cells = <0>;
 
-   cpu@0 {
+   cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
@@ -30,7 +30,7 @@
>;
};
 
-   cpu@1 {
+   cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
-- 
2.7.4

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[U-Boot] [PATCH 01/12] ARM: dt: zynq: Add labels to cpu nodes to allow overriding OPPs.

[Moritz Fischer]

By adding labels to the cpu nodes in the dtsi, a dts that
includes it can change the OPPs by referencing the cpu0
through the label.

[Based on linux (400b6a0cbef55d1ae32808eaa1ef1c28820bf6ac)]
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: u-boot@lists.denx.de
---

Hi Michal,

I thought I've seen this patch on the list at one point,
but seems like it never made it to the tree.
Can you please take this? I have a sg != 1 device running
at 800 MHz and this will allow me to reuse the same dt for
linux and u-boot.

Cheers,
Moritz

---
 arch/arm/dts/zynq-7000.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 6df0329..668f54e 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -16,7 +16,7 @@
#address-cells = <1>;
#size-cells = <0>;
 
-   cpu@0 {
+   cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
@@ -30,7 +30,7 @@
>;
};
 
-   cpu@1 {
+   cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
-- 
2.7.4

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[U-Boot] [PATCH] zynq: spi: Honour the activation / deactivation delay

[Moritz Fischer]

This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Jagan Teki <ja...@openedev.com>
Cc: Simon Glass <s...@chromium.org>
Cc: u-boot@lists.denx.de
---
 drivers/spi/zynq_spi.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 15ca271..5e7954c 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -56,6 +56,8 @@ struct zynq_spi_platdata {
struct zynq_spi_regs *regs;
u32 frequency;  /* input frequency */
u32 speed_hz;
+   uint deactivate_delay_us;   /* Delay to wait after deactivate */
+   uint activate_delay_us; /* Delay to wait after activate */
 };
 
 /* zynq spi priv */
@@ -63,6 +65,7 @@ struct zynq_spi_priv {
struct zynq_spi_regs *regs;
u8 cs;
u8 mode;
+   ulong last_transaction_us;  /* Time of last transaction end */
u8 fifo_depth;
u32 freq;   /* required frequency */
 };
@@ -78,6 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
/* FIXME: Use 250MHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
25000);
+   plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+   "spi-deactivate-delay", 0);
+   plat->activate_delay_us = fdtdec_get_int(blob, node,
+"spi-activate-delay", 0);
plat->speed_hz = plat->frequency / 2;
 
debug("%s: regs=%p max-frequency=%d\n", __func__,
@@ -133,10 +140,19 @@ static int zynq_spi_probe(struct udevice *bus)
 static void spi_cs_activate(struct udevice *dev)
 {
struct udevice *bus = dev->parent;
+   struct zynq_spi_platdata *plat = bus->platdata;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
u32 cr;
 
+   /* If it's too soon to do another transaction, wait */
+   if (plat->deactivate_delay_us && priv->last_transaction_us) {
+   ulong delay_us; /* The delay completed so far */
+   delay_us = timer_get_us() - priv->last_transaction_us;
+   if (delay_us < plat->deactivate_delay_us)
+   udelay(plat->deactivate_delay_us - delay_us);
+   }
+
clrbits_le32(>cr, ZYNQ_SPI_CR_CS_MASK);
cr = readl(>cr);
/*
@@ -147,15 +163,23 @@ static void spi_cs_activate(struct udevice *dev)
 */
cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
writel(cr, >cr);
+
+   if (plat->activate_delay_us)
+   udelay(plat->activate_delay_us);
 }
 
 static void spi_cs_deactivate(struct udevice *dev)
 {
struct udevice *bus = dev->parent;
+   struct zynq_spi_platdata *plat = bus->platdata;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
 
setbits_le32(>cr, ZYNQ_SPI_CR_CS_MASK);
+
+   /* Remember time of this transaction so we can honour the bus delay */
+   if (plat->deactivate_delay_us)
+   priv->last_transaction_us = timer_get_us();
 }
 
 static int zynq_spi_claim_bus(struct udevice *dev)
-- 
2.7.4

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Re: [U-Boot] [PATCH RESEND 6/9] eeprom: Add DS2431 support

[Moritz Fischer]

Hi Maxime,

On Tue, Nov 8, 2016 at 2:19 AM, Maxime Ripard
 wrote:
> Add a driver for the Maxim DS2431 1-Wire EEPROM
>
> Signed-off-by: Maxime Ripard 
> ---
>  drivers/eeprom/Kconfig  |  6 ++
>  drivers/eeprom/Makefile |  1 +
>  drivers/eeprom/ds2431.c | 38 ++
>  3 files changed, 45 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/eeprom/ds2431.c
>
> diff --git a/drivers/eeprom/Kconfig b/drivers/eeprom/Kconfig
> index 8dc597a8d894..98bbd67ba579 100644
> --- a/drivers/eeprom/Kconfig
> +++ b/drivers/eeprom/Kconfig
> @@ -12,6 +12,12 @@ config EEPROM
>
>  if EEPROM
>
> +config EEPROM_DS2431
> +   bool "Enable Maxim DS2431 EEPROM support"
> +   depends on W1
> +   help
> + Maxim DS2431 1-Wire EEPROM support
> +
>  endif
>
>  endmenu
> diff --git a/drivers/eeprom/Makefile b/drivers/eeprom/Makefile
> index 147dba5ec4b8..93dae0bf5d6d 100644
> --- a/drivers/eeprom/Makefile
> +++ b/drivers/eeprom/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_EEPROM) += eeprom-uclass.o
>
> +obj-$(CONFIG_EEPROM_DS2431) += ds2431.o
> diff --git a/drivers/eeprom/ds2431.c b/drivers/eeprom/ds2431.c
> new file mode 100644
> index ..84c1a126c339
> --- /dev/null
> +++ b/drivers/eeprom/ds2431.c
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright (c) 2015 Free Electrons
> + * Copyright (c) 2015 NextThing Co
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define W1_F2D_READ_EEPROM 0xf0
> +
> +static int ds2431_read_buf(struct udevice *dev, unsigned offset,
> +  u8 *buf, unsigned count)
> +{
> +   w1_reset_select(dev);
> +
> +   w1_write_byte(dev, W1_F2D_READ_EEPROM);
> +   w1_write_byte(dev, offset & 0xff);
> +   w1_write_byte(dev, offset >> 8);
> +
> +   return w1_read_buf(dev, buf, count);
> +}
> +
> +static const struct eeprom_ops ds2431_ops = {
> +   .read_buf   = ds2431_read_buf,
> +};
> +
> +U_BOOT_DRIVER(ds2431) = {
> +   .name   = "ds2431",
> +   .id = UCLASS_EEPROM,
> +   .ops= _ops,

Do you want to add a .flags = DM_UC_FLAG_SEQ_ALIAS here?

> +};
> +
> +U_BOOT_W1_DEVICE(ds2431, W1_FAMILY_DS2431);
> --
> git-series 0.8.11
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Cheers,

Moritz
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Re: [U-Boot] [PATCH RESEND 5/9] EEPROM: Add an EEPROM uclass

[Moritz Fischer]

Hi Maxime,

On Fri, Nov 11, 2016 at 8:17 AM, Simon Glass  wrote:
> Hi Maxime,
>
> On 8 November 2016 at 03:19, Maxime Ripard
>  wrote:
>> We might want to access data stored onto EEPROMs. Create a framework to
>> provide a consistent API.
>
> We have UCLASS_I2C_EEPROM. Can we unify these? If not, please add a
> sandbox driver and test.

I've been working on something very similar (the API looks the same obviously,
since the ops are pretty trivial, modulo function names)
In my opinion it should be working as follows:

UCLASS_EEPROM
  \... I2C_EEPROM
  \SPI_EEPROM (AT25)

I also have some code to make the CMD_EEPROM stuff work, I'll submit a
follow up patch,
once we agreed on how the UCLASS_EEPROM looks like.

Cheers,

Moritz
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[U-Boot] [PATCH v2] cmd: crosec: Move cros_ec_decode_region helper to cmd/cros_ec.c

[Moritz Fischer]

The cros_ec_decode_region() function is only used in combination
with the crosec cmds. Move the function to the correct place.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Masahiro Yamada <yamada.masah...@socionext.com>
Cc: u-boot@lists.denx.de
---

Changes from v1:

* make cros_ec_decode_region static
* move over the comments
* fixed commit message s/crosec/cros_ec/g

---
 cmd/cros_ec.c  | 23 +++
 drivers/misc/cros_ec.c | 16 
 include/cros_ec.h  |  9 -
 3 files changed, 23 insertions(+), 25 deletions(-)

diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c
index abf11f0..9d42f87 100644
--- a/cmd/cros_ec.c
+++ b/cmd/cros_ec.c
@@ -20,6 +20,29 @@ static const char * const ec_current_image_name[] = 
{"unknown", "RO", "RW"};
 DECLARE_GLOBAL_DATA_PTR;
 
 /**
+ * Decode a flash region parameter
+ *
+ * @param argc Number of params remaining
+ * @param argv List of remaining parameters
+ * @return flash region (EC_FLASH_REGION_...) or -1 on error
+ */
+static int cros_ec_decode_region(int argc, char * const argv[])
+{
+   if (argc > 0) {
+   if (0 == strcmp(*argv, "rw"))
+   return EC_FLASH_REGION_RW;
+   else if (0 == strcmp(*argv, "ro"))
+   return EC_FLASH_REGION_RO;
+
+   debug("%s: Invalid region '%s'\n", __func__, *argv);
+   } else {
+   debug("%s: Missing region parameter\n", __func__);
+   }
+
+   return -1;
+}
+
+/**
  * Perform a flash read or write command
  *
  * @param dev  CROS-EC device to read/write
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 8073730..759bb46 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1024,22 +1024,6 @@ int cros_ec_register(struct udevice *dev)
return 0;
 }
 
-int cros_ec_decode_region(int argc, char * const argv[])
-{
-   if (argc > 0) {
-   if (0 == strcmp(*argv, "rw"))
-   return EC_FLASH_REGION_RW;
-   else if (0 == strcmp(*argv, "ro"))
-   return EC_FLASH_REGION_RO;
-
-   debug("%s: Invalid region '%s'\n", __func__, *argv);
-   } else {
-   debug("%s: Missing region parameter\n", __func__);
-   }
-
-   return -1;
-}
-
 int cros_ec_decode_ec_flash(const void *blob, int node,
struct fdt_cros_ec *config)
 {
diff --git a/include/cros_ec.h b/include/cros_ec.h
index ec7517c..0271f2b 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -250,15 +250,6 @@ void cros_ec_dump_data(const char *name, int cmd, const 
uint8_t *data, int len);
  */
 int cros_ec_calc_checksum(const uint8_t *data, int size);
 
-/**
- * Decode a flash region parameter
- *
- * @param argc Number of params remaining
- * @param argv List of remaining parameters
- * @return flash region (EC_FLASH_REGION_...) or -1 on error
- */
-int cros_ec_decode_region(int argc, char * const argv[]);
-
 int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t offset,
uint32_t size);
 
-- 
2.10.0

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[U-Boot] [PATCH] cmd: crosec: Move crosec_decode_region helper to cmd/cros_ec.c

[Moritz Fischer]

The cros_ec_decode_region() function is only used in combination
with the crosec cmds. Move the function to the correct place.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Masahiro Yamada <yamada.masah...@socionext.com>
Cc: u-boot@lists.denx.de
---
 cmd/cros_ec.c  | 16 
 drivers/misc/cros_ec.c | 16 
 include/cros_ec.h  |  9 -
 3 files changed, 16 insertions(+), 25 deletions(-)

diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c
index abf11f0..3a45149 100644
--- a/cmd/cros_ec.c
+++ b/cmd/cros_ec.c
@@ -19,6 +19,22 @@ static const char * const ec_current_image_name[] = 
{"unknown", "RO", "RW"};
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int cros_ec_decode_region(int argc, char * const argv[])
+{
+   if (argc > 0) {
+   if (0 == strcmp(*argv, "rw"))
+   return EC_FLASH_REGION_RW;
+   else if (0 == strcmp(*argv, "ro"))
+   return EC_FLASH_REGION_RO;
+
+   debug("%s: Invalid region '%s'\n", __func__, *argv);
+   } else {
+   debug("%s: Missing region parameter\n", __func__);
+   }
+
+   return -1;
+}
+
 /**
  * Perform a flash read or write command
  *
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 9159498..cf851ff 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1070,22 +1070,6 @@ int cros_ec_register(struct udevice *dev)
return 0;
 }
 
-int cros_ec_decode_region(int argc, char * const argv[])
-{
-   if (argc > 0) {
-   if (0 == strcmp(*argv, "rw"))
-   return EC_FLASH_REGION_RW;
-   else if (0 == strcmp(*argv, "ro"))
-   return EC_FLASH_REGION_RO;
-
-   debug("%s: Invalid region '%s'\n", __func__, *argv);
-   } else {
-   debug("%s: Missing region parameter\n", __func__);
-   }
-
-   return -1;
-}
-
 int cros_ec_decode_ec_flash(const void *blob, int node,
struct fdt_cros_ec *config)
 {
diff --git a/include/cros_ec.h b/include/cros_ec.h
index f280c1d..26b4680 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -252,15 +252,6 @@ void cros_ec_dump_data(const char *name, int cmd, const 
uint8_t *data, int len);
  */
 int cros_ec_calc_checksum(const uint8_t *data, int size);
 
-/**
- * Decode a flash region parameter
- *
- * @param argc Number of params remaining
- * @param argv List of remaining parameters
- * @return flash region (EC_FLASH_REGION_...) or -1 on error
- */
-int cros_ec_decode_region(int argc, char * const argv[]);
-
 int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t offset,
uint32_t size);
 
-- 
2.7.4

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Re: [U-Boot] [PATCH] ARM: zynq: Extend picozed board support

[Moritz Fischer]

Hi Oscar,

On Mon, Oct 17, 2016 at 5:33 PM, Oscar Gomez Fuente
 wrote:
> Ok Michal,
>
> Then you're suggesting change the zynq-picozed.dts file to:

If you're planning to include this into others, make it a .dtsi file.

>
> diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts
> index 3408df8..d8ed298 100644
> --- a/arch/arm/dts/zynq-picozed.dts
> +++ b/arch/arm/dts/zynq-picozed.dts
> @@ -14,6 +14,8 @@
>
> aliases {
> serial0 = 
> +   spi0 = 
> +   ethernet0 = 
> };
>
> memory {
> @@ -26,3 +28,18 @@
> u-boot,dm-pre-reloc;
> status = "okay";
>  };
> +
> + {
> +   u-boot,dm-pre-reloc;
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +   phy-mode = "rgmii-id";
> +   phy-handle = <_phy>;
> +
> +   ethernet_phy: ethernet-phy@0 {
> +   reg = <0>;
> +   };
> +};
>
> And add a new dts file with the configuration of the PizoZed FMC Carrier V2
> (in this case V2. Avnet has two PicoZed FMC carriers V1 and V2). For
> example: zynq-picozed-fmc-v2.dts
>
> *
>  * Avnet PicoZed FMC carrier V2 DTS
>  *
>  * Copyright (C) 2015 Xilinx, Inc.
>  *
>  * SPDX-License-Identifier: GPL-2.0+
>  */
> /dts-v1/;
> #include "zynq-picozed.dts"

should be a .dtsi file then.
>
> / {
> compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000";
>
> aliases {
> mmc0 = 
> };
> };
>
>  {
> u-boot,dm-pre-reloc;
> status = "okay";
> };
>
> Do you think the is the best way?
>
>
> Best regards.
>
> Oscar Gomez Fuente
>
> On 17 October 2016 at 16:36, Michal Simek  wrote:
>
>> On 17.10.2016 16:03, Oscar Gomez Fuente wrote:
>> > Hi everyone,
>> >
>> > Sorry for the errors, I know is a very simple patch but it's my first
>> time.
>> >
>> > 
>> --
>> >> Add missing DT nodes.
>> >>
>> >> Signed-off-by: Oscar Gomez Fuente 
>> >> ---
>> >>  arch/arm/dts/zynq-picozed.dts | 20 
>> >>  1 file changed, 20 insertions(+)
>> >>
>> >> diff --git a/arch/arm/dts/zynq-picozed.dts
>> b/arch/arm/dts/zynq-picozed.dts
>> >> index 3408df8..5f703a2 100644
>> >> --- a/arch/arm/dts/zynq-picozed.dts
>> >> +++ b/arch/arm/dts/zynq-picozed.dts
>> >> @@ -26,3 +26,23 @@
>> >>   u-boot,dm-pre-reloc;
>> >>   status = "okay";
>> >>  };
>> >> +
>> >
>> > please also extended aliases list.
>> > 
>> --
>> > -> Ok, Understood.
>> >
>> > 
>> --
>> >> + {
>> >> + status = "okay";
>> >> + phy-mode = "rgmii-id";
>> >> + phy-handle = <_phy>;
>> >> +
>> >> + ethernet_phy: ethernet-phy@0 {
>> >> + reg = <0>;
>> >
>> > I expect that this is on board 88e1512
>> > 
>> --
>> > -> Yes, this is on board 88e1512. Do I have to modify anything? I think
>> > that's good, isn't it?
>>
>> nope.
>>
>> >
>> > 
>> --
>> >> + };
>> >> +};
>> >> +
>> >> + {
>> >> + u-boot,dm-pre-reloc;
>> >> + status = "okay";
>> >> + };
>> >
>> > wrong indentation here.
>> > 
>> --
>> > -> Ok, sorry.
>> >
>> > 
>> --
>> >> +
>> >> + {
>> >
>> > is this sd0 or sd1 hard IP? I expect that this is emmc right?
>> > 
>> --
>> > -> sdhci0 is sd0 IP, the Sd Card on the PicoZed FMC Carrier.
>>
>>
>> Then this shouldn't be the part of this file. picozed is SOM and you
>> should describe all stuff which are just on this module.
>> If you want to support Picozed with any carrier board you should
>> describe it separately. The best carrier and include picozed dts.
>>
>>
>> >
>> >> + u-boot,dm-pre-reloc;
>> >> + status = "okay";
>> >> +};
>> >>
>> >
>> > If everything is ok now, I'll send the patch to mainline mailing list
>> > instead of xilinx one.
>>
>> I have changed emails.
>>
>> >
>> >
>> > Another question: Do you know if there is any perl script to check dts
>> > files before sending it? I've run the ./scripts/checkpatch.pl to check
>> the
>> > arch/arm/dts/zynq-picozed.dts file and I didn't get any error.
>>
>> checkpatch is not designed to parse DTS files and I am not sure if there
>> is any parser.
>>
>> Thanks,
>> Michal
>>
> ___
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Thanks,

Moritz
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Re: [U-Boot] [PATCH 2/3] ARM: zynq(mp): remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT defines

[Moritz Fischer]

On Fri, Oct 14, 2016 at 9:29 AM, Michal Simek <michal.si...@xilinx.com> wrote:
> On 13.10.2016 17:40, Masahiro Yamada wrote:
>> ARCH_ZYNQ(MP) selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT
>> is not used.
>>
>> Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
>> ---
>>
>>  include/configs/xilinx_zynqmp.h | 1 -
>>  include/configs/zynq-common.h   | 1 -
>>  2 files changed, 2 deletions(-)
>>
>> diff --git a/include/configs/xilinx_zynqmp.h 
>> b/include/configs/xilinx_zynqmp.h
>> index adc42cf..c8e1ffa 100644
>> --- a/include/configs/xilinx_zynqmp.h
>> +++ b/include/configs/xilinx_zynqmp.h
>> @@ -110,7 +110,6 @@
>>  #define CONFIG_SYS_LOAD_ADDR 0x800
>>
>>  #if defined(CONFIG_ZYNQMP_USB)
>> -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>>  #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS  2
>>  #define CONFIG_USB_XHCI_ZYNQMP
>>
>> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
>> index 0118fd2..7cca83f 100644
>> --- a/include/configs/zynq-common.h
>> +++ b/include/configs/zynq-common.h
>> @@ -86,7 +86,6 @@
>>
>>  #ifdef CONFIG_USB_EHCI_ZYNQ
>>  # define CONFIG_EHCI_IS_TDI
>> -# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>>
>>  # define CONFIG_SYS_DFU_DATA_BUF_SIZE0x60
>>  # define DFU_DEFAULT_POLL_TIMEOUT300
>>
>
> Acked-by: Michal Simek <michal.si...@xilinx.com>
Acked-by: Moritz Fischer <moritz.fisc...@ettus.com>

Cheers,

Moritz
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[U-Boot] [PATCH v2] cmd: cros_ec: Move crosec commands to cmd subdirectory

[Moritz Fischer]

Move crosec commands from drivers/misc/cros_ec.c to
cmd/cros_ec.c

Acked-by: Simon Glass <s...@chromium.org>
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Heiko Schocher <h...@denx.de>
Cc: Bin Meng <bmeng...@gmail.com>
Cc: Miao Yan <yanmiaob...@gmail.com>
Cc: Masahiro Yamada <yamada.masah...@socionext.com>
Cc: Stefan Roese <s...@denx.de>
Cc: Przemyslaw Marczak <p.marc...@samsung.com>
Cc: Maxime Ripard <maxime.rip...@free-electrons.com>
Cc: Nishanth Menon <n...@ti.com>
Cc: u-boot@lists.denx.de

---
Changes from v1:

- Default to build CMD_CROS_EC in when CROS_EC is activated
- Get rid of leftover const ec_current_image_name[] artifact from
  moving stuff to separate file
- Added Simon's Acked-By:

---
 cmd/Kconfig|  13 ++
 cmd/Makefile   |   1 +
 cmd/cros_ec.c  | 366 +
 drivers/misc/cros_ec.c | 351 ---
 include/cros_ec.h  |  11 ++
 5 files changed, 391 insertions(+), 351 deletions(-)
 create mode 100644 cmd/cros_ec.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 86554ea..e339d86 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -677,6 +677,19 @@ config CMD_TPM_TEST
 
 endmenu
 
+menu "Firmware commands"
+config CMD_CROS_EC
+   bool "Enable crosec command"
+   depends on CROS_EC
+   default y
+   help
+ Enable command-line access to the Chrome OS EC (Embedded
+ Controller). This provides the 'crosec' command which has
+ a number of sub-commands for performing EC tasks such as
+ updating its flash, accessing a small saved context area
+ and talking to the I2C bus behind the EC (if there is one).
+endmenu
+
 menu "Filesystem commands"
 config CMD_EXT2
bool "ext2 command support"
diff --git a/cmd/Makefile b/cmd/Makefile
index 81b98ee..9c9a9d1 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -128,6 +128,7 @@ obj-$(CONFIG_CMD_TRACE) += trace.o
 obj-$(CONFIG_HUSH_PARSER) += test.o
 obj-$(CONFIG_CMD_TPM) += tpm.o
 obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
+obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o
 obj-$(CONFIG_CMD_TSI148) += tsi148.o
 obj-$(CONFIG_CMD_UBI) += ubi.o
 obj-$(CONFIG_CMD_UBIFS) += ubifs.o
diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c
new file mode 100644
index 000..543dd28
--- /dev/null
+++ b/cmd/cros_ec.c
@@ -0,0 +1,366 @@
+/*
+ * Chromium OS cros_ec driver
+ *
+ * Copyright (c) 2016 The Chromium OS Authors.
+ * Copyright (c) 2016 National Instruments Corp
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Note: depends on enum ec_current_image */
+static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Perform a flash read or write command
+ *
+ * @param dev  CROS-EC device to read/write
+ * @param is_write 1 do to a write, 0 to do a read
+ * @param argc Number of arguments
+ * @param argv Arguments (2 is region, 3 is address)
+ * @return 0 for ok, 1 for a usage error or -ve for ec command error
+ * (negative EC_RES_...)
+ */
+static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc,
+char * const argv[])
+{
+   uint32_t offset, size = -1U, region_size;
+   unsigned long addr;
+   char *endp;
+   int region;
+   int ret;
+
+   region = cros_ec_decode_region(argc - 2, argv + 2);
+   if (region == -1)
+   return 1;
+   if (argc < 4)
+   return 1;
+   addr = simple_strtoul(argv[3], , 16);
+   if (*argv[3] == 0 || *endp != 0)
+   return 1;
+   if (argc > 4) {
+   size = simple_strtoul(argv[4], , 16);
+   if (*argv[4] == 0 || *endp != 0)
+   return 1;
+   }
+
+   ret = cros_ec_flash_offset(dev, region, , _size);
+   if (ret) {
+   debug("%s: Could not read region info\n", __func__);
+   return ret;
+   }
+   if (size == -1U)
+   size = region_size;
+
+   ret = is_write ?
+   cros_ec_flash_write(dev, (uint8_t *)addr, offset, size) :
+   cros_ec_flash_read(dev, (uint8_t *)addr, offset, size);
+   if (ret) {
+   debug("%s: Could not %s region\n", __func__,
+ is_write ? "write" : "read");
+   return ret;
+   }
+
+   return 0;
+}
+
+static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
+{
+   struct cros_ec_dev *dev;
+   struct udevice *udev;
+   const char *cmd;
+   int ret = 0;
+
+   if (argc < 2)
+   return CMD_RET_USAGE;
+
+   cmd = argv[1];
+   if (0 == strcmp("

Re: [U-Boot] [PATCH] cmd: cros_ec: Move crosec commands to cmd subdirectory

[Moritz Fischer]

Hi Simon,

On Tue, Oct 4, 2016 at 8:37 AM, Simon Glass  wrote:

>> +menu "Firmware commands"
>> +config CMD_CROS_EC
>> +   bool "Enable crosec command"
>> +   depends on CROS_EC
>
> Can this be enabled by default if CROS_EC is enabled? At present I
> think your change will disable it.

Will send a v2 in a bit. Thanks for the review

Moritz
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[U-Boot] [PATCH] cmd: cros_ec: Move crosec commands to cmd subdirectory

[Moritz Fischer]

Move crosec commands from drivers/misc/cros_ec.c to
cmd/cros_ec.c

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Heiko Schocher <h...@denx.de>
Cc: Bin Meng <bmeng...@gmail.com>
Cc: Miao Yan <yanmiaob...@gmail.com>
Cc: Masahiro Yamada <yamada.masah...@socionext.com>
Cc: Stefan Roese <s...@denx.de>
Cc: Przemyslaw Marczak <p.marc...@samsung.com>
Cc: Maxime Ripard <maxime.rip...@free-electrons.com>
Cc: Nishanth Menon <n...@ti.com>
Cc: u-boot@lists.denx.de
---
 cmd/Kconfig|  12 ++
 cmd/Makefile   |   1 +
 cmd/cros_ec.c  | 366 +
 drivers/misc/cros_ec.c | 348 --
 include/cros_ec.h  |  11 ++
 5 files changed, 390 insertions(+), 348 deletions(-)
 create mode 100644 cmd/cros_ec.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 86554ea..141281f 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -677,6 +677,18 @@ config CMD_TPM_TEST
 
 endmenu
 
+menu "Firmware commands"
+config CMD_CROS_EC
+   bool "Enable crosec command"
+   depends on CROS_EC
+   help
+ Enable command-line access to the Chrome OS EC (Embedded
+ Controller). This provides the 'crosec' command which has
+ a number of sub-commands for performing EC tasks such as
+ updating its flash, accessing a small saved context area
+ and talking to the I2C bus behind the EC (if there is one).
+endmenu
+
 menu "Filesystem commands"
 config CMD_EXT2
bool "ext2 command support"
diff --git a/cmd/Makefile b/cmd/Makefile
index 81b98ee..9c9a9d1 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -128,6 +128,7 @@ obj-$(CONFIG_CMD_TRACE) += trace.o
 obj-$(CONFIG_HUSH_PARSER) += test.o
 obj-$(CONFIG_CMD_TPM) += tpm.o
 obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
+obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o
 obj-$(CONFIG_CMD_TSI148) += tsi148.o
 obj-$(CONFIG_CMD_UBI) += ubi.o
 obj-$(CONFIG_CMD_UBIFS) += ubifs.o
diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c
new file mode 100644
index 000..543dd28
--- /dev/null
+++ b/cmd/cros_ec.c
@@ -0,0 +1,366 @@
+/*
+ * Chromium OS cros_ec driver
+ *
+ * Copyright (c) 2016 The Chromium OS Authors.
+ * Copyright (c) 2016 National Instruments Corp
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Note: depends on enum ec_current_image */
+static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Perform a flash read or write command
+ *
+ * @param dev  CROS-EC device to read/write
+ * @param is_write 1 do to a write, 0 to do a read
+ * @param argc Number of arguments
+ * @param argv Arguments (2 is region, 3 is address)
+ * @return 0 for ok, 1 for a usage error or -ve for ec command error
+ * (negative EC_RES_...)
+ */
+static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc,
+char * const argv[])
+{
+   uint32_t offset, size = -1U, region_size;
+   unsigned long addr;
+   char *endp;
+   int region;
+   int ret;
+
+   region = cros_ec_decode_region(argc - 2, argv + 2);
+   if (region == -1)
+   return 1;
+   if (argc < 4)
+   return 1;
+   addr = simple_strtoul(argv[3], , 16);
+   if (*argv[3] == 0 || *endp != 0)
+   return 1;
+   if (argc > 4) {
+   size = simple_strtoul(argv[4], , 16);
+   if (*argv[4] == 0 || *endp != 0)
+   return 1;
+   }
+
+   ret = cros_ec_flash_offset(dev, region, , _size);
+   if (ret) {
+   debug("%s: Could not read region info\n", __func__);
+   return ret;
+   }
+   if (size == -1U)
+   size = region_size;
+
+   ret = is_write ?
+   cros_ec_flash_write(dev, (uint8_t *)addr, offset, size) :
+   cros_ec_flash_read(dev, (uint8_t *)addr, offset, size);
+   if (ret) {
+   debug("%s: Could not %s region\n", __func__,
+ is_write ? "write" : "read");
+   return ret;
+   }
+
+   return 0;
+}
+
+static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
+{
+   struct cros_ec_dev *dev;
+   struct udevice *udev;
+   const char *cmd;
+   int ret = 0;
+
+   if (argc < 2)
+   return CMD_RET_USAGE;
+
+   cmd = argv[1];
+   if (0 == strcmp("init", cmd)) {
+   /* Remove any existing device */
+   ret = uclass_find_device(UCLASS_CROS_EC, 0, );
+   if (!ret)
+   device_remove(udev);
+   ret = uclass_get_device(UCLASS_CROS_EC, 0

[U-Boot] [PATCH] cros_ec: Honor the google,remote-bus dt property

[Moritz Fischer]

Boards where ECs that use a I2C port != 0 specify this in the
devicetree file via the google,remote-bus property.
Previously this was ignored and hardcoded to port 0.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Heiko Schocher <h...@denx.de>
Cc: u-boot@lists.denx.de
---
 drivers/i2c/cros_ec_tunnel.c | 24 +++-
 drivers/misc/cros_ec.c   |  5 +++--
 include/cros_ec.h|  4 +++-
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c
index e2c6e44..9cf8e7d 100644
--- a/drivers/i2c/cros_ec_tunnel.c
+++ b/drivers/i2c/cros_ec_tunnel.c
@@ -11,6 +11,12 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cros_ec_i2c_bus {
+   int remote_bus;
+};
+
 static int cros_ec_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 {
return 0;
@@ -19,7 +25,21 @@ static int cros_ec_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
 static int cros_ec_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
int nmsgs)
 {
-   return cros_ec_i2c_tunnel(dev->parent, msg, nmsgs);
+   struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev);
+
+   return cros_ec_i2c_tunnel(dev->parent, i2c_bus->remote_bus, msg, nmsgs);
+}
+
+static int cros_ec_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+   struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev);
+   const void *blob = gd->fdt_blob;
+   int node = dev->of_offset;
+
+   i2c_bus->remote_bus = fdtdec_get_uint(blob, node, "google,remote-bus",
+ 0);
+
+   return 0;
 }
 
 static const struct dm_i2c_ops cros_ec_i2c_ops = {
@@ -36,5 +56,7 @@ U_BOOT_DRIVER(cros_ec_tunnel) = {
.name   = "cros_ec_tunnel",
.id = UCLASS_I2C,
.of_match = cros_ec_i2c_ids,
+   .ofdata_to_platdata = cros_ec_i2c_ofdata_to_platdata,
+   .priv_auto_alloc_size = sizeof(struct cros_ec_i2c_bus),
.ops= _ec_i2c_ops,
 };
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index cb5db0f..37160d8 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1098,7 +1098,8 @@ int cros_ec_decode_ec_flash(const void *blob, int node,
return 0;
 }
 
-int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *in, int nmsgs)
+int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *in,
+  int nmsgs)
 {
struct cros_ec_dev *cdev = dev_get_uclass_priv(dev);
union {
@@ -1118,7 +1119,7 @@ int cros_ec_i2c_tunnel(struct udevice *dev, struct 
i2c_msg *in, int nmsgs)
int rv;
int i;
 
-   p->port = 0;
+   p->port = port;
 
p->num_msgs = nmsgs;
size = sizeof(*p) + p->num_msgs * sizeof(*msg);
diff --git a/include/cros_ec.h b/include/cros_ec.h
index 5fa5f6f..30b1908 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -395,9 +395,11 @@ struct i2c_msg;
  * Tunnel an I2C transfer to the EC
  *
  * @param dev  CROS-EC device
+ * @param port The remote port on EC to use
  * @param msg  List of messages to transfer
  * @param nmsgsNumber of messages to transfer
  */
-int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *msg, int nmsgs);
+int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *msg,
+  int nmsgs);
 
 #endif
-- 
2.7.4

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Re: [U-Boot] Chrome OS keyboard not responding on snow

[Moritz Fischer]

Hi Adam

On Mon, Sep 26, 2016 at 12:35 PM, Adam Van Ymeren  wrote:
> I'm trying to run the latest u-boot on the old samsung exynos5250
> chromebook (snow_defconfig).  I've managed to get the u-boot console
> up but it doesn't respond to keyboard input.
>
> I managed to hack the startup procedure to call dm_dump_all() which
> shows the the keyboard-controller of cros_ec was attached I think.
>
> Anyone remember much about this board or have any tips on how I could
> start debugging this?

Not sure if helpful: Try to build with CONFIG_USB_KEYBOARD enabled,
and change stdin?

Cheers,

Moritz
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[U-Boot] [PATCH 1/2] cros_ec: Add function to read back flash parameters

[Moritz Fischer]

Add support for reading back flash parameters as reported by
the ec.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: u-boot@lists.denx.de
---
 drivers/misc/cros_ec.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 06a7dcc..931fdf5 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -809,6 +809,27 @@ static int cros_ec_data_is_erased(const uint32_t *data, 
int size)
return 1;
 }
 
+/**
+ * Read back flash parameters
+ *
+ * This function reads back parameters of the flash as reported by the EC
+ *
+ * @param dev  Pointer to device
+ * @param info Pointer to output flash info struct
+ */
+int cros_ec_read_flashinfo(struct cros_ec_dev *dev,
+ struct ec_response_flash_info *info)
+{
+   int ret;
+
+   ret = ec_command(dev, EC_CMD_FLASH_INFO, 0,
+NULL, 0, info, sizeof(*info));
+   if (ret < 0)
+   return ret;
+
+   return ret < sizeof(*info) ? -1 : 0;
+}
+
 int cros_ec_flash_write(struct cros_ec_dev *dev, const uint8_t *data,
 uint32_t offset, uint32_t size)
 {
-- 
2.7.4

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[U-Boot] [PATCH 2/2] cros_ec: Add crosec flashinfo command

[Moritz Fischer]

Add command to print out the flash info as reported by the
ec. The data read back includes size, write block size,
erase block size.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: Simon Glass <s...@chromium.org>
Cc: u-boot@lists.denx.de
---
 drivers/misc/cros_ec.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 931fdf5..cb5db0f 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1382,6 +1382,15 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
printf("Offset: %x\n", offset);
printf("Size:   %x\n", size);
}
+   } else if (0 == strcmp("flashinfo", cmd)) {
+   struct ec_response_flash_info p;
+
+   ret = cros_ec_read_flashinfo(dev, );
+   if (!ret) {
+   printf("Flash size: %u\n", p.flash_size);
+   printf("Write block size:   %u\n", p.write_block_size);
+   printf("Erase block size:   %u\n", p.erase_block_size);
+   }
} else if (0 == strcmp("vbnvcontext", cmd)) {
uint8_t block[EC_VBNV_BLOCK_SIZE];
char buf[3];
@@ -1501,6 +1510,7 @@ U_BOOT_CMD(
"crosec events  Read CROS-EC host events\n"
"crosec clrevents [mask]Clear CROS-EC host events\n"
"crosec regioninfo <ro|rw>  Read image info\n"
+   "crosec flashinfo   Read flash info\n"
"crosec erase <ro|rw>   Erase EC image\n"
"crosec read <ro|rw>  []   Read EC image\n"
"crosec write <ro|rw>  []  Write EC image\n"
-- 
2.7.4

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[U-Boot] [PATCH v2] cros_ec: Fix issue with cros_ec_flash_write command

[Moritz Fischer]

This commit fixes an issue where data is written to an
invalid memory location.
The issue has been introduced in commit
(88364387 cros: add cros_ec_driver)

Cc: Simon Glass <s...@chromium.org>
Cc: u-boot@lists.denx.de
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
Changes from v1:
 - Fixed accidential change of command version
 - Removed added whitespace
---
 drivers/misc/cros_ec.c | 23 ---
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 44b4f59..06a7dcc 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -760,15 +760,24 @@ int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t 
offset, uint32_t size)
 static int cros_ec_flash_write_block(struct cros_ec_dev *dev,
const uint8_t *data, uint32_t offset, uint32_t size)
 {
-   struct ec_params_flash_write p;
+   struct ec_params_flash_write *p;
+   int ret;
 
-   p.offset = offset;
-   p.size = size;
-   assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE);
-   memcpy( + 1, data, p.size);
+   p = malloc(sizeof(*p) + size);
+   if (!p)
+   return -ENOMEM;
+
+   p->offset = offset;
+   p->size = size;
+   assert(data && p->size <= EC_FLASH_WRITE_VER0_SIZE);
+   memcpy(p + 1, data, p->size);
 
-   return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
- , sizeof(p), NULL, 0) >= 0 ? 0 : -1;
+   ret = ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
+ p, sizeof(*p) + size, NULL, 0) >= 0 ? 0 : -1;
+
+   free(p);
+
+   return ret;
 }
 
 /**
-- 
2.7.4

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Re: [U-Boot] [PATCH] cros_ec: Fix issue with cros_ec_flash_write command

[Moritz Fischer]

Hi Simon,

On Mon, Sep 12, 2016 at 1:48 PM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> -   return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
> - , sizeof(p), NULL, 0) >= 0 ? 0 : -1;
> +   ret = ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 1,
> + p, sizeof(*p) + size, NULL, 0) >= 0 ? 0 : -1;

This shouldn't touch the command version ... I'll resend v2 ... sorry
for the noise ...

Moritz
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[U-Boot] [PATCH] cros_ec: Fix issue with cros_ec_flash_write command

[Moritz Fischer]

This commit fixes an issue where data is written to an
invalid memory location.
The issue has been introduced in commit
88364387 cros: add cros_ec_driver

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: u-boot@lists.denx.de
---
 drivers/misc/cros_ec.c | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 44b4f59..6079e52 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -760,15 +760,26 @@ int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t 
offset, uint32_t size)
 static int cros_ec_flash_write_block(struct cros_ec_dev *dev,
const uint8_t *data, uint32_t offset, uint32_t size)
 {
-   struct ec_params_flash_write p;
+   struct ec_params_flash_write *p;
+   int ret;
 
-   p.offset = offset;
-   p.size = size;
-   assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE);
-   memcpy( + 1, data, p.size);
+   p = malloc(sizeof(*p) + size);
+   if (!p)
+   return -ENOMEM;
+
+
+   p->offset = offset;
+   p->size = size;
+   assert(data && p->size <= EC_FLASH_WRITE_VER0_SIZE);
+   memcpy(p + 1, data, p->size);
 
-   return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
- , sizeof(p), NULL, 0) >= 0 ? 0 : -1;
+   ret = ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 1,
+ p, sizeof(*p) + size, NULL, 0) >= 0 ? 0 : -1;
+
+   free(p);
+
+
+   return ret;
 }
 
 /**
-- 
2.7.4

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Re: [U-Boot] [PATCH 2/3] serial: zynq: Read information about clock from DT

[Moritz Fischer]

On Sun, Jul 17, 2016 at 7:12 AM, Simon Glass <s...@chromium.org> wrote:
> On 14 July 2016 at 07:19, Michal Simek <michal.si...@xilinx.com> wrote:
>> Read information about clock frequency from DT.
>>
>> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
>> ---
>>
>>  drivers/serial/serial_zynq.c | 28 +++-
>>  1 file changed, 27 insertions(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass <s...@chromium.org>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>
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Re: [U-Boot] [PATCHv2][RESEND] spi: Add support for N25Q016A

[Moritz Fischer]

Jagan,

thanks for your review!

On Thu, Jul 14, 2016 at 12:01 AM, Jagan Teki <jagannadh.t...@gmail.com> wrote:
> On 14 July 2016 at 00:00, Moritz Fischer <moritz.fisc...@ettus.com> wrote:
>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>> ---
>>  drivers/mtd/spi/sf_params.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
>> index 4f37e33..8ae4eea 100644
>> --- a/drivers/mtd/spi/sf_params.c
>> +++ b/drivers/mtd/spi/sf_params.c
>> @@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
>> {"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,   
>>  0},
>> {"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,   
>>  0},
>> {"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,   
>>SECT_4K},
>> +   {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_NORM,   
>>SECT_4K},
>
> Why would we need this ext_id (0x1000) here? I understand this is true
> number for this part but it shouldn't require for probe or require
> somewhere else?

You're right. I just sent v3.

Cheers,

Moritz
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[U-Boot] [PATCHv3] spi: Add support for N25Q016A

[Moritz Fischer]

This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..0ac7971 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,  
  0},
{"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,  
  0},
{"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
+   {"N25Q016A",   0x20bb15, 0x0,   64 * 1024,32, RD_NORM,  
SECT_4K},
{"N25Q32", 0x20ba16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32A",0x20bb16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0,   64 * 1024,   128, RD_FULL,  
   WR_QPP | SECT_4K},
-- 
2.7.4

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[U-Boot] [PATCHv2][RESEND] spi: Add support for N25Q016A

[Moritz Fischer]

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..8ae4eea 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,  
  0},
{"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,  
  0},
{"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
+   {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_NORM,  
SECT_4K},
{"N25Q32", 0x20ba16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32A",0x20bb16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0,   64 * 1024,   128, RD_FULL,  
   WR_QPP | SECT_4K},
-- 
2.5.5

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[U-Boot] [PATCHv2][RESEND] spi: Add support for N25016A

[Moritz Fischer]

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..8ae4eea 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,  
  0},
{"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,  
  0},
{"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
+   {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_NORM,  
SECT_4K},
{"N25Q32", 0x20ba16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32A",0x20bb16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0,   64 * 1024,   128, RD_FULL,  
   WR_QPP | SECT_4K},
-- 
2.5.5

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Re: [U-Boot] [PATCHv2] sf: params: Add support for n25q016a

[Moritz Fischer]

On Thu, Mar 31, 2016 at 11:06 AM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> This commits adds support for the N25Q016A, a 16Mbit
> serial NOR flash from Micron.
>
> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
> ---
> Changes from v1:
>
> * RD_FULL
> * WR_QPP as suggested by Marek
>
>  drivers/mtd/spi/sf_params.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
> index 4f37e33..44881b6 100644
> --- a/drivers/mtd/spi/sf_params.c
> +++ b/drivers/mtd/spi/sf_params.c
> @@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
> {"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,
> 0},
> {"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,
> 0},
> {"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,
>   SECT_4K},
> +   {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_FULL,
>  WR_QPP | SECT_4K},
> {"N25Q32", 0x20ba16, 0x0,   64 * 1024,64, RD_FULL,
>  WR_QPP | SECT_4K},
> {"N25Q32A",0x20bb16, 0x0,   64 * 1024,64, RD_FULL,
>  WR_QPP | SECT_4K},
> {"N25Q64", 0x20ba17, 0x0,   64 * 1024,   128, RD_FULL,
>  WR_QPP | SECT_4K},
> --
> 2.5.5
>
Ping?
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[U-Boot] [PATCHv2] sf: params: Add support for n25q016a

[Moritz Fischer]

This commits adds support for the N25Q016A, a 16Mbit
serial NOR flash from Micron.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
Changes from v1:

* RD_FULL
* WR_QPP as suggested by Marek

 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..44881b6 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,  
  0},
{"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,  
  0},
{"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
+   {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32", 0x20ba16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32A",0x20bb16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0,   64 * 1024,   128, RD_FULL,  
   WR_QPP | SECT_4K},
-- 
2.5.5

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Re: [U-Boot] [PATCH] sf: params: Add support for n25q016a

[Moritz Fischer]

Hi Marek,

On Wed, Mar 30, 2016 at 5:34 PM, Marek Vasut <marek.va...@gmail.com> wrote:
> On 03/31/2016 12:23 AM, Moritz Fischer wrote:
>> This commits adds support for the N25Q016A, a 16Mbit
>> serial NOR flash from Micron.
>>
>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>> ---
>>  drivers/mtd/spi/sf_params.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
>> index 4f37e33..8ae4eea 100644
>> --- a/drivers/mtd/spi/sf_params.c
>> +++ b/drivers/mtd/spi/sf_params.c
>> @@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
>>   {"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM, 
>>0},
>>   {"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM, 
>>0},
>>   {"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM, 
>>  SECT_4K},
>> + {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_NORM, 
>>  SECT_4K},
>
> According to [1], the device supports Quad I/O, so WR_QPP flag should be
> here in addition to SECT_4K .

Just finished testing your suggestion. Will resubmit v2. Thanks for the review.

Moritz
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[U-Boot] [PATCH] sf: params: Add support for n25q016a

[Moritz Fischer]

This commits adds support for the N25Q016A, a 16Mbit
serial NOR flash from Micron.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..8ae4eea 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -83,6 +83,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"M25P64", 0x202017, 0x0,   64 * 1024,   128, RD_NORM,  
  0},
{"M25P128",0x202018, 0x0,  256 * 1024,64, RD_NORM,  
  0},
{"M25PX64",0x207117, 0x0,   64 * 1024,   128, RD_NORM,  
SECT_4K},
+   {"N25Q016A",   0x20bb15, 0x1000,64 * 1024,32, RD_NORM,  
SECT_4K},
{"N25Q32", 0x20ba16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q32A",0x20bb16, 0x0,   64 * 1024,64, RD_FULL,  
   WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0,   64 * 1024,   128, RD_FULL,  
   WR_QPP | SECT_4K},
-- 
2.5.5

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Re: [U-Boot] [PATCH] ARM: zynq: Enable SPL RAM support by default

[Moritz Fischer]

On Tue, Feb 16, 2016 at 11:39 PM, Michal Simek <michal.si...@xilinx.com> wrote:
> Use RAM support in jtagboot mode.
>
> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>

Looks good to me,

Moritz
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Re: [U-Boot] [PATCH] serial: zynq: Change logic in putc

[Moritz Fischer]

On Wed, Feb 3, 2016 at 6:34 AM, Michal Simek <michal.si...@xilinx.com> wrote:
> Sync logic with Linux kernel where TX empty flag is checked before char
> is sent.
> This logic is fixing problem with console on zynqmp platform.
>
> For example:
> DRAM:  2 GiB
> Enabling Caches...
> EL Level:   ��   sdhci@ff17: 0
> Using default environment
>
> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>
> ---
>
>  drivers/serial/serial_zynq.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
> index e79d997cbab7..66d54e32ab38 100644
> --- a/drivers/serial/serial_zynq.c
> +++ b/drivers/serial/serial_zynq.c
> @@ -19,7 +19,7 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -#define ZYNQ_UART_SR_TXFULL0x0010 /* TX FIFO full */
> +#define ZYNQ_UART_SR_TXEMPTY   (1 << 3) /* TX FIFO empty */
>  #define ZYNQ_UART_SR_TXACTIVE  (1 << 11)  /* TX active */
>  #define ZYNQ_UART_SR_RXEMPTY   0x0002 /* RX FIFO empty */
>
> @@ -97,7 +97,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs)
>
>  static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
>  {
> -   if (readl(>channel_sts) & ZYNQ_UART_SR_TXFULL)
> +   if (!(readl(>channel_sts) & ZYNQ_UART_SR_TXEMPTY))
> return -EAGAIN;
>
> writel(c, >tx_rx_fifo);
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH] ARM: zynq: Remove unused SPI base addresses

[Moritz Fischer]

On Thu, Feb 4, 2016 at 1:07 AM, Michal Simek <michal.si...@xilinx.com> wrote:
> Remove unused macros. Adresses are taken from DT.
>
> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>
> ---
>
>  arch/arm/include/asm/arch-zynqmp/hardware.h | 3 ---
>  arch/arm/mach-zynq/include/mach/hardware.h  | 2 --
>  2 files changed, 5 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h 
> b/arch/arm/include/asm/arch-zynqmp/hardware.h
> index 587938249e8f..1ab301f0d21f 100644
> --- a/arch/arm/include/asm/arch-zynqmp/hardware.h
> +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
> @@ -13,9 +13,6 @@
>  #define ZYNQ_GEM_BASEADDR2 0xFF0D
>  #define ZYNQ_GEM_BASEADDR3 0xFF0E
>
> -#define ZYNQ_SPI_BASEADDR0 0xFF04
> -#define ZYNQ_SPI_BASEADDR1 0xFF05
> -
>  #define ZYNQ_I2C_BASEADDR0 0xFF02
>  #define ZYNQ_I2C_BASEADDR1 0xFF03
>
> diff --git a/arch/arm/mach-zynq/include/mach/hardware.h 
> b/arch/arm/mach-zynq/include/mach/hardware.h
> index 830e1fea1809..79347a83eaff 100644
> --- a/arch/arm/mach-zynq/include/mach/hardware.h
> +++ b/arch/arm/mach-zynq/include/mach/hardware.h
> @@ -14,8 +14,6 @@
>  #define ZYNQ_GEM_BASEADDR1 0xE000C000
>  #define ZYNQ_I2C_BASEADDR0 0xE0004000
>  #define ZYNQ_I2C_BASEADDR1 0xE0005000
> -#define ZYNQ_SPI_BASEADDR0 0xE0006000
> -#define ZYNQ_SPI_BASEADDR1 0xE0007000
>  #define ZYNQ_QSPI_BASEADDR 0xE000D000
>  #define ZYNQ_SMC_BASEADDR  0xE000E000
>  #define ZYNQ_NAND_BASEADDR 0xE100
> --
> 1.9.1
>
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[U-Boot] [PATCH] ARM: zynq: Add function to get reboot status register value.

[Moritz Fischer]

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
Hi Michal,

   I was planning to use this in future to boot into recovery mode.
   The change is small enough I feel that we could directly take it.
   If you want to hold off until there's a user that's fine for me, too.

   Cheers,

   Moritz
---
 arch/arm/mach-zynq/slcr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 05f4099..709711a 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -166,6 +166,11 @@ u32 zynq_slcr_get_boot_mode(void)
return readl(_base->boot_mode);
 }
 
+u32 zynq_slcr_get_reboot_status(void)
+{
+   return readl(_base->reboot_status);
+}
+
 u32 zynq_slcr_get_idcode(void)
 {
return (readl(_base->pss_idcode) & SLCR_IDCODE_MASK) >>
-- 
2.7.0

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Re: [U-Boot] [PATCH] ARM: zynq: Add function to get reboot status register value.

[Moritz Fischer]

Hi Michal,

On Wed, Jan 27, 2016 at 2:15 PM, Michal Simek <michal.si...@xilinx.com> wrote:
> On 27.1.2016 12:22, Moritz Fischer wrote:
>> Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
>> ---
>> Hi Michal,
>>
>>I was planning to use this in future to boot into recovery mode.
>>The change is small enough I feel that we could directly take it.
>>If you want to hold off until there's a user that's fine for me, too.
>>
>>Cheers,
>>
>>Moritz
>> ---
>>  arch/arm/mach-zynq/slcr.c | 5 +
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
>> index 05f4099..709711a 100644
>> --- a/arch/arm/mach-zynq/slcr.c
>> +++ b/arch/arm/mach-zynq/slcr.c
>> @@ -166,6 +166,11 @@ u32 zynq_slcr_get_boot_mode(void)
>>   return readl(_base->boot_mode);
>>  }
>>
>> +u32 zynq_slcr_get_reboot_status(void)
>> +{
>> + return readl(_base->reboot_status);
>> +}
>> +
>>  u32 zynq_slcr_get_idcode(void)
>>  {
>>   return (readl(_base->pss_idcode) & SLCR_IDCODE_MASK) >>
>>
>
> Isn't this generating sparse warning if it is not used and declared?

Derp. It doesn't generate a warning for not being used, however for
not being declared it does,
the entry in sys_proto.h is missing:

  CHECK   arch/arm/mach-zynq/slcr.c
arch/arm/mach-zynq/slcr.c:97:9: warning: cast to restricted __le32
arch/arm/mach-zynq/slcr.c:97:9: warning: incorrect type in assignment
(different base types)
arch/arm/mach-zynq/slcr.c:97:9:expected unsigned int volatile
[unsigned] 
arch/arm/mach-zynq/slcr.c:97:9:got restricted __le32 [usertype] 
arch/arm/mach-zynq/slcr.c:169:5: warning: symbol
'zynq_slcr_get_reboot_status' was not declared. Should it be static?
  CC  arch/arm/mach-zynq/slcr.o
  LD  arch/arm/mach-zynq/built-in.o

when added to header this becomes:

  CHECK   arch/arm/mach-zynq/slcr.c
arch/arm/mach-zynq/slcr.c:97:9: warning: cast to restricted __le32
arch/arm/mach-zynq/slcr.c:97:9: warning: incorrect type in assignment
(different base types)
arch/arm/mach-zynq/slcr.c:97:9:expected unsigned int volatile
[unsigned] 
arch/arm/mach-zynq/slcr.c:97:9:got restricted __le32 [usertype] 
  CC  arch/arm/mach-zynq/slcr.o
  LD  arch/arm/mach-zynq/built-in.o

These were there before ;-)

I can resend with the header line added,

Moritz
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Re: [U-Boot] [PATCH] ARM: zynq: zynqmp: Line up checkboard message

[Moritz Fischer]

Hi Michal,

On Mon, Jan 25, 2016 at 11:09 AM, Michal Simek <mon...@monstr.eu> wrote:
> On 25.1.2016 11:08, Michal Simek wrote:
>> Use space instead of tab in checkboard print to aligned
>> it with others boards.
>>
>> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>

Cheers,
Moritz
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Re: [U-Boot] [PATCH v3 5/5] net: zynq_gem: Use shared wait_for_bit

[Moritz Fischer]

On Thu, Jan 14, 2016 at 12:08 PM, Tom Rini <tr...@konsulko.com> wrote:
> On Sun, Dec 27, 2015 at 06:28:12PM +0100, Mateusz Kulikowski wrote:
>
>> Use existing library function to poll bit(s).
>> Signed-off-by: Mateusz Kulikowski <mateusz.kulikow...@gmail.com>
>
> Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>

Cheers,

Moritz
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Re: [U-Boot] [PATCH 6/9] ARM: zynq: Clean DTSI coding style

[Moritz Fischer]

On Thu, Jan 14, 2016 at 7:48 AM, Sören Brinkmann
<soren.brinkm...@xilinx.com> wrote:
> On Thu, 2016-01-14 at 02:44PM +0100, Michal Simek wrote:
>> From: Michal Simek <mon...@monstr.eu>
>>
>> Fix minor indentation problems.
>>
>> Signed-off-by: Michal Simek <mon...@monstr.eu>
>> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
> Reviewed-by: Sören Brinkmann <soren.brinkm...@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>
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Re: [U-Boot] [RFC 0/2] Add cdns-i2c driver as drop in for zynq-i2c

[Moritz Fischer]

On Tue, Jan 5, 2016 at 11:53 PM, Michal Simek <michal.si...@xilinx.com> wrote:
> On 5.1.2016 18:30, Moritz Fischer wrote:
>> Hi Michal,
>>
>> On Tue, Jan 5, 2016 at 7:44 AM, Michal Simek <michal.si...@xilinx.com> wrote:
>>
>>> I have looked at these patches and I don't know why there is 100k
>>> limitation in cdns_i2c_set_bus_speed. DTS is using 400k in Linux without
>>> any problem.
>>
>> Well I could statically calculate the values for 400K, too but anyway that 
>> works
>> only if your CPU_CLK_1X is 111MHz. Is there a way to figure out the 
>> CPU_CLK_1X
>> frequency?
>
> Check the clock driver.

Wouldn't that nececitate dm capable clk drivers? Were you talking about
arch/arm/mach-zynq/clk.c?

> It is simple to create that mux drivers but I am scared about that need
> for aliases and also i2c-parent has to go out of mux class too.
> I see that it is used in the mainline kernel but it has be changed.

I'll need to further investigate that.
>
>
>>> Also I have found that there is eeprom dependency which needs to be
>>> resolved to be able to use this driver instead of old one.
>>
>> Yeah I realized that. Do any of the zynq boards actually use CMD_EEPROM?
>
> We have a code for zc702 to save internal variables to EEPROM. zc706
> should have that memory too.

Ok, I'll look into it.

Moritz
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Re: [U-Boot] [RFC 0/2] Add cdns-i2c driver as drop in for zynq-i2c

[Moritz Fischer]

Hi Michal,

On Tue, Jan 5, 2016 at 7:44 AM, Michal Simek  wrote:

> I have looked at these patches and I don't know why there is 100k
> limitation in cdns_i2c_set_bus_speed. DTS is using 400k in Linux without
> any problem.

Well I could statically calculate the values for 400K, too but anyway that works
only if your CPU_CLK_1X is 111MHz. Is there a way to figure out the CPU_CLK_1X
frequency?

> Unfortunately I found that i2c muxes like pca9548 are not supported yet
> but I have create sort of skeleton for that but it looks like that there
> is no standard binding where i2c-parent is required. Also every muxes
> bus needs to have correct label and alias.

Yeah, I realized that last night when I started playing around with
it. I was trying
to pull in the linux one but didn't get around to finish that yet.

> Also I have found that there is eeprom dependency which needs to be
> resolved to be able to use this driver instead of old one.

Yeah I realized that. Do any of the zynq boards actually use CMD_EEPROM?

Thanks for you feedback,

Moritz
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[U-Boot] [RFC 0/2] Add cdns-i2c driver as drop in for zynq-i2c

[Moritz Fischer]

Hi all,

I spent some time moving over the zynq-i2c.c to support dm.
While doing that I realized that renaming it to cdns-i2c might
make sense since it now could be used with other SoCs that also use the
the Cadence IP.

This is a first shot, but I'd like to get some early feedback ;-)

Cheers,

Moritz

PS: I skipped touching the Zynq board files for now, since I wanted to make sure
I get the driver right first ;-)

Moritz Fischer (2):
  i2c: Describe Cadence I2C devicetree bindings
  dm: i2c: Add driver for Cadence I2C IP

 doc/device-tree-bindings/i2c/i2c-cdns.txt |  20 ++
 drivers/i2c/Kconfig   |   7 +
 drivers/i2c/Makefile  |   1 +
 drivers/i2c/i2c-cdns.c| 339 ++
 4 files changed, 367 insertions(+)
 create mode 100644 doc/device-tree-bindings/i2c/i2c-cdns.txt
 create mode 100644 drivers/i2c/i2c-cdns.c

-- 
2.4.3

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[U-Boot] [RFC 1/2] i2c: Describe Cadence I2C devicetree bindings

[Moritz Fischer]

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 doc/device-tree-bindings/i2c/i2c-cdns.txt | 20 
 1 file changed, 20 insertions(+)
 create mode 100644 doc/device-tree-bindings/i2c/i2c-cdns.txt

diff --git a/doc/device-tree-bindings/i2c/i2c-cdns.txt 
b/doc/device-tree-bindings/i2c/i2c-cdns.txt
new file mode 100644
index 000..202e0b7
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/i2c-cdns.txt
@@ -0,0 +1,20 @@
+Cadence I2C controller Device Tree Bindings
+---
+
+Required properties:
+- compatible   : Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10".
+- reg  : Physical base address and size of I2C registers map.
+- interrupts   : Property with a value describing the interrupt
+ number.
+- interrupt-parent : Must be core interrupt controller
+- clocks   : Clock phandles (see clock bindings for details).
+
+Example:
+   i2c0: i2c@e0004000 {
+   compatible = "cdns,i2c-r1p10";
+   reg = <0xe0004000 0x1000>;
+   clocks = < 38>;
+   interrupts = <0 25 4>;
+   interrupt-parent = <>;
+   status = "disabled";
+   };
-- 
2.4.3

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[U-Boot] [RFC 2/2] dm: i2c: Add driver for Cadence I2C IP

[Moritz Fischer]

This is a possible drop in replacement for drivers/i2c/zynq-i2c.c

Since this is cadence IP it has been renamed to cdns-i2c,
to make sense with the compatible string.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 drivers/i2c/Kconfig|   7 +
 drivers/i2c/Makefile   |   1 +
 drivers/i2c/i2c-cdns.c | 339 +
 3 files changed, 347 insertions(+)
 create mode 100644 drivers/i2c/i2c-cdns.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 14adda2..c058dc5 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,13 @@ config DM_I2C_GPIO
  bindings are supported.
  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_CADENCE
+   tristate "Cadence I2C Controller"
+   depends on DM_I2C && (ARCH_ZYNQ || ARM64)
+   help
+ Say yes here to select Cadence I2C Host Controller. This controller is
+ e.g. used by Xilinx Zynq.
+
 config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 811ad9b..35ad0d3 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
 obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
new file mode 100644
index 000..fab9609
--- /dev/null
+++ b/drivers/i2c/i2c-cdns.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright (C) 2015 Moritz Fischer <moritz.fisc...@ettus.com>
+ * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
+ *
+ * This file is based on: drivers/i2c/zynq_i2c.c,
+ * with added driver-model support and code cleanup.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* i2c register set */
+struct cdns_i2c_regs {
+   u32 control;
+   u32 status;
+   u32 address;
+   u32 data;
+   u32 interrupt_status;
+   u32 transfer_size;
+   u32 slave_mon_pause;
+   u32 time_out;
+   u32 interrupt_mask;
+   u32 interrupt_enable;
+   u32 interrupt_disable;
+};
+
+/* Control register fields */
+#define CDNS_I2C_CONTROL_RW0x0001
+#define CDNS_I2C_CONTROL_MS0x0002
+#define CDNS_I2C_CONTROL_NEA   0x0004
+#define CDNS_I2C_CONTROL_ACKEN 0x0008
+#define CDNS_I2C_CONTROL_HOLD  0x0010
+#define CDNS_I2C_CONTROL_SLVMON0x0020
+#define CDNS_I2C_CONTROL_CLR_FIFO  0x0040
+#define CDNS_I2C_CONTROL_DIV_B_SHIFT   8
+#define CDNS_I2C_CONTROL_DIV_B_MASK0x3F00
+#define CDNS_I2C_CONTROL_DIV_A_SHIFT   14
+#define CDNS_I2C_CONTROL_DIV_A_MASK0xC000
+
+/* Status register values */
+#define CDNS_I2C_STATUS_RXDV   0x0020
+#define CDNS_I2C_STATUS_TXDV   0x0040
+#define CDNS_I2C_STATUS_RXOVF  0x0080
+#define CDNS_I2C_STATUS_BA 0x0100
+
+/* Interrupt register fields */
+#define CDNS_I2C_INTERRUPT_COMP0x0001
+#define CDNS_I2C_INTERRUPT_DATA0x0002
+#define CDNS_I2C_INTERRUPT_NACK0x0004
+#define CDNS_I2C_INTERRUPT_TO  0x0008
+#define CDNS_I2C_INTERRUPT_SLVRDY  0x0010
+#define CDNS_I2C_INTERRUPT_RXOVF   0x0020
+#define CDNS_I2C_INTERRUPT_TXOVF   0x0040
+#define CDNS_I2C_INTERRUPT_RXUNF   0x0080
+#define CDNS_I2C_INTERRUPT_ARBLOST 0x0200
+
+#define CDNS_I2C_FIFO_DEPTH16
+#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+
+#ifdef DEBUG
+static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
+{
+   int int_status;
+   int status;
+   int_status = readl(_i2c->interrupt_status);
+
+   status = readl(_i2c->status);
+   if (int_status || status) {
+   debug("Status: ");
+   if (int_status & CDNS_I2C_INTERRUPT_COMP)
+   debug("COMP ");
+   if (int_status & CDNS_I2C_INTERRUPT_DATA)
+   debug("DATA ");
+   if (int_status & CDNS_I2C_INTERRUPT_NACK)
+   debug("NACK ");
+   if (int_status & CDNS_I2C_INTERRUPT_TO)
+   debug("TO ");
+   if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
+   debug("SLVRDY ");
+   if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
+   debug("RXOVF ");
+   if (int_status & CDNS_I2C_INTERRUPT