Re: [PATCH v5 10/10] mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t

size' parameter that is used > to iterate register update for all dies in the device. As explained in v4 [0], Nacked-by: Pratyush Yadav [0] https://patchwork.ozlabs.org/project/uboot/patch/a5c3cf1353d9a621379e2fcfefc51fb44c9680c5.1611729896.git.takahiro.kuw...@infineon.com/ -- Regards, Pr

Re: [PATCH v5 09/10] mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t

can(struct spi_nor *nor) > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 25234177de..cfb2104fee 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -125,6 +125,9 @@ > #define SPINOR_OP_WRAR 0x71/* Write any register */ > #define SPINOR_REG_ADDR_STR1V0x0080 > #define SPINOR_REG_ADDR_CFR1V0x0082 > +#define SPINOR_REG_ADDR_CFR3V0x0084 > +#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */ > +#define CFR3V_PGMBUF BIT(4) /* Program buffer size */ Ok. > > /* Used for Micron flashes only. */ > #define SPINOR_OP_RD_EVCR 0x65/* Read EVCR register */ > -- > 2.25.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v5 08/10] mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte

e SNOR_MFR_MACRONIX: > case SNOR_MFR_WINBOND: > + case SNOR_MFR_CYPRESS: > if (need_wren) > write_enable(nor); > > -- > 2.25.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v5 07/10] mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress

that is a separate fix. > + > + ret = spi_nor_wait_till_ready(nor); > + if (ret) > + break; > + } > + > + write_disable(nor); > + > + return ret; > +} > +#endif > + > #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) > /* Write status register and ensure bits in mask match written values */ > static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) > -- > 2.25.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v5 06/10] mtd: spi-nor-core: Read status by Read Any Register

s from Spansion/Cypress. > > Signed-off-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v5 05/10] mtd: spi-nor-core: Add the ->ready() hook

ta" that says how the patch should be applied. One it is applied this has no use in the Git history. So it should go below the 3 dashed lines, like the changelog. Other than this, Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v5 02/10] mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t

-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 I created an account to view these. I get "Access denied" on both. -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [RFC PATCH 07/13] mux: mmio: Only complain about idle-states if it is malformed

dle_states); > + /* dev_read_u32_array returns -EINVAL on missing property */ > + if (ret != -EINVAL) > + return log_msg_ret("idle-states", -EINVAL); Return ret here. I don't see any reason to return -EINVAL when the error is _not_ -EINVAL.

Re: [RFC PATCH 06/13] mux: Define a stub for mux_get_by_index if CONFIG_MUX is disabled

t() on the other side of this ifdef has a completely different signature. Can you please add that fix in your series as well? For this patch, Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [RFC PATCH 05/13] mux: Inline mux functions when CONFIG_MUX is disabled

On 04/02/21 11:39PM, Sean Anderson wrote: > This prevents multiple-definition errors. > > Fixes: 0ad40b2463 ("drivers: Add a new framework for multiplexer devices") > > Signed-off-by: Sean Anderson Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v3 4/9] doc: Add a note about how to produce 'md' output using hexdump

Hexdump obviously does not know this address so it will produce something like: 0000: 00 00 00 00 00 ... Dunno what to do about this though. Just figured I'd point it out. > + > > Example > --- -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v3 06/41] doc: Document how sandbox_spl_tests are run

un SPL tests in U-Boot proper, firstly because they > are > +not built into U-Boot proper and secondly because the environment is very > +different, e.g. some SPL tests rely on of-pldata which is only available in > SPL. s/of-pldata/of-platdata/ Other than this, Acked-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v4 9/9] mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t

shes will increase the size quite a bit. I know that some flashes already have their quad enable hooks, and I don't think they should be there either. Of course, the maintainers have the final call, but from my side, Nacked-by: Pratyush Yadav Anyway, comments below in case the maintainers

Re: [PATCH v4 8/9] mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t

8V) */ > + nor->fixups = _t_fixups; > + break; I recall using strcmp() in my series but I guess this should also work just as well. > + > + default: > + break; > + } > + } > +#endif > } > > int spi_nor_scan(struct spi_nor *nor) > -- > 2.25.1 > [0] https://lore.kernel.org/linux-mtd/4c0e3207-72a4-8c1a-5fca-e9f30cc60...@ti.com/ [1] https://lore.kernel.org/linux-mtd/20201201102711.8727-3-p.ya...@ti.com/ [2] https://lore.kernel.org/linux-mtd/20201201102711.8727-4-p.ya...@ti.com/ [3] https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-9-p.ya...@ti.com/ -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v4 6/9] mtd: spi-nor-core: Add overlaid sector erase feature

; #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) > /* Write status register and ensure bits in mask match written values */ > static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) > -- > 2.25.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v2 1/8] spl: Drop duplicate 'Jumping to U-Boot' message

penSBI, etc. This would also avoid saying "jumping to u-boot" right after saying "jumping to linux". > break; > #if CONFIG_IS_ENABLED(ATF) > case IH_OS_ARM_TRUSTED_FIRMWARE: > -- > 2.30.0.280.ga3ce27912f-goog > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH 05/14] spi: spi-mem: Add debug message for spi-mem ops

On 01/02/21 10:33AM, Sean Anderson wrote: > On 2/1/21 7:18 AM, Pratyush Yadav wrote: > > On 31/01/21 07:34PM, Sean Anderson wrote: > > > This prints some basic metadata about the SPI memory op. This information > > > may be used to debug SPI drivers (e.g. determ

Re: [PATCH v2 05/40] doc: Document how sandbox_spl_tests are run

test_of_plat_base: of_platdata.c (flat tree) > + Test: dm_test_of_plat_dev: of_platdata.c (flat tree) > + Test: dm_test_of_plat_parent: of_platdata.c (flat tree) > + Test: dm_test_of_plat_phandle: of_platdata.c (flat tree) > + Test: dm_test_of_plat_props: of_platdata.c (flat tree) > + Failures: 0 > + > + > + U-Boot 2021.01-00723-g43c77b51be5-dirty (Jan 24 2021 - 16:38:24 -0700) > + > + DRAM: 128 MiB > + ... > + > + -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH 02/14] cmd: sf: Print error on test failure

On 31/01/21 07:34PM, Sean Anderson wrote: > The sf test command is used to test spi flashes (and spi masters). Printing > the exact error code is very helpful to those debugging the spi stack. > > Signed-off-by: Sean Anderson Reviewed-by: Pratyush Yadav -- Regards, Pratyush

Re: [PATCH 01/14] cmd: sf: Display errno on erase failure

On 31/01/21 07:34PM, Sean Anderson wrote: > If there is an error while erasing SPI flash, no errno is displayed. This > makes it difficult to determine the cause of the error. This change mirrors > the logic for write errors above. > > Signed-off-by: Sean Anderson Reviewed-by:

Re: [PATCH 03/14] mtd: spi-nor-core: Fix typo in documentation

atch should take priority and Takahiro should drop it from his. Reviewed-by: Pratyush Yadav [0] https://patchwork.ozlabs.org/project/uboot/patch/6442361cd0a3acf98525b475992eb9d0ec014994.1611729896.git.takahiro.kuw...@infineon.com/ > --- > > include/linux/mtd/spi-nor.h | 2 +- &g

Re: [PATCH 05/14] spi: spi-mem: Add debug message for spi-mem ops

[0] For now. This might change later. See https://lore.kernel.org/linux-mtd/6396018a-485f-6eb4-7742-bdb5c4335...@microchip.com/ With these fixed, Reviewed-by: Pratyush Yadav > + op->data.nbytes); > + > if (!spi_mem_supports_op(slave, op)) > return -ENOTSUPP; > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH 04/14] mtd: spi-mem: Export spi_mem_default_supports_op

Hi Sean, On 31/01/21 07:34PM, Sean Anderson wrote: > This is useful for extending the default functionality. > > Signed-off-by: Sean Anderson I saw a similar patch a few days ago [0]. Which one to pick is up to the maintainer I guess. Reviewed-by: Pratyush Yadav [

Re: [PATCH v4 5/9] mtd: spi-nor-core: Add the ->ready() hook

int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); > int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); > int (*quad_enable)(struct spi_nor *nor); > + int (*ready)(struct spi_nor *nor); > > void *priv; > /* Compatibility for spi_flash, remove once sf layer is merged with mtd */ > -- > 2.25.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v4 4/9] mtd: spi-nor-core: Add support for volatile QE bit

ansion_read_any_reg(nor, addr, dummy, ); > + if (ret || !(cr & CR_QUAD_EN_SPAN)) { > + dev_dbg(nor->dev, "Spansion Quad bit not set\n"); > + return -EINVAL; > + } > + > + return 0; > +} > + Rest of the patch LGTM. > #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) > /** > * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. > -- > 2.25.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v4 3/9] mtd: spi-nor-core: Add support for Read/Write Any Register

any register */ > +#define SPINOR_REG_ADDR_STR1V0x0080 > +#define SPINOR_REG_ADDR_CFR1V0x0082 These two defines are not used by this patch. Remove them from this one and add them to the one that actually uses them for the first time. With this fixed, Reviewed-by: Pratyush Yadav > > /* Used for Micron flashes only. */ > #define SPINOR_OP_RD_EVCR 0x65/* Read EVCR register */ > -- > 2.25.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v4 2/9] mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t

4B_OPCODES | > + USE_CLSR) }, > + { INFO6("s25hs04gt", 0x342b1d, 0x0f0090, 256 * 1024, 2048, > + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | > + USE_CLSR) }, The datasheets you have linked do not specify a mapping between d

Re: [PATCH v4 1/9] mtd: spi-nor: Add Cypress manufacturer ID

On 28/01/21 01:36PM, tkuw584...@gmail.com wrote: > From: Takahiro Kuwano > > This patch adds Cypress manufacturer ID (34h) definition. > > Signed-off-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments Inc.

Re: [PATCH v2 05/12] pinctrl: single: get register area size by device API

On 28/01/21 11:24PM, Dario Binacchi wrote: > Use dev_read_addr_size to get size of the controller's register area. > > Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH v2 04/12] pinctrl: single: fix debug messages formatting

epends/ Other than that, Reviewed-by: Pratyush Yadav > address displayed. > > Signed-off-by: Dario Binacchi > > --- > > Changes in v2: > - Updated commit message > - Split in 2 commits > > drivers/pinctrl/pinctrl-single.c | 4 ++-- > 1 file changed, 2 insertio

Re: [PATCH v2 03/12] pinctrl: single: fix offset management

ed. Printing an offset also requires a different > formatting option than a physical address. > > Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 03/11] pinctrl: single: fix debug messages formatting

On 26/01/21 12:20PM, Dario Binacchi wrote: > Hi Pratyush, > > > Il 25/01/2021 18:09 Pratyush Yadav ha scritto: > > > > > > Hi Dario, > > > > On 23/01/21 07:27PM, Dario Binacchi wrote: > > > The printf '%pa' format specifier appends the '0x'

Re: [PATCH 03/11] pinctrl: single: fix debug messages formatting

continue; > } > - reg += pdata->base; > + > + reg = pdata->base + offset; > > mask = fdt32_to_cpu(pins->mask); > val = fdt32_to_cpu(pins->val) & mask; > @@ -136,7 +140,7 @@ static int single_configure_bits(struct udevice *dev, >pdata->width); > continue; > } > - dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", , val); > + dev_dbg(dev, " reg/val %pa/0x%08x\n", , val); > } > return 0; > } > -- > 2.17.1 > -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 02/11] pinctrl: single: fix the loop counter variable type

dea to add something like: n is used as a loop counter, not as a physical address, and is used in a comparison with an int. So it makes sense to set its type to int. Other than that, Reviewed-by: Pratyush Yadav > Signed-off-by: Dario Binacchi > --- > > drivers/pinctrl/pinct

Re: [PATCH v2 1/3] mem: spi-mem: add declaration for spi_mem_default_supports_op

Signed-off-by: Mathew McBride Reviewed-by: Pratyush Yadav > --- > include/spi-mem.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/spi-mem.h b/include/spi-mem.h > index ca0f55c8fd..8be3e2bf6b 100644 > --- a/include/spi-mem.h > +++ b

Re: [PATCH 0/2] Console/stdio use after free

ail. Could you > please update it to include your name as well? >From shows the full name on my email client. For everybody apart from Nicholas it shows just the email, but for Nicholas I can see full name in both From and Cc. Maybe something wrong with your email client settings. > Regards, > Simon -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 1/2] spi: nxp_fspi: Fix error reporting

hen handling errors. > > Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") > Signed-off-by: Adam Ford Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 1/3] mem: spi-mem: define spi_mem_default_supports_op

spi_controller *ctlr, >struct sg_table *sg) > { > } > + > +bool spi_mem_default_supports_op(struct spi_mem *mem, > + const struct spi_mem_op *op) > +{ > + return false; > +} > #endif /* CONFIG_SPI_MEM */ > #endif /* __UBOOT__ */ > > -- > 2.30.0 > -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 04/15] gpio: Rename dm_gpio_get_dir_flags() to dm_gpio_get_flags()

dir(struct gpio_desc *desc); > int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); > > /** > - * dm_gpio_get_dir_flags() - Get direction flags > + * dm_gpio_get_flags() - Get direction flags s/Get direction flags/Get flags/ With this fixed, Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 03/15] dm: gpio: Rename get_dir_flags() method to get_flags()

> drivers/pinctrl/pinctrl-stmfx.c | 8 > include/asm-generic/gpio.h | 13 +++-- > 5 files changed, 34 insertions(+), 33 deletions(-) > Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 02/15] dm: gpio: Rename set_dir_flags() method to update_flags()

and reset it */ > ut_asserteq(GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE, > sandbox_gpio_get_dir_flags(dev, offset)); > - ut_assertok(ops->set_dir_flags(dev, offset, > - GPIOD_IS_OUT | GPIOD_OPEN_DRAIN)); > + ut_assertok(ops->update_flags(dev, offset, > + GPIOD_IS_OUT | GPIOD_OPEN_DRAIN)); > ut_asserteq(GPIOD_IS_OUT | GPIOD_OPEN_DRAIN, > sandbox_gpio_get_dir_flags(dev, offset)); > - ut_assertok(ops->set_dir_flags(dev, offset, > -GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)); > + ut_assertok(ops->update_flags(dev, offset, > + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)); > ut_asserteq(GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE, > sandbox_gpio_get_dir_flags(dev, offset)); > With these fixed, Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 01/15] gpio: Disable functions not used with of-platdata

) > @@ -1109,6 +1110,7 @@ int gpio_get_list_count(struct udevice *dev, const char > *list_name) > > return ret; > } > +#endif /* OF_PLATDATA */ > > int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc) > { > -- > 2.30.0.284.gd98b1dd5eaa7-goog > -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 16/18] dm: Use access methods for dev/uclass private data

d *base = priv->regbase; > int err = 0; > @@ -284,7 +284,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, > > static int cadence_spi_of_to_plat(struct udevice *bus) > { > - struct cadence_spi_plat *plat = bus->plat; > + struct cadence_spi_plat *pl

Re: [PATCH 2/3] TI QSPI: add support for dual and quad-bit I/O read

rame length > + if (op->data.dir == SPI_MEM_DATA_IN) { > + unsigned int data_len = CONFIG_TI_QSPI_MAX_FRAME_SIZE - > + > sizeof(op->cmd.opcode) - op->addr.nbytes - > + > op->dummy.nbytes; > + // Align the data on cache line > + data_len = data_len & ~(ARCH_DMA_MINALIGN - 1); > + op->data.nbytes = min(op->data.nbytes, data_len); > + } > +#endif > + > + return 0; > +} > + > static int ti_qspi_claim_bus(struct udevice *dev) > { > struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); > @@ -482,6 +527,7 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus) > > static const struct spi_controller_mem_ops ti_qspi_mem_ops = { > .exec_op = ti_qspi_exec_mem_op, > + .adjust_op_size = ti_qspi_adjust_size, > }; > > static const struct dm_spi_ops ti_qspi_ops = { > -- > 2.26.2 > -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH 1/3] mtd: spi nor: add support for dual and quad bit transfers

; index ef8c1f6692..cf5f05e526 100644 > --- a/include/spi.h > +++ b/include/spi.h > @@ -146,6 +146,8 @@ struct spi_slave { > #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ > #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ > #define SPI_XFER_ONCE(SPI_XFER_BEGIN | SPI_XFER_END) > +#define SPI_XFER_DUAL_READ BIT(2) /* Dual I/O read */ > +#define SPI_XFER_QUAD_READ BIT(3) /* Quad I/O read */ > }; > > /** > -- > 2.26.2 > -- Regards, Pratyush Yadav Texas Instruments India

Re: [scan-ad...@coverity.com: New Defects reported by Coverity Scan for Das U-Boot]

])) { > 112 ret = PTR_ERR(fields[i]); > > > To view the defects in Coverity Scan visit, > https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P0qcxCbhZ31OYv50yoA22WlOQ-2By3ieUvdbKmOyw68TMVT4Kip-2BBzfOGWXJ5yIiYplmPF9KAnKIja4Zd7tU-3DG16z_EEm8SbLgSDsaDZif-2Bv7ch8WqhKpLoKErHi4nXpwDNTttU5wxtf-2BIrYIlH6m8usGJ6Lj2sxuVx1MrdzdzgACo0LT3OFouHYVv45XtjGnMdnBHVdXsmw-2F0hVbOCFNnsrngQZqCc0sAyWQDCDYCMOEtivMS6hgdPFHSlGRRb51oma2tiPKUAklqWROrvI4MyXxqrp-2Fd4gBcYvc7-2FLXQFG0CyHS3IAPBDTyEFObYQ4RE2yA-3D > > To manage Coverity Scan email notifications for > "tom.r...@gmail.com", click > https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P0qcxCbhZ31OYv50yped04pjJnmXOsUBtKYNIXxWeIHzDeopm-2BEWQ6S6K-2FtUHv9ZTk8qZbuzkkz9sa-2BJFw4elYDyedRVZOC-2ButxjBZdouVmTGuWB6Aj6G7lm7t25-2Biv1B-2B9082pHzCCex2kqMs-3DEOqJ_EEm8SbLgSDsaDZif-2Bv7ch8WqhKpLoKErHi4nXpwDNTttU5wxtf-2BIrYIlH6m8usGJzaB1PzDyVpqw-2FdKI2nmJ1aeEn5herkK9wV7V6RjSEoYxghGutNP9BcObkZR3VG0GThMSPIO3YwHDptrjReecWG99Q7RAogK2ghwHTok4ICj9O-2FAA-2FumHtxTSCVEgN8DQdszAdaF0kCwbpvbxr33-2Bx8r4btBT-2Bj-2BqyAjW5wzAVl4-3D Whew! That's a lot of issues with the patches I submitted! IMO the tool is mostly raising valid concerns and I think most of these are actual bugs. I don't know how useful the rand() warning is though. I think it will be a false positive most of the time but maybe it is worth it for the one time it actually catches a security issue. Dunno. -- Regards, Pratyush Yadav Texas Instruments India

[PATCH v4 7/7] test: mux-cmd: Add tests for the 'mux' command

Tests tests run the three mux subcommands: list, select, and deselect, and verify that the commands do what we expect. Signed-off-by: Pratyush Yadav --- Notes: New in v4. configs/sandbox_defconfig | 1 + test/dm/Makefile | 1 + test/dm/mux-cmd.c | 177

[PATCH v4 4/7] Kconfig: Increase the pre-relocation memory

The memory is close to full and adding a syscon node in test.dts makes it go over the limit and makes malloc() fail on startup. Signed-off-by: Pratyush Yadav --- Notes: New in v4. Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index

[PATCH v4 6/7] cmd: Add a mux command

roller: ID SelectedCurrent State Idle State Num States 0 no 0x1 0x1 0x4 1 no 0x1 0x1 0x4 Signed-off-by: Pratyush Yadav --- Notes: Changes in v4: - Use space

[PATCH v4 3/7] drivers: mux: mmio-based syscon mux controller

From: Jean-Jacques Hiblot This adds a driver for mmio-based syscon multiplexers controlled by bitfields in a syscon register range. This is heavily based on the linux mmio-mux driver. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes

[PATCH v4 5/7] test: Add tests for the multiplexer framework

to it. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Pratyush Yadav --- Notes: Changes in v4: - Add an emulated mux driver that makes it easier to test some basic functionality. It is used to test basic things like setting default state, and simple set/unset

[PATCH v4 1/7] drivers: Add a new framework for multiplexer devices

From: Jean-Jacques Hiblot Add a new subsystem that handles multiplexer controllers. The API is the same as in Linux. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes: No changes on v4. drivers/Kconfig | 2 + drivers

[PATCH v4 0/7] drivers: Add a framework for MUX drivers

: complete the initialization of the muxes in initr_dm() drivers: mux: mmio-based syscon mux controller test: Add tests for the multiplexer framework Pratyush Yadav (3): Kconfig: Increase the pre-relocation memory cmd: Add a mux command test: mux-cmd: Add tests for the 'mux' command Kconfig

[PATCH v4 2/7] dm: board: complete the initialization of the muxes in initr_dm()

From: Jean-Jacques Hiblot This will probe the multiplexer devices that have a "u-boot,mux-autoprobe" property. As a consequence they will be put in their idle state. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes: No cha

Re: [PATCH v3 0/9] regmap: Add managed API, regmap fields, regmap config

On 24/09/20 10:04AM, Pratyush Yadav wrote: > Hi, > > This series is a re-spin of Jean-Jacques' earlier effort [0], the goal > of which was to facilitate porting drivers from the Linux kernel. It > adds the managed API, using the same API as Linux. It also adds support >

Re: [PATCH] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t

On 25/09/20 03:13PM, Pratyush Yadav wrote: > > + if (instr->addr < erasesize) { > > + instr_4k.addr = 0; > > + ret = spi_nor_erase(mtd, _4k); > > + } > > + if (!ret && instr->addr + instr->len >= mtd->size

Re: [PATCH] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t

; + err = spansion_quad_enable_volatile(nor); > + break; > +#endif > + > default: > #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) > /* Kept only for backward compatibility purpose. */ > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 233fdc341a..83d13ebe66 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -27,6 +27,7 @@ > #define SNOR_MFR_SPANSIONCFI_MFR_AMD > #define SNOR_MFR_SST CFI_MFR_SST > #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ > +#define SNOR_MFR_CYPRESS 0x34 > > /* > * Note on opcode nomenclature: some opcodes have a format like > @@ -120,6 +121,8 @@ > #define SPINOR_OP_BRWR 0x17/* Bank register write */ > #define SPINOR_OP_BRRD 0x16/* Bank register read */ > #define SPINOR_OP_CLSR 0x30/* Clear status register 1 */ > +#define SPINOR_OP_WRAR 0x71/* Write any register */ > +#define SPINOR_REG_ADDR_CFR1V0x0082 > > /* Used for Micron flashes only. */ > #define SPINOR_OP_RD_EVCR 0x65/* Read EVCR register */ > -- > 2.25.1 > [0] https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-21-p.ya...@ti.com/ [1] https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-9-p.ya...@ti.com/ -- Regards, Pratyush Yadav Texas Instruments India

[PATCH v3 9/9] test: dm: Add tests for regmap managed API and regmap fields

behave properly (mask and shift are ok) by peeking into the regmap. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- Notes: Changes in v3: - s/DM_TESTF/UT_TESTF/g - Fix merge conflicts in test.dts arch/sandbox/dts/test.dts | 13

[PATCH v3 5/9] regmap: Add regmap_init_mem_range()

by the driver based on calculations at runtime. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- Notes: No changes in v3. drivers/core/regmap.c | 27 +++ include/regmap.h | 19 +++ 2 files changed, 46 insertions(+) diff --git

[PATCH v3 7/9] regmap: Add support for regmap fields

From: Jean-Jacques Hiblot A regmap field is an abstraction available in Linux. It provides to access bitfields in a regmap without having to worry about shifts and masks. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes: No changes

[PATCH v3 4/9] regmap: Allow left shifting register offset before access

Drivers can configure it to adjust the final read/write location. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- Notes: No changes in v3. drivers/core/regmap.c | 6 +- include/regmap.h | 6 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers

[PATCH v3 2/9] regmap: zero out the regmap on allocation

Some fields will be introduced in the regmap structure that should be set to 0 by default. So, once we allocate a regmap, make sure it is zeroed out to avoid unexpected defaults for those values. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- Notes: No changes in v3. drivers

[PATCH v3 8/9] test/py: allow multi-digit index in in_tree()

when adding a simple_bus node in test.dts made test_bind_unbind_with_uclass() fail because the index went up to 10. Signed-off-by: Pratyush Yadav --- Notes: New in v3. test/py/tests/test_bind.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_bind.py b

[PATCH v3 3/9] regmap: Allow specifying read/write width

callsite. This makes the port harder to maintain. So, allow specifying the read/write width to make it easier to port the drivers, since now the only change needed is when initializing the regmap. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- Notes: No changes in v3. drivers/core

[PATCH v3 6/9] regmap: Allow devices to specify regmap range start and size in config

. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- Notes: No changes in v3. drivers/core/regmap.c | 6 +- include/regmap.h | 6 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index a9087df32b

[PATCH v3 1/9] regmap: Add devm_regmap_init()

-off-by: Pratyush Yadav --- Notes: No changes in v3. drivers/core/regmap.c | 29 + include/regmap.h | 18 ++ 2 files changed, 47 insertions(+) diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index a67a237b88..74225361fd 100644

[PATCH v3 0/9] regmap: Add managed API, regmap fields, regmap config

(3): regmap: Add devm_regmap_init() regmap: Add support for regmap fields test: dm: Add tests for regmap managed API and regmap fields Pratyush Yadav (6): regmap: zero out the regmap on allocation regmap: Allow specifying read/write width regmap: Allow left shifting register offset bef

[PATCH v5 2/2] test: gpio: Add tests for the managed API

From: Jean-Jacques Hiblot Add a test to verify that GPIOs can be acquired/released using the managed API. Also check that the GPIOs are released when the consumer device is removed. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes

[PATCH v5 1/2] drivers: gpio: Add a managed API to get a GPIO from the device-tree

Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes: Heinrich, I tried adding API documentation for GPIO but sphinx throws a lot of warnings and errors, some of which are not trivial to fix. I will send those changes as a separate series. Since it will just pull

[PATCH v5 0/2] gpio: Add a managed API

Hi, This is a re-submission of Jean-Jacques' earlier work in October last year. It can be found at [0]. The goal is to facilitate porting drivers from the Linux kernel. Most of the series will be about adding managed APIs to existing infrastructure (GPIO, reset, regmap). This particular series

Re: [PATCH v3 0/2] reset: Add a managed API

On 09/09/20 03:37PM, Pratyush Yadav wrote: > Hi, > > This is the 4th of a few series that are re-rolls of Jean-Jacques' > earlier efforts. The goal is to facilitate porting drivers from the > Linux kernel. > > This particular series is about reset controllers. It adds a

[PATCH v3 1/2] drivers: reset: Add a managed API to get reset controllers from the DT

and the data structure is freed. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes: Changes in v3: - Include linux/err.h instead of linux/errno.h because it includes the definition of ERR_PTR(), which we use in the inline variants

[PATCH v3 2/2] test: reset: Add tests for the managed API

From: Jean-Jacques Hiblot The tests are basically the same as for the regular API. Except that the reset are initialized using the managed API, and no freed manually. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- Notes: Changes in v3

[PATCH v3 0/2] reset: Add a managed API

Hi, This is the 4th of a few series that are re-rolls of Jean-Jacques' earlier efforts. The goal is to facilitate porting drivers from the Linux kernel. This particular series is about reset controllers. It adds a managed API, close to that of Linux. The main difference is that bulk and

Re: [PATCH v4 2/2] test: gpio: Add tests for the managed API

On 08/09/20 05:56PM, Simon Glass wrote: > On Mon, 7 Sep 2020 at 23:40, Pratyush Yadav wrote: > > > > From: Jean-Jacques Hiblot > > > > Add a test to verify that GPIOs can be acquired/released using the managed > > API. Also check that the GPIOs are

Re: [PATCH v4 1/2] drivers: gpio: Add a managed API to get a GPIO from the device-tree

On 08/09/20 04:12PM, Heinrich Schuchardt wrote: > On 08.09.20 07:40, Pratyush Yadav wrote: > > From: Jean-Jacques Hiblot > > > > Add managed functions to get a gpio from the devce-tree, based on a > > property name (minus the '-gpios' suffix) and optionally an ind

[PATCH v4 2/2] test: gpio: Add tests for the managed API

From: Jean-Jacques Hiblot Add a test to verify that GPIOs can be acquired/released using the managed API. Also check that the GPIOs are released when the consumer device is removed. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Pratyush Yadav --- arch/sandbox/dts/test.dts | 10

[PATCH v4 1/2] drivers: gpio: Add a managed API to get a GPIO from the device-tree

Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- drivers/gpio/gpio-uclass.c | 71 ++ include/asm-generic/gpio.h | 47 + 2 files changed, 118 insertions(+) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c

[PATCH v4 0/2] gpio: Add a managed API

Hi, This is a re-submission of Jean-Jacques' earlier work in October last year. It can be found at [0]. The goal is to facilitate porting drivers from the Linux kernel. Most of the series will be about adding managed APIs to existing infrastructure (GPIO, reset, regmap). This particular series

Re: [PATCH v7 05/21] arm: mvebu: x530: Use tiny SPI NOR

On 06/09/20 08:34PM, Chris Packham wrote: > > On 5/09/20 3:39 am, Pratyush Yadav wrote: > > Chris, > > > > On 04/09/20 09:04PM, Pratyush Yadav wrote: > >> The SPI NOR core will get Octal DTR in following commits. This has > >> presented a significant

Re: [PATCH v7 05/21] arm: mvebu: x530: Use tiny SPI NOR

Chris, On 04/09/20 09:04PM, Pratyush Yadav wrote: > The SPI NOR core will get Octal DTR in following commits. This has > presented a significant challenge of keeping the SPL size in check on > the x530 platform. > > On a previous iteration of the series, adding a set of compile-

[PATCH v7 20/21] mtd: spi-nor-core: Add support for Cypress Semper flash

versions of the flash was incorrect. Fixes for that are included in the fixup hooks. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/Kconfig| 8 ++ drivers/mtd/spi/spi-nor-core.c | 199 + drivers/mtd/spi/spi-nor-ids.c | 3 + include/linux/mtd/spi-nor.h

[PATCH v7 21/21] mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode

reset sequence. So, add the flag in the flash's info. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/Kconfig| 8 drivers/mtd/spi/spi-nor-core.c | 85 ++ drivers/mtd/spi/spi-nor-ids.c | 4 +- include/linux/mtd/spi-nor.h| 10 +++- 4 files changed

[PATCH v7 19/21] mtd: spi-nor-core: Perform a Soft Reset on boot

ROM hands it to us in Octal DTR mode. To accommodate cases where there is more than one flash on a board, and only one of them needs a soft reset, failure to reset is not made fatal, and we still try to read ID if possible. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/Kconfig

[PATCH v7 18/21] mtd: spi-nor-core: Perform a Soft Reset on shutdown

assumes that we don't set any non-volatile bits anywhere, and the flash doesn't have any non-volatile Octal DTR mode configuration. Since spi-nor-tiny doesn't (and likely shouldn't) have spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does nothing. Signed-off-by: Pratyush Yadav

[PATCH v7 17/21] mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT

A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 6 ++ include/linux/mtd/spi

[PATCH v7 16/21] mtd: spi-nor-core: Do not make invalid quad enable fatal

o abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-cor

[PATCH v7 14/21] mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode

mode read 2 bytes and discard the second. This shows no side effects with the two flashes I tested: Micron mt35xu512aba and Cypress s28hs512t. Update Read FSR to mimic Read SR because they share the same characteristics. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 48

[PATCH v7 15/21] mtd: spi-nor-core: Enable octal DTR mode when possible

Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 31 +++ include/linux/mtd/spi-nor.h| 2 ++ 2 files changed, 33 insertions

[PATCH v7 13/21] mtd: spi-nor-core: Parse xSPI Profile 1.0 table

dummy cycles for a fast octal DTR read are set to 20. Since there is no simple way of determining the dummy cycles needed for the fast read command, flashes that use a different value should update it in their flash-specific hooks. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c

[PATCH v7 09/21] mtd: spi-nor-core: Rework hwcaps selection

: Rework hwcaps selection for the spi-mem case, 2019-08-06) Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/Kconfig| 9 ++ drivers/mtd/spi/spi-nor-core.c | 244 ++--- drivers/spi/spi-mem-nodm.c | 62 + include/linux/mtd/spi-nor.h| 17 ++- 4

[PATCH v7 12/21] mtd: spi-nor-core: Get command opcode extension type from BFPT

d "inverse" extensions are supported. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 25 + 1 file changed, 25 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9bba61a3f7..30fc079fd4 100644 --- a/dri

[PATCH v7 08/21] mtd: spi-nor-core: Introduce flash-specific fixup hooks

uct spi_nor_fixups in nor->info. This is not possible in U-Boot because the spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c. Since spi-nor-tiny shouldn't have those fixup hooks populated, add a separate function that lets flashes populate their fixup hooks. Signed-off-by: Pratyush

[PATCH v7 10/21] mtd: spi-nor-core: Add support for DTR protocol

phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/sf_internal.h | 2 + drivers/mtd/spi/spi-nor-core.c | 151 +++-- include/linux/mtd/spi-nor.h| 50 --- 3 files changed, 163 insertions(+), 40 deletions(-) diff --git

[PATCH v7 11/21] mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D

-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 09a24c40f4..9bba61a3f7 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor

[PATCH v7 05/21] arm: mvebu: x530: Use tiny SPI NOR

-by: Pratyush Yadav --- configs/x530_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 890c94b5c1..0570dbe9ea 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -62,7 +62,6 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y

[PATCH v7 06/21] mtd: spi-nor-core: Add a ->setup() hook

ons to avoid forward declarations. Inspired by the Linux kernel's setup() hook. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 84 +++ drivers/mtd/spi/spi-nor-tiny.c | 22 include/linux/mtd/spi-nor.h| 192 ++--- 3 files changed,

[PATCH v7 07/21] mtd: spi-nor-core: Move SFDP related declarations to top

These structures will be used in a later commit inside another structure definition. Also take the declarations out of the ifdef since they won't affect the final binary anyway and will be used in a later commit. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 224

[PATCH v7 00/21] mtd: spi-nor-core: add xSPI Octal DTR support

e data phase exists or not. This fixes data buswidth not being updadted for SR and FSR reads because they keep data buffer as NULL when calling spi_nor_setup_op(). - Add support for Micron mt35xu512aba to run in Octal DTR mode. Pratyush Yadav (21): spi: spi-mem: allow specifying whet

[PATCH v7 01/21] spi: spi-mem: allow specifying whether an op is DTR or not

Each phase is given a separate 'dtr' field so mixed protocols like 4S-4D-4D can be supported. Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mem.c | 3 +++ include/spi-mem.h | 8 2 files changed, 11 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index

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