DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
README|8
arch/powerpc/include/asm/config_mpc85xx.h |4
arch/powerpc/include/asm/fsl_law.h
side DDR controller as
memories are exactly similar.
Signed-off-by: Manish Jaggi
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
board/freescale/bsc9132qds/bsc9132qds.c | 22 ++
2 files changed, 28 insertions
Add support for Micron N25Q512A serial flash memory
Features: 64MB size, 1.8V, Multiple I/O, 4KB Sector erase
Memory is organised a 1024(64KB) main sectors.
Each sector is divided into 256 pages
Register set/Opcodes is similar to other N25Q family products
Signed-off-by: Priyanka Jain priyanka.j
DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi manish.ja...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Added Manish's email-id
README|8
arch/powerpc/include/asm
side DDR controller as
memories are exactly similar.
Signed-off-by: Manish Jaggi manish.ja...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Added Manish's email-id
arch/powerpc/include/asm/immap_85xx.h |6 ++
board/freescale/bsc9132qds
Add support for EON EN25S64 SPI flash memory
Features: 64Mb size, 1.8V, 4KB sector
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
drivers/mtd/spi/eon.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c
index
...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Dependent on nand_spl patch set(0001-0006)
http://patchwork.ozlabs.org/patch/229892/ to be present
board/freescale/bsc9131rdb/README |8 ++--
boards.cfg|2 ++
include/configs/BSC9131RDB.h
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: Priyanka Jain
.
For this bootargs are modified to pass parameter to create 1 hugetlb
page of 256MB via default_hugepagesz, hugepagesz and hugepages
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/bsc9131rdb/README | 10 ++
include/configs/BSC9131RDB.h |4 +++-
2 files changed
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/p1_p2_rdb/p1_p2_rdb.c |1 +
include/configs/P1_P2_RDB.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index fae31f2
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is being manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Acked-by: Timur Tabi ti
= timeout + 13 = log2(mmc-tran_speed/4) + 1
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Acked-by: Mingkai Hu mingkai...@freescale.com
---
Changes for v2:
Added proper
= timeout + 13 = log2(mmc-tran_speed/4) + 1
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Acked-by: Mingkai Hu mingkai...@freescale.com
---
Changes for v3:
Including code
= timeout + 13 = log2(mmc-tran_speed/4) + 1
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Acked-by: Mingkai Hu mingkai...@freescale.com
---
Changes for v3:
Including code
-boot code
-Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
include/configs/T1040RDB.h | 15 ---
1 files changed, 8 insertions(+), 7 deletions(-)
diff
-boot code
-Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
correct usb1 string for ;
include/configs/T1040RDB.h | 15 ---
1
0x06 which can
support following interfaces
-2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t104xrdb/Makefile |1 +
board/freescale/t104xrdb/eth.c| 72
0x06 which can
support following interfaces
-2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Initialized phy_addr to remove compilation warning.
board/freescale/t104xrdb/Makefile
interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/Makefile |1 +
board/freescale
register
-Bits definition of SCFG_PIXCLK register
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm
.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Vijay Rai vijay@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/README |4 ++--
board/freescale/t104xrdb/README |4 ++--
include/configs/T1040QDS.h |2
to off, as some board issues are observed.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/t104xrdb/ddr.c
to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka
interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Fix compilation warnings
Depends on http
interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Fix compilation warnings
board/freescale/t1040qds
Hello Shengzhou,
T1040 has two dual I2C controller.
First Dual I2C Controller : 0x118 (first i2c bus), 0x1181000(second I2C bus)
Second Dual I2C Controller : 0x119 (third i2c bus), 0x1191000(fourth I2C
bus)
My understanding is CONFIG_SYS_FSL_I2C_OFFSET is offset for first I2C
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Updated description based on Sun York's inputs
drivers/mmc/fsl_esdhc_spl.c |5 +
1 files changed, 5 insertions
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Updated description based on Sun York's inputs
drivers/mtd/spi/fsl_espi_spl.c |5 +
1 files changed, 5
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v3:
Send as independent patch (not as part of patch set)
Changes for v2:
Updated description based on Sun York's
mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v3:
Send as independent patch (not as part of patch set)
Changes for v2:
Updated description based on Sun York's
mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j
mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j
.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/ddr.h | 22 --
include/configs/T1040QDS.h |6 +++---
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git
.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Reduced I2C speed to 50KHz.
board/freescale/t1040qds/ddr.h | 22 --
include/configs/T1040QDS.h |6 +++---
2 files changed
in
normal clocking mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain
.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v3:
Updated
DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch setting
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t104xrdb/README
-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/eth.c |4
drivers/net/fm/t1040.c |2 --
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 1929bba..06d9086 100644
using DCSR space in PBI phase
Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t104xrdb/t104x_pbi.cfg | 10
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Add support for T1040RDB and T1042RDB_PI boards
T1040RDB and T1042RDB_PI are similar boards with few differences like
-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
board/freescale/t104xrdb/README | 38 ++
boards.cfg |1 +
include/configs/T1042RDB_PI.h | 709 +++
3 files changed, 748 insertions(+), 0 deletions
and immap_85xx.h to support all
T1040 personalities
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
arch/powerpc/include/asm/config_mpc85xx.h |3 ++-
arch/powerpc/include/asm/immap_85xx.h
, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
Changes for v2:
Updated defined in arch/powerpc/cpu
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Add support for T1040RDB and T1042RDB_PI boards
T1040RDB and T1042RDB_PI are similar boards with few differences like
poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
Depends on patch at http://patchwork.ozlabs.org/patch/284452/
Changes for v2:
Updated CONFIG_PPC to CONFIG_PPC_T1042
get
accidently erased or is not working properly during initial
bring-up. In that circumnstance, DDR raw timing structure can be
use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Update T1040QDS naem to Poonam Aggrwal.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
boards.cfg |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 5e10125..dfe1c59 100644
--- a/boards.cfg
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
This patch depends upon following patches:
1)[U-Boot] powerpc/t1040qds: Add DDR Raw
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Incorporated Wolfgang Denk's review comments
Based on u-boot-mpc85xx/next branch.
This patch depends upon
be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
drivers/mtd/spi/fsl_espi_spl.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index 6263d8c..e5ac79b
SPI flash
to DDR and transfer control to final u-boot.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
This patch depends upon following patches:
1)[U-Boot] powerpc/t1040: enable PBL tool for T1040
http://patchwork.ozlabs.org/patch/279366/
2
be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
drivers/mmc/fsl_esdhc_spl.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index 65c52a2..8fc263f 100644
card
to DDR and transfer control to final u-boot.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
This patch depends upon following patches:
1)[U-Boot,2/2] T1040QDS: Add support of 2 stage SPI bootloader
http://patchwork.ozlabs.org/patch
support
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Incorporated Wolfgang Denk's review comments
Based on u-boot-mpc85xx/next branch
/t1040qds: Add DDR Raw Timing support
On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR:
Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10).
Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and
calculating values
code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Change-Id: I1d2240fe424ecda55a9028190108a2677228ade5
Reviewed-on: http://git.am.freescale.net:8181/9839
Tested
: Wednesday, March 26, 2014 4:19 AM
To: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH 2/2] T1040QDS: Add support of 2 stage SPI
bootloader
Dear Priyanka Jain,
Priyanka Jain Priyanka.Jain at freescale.com writes:
Add support of 2-stage T1040QDS SPI bootloader using SPL framework
code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Corrected Signed-off footer
drivers/net/fm/memac_phy.c | 12
1 files changed
@@ -1,97 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Author: Priyanka Jain priyanka.j...@freescale.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include common.h
-#include command.h
-#include linux/ctype.h
-#include asm/io.h
-#include stdio_dev.h
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
arch/powerpc/cpu/mpc85xx/t1040_ids.c | 26 +++---
1 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index a5dfb81..2903d57
Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t102xqds/t1024_pbi.cfg |2 +-
board/freescale/t102xrdb/t1024_pbi.cfg |2 +-
board/freescale/t1040qds
sw variable in checkboard function is storing vbank value
which can only take 4-bit value.
So check of sw value for if greater than 7 is redundant.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t104xrdb/t104xrdb.c |5 +
1 files changed, 1 insertions(+), 4
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
changes from
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
changes from
RTC devices can generate 32KHz output if for
-DS3232 device, EN32KHz bit and BB32KHz bit are set
-DS3231 device, EN32KHz bit is set, BB32KHz bit is don't care
Patch adds rtc_enable_32khz_output() which when called
will enable 32KHz output on 32KHz pin
Signed-off-by: Priyanka Jain priyanka.j
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on git://git.denx.de/u-boot-fsl-qoriq
board/freescale/ls2085aqds/ls2085aqds.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c
b/board/freescale/ls2085aqds
-
From: Sun York-R58495
Sent: Tuesday, June 30, 2015 4:58 AM
To: Jain Priyanka-B32167; u-boot@lists.denx.de
Cc: Ciubotariu Codrin Constantin-B43658; Wang Dongsheng-B40534
Subject: Re: [PATCH][v7] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support
On 06/05/2015 02:59 AM, Priyanka Jain wrote
-Original Message-
From: Sun York-R58495
Sent: Tuesday, July 28, 2015 12:37 AM
To: Jain Priyanka-B32167; u-boot@lists.denx.de
Subject: Re: [PATCH] mpc85xx/T104xRDB: Remove vbank check redundant
code
On 05/17/2015 11:31 PM, Priyanka Jain wrote:
sw variable in checkboard
sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Corrected description to check is for 3-bit value
board/freescale
Hello York,
For T1040QDS, we can change the name.
For T1024 also, I think there should not be any issue. Shengzhou please confirm.
Regards
Priyanka
From: Sun York-R58495
Sent: Monday, August 10, 2015 8:18 PM
To: Jain Priyanka-B32167; Sun York-R58495; U-Boot Mailing List
Cc: Wood Scott-B07421;
Hello York,
T1040D4RDB/T1042D4RDB boards have other difference as well apart from DDR4
w.r.t old T1040RDB/T1042RDB.
T1040D4RDB/T1042D4RDB is the naming convection that has been used to
distinguished new T1040RDB/T1042RDB board with DDR4 memory, new serdes protocol
support , new muxes , etc.
> -Original Message-
> From: york sun
> Sent: Tuesday, February 07, 2017 10:38 PM
> To: Priyanka Jain <priyanka.j...@nxp.com>; u-boot@lists.denx.de
> Cc: Arpit Goel <arpit.g...@nxp.com>
> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
>
&
> -Original Message-
> From: york sun
> Sent: Friday, January 27, 2017 11:13 PM
> To: Priyanka Jain <priyanka.j...@nxp.com>; u-boot@lists.denx.de
> Cc: Arpit Goel <arpit.g...@nxp.com>
> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
>
&
Erratum A009635 is valid only for LS2080A SoC and its
personality.
Add SoC svr check for execution
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c |9 -
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu
Based on latest hardware documentation,
update ccsr_gur structure (represents DCFG register map)
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
Signed-off-by: Arpit Goel <arpit.g...@nxp.com>
---
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 65 ++--
1 f
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
Signed-off-by: Arpit Goel <arpit.g...@nxp.com>
---
board/freescale/ls2080aqds/ls2080aqds.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescal
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
LS2088A, LS2080A differs from existing logic.
-VDD voltage array is different
-Registers are different
-VDD calculation logic is different
Add new function adjust_vdd() for LSCH3 compliant SoCs
Signed-off-by: Priyanka Jain
Priyanka Jain (3):
armv8: fsl-layerscape: Updates DCFG register map.
armv8: fsl-lsch3: Update VID support
armv8: fsl-layerscape: Add vid support for LS2080AQDS.
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 69 ++---
board/freescale/common/vid.c | 174
It is recommended to set forced-order mode in RNI-6,
RNI-20 for performance optimization in LS2088A.
Both LS2080A, LS2088A families has CONFIG_LS2080A define.
As above update is required only for LS2088A, skip this
for LS2080A SoC family
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.
From: Priyanka Jain <priyanka.j...@freescale.com>
LS2088A is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)Process to release secondary cores is different
4)LS2088A SoC has TZASC controller
In preparation of using same
LS2080 SoC and its personalities does not support TZASC
But other new SoCs like LS2088A, LS1088A supports TASC
Hence, skip initializing TZASC for Ls2080A based on SVR
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layersca
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
arch/a
NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one to avoid power spike.
Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs
Signed-off-by: Priyanka
Timer base address has been changed from LS2080A SoC to
new SoCs like LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
---
The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layersca
NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one to avoid power spike.
Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs
Signed-off-by: Priyanka
LS2080 SoC and its personalities does not support TZASC
But other new SoCs like LS2088A, LS1088A supports TASC
Hence, skip initializing TZASC for Ls2080A based on SVR
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
arch/a
From: Priyanka Jain <priyanka.j...@freescale.com>
LS2088A is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)Process to release secondary cores is different
4)LS2088A SoC has TZASC controller
In preparation of using same
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: Thursday, October 20, 2016 9:03 AM
> To: u-boot@lists.denx.de
> Cc: Priyanka Jain <priyanka.j...@nxp.com>
> Subject: RE: [U-Boot] [PATCH 4/5] armv8: fsl-layerscape: Add NXP LS2088A
> SoC support
>
Firmware of Management Complex (MC) should be loaded at 512MB aligned
address.
So use aligned address for firmware load.
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
Signed-off-by: Ashish Kumar <ashis
Timer base address has been changed from LS2080A SoC to
new SoCs like LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
---
Ch
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
---
drivers/net/ldpaa_eth/ldpaa_eth.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 75b2b6b..4e61700 100644
--- a/drivers/net/ldp
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