-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/eth.c |4
drivers/net/fm/t1040.c |2 --
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 1929bba..06d9086 100644
DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch setting
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t104xrdb/README
Hello Shengzhou,
T1040 has two dual I2C controller.
First Dual I2C Controller : 0x118 (first i2c bus), 0x1181000(second I2C bus)
Second Dual I2C Controller : 0x119 (third i2c bus), 0x1191000(fourth I2C
bus)
My understanding is CONFIG_SYS_FSL_I2C_OFFSET is offset for first I2C
@@ -1,97 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Author: Priyanka Jain priyanka.j...@freescale.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include common.h
-#include command.h
-#include linux/ctype.h
-#include asm/io.h
-#include stdio_dev.h
code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Corrected Signed-off footer
drivers/net/fm/memac_phy.c | 12
1 files changed
: Wednesday, March 26, 2014 4:19 AM
To: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH 2/2] T1040QDS: Add support of 2 stage SPI
bootloader
Dear Priyanka Jain,
Priyanka Jain Priyanka.Jain at freescale.com writes:
Add support of 2-stage T1040QDS SPI bootloader using SPL framework
code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Change-Id: I1d2240fe424ecda55a9028190108a2677228ade5
Reviewed-on: http://git.am.freescale.net:8181/9839
Tested
interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Fix compilation warnings
Depends on http
interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Fix compilation warnings
board/freescale/t1040qds
to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka
to off, as some board issues are observed.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/t104xrdb/ddr.c
.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Vijay Rai vijay@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/README |4 ++--
board/freescale/t104xrdb/README |4 ++--
include/configs/T1040QDS.h |2
interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/Makefile |1 +
board/freescale
register
-Bits definition of SCFG_PIXCLK register
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm
0x06 which can
support following interfaces
-2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Initialized phy_addr to remove compilation warning.
board/freescale/t104xrdb/Makefile
-boot code
-Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
correct usb1 string for ;
include/configs/T1040RDB.h | 15 ---
1
0x06 which can
support following interfaces
-2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t104xrdb/Makefile |1 +
board/freescale/t104xrdb/eth.c| 72
-boot code
-Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
include/configs/T1040RDB.h | 15 ---
1 files changed, 8 insertions(+), 7 deletions(-)
diff
.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v3:
Updated
in
normal clocking mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain
.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Reduced I2C speed to 50KHz.
board/freescale/t1040qds/ddr.h | 22 --
include/configs/T1040QDS.h |6 +++---
2 files changed
mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j
.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/t1040qds/ddr.h | 22 --
include/configs/T1040QDS.h |6 +++---
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git
mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v3:
Send as independent patch (not as part of patch set)
Changes for v2:
Updated description based on Sun York's
mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v3:
Send as independent patch (not as part of patch set)
Changes for v2:
Updated description based on Sun York's
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Updated description based on Sun York's inputs
drivers/mmc/fsl_esdhc_spl.c |5 +
1 files changed, 5 insertions
values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2:
Updated description based on Sun York's inputs
drivers/mtd/spi/fsl_espi_spl.c |5 +
1 files changed, 5
support
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Incorporated Wolfgang Denk's review comments
Based on u-boot-mpc85xx/next branch
/t1040qds: Add DDR Raw Timing support
On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR:
Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10).
Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and
calculating values
be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
drivers/mmc/fsl_esdhc_spl.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index 65c52a2..8fc263f 100644
card
to DDR and transfer control to final u-boot.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
This patch depends upon following patches:
1)[U-Boot,2/2] T1040QDS: Add support of 2 stage SPI bootloader
http://patchwork.ozlabs.org/patch
be defined in board
specific config file.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
drivers/mtd/spi/fsl_espi_spl.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index 6263d8c..e5ac79b
SPI flash
to DDR and transfer control to final u-boot.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
This patch depends upon following patches:
1)[U-Boot] powerpc/t1040: enable PBL tool for T1040
http://patchwork.ozlabs.org/patch/279366/
2
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Incorporated Wolfgang Denk's review comments
Based on u-boot-mpc85xx/next branch.
This patch depends upon
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
This patch depends upon following patches:
1)[U-Boot] powerpc/t1040qds: Add DDR Raw
get
accidently erased or is not working properly during initial
bring-up. In that circumnstance, DDR raw timing structure can be
use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Update T1040QDS naem to Poonam Aggrwal.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
boards.cfg |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 5e10125..dfe1c59 100644
--- a/boards.cfg
, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
Changes for v2:
Updated defined in arch/powerpc/cpu
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Add support for T1040RDB and T1042RDB_PI boards
T1040RDB and T1042RDB_PI are similar boards with few differences like
poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
Depends on patch at http://patchwork.ozlabs.org/patch/284452/
Changes for v2:
Updated CONFIG_PPC to CONFIG_PPC_T1042
and immap_85xx.h to support all
T1040 personalities
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
arch/powerpc/include/asm/config_mpc85xx.h |3 ++-
arch/powerpc/include/asm/immap_85xx.h
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Add support for T1040RDB and T1042RDB_PI boards
T1040RDB and T1042RDB_PI are similar boards with few differences like
-by: Priyanka Jain priyanka.j...@freescale.com
---
Based on u-boot-mpc85xx/next branch.
board/freescale/t104xrdb/README | 38 ++
boards.cfg |1 +
include/configs/T1042RDB_PI.h | 709 +++
3 files changed, 748 insertions(+), 0 deletions
Add support for EON EN25S64 SPI flash memory
Features: 64Mb size, 1.8V, 4KB sector
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
drivers/mtd/spi/eon.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c
index
DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi manish.ja...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Added Manish's email-id
README|8
arch/powerpc/include/asm
side DDR controller as
memories are exactly similar.
Signed-off-by: Manish Jaggi manish.ja...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Added Manish's email-id
arch/powerpc/include/asm/immap_85xx.h |6 ++
board/freescale/bsc9132qds
Add support for Micron N25Q512A serial flash memory
Features: 64MB size, 1.8V, Multiple I/O, 4KB Sector erase
Memory is organised a 1024(64KB) main sectors.
Each sector is divided into 256 pages
Register set/Opcodes is similar to other N25Q family products
Signed-off-by: Priyanka Jain priyanka.j
DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
README|8
arch/powerpc/include/asm/config_mpc85xx.h |4
arch/powerpc/include/asm/fsl_law.h
side DDR controller as
memories are exactly similar.
Signed-off-by: Manish Jaggi
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
board/freescale/bsc9132qds/bsc9132qds.c | 22 ++
2 files changed, 28 insertions
.
For this bootargs are modified to pass parameter to create 1 hugetlb
page of 256MB via default_hugepagesz, hugepagesz and hugepages
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/bsc9131rdb/README | 10 ++
include/configs/BSC9131RDB.h |4 +++-
2 files changed
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: Priyanka Jain
...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Dependent on nand_spl patch set(0001-0006)
http://patchwork.ozlabs.org/patch/229892/ to be present
board/freescale/bsc9131rdb/README |8 ++--
boards.cfg|2 ++
include/configs/BSC9131RDB.h
= timeout + 13 = log2(mmc-tran_speed/4) + 1
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Acked-by: Mingkai Hu mingkai...@freescale.com
---
Changes for v3:
Including code
= timeout + 13 = log2(mmc-tran_speed/4) + 1
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Acked-by: Mingkai Hu mingkai...@freescale.com
---
Changes for v2:
Added proper
= timeout + 13 = log2(mmc-tran_speed/4) + 1
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Acked-by: Mingkai Hu mingkai...@freescale.com
---
Changes for v3:
Including code
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is being manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Acked-by: Timur Tabi ti
-by: Priyanka Jain priyanka.j...@freescale.com
---
board/freescale/p1_p2_rdb/p1_p2_rdb.c |1 +
include/configs/P1_P2_RDB.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index fae31f2
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
PT7C4338 chip is manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Freescale P1010RDB uses PT7C4338 as RTC.
Signed-off-by: Priyanka Jain priyanka.j
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