The HSS source uses an "mpfs" prefix with the icicle board name. Change our
documentation to match.
Signed-off-by: Sean Anderson
---
doc/board/microchip/mpfs_icicle.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/board/microchip/mpfs_icicle.rst
b
This define was left over from a previous revision, and was never used.
Signed-off-by: Sean Anderson
Reviewed-by: Heinrich Schuchardt
Reviewed-by: Bin Meng
---
Changes in v2:
- Rebase onto u-boot/master
include/configs/sipeed-maix.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a
Fix build error without CONFIG_CLK
Changes in v2:
- Fix fls being off-by-one when compared to log_2_n_round_up
- Move watchdog enable to k210.dtsi as it does not depend on anything
board-specific.
Sean Anderson (6):
wdt: dw: Switch to using fls for log2
wdt: dw: Switch to if(CONFIG()) instead of
log_2_n_round_up is only found in arm. fls performs the same job and is
generic.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Fix fls being off-by-one when compared to log_2_n_round_up
drivers/watchdog/designware_wdt.c | 3 +--
1 file
This is preferred over #if because the compiler can check syntax even if
the feature is disabled. This cannot be used for CONFIG_CLK because
CONFIG_DW_WDT_CLOCK_KHZ is not defined on all platforms.
Signed-off-by: Sean Anderson
Reviewed-by: Heinrich Schuchardt
---
(no changes since v1
The watchdog won't work if the clock isn't enabled.
Fixes: cf89ef8d10f240554541c20b2e1bdcdd58d1d7e6
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
(no changes since v1)
drivers/watchdog/designware_wdt.c | 4
1 file changed, 4 insertions(+)
diff --git a/driver
This adds the necessary bindings. Most of them are already there.
Signed-off-by: Sean Anderson
Acked-by: Rick Chen
---
(no changes since v2)
Changes in v2:
- Move watchdog enable to k210.dtsi as it does not depend on anything
board-specific.
arch/riscv/dts/k210.dtsi | 1 -
1 file changed
This enables the necessary config options.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
(no changes since v1)
board/sipeed/maix/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
index 2cdea8ea81..adf6abb572 100644
The clock subsystem requires that clk_free be called on clocks obtained via
clk_get_*.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
(no changes since v4)
Changes in v4:
- Fix build error without CONFIG_CLK
drivers/watchdog/designware_wdt.c | 18 +-
1 file
On 3/10/21 9:42 PM, Tom Rini wrote:
On Wed, Mar 10, 2021 at 08:45:27PM -0500, Sean Anderson wrote:
strn(cat|cpy) has a bad habit of not nul-terminating the destination,
resulting in constructions like
strncpy(foo, bar, sizeof(foo) - 1);
foo[sizeof(foo) - 1] = '\0'
provide a much
better interface, which removes some footguns from U-Boot.
Changes in v2:
- Fix strlcpy return value
- Add implementation of strlcat
- Add test for strlcat
- Fix bug in fastboot
- Move check to u_boot_line
Sean Anderson (5):
lib: string: Fix strlcpy return value
lib: string
implementation.
Signed-off-by: Sean Anderson
---
Changes in v2:
- New
drivers/usb/dwc3/linux-compat.h | 6 --
include/linux/string.h | 3 +++
lib/string.c| 19 +++
3 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3
strlcpy should always return the number of bytes copied. We were
accidentally missing the nul-terminator. We also always used to return a
non-zero value, even if we did not actually copy anything.
Fixes: 23cd138503 ("Integrate USB gadget layer and USB CDC driver layer")
Signed-of
This test is adapted from glibc, which is very concerned about alignment.
It also tests strlcpy by dependency.
Signed-off-by: Sean Anderson
---
Changes in v2:
- New
test/lib/Makefile | 1 +
test/lib/strlcat.c | 126 +
2 files changed, 127
rn(cat|cpy).
[1] https://lists.denx.de/pipermail/u-boot/2021-March/442888.html
[2] https://lists.denx.de/pipermail/u-boot/2021-January/438073.html
Signed-off-by: Sean Anderson
---
Changes in v2:
- Move check to u_boot_line
scripts/checkpatch.pl | 6 ++
tools/patman/test_checkpat
This fixes several uses of strn(cpy|cat) which did not terminate their
destinations properly.
Fixes de1728ce4c ("fastboot: Allow u-boot-style partitions")
Reported-by: Coverity Scan
Signed-off-by: Sean Anderson
---
Changes in v2:
- New
drivers/fastboot/fb_mmc.c | 6 +++---
1 file
);
else if (!uc_priv->clock_rate)
uc_priv->clock_rate = SANDBOX_TIMER_RATE;
Reviewed-by: Sean Anderson
On 3/16/21 12:05 AM, Padmarao Begari wrote:
Hi Sean,
On Thu, Mar 11, 2021 at 7:18 AM Sean Anderson mailto:sean...@gmail.com>> wrote:
The HSS source uses an "mpfs" prefix with the icicle board name. Change our
documentation to match.
Signed-off-by: Sean Ande
On 3/16/21 12:15 AM, Padmarao Begari wrote:
Hi Sean,
On Tue, Mar 16, 2021 at 9:52 AM Sean Anderson mailto:sean...@gmail.com>> wrote:
On 3/16/21 12:05 AM, Padmarao Begari wrote:
> Hi Sean,
>
> On Thu, Mar 11, 2021 at 7:18 AM Sean Anderson mailto:se
On 2/26/21 3:00 PM, Sean Anderson wrote:
On 2/26/21 5:25 AM, Jagan Teki wrote:
On Fri, Feb 5, 2021 at 9:41 AM Sean Anderson wrote:
This series adds support for enhanced SPI modes. It was tested on a K210 (DWC
SSI with QSPI flash).
If anyone has a designware device with QSPI flash attached
On 3/16/21 4:51 AM, Heinrich Schuchardt wrote:
On 11.03.21 02:48, Sean Anderson wrote:
The HSS source uses an "mpfs" prefix with the icicle board name. Change our
documentation to match.
Signed-off-by: Sean Anderson
---
doc/board/microchip/mpfs_icicle.rst | 6 +++---
1 file
arent(mux, parent);
- else
- return -ENOTSUPP;
+ if (!mux || !mux_ops)
+ return -ENOSYS;
+
+ return mux_ops->set_parent(mux, parent);
}
static unsigned long clk_composite_recalc_rate(struct clk *clk)
Reviewed-by: Sean Anderson
Will this be applie
On 3/20/21 11:18 PM, Simon Glass wrote:
We don't need to check -ENOTSUPP since this is not used for this purpose
in U-Boot. Update the code accordingly.
Signed-off-by: Simon Glass
---
drivers/core/simple-pm-bus.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/driv
On 3/21/21 9:34 PM, Trevor Woerner wrote:
Add the dts file for the Olimex Olinuxino from the linux kernel, and enable
its use in this machine's defconfig.
Signed-off-by: Trevor Woerner
---
arch/arm/dts/Makefile| 3 +
arch/arm/dts/imx23-olinuxino.dts | 131 ++
if passed 0. */
- beq a1, zero, longjmp_1
- mv a0, a1
- ret
-
- longjmp_1:
- li a0, 1
+ seqz a0, a1
+ add a0, a0, a1
ret
ENDPROC(longjmp)
.popsection
--
2.30.2
Reviewed-by: Sean Anderson
On 3/22/21 8:04 AM, Fabio Estevam wrote:
Hi Haibo,
On Mon, Mar 22, 2021 at 8:09 AM wrote:
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -102,6 +102,7 @@
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
+ fsl,signal-voltage
On 3/22/21 7:02 AM, Heinrich Schuchardt wrote:
The value returned by setjmp must be nonzero. If zero is passed as
parameter it must be replaced by 1.
This patch reduces the code size a bit.
Signed-off-by: Heinrich Schuchardt
Sean Anderson
You are missing something here.
---
v2
We need this header for U_BOOT_CMD, which is always present even without
EFI.
Fixes: 82c468a049 dm: test: Update Makefile conditions
Signed-off-by: Sean Anderson
---
test/print_ut.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/print_ut.c b/test/print_ut.c
index
_ret(i));
+ return 0;
+}
+LIB_TEST(lib_test_longjmp, 0);
--
2.30.2
Reviewed-by: Sean Anderson
Tested-by: Sean Anderson
Though I would like to test that variables are set correctly e.g. by doing
int test_longjmp_ret(int i)
{
jmp_buf env;
int ret;
ret = setjmp(env);
i
On 3/7/21 7:34 PM, Simon Glass wrote:
Move this function into test-main so that all the init is in one place.
Rename it so that its purpose is clearer.
Signed-off-by: Simon Glass
---
(no changes since v1)
include/test/ut.h | 9 -
test/dm/test-dm.c | 22 --
tes
On 3/22/21 9:23 AM, Sean Anderson wrote:
On 3/22/21 7:02 AM, Heinrich Schuchardt wrote:
Provide a unit test for the longjmp() library function
Signed-off-by: Heinrich Schuchardt
---
v2:
no change
---
test/lib/Makefile | 1 +
test/lib/longjmp.c | 44
--- a/drivers/clk/kendryte/bypass.c
+++ b/drivers/clk/kendryte/bypass.c
@@ -157,7 +157,7 @@ static int k210_bypass_set_parent(struct clk *clk, struct
clk *parent)
if (ops->set_parent)
return ops->set_parent(bypass->bypassee, parent);
else
- ret
struct clk_bulk *bulk = dev_get_priv(dev);
ret = clk_release_bulk(bulk);
- if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+ if (ret && ret != -ENOSYS)
return ret;
else
return 0;
Reviewed-by: Sean Anderson
On 3/23/21 12:14 AM, Simon Glass wrote:
Driver model uses quite strong conventions on error codes, but these are
currently not clearly documented. Add a description of the commonly used
errors.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add a patch to document the common error codes
do
On 3/22/21 12:42 PM, Heinrich Schuchardt wrote:
On 22.03.21 14:30, Sean Anderson wrote:
On 3/22/21 9:23 AM, Sean Anderson wrote:
On 3/22/21 7:02 AM, Heinrich Schuchardt wrote:
Provide a unit test for the longjmp() library function
Signed-off-by: Heinrich Schuchardt
---
v2:
no change
On 3/23/21 9:48 AM, Ying-Chun Liu wrote:
> From: "Ying-Chun Liu (PaulLiu)"
>
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop
On 3/23/21 4:35 AM, Green Wan wrote:
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the calback, they must be able
nit: callback
to run the same setup.
Signed-of
On 3/23/21 4:35 AM, Green Wan wrote:
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
-boot.10912.n7.nabble.com/PATCH-v2-time-Fix-get-ticks-being-non-monotonic-td426172.html
Sean Anderson asks:
"So nothing here is probed, but additionally nothing has UCLASS_TIMER.
What do you expect the timer device to be?"
There are timers on the board. How come it used to work, before
On 3/23/21 1:40 AM, Simon Glass wrote:
HI Sean,
On Tue, 23 Mar 2021 at 17:45, Sean Anderson wrote:
On 3/23/21 12:14 AM, Simon Glass wrote:
Driver model uses quite strong conventions on error codes, but these are
currently not clearly documented. Add a description of the commonly used
errors
On 3/24/21 5:26 PM, Simon Glass wrote:
Driver model uses quite strong conventions on error codes, but these are
currently not clearly documented. Add a description of the commonly used
errors.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add updates based on feedback from Sean Anderson
On 3/11/21 12:15 AM, Sean Anderson wrote:
strlcpy should always return the number of bytes copied. We were
accidentally missing the nul-terminator. We also always used to return a
It looks like I was a bit bullish in assuming a mistake. After reviewing
the man page, it looks like the nul
On 3/24/21 8:38 PM, Simon Glass wrote:
Hi Sean,
On Thu, 11 Mar 2021 at 18:15, Sean Anderson wrote:
strlcpy should always return the number of bytes copied. We were
accidentally missing the nul-terminator. We also always used to return a
non-zero value, even if we did not actually copy
On 3/23/21 10:01 PM, Ying-Chun Liu (PaulLiu) wrote:
Hi Sean,
Thanks for the review. I fix almost of the issues. Will upload the v3 soon.
Still have some questions.
Sean Anderson 於 2021/3/23 下午11:06 寫道:
if (anatop_reg->supply) {
ret = regulator_set_value(anatop_
B).
> This patch adds the Anatop regulator driver.
>
> Signed-off-by: Ying-Chun Liu (PaulLiu)
> Cc: Fabio Estevam
> Cc: Jaehoon Chung
> Cc: Peng Fan
> Cc: Sean Anderson
> ---
> v2: add functions for set selector and delay. Define ANATOP_REGULATOR_STEP
> v3: add vin-
On 3/25/21 2:44 PM, Ying-Chun Liu wrote:
From: "Ying-Chun Liu (PaulLiu)"
Document the bindings for fsl,anatop-regulator
Signed-off-by: Ying-Chun Liu (PaulLiu)
Cc: Fabio Estevam
Cc: Jaehoon Chung
Cc: Peng Fan
Cc: Sean Anderson
---
.../regulator/fsl,anatop-regulator.txt
On 3/25/21 9:22 PM, Leo Liang wrote:
Hi Green,
On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote:
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the calback
On 3/24/21 5:44 PM, Simon Glass wrote:
Due to a recent change, tests are limited to running on sandbox only.
Correct this so that any architecture can run them.
Signed-off-by: Simon Glass
Reported-by: Sean Anderson
Fixes: c79705ea938 ("test: Move dm_test_init() into test-m
We need this header for U_BOOT_CMD, which is always present even without
EFI.
Fixes: 82c468a049 ("dm: test: Update Makefile conditions")
Signed-off-by: Sean Anderson
---
Changes in v2:
- Remove ifdef
test/print_ut.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/test/print_u
the Anatop regulator driver.
Signed-off-by: Ying-Chun Liu (PaulLiu)
Cc: Fabio Estevam
Cc: Jaehoon Chung
Cc: Peng Fan
Cc: Sean Anderson
---
v2: add functions for set selector and delay. Define ANATOP_REGULATOR_STEP
v3: add vin-supply. move regmap retrival to probe
v4: check control_reg and return -ENOSY
On 3/26/21 10:18 PM, Green Wan wrote:
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the callback, they must be able
to run the same setup.
Signed-off-by: Green Wan
4_FEATURE_DISABLE, 0);
+ }
These braces are not strictly necessary.
+}
+
int spl_board_init_f(void)
{
int ret;
Reviewed-by: Sean Anderson
This macro clarifies accesses, and eliminates the need to have a
separate shift define.
Signed-off-by: Sean Anderson
---
arch/arm/include/asm/mach-imx/sys_proto.h | 5 +
arch/arm/mach-imx/spl.c | 8
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a
ve DT")
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
Changes in v3:
- Fix assuming any nonzero return of dev_count_phandle_with_args was an error.
Changes in v2:
- Change Fixes tag to the most recent commit touching these lines
drivers/gpio/gpio-uclass.c | 6 +++---
1 file
antee.
- Reorder includes
- Set BOARD_HWVERSION to SYSINFO_ID_REVISION, as they represent the same
content.
- Use enums instead of defines for sysinfo ids
Sean Anderson (5):
dm: gpio: Fix gpio_get_list_count failing with livetree
sysinfo: Use global sysinfo IDs for existing sysinfo dr
Since 07c9e683a4 ("smbios: Allow a few values to come from sysinfo")
there are common global sysinfo IDs. This patch moved existing IDs above
SYSINFO_ID_USER.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
Changes in v3:
- Rework patch to use sjg's sysinfo IDs
Chang
This has the uclass enforce calling detect() before other methods. This
allows drivers to cache information in detect() and perform (cheaper)
retrieval in the other accessors. This also modifies the only instance
where this sequencing was not followed.
Signed-off-by: Sean Anderson
Reviewed-by
This uses the newly-added dm_gpio_get_values_as_int_base3 function to
implement a sysinfo device. The revision map is stored in the device tree.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
Changes in v3:
- Fix assuming nonzero return from dm_gpio_get_values_as_int_base3 is an
This adds a test for the gpio-sysinfo driver.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
Changes in v3:
- Use SYSINFO_ID_BOARD_MODEL instead of SYSINFO_ID_REVISION
Changes in v2:
- Reorder includes
arch/sandbox/dts/test.dts | 7
test/dm/Makefile | 1 +
test/dm
d the
first config is *not* the default.
Signed-off-by: Sean Anderson
---
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 9 -
arch/arm/mach-rockchip/spl.c| 10 --
common/common_fit.c | 5 +
3 files changed, 5 insertions(+), 19 deletions(-)
diff --
*slave,
+const struct spi_mem_op *op);
+
int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op);
bool spi_mem_default_supports_op(struct spi_slave *mem,
Reviewed-by: Sean Anderson
c.f.
https://patchwork.ozlabs.org/project/uboot/patch
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drive
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
Hi,
This series adds support for octal DTR flashes in the SPI NOR framework,
As an overall question, is this the same as "DDR" mode?
--Sean
and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
flashes. Reviving this series after a lo
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", th
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them
On 3/30/21 1:26 AM, Green Wan wrote:
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the callback, they must be able
to run the same setup.
Signed-off-by: Green Wan
On 3/10/21 9:02 PM, Sean Anderson wrote:
Please merge! I don't want to have to keep rebasing.
Changes in v6:
- Rebase on u-boot/master
Changes in v5:
- Note dependency on "time: Fix get_ticks being non-monotonic"
- Add a few signed-off-bys which were sent for version 1
- R
- Fix some inconsistencies in register naming and usage
- Moved some hunks between commits so things make more sense
Sean Anderson (10):
mtd: spi-mem: Export spi_mem_default_supports_op
spi: spi-mem: Add debug message for spi-mem ops
spi: dw: Log status register on timeout
spi: dw: Actually mask
This is useful for extending the default functionality. This mirrors the
change in Linux commit 46109648052f ("spi: spi-mem: export
spi_mem_default_supports_op()").
Signed-off-by: Sean Anderson
Reviewed-by: Bin Meng
Reviewed-by: Pratyush Yadav
---
(no changes since v1)
include/spi
This logs the status register on timeout, so it is easier to determine the
cause of the failure.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi
printed with a format of %02Xh to match the notation commonly used in flash
datasheets.
Signed-off-by: Sean Anderson
Reviewed-by: Pratyush Yadav
---
(no changes since v2)
Changes in v2:
- Add more information to exec_op debug message
drivers/spi/spi-mem.c | 7 +++
1 file changed, 7
Writing 1s to this register *unmasks* interrupts. Mask them instead.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- Actually mask interrupts
drivers/spi/designware_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c
m being an
initialization function to being a set of default capabilities. This is
necessary since some capabilities cannot be determined at runtime.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 151 +--
1 file changed, 73
into several commits, but
several depend on each other, and it would be difficult to break this up
while preserving bisectability.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 284 +--
1 file changed, 171 insertions(+), 11
+QUAD+OCTAL and let the slave determine what we actually use.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- Merge CAP_{DUAL,QUAD,OCTAL} into CAP_ENHANCED
drivers/spi/designware_spi.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --
This adds some registers needed for DUAL/QUAD/OCTAL modes. It also adds the
fields in (R)ISR so we can check for over-/under-flow.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- Fix some inconsistencies in register naming and usage
drivers/spi/designware_spi.c | 60
will
result in the device never restarting reception if there is an overflow. On
the transmit side, we need to set CTRL1 so that the device knows when to
keep stretching the clock if the FIFO is empty.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 7 +
: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 136 ++-
1 file changed, 119 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index e110c5bca1..64a3a8556b 100644
--- a/drivers/spi
On 4/2/21 7:05 PM, Sean Anderson wrote:
This series adds support for enhanced SPI modes. It was tested on a K210 (DWC
SSI with QSPI flash).
If anyone has a designware device with QSPI flash attached (especially a DW SSI
APB device), I'd greatly appreciate them testing out this patch s
On 4/3/21 6:26 AM, Heinrich Schuchardt wrote:
Hello Sean,
thanks for getting MMC running on the MAIX.
Reading files works fine. But if try to write I get a failure:
=> save mmc 0:1 ${loadaddr} foo 0x100
mmc write failed
Error: writing contents
** Unable to write file foo **
=> ls mmc 0:1
** No
On 4/4/21 8:47 PM, Damien Le Moal wrote:
On 2021/04/03 8:05, Sean Anderson wrote:
This rewrites poll_transfer, dw_writer, and dw_reader.
* We now use RO transfers (instead of always using TR). This eliminates the
need to send out dummy words, and simplifies the transmit logic.
* All
On 4/5/21 7:47 AM, Tom Rini wrote:
On Mon, Apr 05, 2021 at 01:55:06PM +0530, Pratyush Yadav wrote:
On 02/04/21 06:21PM, Sean Anderson wrote:
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Sig
On 4/5/21 3:40 AM, Pratyush Yadav wrote:
On 02/04/21 06:31PM, Sean Anderson wrote:
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It
On 4/5/21 3:43 AM, Pratyush Yadav wrote:
On 02/04/21 06:28PM, Sean Anderson wrote:
On 4/1/21 3:31 PM, Pratyush Yadav wrote:
Hi,
This series adds support for octal DTR flashes in the SPI NOR framework,
As an overall question, is this the same as "DDR" mode?
Sort of...
DDR
On 4/6/21 4:10 PM, Marek Vasut wrote:
> On 4/6/21 9:52 PM, Tim Harvey wrote:
>> On Mon, Apr 5, 2021 at 10:36 AM Marek Vasut wrote:
>>>
>>> On 4/5/21 6:27 PM, Tim Harvey wrote:
On Sat, Apr 3, 2021 at 12:09 PM Marek Vasut wrote:
>
> On 4/3/21 6:43 PM, Tim Harvey wrote:
>
>
On 4/7/21 1:30 AM, Peng Fan (OSS) wrote:
Hi Stefano,
Hi Peng,
Did you address the following comments for "imx: hab/caam new feature
and update" from Horia Geantă?
On 3/31/21 8:32 AM, Horia Geantă wrote:
I don't think adding yet another caam driver (drivers/crypto/fsl_caam.c)
is a good idea.
On 4/7/21 3:02 PM, Giulio Benetti wrote:
This timer driver is using GPT Timer (General Purpose Timer) available
on almost all i.MX SoCs family. Since this driver is only meant to
provide u-boot's timer and counter, and most of the i.MX* SoCs use a
24Mhz crystal, let's only deal with that specific
If a phy is disabled, don't use it. This matches Linux's behavior.
Signed-off-by: Sean Anderson
---
drivers/net/fec_mxc.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ec21157d71..37eb894248 10
h phy
interfaces")
Signed-off-by: Sean Anderson
---
drivers/net/fec_mxc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 37eb894248..a64ba955a5 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
If there are no nodes or if all nodes are disabled, this function would
return err without setting it first. Fix this by initializing err to
zero.
Fixes: 94f7afdf7e ("dm: core: Ignore disabled devices when binding")
Signed-off-by: Sean Anderson
---
drivers/core/root.c | 2 +-
1 fi
ify PLL instantiation
- Modify clock tree so clint is a child of aclk
- Sync memory dts node with Linux
- Use correct aisram clock
Sean Anderson (11):
clk: Warn on failure to assign rate
clk: k210: Fix PLLs not being enabled
clk: k210: Fix PLL enable always getting taken
clk: k210: Remove
If the user/dev explicitly requests a clock be assigned a certain rate,
then we should warn them if we can't do it. This makes it clear if the
clock is running at the default rate.
Signed-off-by: Sean Anderson
---
Changes in v3:
- New
drivers/clk/clk-uclass.c | 11 +++
1 file ch
After starting or setting the rate of a PLL, the enable bit must be set.
This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/clk/kendryte/pll.c | 2 ++
1 file changed, 2 insertions
No other (real) clocks have the cpu clock as their parent; instead they are
children of aclk. Move the clint clock under aclk to match them.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
drivers/clk/kendryte/clk.c | 2 +-
1 file changed, 1 insertion(+), 1
This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
drivers/clk/kendryte/clk.c | 10 +++---
drivers/clk/kendryte/pll.c | 21 -
in
This conditional always evaluated as false, regardless of the value of reg.
Fix it so that it properly tests the bits in the PLL register. Also test
PLL_EN, now that we set it.
Reported-by: Damien Le Moal
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
drivers
Variables which had previously been stored in .bss are moved to .data. In
addition, probed needs to be reset when the clock driver is re-bound
post-relocation.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/clk/kendryte/clk.c | 14 ++
1 file changed, 10 insertions
We just need to initialize all the clocks pre-reloc. The clock driver
creates a bunch of devices, so we need to increase the pre-reloc malloc
arena.
Signed-off-by: Sean Anderson
---
(no changes since v1)
board/sipeed/maix/maix.c | 12 +++-
configs/sipeed_maix_bitm_defconfig
These devices are necessary for the clock driver, which is required by the
sram driver, to run pre-relocation.
Signed-off-by: Sean Anderson
---
(no changes since v1)
arch/riscv/dts/k210.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210
This is more consistent with the naming of other ram banks, and matches
what Linux is doing.
Reported-by: Damien Le Moal
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
arch/riscv/dts/k210.dtsi | 4 ++--
board/sipeed/maix/maix.c | 2 +-
2 files changed, 3
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