On Fri, Nov 19, 2010 at 11:56 PM, Paulraj, Sandeep s-paul...@ti.com wrote:
I came across this patch that might be useful
http://lists.denx.de/pipermail/u-boot/2010-February/067534.html
In any case since the u-boot structure has changed this cannot be applied.
If anybody is interested please
.
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Siarhei Siamashka
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725233: PLD instructions executed with PLD data forwarding
enabled can result in a processor deadlock
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
cpu/arm_cortexa8/omap3/board.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/cpu/arm_cortexa8
}\n
);
}
int main()
{
f(1000, rand);
return 0;
}
/ end of bench_ASA.c /
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
cpu/arm_cortexa8/omap3/board.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu
On Sunday 07 February 2010, Tom wrote:
Siarhei Siamashka wrote:
725233: PLD instructions executed with PLD data forwarding
enabled can result in a processor deadlock
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Please add a detailed comment on the errata.
The short
On Monday 08 February 2010, Måns Rullgård wrote:
Siarhei Siamashka siarhei.siamas...@gmail.com writes:
On Sunday 07 February 2010, Tom wrote:
Siarhei Siamashka wrote:
725233: PLD instructions executed with PLD data forwarding
enabled can result in a processor deadlock
Signed-off
on r1pX revisions of Cortex-A8 (used in
OMAP34xx/OMAP35xx). Performance impact of the workaround is practically
non-existant.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Revision history:
v2 - Comment text extended with a bit more information about the
affected Cortex-A8 core
requirements.
But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi
three commands 0x12, 0x17, 0x13
(Self-Refresh entry, Self-Refresh exit, Refresh), but in the u-boot they
have become 0x12, 0x12, 0x13 (Self-Refresh entry, Self-Refresh entry,
Refresh)
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 67
if such hardware actually exists.
As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.
Signed-off-by: Siarhei Siamashka
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors (found no result and found more than one
possible result). Both are handled now.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
, but performed the DDR3 reset very early. Possibly
resulting in a sufficient time gap between the DDR3 reset and the DDR3
initialization steps.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 45 ++---
1 file changed, 38
DRAM initialization
code appeared to be sufficient.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index
This configures the PLL5P clock frequency to something in the ballpark of
1GHz and allows more choices for MBUS and G2D clock frequency selection
(using their own divisors). In particular, it enables the use of 2/3 clock
speed ratio between MBUS and DRAM.
Signed-off-by: Siarhei Siamashka
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.
Signed-off-by: Siarhei Siamashka
Add the necessary missing bits from the legacy u-boot-sunxi for the
Allwinner A10 and A13 support (originally authored by Henrik Nordstrom,
Stefan Roese, Oliver Schinagl and Hans de Goede).
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 55
DDR3 initialiazation for a universal single bootloader
binary, which can be compatible with all Allwinner A10/A13/A20 based devices
(if the ifdefs are replaced with a runtime SoC type detection).
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 52
the older hardcoded settings.
Attempting to set the MBUS clock speed has no effect on sun4i, but does no
harm either.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c| 41 +-
arch/arm/include/asm/arch-sunxi
to settle with something more modest in the end.
But, for example, the DRAM in my Cubietruck can be clocked up to 648 MHz.
The preliminary DRAM parameters tuning instructions are available at:
http://linux-sunxi.org/A10_DRAM_Controller_Calibration
Siarhei Siamashka (14):
sunxi: dram: Remove useless
It is going to be useful in more than one place.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu
in the 'dram_tpr3' variable of the 'dram_para' struct (per-board dram
configuration). But none of the linux-sunxi devices has ever used it for
real. Basically, this code is just a dead weight.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 125
in the 'dram_para'
struct,
then ODT now actually gets enabled in the DRAM_IOCR register (which the older
code failed to do and was always running without ODT no matter the settings).
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c| 71
disabled, and this is not very nice for the performance. These two patches
make FEL boot mode more usable.
Siarhei Siamashka (2):
sunxi: Use Thumb2 and move stack to gain more SRAM space in FEL mode
sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
arch/arm/cpu/armv7/sunxi
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache
disabled.
Signed-off-by: Siarhei Siamashka
for program use area. Additionally, the BSS segment is cleared.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/start_fel.S| 42 +
arch/arm/cpu/armv7/sunxi/u-boot-spl
the initial
sun7i cleanup is done.
Is anyone really in a hurry to get this stuff pushed out of the
u-boot-sunxi tree to upstream right now? Can't we get a 'testing'
branch in the sunxi repository and have everything reviewed first?
--
Best regards,
Siarhei Siamashka
.
file_size is already aligned to BLOCK_SIZE before being stored in
img.header.length, so there is no need for load_size at all.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Acked-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Was there any valid
by simply removing the dma code, resulting in smaller bug-free
code.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Acked-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Was it a good idea to keep v2014.07 release relying on luck without
this patch
On Mon, 9 Jun 2014 11:36:56 +0200
Hans de Goede hdego...@redhat.com wrote:
There is no way to reset the cpu, so use the watchdog for this.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Acked-by: Siarhei Siamashka siarhei.siamas...@gmail.com
/sun4i.h
This patch is piling up a lot of various loosely related changes.
Isn't the addition of Cubieboard to boards.cfg kind of orthogonal
to the sun4i SoC variant support? This makes cherry picking or
reverting the patch unnecessarily difficult.
--
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Siarhei Siamashka
if there is a valid reason to bundle the addition of some example
sun5i based board to boards.cfg with the changes needed for sun5i SoC
variant, why is it *two* boards this time?
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Siarhei Siamashka
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problems?
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these boards in a later patch).
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Acked-by: Siarhei Siamashka siarhei.siamas...@gmail.com
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after the fact.
And again, this patch is currently rather cherry-picking unfriendly.
So even if I wanted to reorder the patches to trivially address the
problem, the interdependencies via the dreaded 'boards.cfg' get in the
way.
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Siarhei Siamashka
there)
in order to have bug free code after every commit instead of fixing
the problem after the fact.
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for this was taken
from the linux-sunxi.org kernels.
Signed-off-by: Jonathan Liu net...@gmail.com
[hdego...@redhat.com: Expanded the commit message with some more info]
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Acked-by: Siarhei Siamashka
anywhere in its current form.
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On Thu, 24 Jul 2014 11:18:15 +0800
Chen-Yu Tsai w...@csie.org wrote:
On Thu, Jul 24, 2014 at 11:12 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Thu, 5 Jun 2014 19:00:14 +0100
Ian Campbell i...@hellion.org.uk wrote:
This is a sun7i (A20) based followup to the sun4i (A10
On Thu, 24 Jul 2014 07:45:44 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Thu, 2014-07-24 at 06:12 +0300, Siarhei Siamashka wrote:
On Thu, 5 Jun 2014 19:00:14 +0100
Ian Campbell i...@hellion.org.uk wrote:
This is a sun7i (A20) based followup to the sun4i (A10)
Cubieboard
On Thu, 24 Jul 2014 11:00:31 -0400
Tom Rini tr...@ti.com wrote:
On Thu, Jul 24, 2014 at 03:47:53PM +0300, Siarhei Siamashka wrote:
On Thu, 24 Jul 2014 11:18:15 +0800
Chen-Yu Tsai w...@csie.org wrote:
On Thu, Jul 24, 2014 at 11:12 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com
, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache
disabled.
I
On Mon, 21 Jul 2014 19:31:45 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-07-18 at 20:09 +0300, Siarhei Siamashka wrote:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
I think a better reference is
https://github.com/hno/Allwinner-Info/blob/master
On Fri, 18 Jul 2014 20:09:44 +0300
Siarhei Siamashka siarhei.siamas...@gmail.com wrote:
The Allwinner SoCs support a special FEL boot mode, which can be activated
by users via a button press (or other means). In the FEL mode, the BROM
implements a custom FEL protocol over USB, which allows
On Mon, 21 Jul 2014 19:51:50 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.
The DRAM
On Mon, 21 Jul 2014 20:20:20 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
Moved the impedance setup code part into a separate function. Added explicit
wait for ZQ calibration completion before proceeding to the next
On Mon, 21 Jul 2014 20:31:30 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed.
Allwinner A13 uses only 16-bit data bus width to connect the external DRAM
On Mon, 21 Jul 2014 20:41:33 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote:
It is going to be useful in more than one place.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c
On Mon, 21 Jul 2014 20:51:12 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote:
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because
On Fri, 25 Jul 2014 07:52:28 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-07-25 at 00:12 +0300, Siarhei Siamashka wrote:
The multi-soc support (within the Allwinner A10/A13/A20 family) is the
feature, which is scheduled for this merge window. It is a present
piece of work
This is version 2 of
http://lists.denx.de/pipermail/u-boot/2014-July/183981.html
Rebased on git://git.denx.de/u-boot-sunxi.git master branch (commit
3340eab26d89176dd0bf543e6d2590665c577423 sun7i: Add bananapi board)
Siarhei Siamashka (16):
sunxi: dram: Remove useless 'dramc_scan_dll_para
power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.
The impedance and ODT configuration code will be re-introdeced in
one of the next comits.
Signed-off-by: Siarhei Siamashka
DRAM initialization
code appeared to be sufficient.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
- rebase on git://git.denx.de/u-boot-sunxi.git master and resolve
minor conflicts (udelay in two places instead of one)
arch/arm/cpu/armv7/sunxi/dram.c | 9
it was issuing three commands 0x12, 0x17,
0x13 (Self-Refresh entry, Self-Refresh exit, Refresh), but in the
u-boot they have become 0x12, 0x12, 0x13 (Self-Refresh entry,
Self-Refresh entry, Refresh)
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
- break lines
in the 'dram_tpr3' variable of the 'dram_para' struct (per-board
dram configuration). But none of the linux-sunxi devices has ever used
it for real. Basically, this code is just a dead weight.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Acked-by: Ian Campbell i...@hellion.org.uk
The old 'await_completion' function is not sufficient, because
in some cases we want to wait for bits to be cleared, and in the
other cases we want to wait for bits to be set. So split the
'await_completion' into two new 'await_bits_clear' and
'await_bits_set' functions.
Signed-off-by: Siarhei
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors (found no result and found more than one
possible result). Both are handled now.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
This configures the PLL5P clock frequency to something in the ballpark
of 1GHz and allows more choices for MBUS and G2D clock frequency
selection (using their own divisors). In particular, it enables the use
of 2/3 clock speed ratio between MBUS and DRAM.
Signed-off-by: Siarhei Siamashka
' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
- this is the last part half of the old patch [PATCH 05/14
priority.
Attempting to set the MBUS clock speed has no effect on sun4i, but does
no harm either.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
- update commit message to explain PLL5P vs. PLL6 selection,
as requested during review
- introduce
The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2
/sun5i. This resulted
in a larger time gap between the DDR3 reset and the DDR3 initialization
steps and reduced the chances of CKE delay timing violation to cause
real troubles.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
- use both methods for implementing
It is going to be useful in more than one place.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
- remove DRAM_DCR_NR_DLLCR_32BIT/DRAM_DCR_NR_DLLCR_16BIT/
DRAM_DCR_NR_DLLCR_8BIT macros
- handle only 4 and 2 lanes (32-bit and 16-bit bus width), just like
if such hardware actually exists.
As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.
Signed-off-by: Siarhei Siamashka
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.
Signed-off-by: Siarhei Siamashka
requirements.
But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2
DDR3 initialiazation for a universal single
bootloader binary, which can be compatible with all Allwinner
A10/A13/A20 based devices (if the ifdefs are replaced with a runtime
SoC type detection).
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Acked-by: Ian Campbell i...@hellion.org.uk
mode as a fallback. In the
case is this define is not provided, the failure to switch to
non-secure mode is treated as a fatal error and an appropriate
message is displayed.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/virt-dt.c | 3 +++
arch/arm/cpu/armv7
://lists.denx.de/pipermail/u-boot/2014-August/185200.html
Siarhei Siamashka (2):
sunxi: Replace CONFIG_SUN[457]I ifdefs with SOC_IS_SUN[457]I() calls
sunxi: Universal Allwinner A10/A13/A20 u-boot binary support
arch/arm/Kconfig| 3 +
arch/arm/cpu/armv7/sunxi
This is a purely mechanical conversion, replacing the ifdefs and
preparing the code for the use of runtime Allwinner SoC type
detection (within Allwinner A10/A13/A20 family).
Similar 'board_is_xxx()' calls are used for TI hardware.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
binary should be sufficient for booting
the system from SD card and/or getting the u-boot command
prompt on the serial console.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/Kconfig| 3 ++
arch/arm/cpu/armv7/sunxi/Makefile
the v7_dcache_inval_range function is noisy enough if anything
is wrong :-)
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On Wed, 14 May 2014 08:52:50 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Wed, 2014-05-14 at 10:44 +0300, Siarhei Siamashka wrote:
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 382b0c7..6d94b3a 100644
--- a/drivers/net/designware.h
+++ b/drivers/net
On Wed, 14 May 2014 11:01:59 +0300
Siarhei Siamashka siarhei.siamas...@gmail.com wrote:
On Wed, 14 May 2014 08:52:50 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Wed, 2014-05-14 at 10:44 +0300, Siarhei Siamashka wrote:
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
(and on the other ARM hardware, which
happens to use the same designware driver). Now everything looks
perfect. The whole v3 patch set with this v3.1 reorder fix is
Tested-by: Siarhei Siamashka siarhei.siamas...@gmail.com
and also if anybody cares
Reviewed-by: Siarhei Siamashka siarhei.siamas...@gmail.com
On Sun, 28 Sep 2014 21:34:57 +0200
Arnd Gronenberg a...@gronenberg.com wrote:
On 09/28/2014 05:58 PM, Hans de Goede wrote:
[...]
On 09/18/2014 06:07 PM, Siarhei Siamashka wrote:
Which revision of A10-OLinuXino-LIME do you have? Revision A is known
to have troubles running stable
On Sun, 28 Sep 2014 17:58:41 +0200
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 09/18/2014 06:07 PM, Siarhei Siamashka wrote:
On Sun, 27 Jul 2014 23:25:21 +0200
Hans de Goede hdego...@redhat.com wrote:
Which revision of A10-OLinuXino-LIME do you have? Revision A is known
to have
On Mon, 29 Sep 2014 08:38:42 +0300
Siarhei Siamashka siarhei.siamas...@gmail.com wrote:
On Sun, 28 Sep 2014 17:58:41 +0200
Hans de Goede hdego...@redhat.com wrote:
Do you have any easy step-by-step document (or ready to use sdcard
image to download) to do some stress tests on my revision
= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
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On Mon, 29 Sep 2014 20:16:35 +0200
Karsten Merker mer...@debian.org wrote:
On Mon, Sep 29, 2014 at 09:13:37AM +0300, Siarhei Siamashka wrote:
On Sun, 28 Sep 2014 20:13:21 +0200
Hans de Goede hdego...@redhat.com wrote:
In order for the gmac nic to work reliable on the Bananapi, we
) and the
sunxi-3.4 kernel compatibility tweaks is going to be available shortly
after the u-boot v2014.10 release.
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, but without the need to do
extra environment configuration gymnastics for the end users:
https://github.com/ssvb/u-boot-sunxi-dram/commit/e914abe551e712a59a8fc1ac9a4b8490e8e7c866
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the G2D driver and it needs
to run at a decent clock speed to be provide reasonable performance.
Low PLL5P clock speed is limiting our options.
This revert does not do anyone any favour and only postpones the
resolution of the problem.
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On Wed, 15 Oct 2014 11:31:44 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
On Wed, Oct 15 2014 at 11:25:10 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 12:13:05 +0200
Hans de Goede hdego...@redhat.com wrote:
Older Linux kernels will not properly boot
the safety guards (which exist
there for a reason!) without addressing the real compatibility
issues. This is a very bad idea in my opinion. We can do a better
job.
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On Wed, 15 Oct 2014 13:42:33 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
On Wed, Oct 15 2014 at 11:40:24 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 11:31:44 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
On Wed, Oct 15 2014 at 11:25:10 AM, Siarhei
On Wed, 15 Oct 2014 17:40:38 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
On Wed, Oct 15 2014 at 03:05:24 PM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 13:42:33 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
On Wed, Oct 15 2014 at 11:40:24 AM, Siarhei
regards,
Siarhei Siamashka
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On Fri, 03 Oct 2014 11:19:47 +0200
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10/03/2014 10:49 AM, Siarhei Siamashka wrote:
On Fri, 03 Oct 2014 10:04:29 +0200
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10/01/2014 07:43 PM, Hendrik wrote:
I have always been using
On Thu, 16 Oct 2014 10:48:34 +0200
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10/15/2014 12:34 PM, Siarhei Siamashka wrote:
On Wed, 15 Oct 2014 12:12:11 +0200
Hans de Goede hdego...@redhat.com wrote:
This change breaks various hardcoded assumptions in the linux-sunxi-3.4
On Thu, 16 Oct 2014 10:50:42 +0200
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10/15/2014 12:48 PM, Siarhei Siamashka wrote:
On Mon, 13 Oct 2014 14:55:35 +0200
Hans de Goede hdego...@redhat.com wrote:
Many people are still using old linux-sunxi-3.4 kernels on sunxi devices
? Nothing?).
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. However all these settings have to be eventually
formally validated in some way (ensure that the supported boards at
least do not obviously fail the https://github.com/ssvb/lima-memtester
test). And IMHO this preferably should be done before the v2014.10
release.
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assumptions and
hoping for the best). But again, wasting time on doing this only makes
sense if Allwinner in fact has no plans to release proper documentation
for the DRAM controllers used in their SoCs.
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commit messages. Keep up
the good job.
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tools to measure DRAM
reliability. These tools can help to pick good ZQ settings. Something
similar may be potentially implemented for A31 too.
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progress with
http://lists.denx.de/pipermail/u-boot/2014-August/185722.html
To sum it up. Just try to reduce the SPL size. Maybe try a different
gcc version to compile it. Maybe try to apply the Thumb2 tweak.
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On Sat, 13 Dec 2014 12:00:44 +0100
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 12-12-14 21:25, Siarhei Siamashka wrote:
On Sun, 23 Nov 2014 14:43:13 +0100
Hans de Goede hdego...@redhat.com wrote:
The A31s only has one dram channel, so do not bother with trying to
initialize
@@ -308,4 +311,6 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_PLL10(5 24)
#define CCM_DE_CTRL_GATE (1 31)
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+
#endif /* _SUNXI_CLOCK_SUN6I_H */
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/* _SUNXI_CLOCK_SUN6I_H */
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