Re: [PATCHv8 03/15] net/lwip: implement dns cmd
On 13.09.2023 07:56, Ilias Apalodimas wrote:
On Fri, Sep 08, 2023 at 07:53:08PM +0600, Maxim Uvarov wrote:
U-Boot recently got support for an alternative network stack using LWIP.
Replace dns command with the LWIP variant while keeping the output and
error messages identical.
Signed-off-by: Maxim Uvarov
---
include/net/lwip.h | 19 +++
net/lwip/Makefile| 2 ++
net/lwip/apps/dns/lwip-dns.c | 63
3 files changed, 84 insertions(+)
create mode 100644 include/net/lwip.h
create mode 100644 net/lwip/apps/dns/lwip-dns.c
diff --git a/include/net/lwip.h b/include/net/lwip.h
new file mode 100644
index 00..ab3db1a214
--- /dev/null
+++ b/include/net/lwip.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+int do_lwip_dns(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
+
+/**
+ * ulwip_dns() - creates the DNS request to resolve a domain host name
+ *
+ * This function creates the DNS request to resolve a domain host name.
Function
+ * can return immediately if previous request was cached or it might require
+ * entering the polling loop for a request to a remote server.
+ *
+ * @name:dns name to resolve
+ * @varname: (optional) U-Boot variable name to store the result
+ * Returns: ERR_OK(0) for fetching entry from the cache
+ * -EINPROGRESS success, can go to the polling loop
+ * Other value < 0, if error
+ */
+int ulwip_dns(char *name, char *varname);
diff --git a/net/lwip/Makefile b/net/lwip/Makefile
index 3fd5d34564..5d8d5527c6 100644
--- a/net/lwip/Makefile
+++ b/net/lwip/Makefile
@@ -62,3 +62,5 @@ obj-$(CONFIG_NET) += lwip-external/src/netif/ethernet.o
obj-$(CONFIG_NET) += port/if.o
obj-$(CONFIG_NET) += port/sys-arch.o
+
+obj-y += apps/dns/lwip-dns.o
diff --git a/net/lwip/apps/dns/lwip-dns.c b/net/lwip/apps/dns/lwip-dns.c
new file mode 100644
index 00..b340302f2c
--- /dev/null
+++ b/net/lwip/apps/dns/lwip-dns.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * (C) Copyright 2023 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+static void dns_found_cb(const char *name, const ip_addr_t *ipaddr, void
*callback_arg)
+{
+ char *varname = (char *)callback_arg;
+ char *ipstr = ip4addr_ntoa(ipaddr);
+
+ if (varname)
+ env_set(varname, ipstr);
+ log_info("resolved %s to %s\n", name, ipstr);
+ ulwip_exit(0);
+}
+
+int ulwip_dns(char *name, char *varname)
+{
+ int err;
+ ip_addr_t ipaddr; /* not used */
+ ip_addr_t dns1;
+ ip_addr_t dns2;
+ char *dnsenv = env_get("dnsip");
+ char *dns2env = env_get("dnsip2");
+
+ if (!dnsenv && !dns2env) {
+ log_err("nameserver is not set with dnsip and dnsip2 vars\n");
+ return -ENOENT;
+ }
+
+ if (!dnsenv)
+ log_warning("dnsip var is not set\n");
+ if (!dns2env)
+ log_warning("dnsip2 var is not set\n");
+
+ dns_init();
+
+ if (ipaddr_aton(dnsenv, &dns1))
+ dns_setserver(0, &dns1);
+
+ if (ipaddr_aton(dns2env, &dns2))
+ dns_setserver(1, &dns2);
env_get will return NULL if any of these is not set. Looking at
ipaddr_aton() of lwip that might lead to a NULL deref in ip_2_ip6()
Looking at the NULL checks in ipaddr_aton(), you found a bug in lwIP.
I'd vote to leave the above code as is and rely on the bug being fixed
in lwIP before U-Boot enables IPv6 (this is only a bug in dual-stack
mode where IPv4 and IPv6 is enabled).
Regards,
Simon
+
+ err = dns_gethostbyname(name, &ipaddr, dns_found_cb, varname);
+ if (err == ERR_OK)
+ dns_found_cb(name, &ipaddr, varname);
+
+ /* convert lwIP ERR_INPROGRESS to U-Boot -EINPROGRESS */
+ if (err == ERR_INPROGRESS)
+ err = -EINPROGRESS;
+
+ return err;
+}
--
2.30.2
Re: [PATCHv8 04/15] net/lwip: implement dhcp cmd
On 13.09.2023 08:07, Ilias Apalodimas wrote:
On Fri, Sep 08, 2023 at 07:53:09PM +0600, Maxim Uvarov wrote:
+
+#include
+#include
+#include
+
+#include
+#include
+#include "lwip/timeouts.h"
+
+#include
+#include
+
+#define DHCP_WAIT_MS 2000
Is this the time we wait for a dhcp reply? If so we should bump it to
something higher
+
+static void dhcp_tmo(void *arg)
+{
+ struct netif *netif = (struct netif *)arg;
+ struct dhcp *dhcp;
+ int err = 0;
+
+ dhcp = netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP);
+ if (!dhcp)
+ return;
+
+ switch (dhcp->state) {
+ case DHCP_STATE_BOUND:
+ err += env_set("bootfile", dhcp->boot_file_name);
+ err += env_set("ipaddr", ip4addr_ntoa(&dhcp->offered_ip_addr));
+ err += env_set("netmask", ip4addr_ntoa(&dhcp->offered_sn_mask));
+ err += env_set("serverip", ip4addr_ntoa(&dhcp->server_ip_addr));
+ if (err)
+ log_err("error update envs\n");
+ log_info("DHCP client bound to address %s\n",
ip4addr_ntoa(&dhcp->offered_ip_addr));
+ break;
+ default:
+ return;
+ }
+}
+
+int ulwip_dhcp(void)
+{
+ struct netif *netif;
+ int eth_idx;
+
+ eth_idx = eth_get_dev_index();
+ if (eth_idx < 0)
+ return -EPERM;
+
+ netif = netif_get_by_index(eth_idx + 1);
Why is the +1 needed here?
Netif index is driven by posix design and is 1-based in contrast to
U-Boot's 0-based dev index. A comment noting that would probably help
the ones not knowing lwIP.
Regards,
Simon
+ if (!netif)
+ return -ENOENT;
+
+ sys_timeout(DHCP_WAIT_MS, dhcp_tmo, netif);
+
+ return dhcp_start(netif) ? 0 : -EPERM;
+}
--
2.30.2
Re: [PATCHv8 05/15] net/lwip: implement tftp cmd
On 13.09.2023 08:15, Ilias Apalodimas wrote:
+
+/*
+ * (C) Copyright 2023 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "tftp_client.h"
+#include "tftp_server.h"
+#include
+
+#include
+
+#include
+
+static ulong daddr;
+static ulong size;
+
+static void *tftp_open(const char *fname, const char *mode, u8_t is_write)
+{
+ return NULL;
+}
+
+static void tftp_close(void *handle)
+{
+ log_info("\ndone\n");
+ log_info("Bytes transferred = %ld (0x%lx hex)\n", size, size);
+
+ bootstage_mark_name(BOOTSTAGE_KERNELREAD_STOP, "tftp_done");
+ if (env_set_hex("filesize", size)) {
+ log_err("filesize not updated\n");
+ ulwip_exit(-1);
+ return;
+ }
+ ulwip_exit(0);
+}
+
+static int tftp_read(void *handle, void *buf, int bytes)
+{
+ return 0;
+}
+
+static int tftp_write(void *handle, struct pbuf *p)
+{
+ struct pbuf *q;
+
+ for (q = p; q != NULL; q = q->next) {
+ memcpy((void *)daddr, q->payload, q->len);
+ daddr += q->len;
+ size += q->len;
+ log_info("#");
+ }
+
+ return 0;
+}
+
+static void tftp_error(void *handle, int err, const char *msg, int size)
+{
+ char message[100];
+
+ memset(message, 0, sizeof(message));
+ memcpy(message, msg, LWIP_MIN(sizeof(message) - 1, (size_t)size));
+
+ log_info("TFTP error: %d (%s)", err, message);
+}
+
+static const struct tftp_context tftp = {
+ tftp_open,
+ tftp_close,
+ tftp_read,
+ tftp_write,
+ tftp_error
+};
+
+int ulwip_tftp(ulong addr, char *fname)
+{
+ void *f = (void *)0x1; /* unused fake file handle*/
I haven't dug into lwip details yet, but I am not sure this is safe to use.
Simon, since you maintain the lwip part can you elaborate a bit more?
From the lwIP design, using an invalid pointer here is ok: that pointer
is only used as a client handle which is never dereferenced internally.
The only requirement is that it is not NULL, as that is the validity
check for the tftp client to know the handle is valid (or e.g. open
failed etc.).
So while we can leave 0x1 here, using a static uint8_t would probably be
better, at the expense of using a byte for nothing.
Regards,
Simon
+ err_t err;
+ ip_addr_t srv;
+ int ret;
+ char *server_ip;
+
+ if (!fname || addr == 0)
+ return CMD_RET_FAILURE;
+
+ size = 0;
+ daddr = addr;
+ server_ip = env_get("serverip");
+ if (!server_ip) {
+ log_err("error: serverip variable has to be set\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = ipaddr_aton(server_ip, &srv);
+ if (!ret) {
+ log_err("error: ipaddr_aton\n");
+ return CMD_RET_FAILURE;
+ }
+
+ log_info("TFTP from server %s; our IP address is %s\n",
+server_ip, env_get("ipaddr"));
+ log_info("Filename '%s'.\n", fname);
+ log_info("Load address: 0x%lx\n", daddr);
+ log_info("Loading:");
+
+ bootstage_mark_name(BOOTSTAGE_KERNELREAD_START, "tftp_start");
+
+ err = tftp_init_client(&tftp);
+ if (!(err == ERR_OK || err == ERR_USE))
+ log_err("tftp_init_client err: %d\n", err);
+
+ err = tftp_get(f, &srv, TFTP_PORT, fname, TFTP_MODE_OCTET);
+ /* might return different errors, like routing problems */
+ if (err != ERR_OK) {
+ log_err("tftp_get err=%d\n", err);
+ return CMD_RET_FAILURE;
+ }
+
+ if (env_set_hex("fileaddr", addr)) {
+ log_err("fileaddr not updated\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
--
2.30.2
Thanks
/Ilias
Re: [PATCHv8 00/15] net/lwip: add lwip library for the network stack
On 13.09.2023 09:53, Ilias Apalodimas wrote: Hi Maxim, On Wed, 13 Sept 2023 at 10:32, Maxim Uvarov wrote: On Wed, 13 Sept 2023 at 01:27, Simon Glass wrote: Hi Maxim, On Tue, 12 Sept 2023 at 05:42, Maxim Uvarov wrote: On Fri, 8 Sept 2023 at 19:59, Tom Rini wrote: On Fri, Sep 08, 2023 at 07:53:05PM +0600, Maxim Uvarov wrote: Before apply these patches it is needed to create lwIP merge into U-Boot: git subtree add --prefix net/lwip/lwip-external https://git.savannah.nongnu.org/git/lwip.git master --squash or create git submodule, depends how it's more easy to maintain external library. So, I think we're going to go with subtree. Please work out how to integrate the above in to the build process automatically (and such that we can maintain it via upgrades moving forward). -- Tom I did not find a good way to friend git format-patch, git am and subtree. And now with using subtree I can provide my thoughts, in general I do not see any big advantages with maintaining subtree code. Problem is that: 1. subtree does some root reset. So rebase looks like: label onto # Branch acbc0469a49de7055141cc730aa9c728e61b6de2-2 reset [new root] pick acbc0469a4 Squashed 'net/lwip/lwip-external/' content from commit 84fde1ebbf label acbc0469a49de7055141cc730aa9c728e61b6de2-2 reset onto merge -C ec4a128c8d acbc0469a49de7055141cc730aa9c728e61b6de2-2 # Merge commit 'acbc0469a49de7055141cc730aa9c728e61b6de2' as 'net/lwip/lwip-external' pick 739681a6f5 net/lwip: add doc/develop/net_lwip.rst pick f0ecab85e0 net/lwip: integrate lwIP library 2. if --rebase-merges option was not provided to rebase, then rebase will omit subtree directory and try to apply rebase patches to root directory. I.e. in current case squashed commit for lwip, will be applied to uboot root directory instead of ./net/lwip/lwip-external. 3. due to broken rebases without --rebase-merges more likely things like git bisect also will not work. 4. change in subtree code ./net/lwip/lwip-external/../something.c will create a git commit which looks like a standard U-Boot commit. I.e. path starts with ./net/lwip/lwip-external/ I don't really understand most of the above, but I take it that subtree has some problems...I did find an article about subtree [1] 5. lwip maintains code with a mailing list. So we don't need to push subtree git somewhere to create a pull request. 6. I rechecked the latest edk2 and they use submodules now. (openssl, libfdt, berkeley-softfloat-3 and others). 7. dynamic download also looks horrible for me. I.e. create subtree in Makefile on compilation process. I think maintaining that will give you a bunch of problems. I think we should not touch git structure after cloning. So what I can here suggest: 1. lwip source code is 9.4M. If we compare all code it will be 564M in total. So just having 1 commit witn copy of lwip library will work here. So we add a 9.4MB patch for the code we need? I suppose that is OK, although it is much larger than net/ today (0.5MB). What is the churn on lwip? E.g. would it be easy to add a commit every few months to bring in upstream changes? or 2. use git submodules. Size of the project will be lower. Submodule will not allow you to use local changes. I.e. change needs to be merged into the upstream project and then you can update git HEAD for the submodule. I really don't want to work with a submodule project. I've just had too many problems. or 3. inside u-boot.git create branch lib-lwip and clone lwip repo there. Then use git submoule to connect this branch as a folder to the main U-Boot code. It really needs to be properly part of U-Boot. Ok. Then more likely we don't need all the git history of lwip inside uboot.git. Then the option with a single commit is more preferable. Then we can use part 2 of this article, how to go with standard git commands: 1. git remote add -f lwip https://git.savannah.nongnu.org/git/lwip.git git read-tree --prefix=net/lwip/lwip-external -u lwip/master git commit -m "lwip merge sha: " this will create a git format-patch friendly commit. Then we send it to the mailing list and apply. I hope the mailing list will allow us to send a 7.8 MB patch. Then if for development you need to pull he history of lwip, you can do it with: git pull -s subtree lwip master --allow-unrelated-histories (but I think nobody will need this.) New update of the lwip net/lwip/lwip-external dir will be done with: git pull -s subtree lwip master --allow-unrelated-histories --squash Squash commit also has to be git format-patch friendly. If you are ok with that proposal I will send v9 with the first patch created with steps above. We've gone through this before. The whole purpose of this is not having to maintain patches. Simon, instead of "I had problems in the past", can you elaborate a bit more? Tom said he is fine with subtrees instead of submodules and I know for a fact EDK2 doesn't have too many issues with submo
Re: [PATCHv8 00/15] net/lwip: add lwip library for the network stack
On 21.09.2023 18:29, Simon Glass wrote: Hi, On Wed, 13 Sept 2023 at 07:35, Maxim Uvarov wrote: On Wed, 13 Sept 2023 at 19:14, Tom Rini wrote: On Wed, Sep 13, 2023 at 11:06:13AM +0100, Peter Robinson wrote: Then if for development you need to pull he history of lwip, you can do it with: git pull -s subtree lwip master --allow-unrelated-histories (but I think nobody will need this.) New update of the lwip net/lwip/lwip-external dir will be done with: git pull -s subtree lwip master --allow-unrelated-histories --squash Squash commit also has to be git format-patch friendly. If you are ok with that proposal I will send v9 with the first patch created with steps above. We've gone through this before. The whole purpose of this is not having to maintain patches. Simon, instead of "I had problems in the past", can you elaborate a bit more? Tom said he is fine with subtrees instead of submodules and I know for a fact EDK2 doesn't have too many issues with submodules. Their documentation is pretty clear on building and requires git clone https://github.com/tianocore/edk2.git cd edk2 git submodule update --init Perhaps the situation has improved since you had issues? Nope. While I don't really care how you solve this technically, I'd *strongly* be interested for U-Boot to use *unmodified* lwIP sources where an explicit reference to an lwIP commit is used. I'd rather integrate bugfixes for U-Boot into lwIP than having the sources drift apart. Strongly agree here, we want to use upstream and all the combined development and reviews etc rather than forking off and ending up with yet another slightly different IP stack. The whole advantage of adopting LWIP is the advantage of combined security, features and bugs from a wide range of projects :-) Yes, this is what I want as well, and why I'm perhaps more agreeable with the approaches where it's a lot harder for us to start forking things unintentionally. I gather submodule rather than subtree would be better for that case? -- Tom Yes, submodule will be a much better solution for us. And I also don't think that today there are any issues with submodules. It works well of OE, RPM and DEB builds, distributions should not have problems with it. My particular experience is with coreboot. Some problems I have: 1. Updating the modules doesn't work and I need to reset, try the --init thing, fetch things manually, etc. etc. 2. In ChromiumOS coreboot we can't use submodules internally since each package has its own build script. E.g. we need to build coreboot separately from its blobs, fsp, external libraries, etc. At least there we can do this, but if U-Boot adopts a submodule for a core feature, this is going to create no end of problems. 3. It makes it impossible to patch lwip for any fix we need for a release 4. We still have to 'fast forward' to a new commit every now and then, which really is no easier than doing a merge commit for the changes since the last sync, is it? Really, we need a maintainer for the lwip piece, if we are to adopt it. Using submodules is not a substitute for that. As an lwIP maintainer, I cannot step up as a maintainer of lwIP in U-Boot, however, I can assure you I will do my best to work with you on integrating fixes into upstream lwIP if required. Without wanting to promote using submodules: all other examples of lwIP being copied into another repository have practically never resulted in bugfixes being sent back to us (ok, that's not 100% true, but we do get them only once in a while) and being like that, those projects are facing problems upgrading our stack in turn. I wouldn't want to be a maintainer of such code, either. Regards, Simon
Re: [PATCHv9 01/15] submodule: add lwIP as git submodule
On 21.09.2023 09:09, Maxim Uvarov wrote: On Thu, 21 Sept 2023 at 07:06, Simon Glass wrote: Hi Maxim, On Thu, 14 Sept 2023 at 10:20, Maxim Uvarov wrote: add external lwIP library as a git submodule. Oh dear...what is the motivation for using a submodule? Our current stack is nicely integrated into U-Boot. This would make moving between development branches much more painful. I would much prefer that we bring in the necessary code, and that you send a patch every 3 months or so to deal with updates, making sure there are no code-size regressions. Regards, Simon I would like the project maintainer to make the final decision. And this time I'm trying to understand how lwIP maintenance works. And how long does it take to merge a patch to lwip. For the latest Ilias comment I did a fix to lwip, which is pending. https://lists.nongnu.org/archive/html/lwip-devel/2023-09/msg4.html and created a bug with the same patch: https://savannah.nongnu.org/bugs/?64697 And it's interesting when patches get merged. Also there is a long list of not yet accepted patches (86 open items): https://savannah.nongnu.org/patch/?group=lwip The list of open bugs and patches has largely to do with users sending things in the form of "this or that doesn't work for me, here's my poor quality patch that fixes exactly my issue". We simply don't have the manpower to check all that for correctness and for not breaking other use cases. Nearly noone sends a working test case for things. But we're trying to catch up. I am afraid that if lwip patch acceptance will be too slow it also can slow down U-Boot development. Our response time greatly varies and greatly depends on how the supplier of a patch works with us. Many bugs in our bug tracker are like "this doesn't work for me, please do my work and fix it for me". Nearly noone even sends so much as a working reproduction. We're not a project like that. We need people needing things fixed to implement the fix. However, if you're talking about accepting and pushing code that easy for us to review, clear, and in good form, accepting should normally be a matter of some days. Regards, Simon
Re: [PATCHv10 14/15] net/lwip: replace original net commands with lwip
Am 4. Oktober 2023 10:29:54 MESZ schrieb Maxim Uvarov :
>On Wed, 4 Oct 2023 at 08:12, Simon Glass wrote:
>
>> Hi Sean,
>>
>> On Tue, 3 Oct 2023 at 11:58, Sean Edmond
>> wrote:
>> >
>> >
>> > On 2023-09-26 2:41 a.m., Maxim Uvarov wrote:
>> > > Replace original commands: ping, tftp, dhcp and wget.
>> > >
>> > > Signed-off-by: Maxim Uvarov
>> > > ---
>> > > boot/bootmeth_efi.c | 18 +++---
>> > > boot/bootmeth_pxe.c | 21 ++-
>> > > cmd/net.c | 86
>> +
>> > > cmd/pxe.c | 19 +-
>> > > include/net.h | 8 +++--
>> > > include/net/ulwip.h | 64 +
>> > > 6 files changed, 113 insertions(+), 103 deletions(-)
>> > > create mode 100644 include/net/ulwip.h
>> > >
>> > > diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
>> > > index ae936c8daa..52399d627c 100644
>> > > --- a/boot/bootmeth_efi.c
>> > > +++ b/boot/bootmeth_efi.c
>> > > @@ -20,6 +20,8 @@
>> > > #include
>> > > #include
>> > > #include
>> > > +#include
>> > > +#include
>> > > #include
>> > > #include
>> > >
>> > > @@ -319,9 +321,7 @@ static int distro_efi_try_bootflow_files(struct
>> udevice *dev,
>> > >
>> > > static int distro_efi_read_bootflow_net(struct bootflow *bflow)
>> > > {
>> > > - char file_addr[17], fname[256];
>> > > - char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
>> > > - struct cmd_tbl cmdtp = {}; /* dummy */
>> > > + char fname[256];
>> > > const char *addr_str, *fdt_addr_str;
>> > > int ret, arch, size;
>> > > ulong addr, fdt_addr;
>> > > @@ -368,7 +368,6 @@ static int distro_efi_read_bootflow_net(struct
>> bootflow *bflow)
>> > > if (!fdt_addr_str)
>> > > return log_msg_ret("fdt", -EINVAL);
>> > > fdt_addr = hextoul(fdt_addr_str, NULL);
>> > > - sprintf(file_addr, "%lx", fdt_addr);
>> > >
>> > > /* We only allow the first prefix with PXE */
>> > > ret = distro_efi_get_fdt_name(fname, sizeof(fname), 0);
>> > > @@ -379,7 +378,16 @@ static int distro_efi_read_bootflow_net(struct
>> bootflow *bflow)
>> > > if (!bflow->fdt_fname)
>> > > return log_msg_ret("fil", -ENOMEM);
>> > >
>> > > - if (!do_tftpb(&cmdtp, 0, 3, tftp_argv)) {
>> > > + ret = ulwip_init();
>> > > + if (ret)
>> > > + return log_msg_ret("ulwip_init", ret);
>> > > +
>> > > + ret = ulwip_tftp(fdt_addr, fname);
>> > > + if (ret)
>> > > + return log_msg_ret("ulwip_tftp", ret);
>> > > +
>> > > + ret = ulwip_loop();
>> > > + if (!ret) {
>> > > bflow->fdt_size = env_get_hex("filesize", 0);
>> > > bflow->fdt_addr = fdt_addr;
>> > > } else {
>> > > diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
>> > > index 8d489a11aa..fc6aabaa18 100644
>> > > --- a/boot/bootmeth_pxe.c
>> > > +++ b/boot/bootmeth_pxe.c
>> > > @@ -21,6 +21,8 @@
>> > > #include
>> > > #include
>> > > #include
>> > > +#include
>> > > +#include
>> > > #include
>> > >
>> > > static int extlinux_pxe_getfile(struct pxe_context *ctx, const char
>> *file_path,
>> > > @@ -116,18 +118,21 @@ static int extlinux_pxe_read_file(struct udevice
>> *dev, struct bootflow *bflow,
>> > > const char *file_path, ulong addr,
>> > > ulong *sizep)
>> > > {
>> > > - char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
>> > > - struct pxe_context *ctx = dev_get_priv(dev);
>> > > - char file_addr[17];
>> > > ulong size;
>> > > int ret;
>> > >
>> > > - sprintf(file_addr, "%lx", addr);
>> > > - tftp_argv[1] = file_addr;
>> > > - tftp_argv[2] = (void *)file_path;
>> > > + ret = ulwip_init();
>> > > + if (ret)
>> > > + return log_msg_ret("ulwip_init", ret);
>> > > +
>> > > + ret = ulwip_tftp(addr, file_path);
>> > > + if (ret)
>> > > + return log_msg_ret("ulwip_tftp", ret);
>> > > +
>> > > + ret = ulwip_loop();
>> > > + if (ret)
>> > > + return log_msg_ret("ulwip_loop", ret);
>> > >
>> > > - if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv))
>> > > - return -ENOENT;
>> > > ret = pxe_get_file_size(&size);
>> > > if (ret)
>> > > return log_msg_ret("tftp", ret);
>> > > diff --git a/cmd/net.c b/cmd/net.c
>> > > index d407d8320a..dc5a114309 100644
>> > > --- a/cmd/net.c
>> > > +++ b/cmd/net.c
>> > > @@ -22,6 +22,7 @@
>> > > #include
>> > > #include
>> > > #include
>> > > +#include
>> > >
>> > > static int netboot_common(enum proto_t, struct cmd_tbl *, int, char
>> * const []);
>> > >
>> > > @@ -40,19 +41,9 @@ U_BOOT_CMD(
>> > > #endif
>> > >
>> > > #ifdef CONFIG_CMD_TFTPBOOT
>> > > -int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const
>> argv[])
>> > > -{
>> > > - int ret;
>> > > -
>> > > - bootstage_mark_name(BOOTSTAGE_KERNELREAD_START, "tftp_start");
>>
Re: [PATCHv5 05/13] net/lwip: implement tftp cmd
On 10.08.2023 13:28, Maxim Uvarov wrote:
On Thu, 3 Aug 2023 at 12:42, Ilias Apalodimas
wrote:
On Wed, Aug 02, 2023 at 08:06:50PM +0600, Maxim Uvarov wrote:
Signed-off-by: Maxim Uvarov
---
lib/lwip/Makefile | 1 +
lib/lwip/apps/tftp/Makefile| 16 +
lib/lwip/apps/tftp/lwip-tftp.c | 124 +
3 files changed, 141 insertions(+)
create mode 100644 lib/lwip/apps/tftp/Makefile
create mode 100644 lib/lwip/apps/tftp/lwip-tftp.c
diff --git a/lib/lwip/Makefile b/lib/lwip/Makefile
index a3521a9d18..1893162c1a 100644
--- a/lib/lwip/Makefile
+++ b/lib/lwip/Makefile
@@ -67,3 +67,4 @@ obj-$(CONFIG_NET) += port/sys-arch.o
obj-$(CONFIG_CMD_DHCP) += apps/dhcp/lwip-dhcp.o
obj-$(CONFIG_CMD_DNS) += apps/dns/lwip-dns.o
+obj-$(CONFIG_CMD_TFTPBOOT) += apps/tftp/
diff --git a/lib/lwip/apps/tftp/Makefile b/lib/lwip/apps/tftp/Makefile
new file mode 100644
index 00..299c95e9c0
--- /dev/null
+++ b/lib/lwip/apps/tftp/Makefile
@@ -0,0 +1,16 @@
+
+ccflags-y += -I$(srctree)/lib/lwip/port/include
+ccflags-y += -I$(srctree)/lib/lwip/lwip-external/src/include
-I$(srctree)/lib/lwip
+ccflags-y += -I$(obj)
+
+$(obj)/tftp.o: $(obj)/tftp.c
+.PHONY: $(obj)/tftp.c
+$(obj)/tftp.c:
+ cp $(srctree)/lib/lwip/lwip-external/src/apps/tftp/tftp.c
$(obj)/tftp.c
+ cp
$(srctree)/lib/lwip/lwip-external/src/include/lwip/apps/tftp_client.h
$(obj)/tftp_client.h
+ cp
$(srctree)/lib/lwip/lwip-external/src/include/lwip/apps/tftp_common.h
$(obj)/tftp_common.h
+ cp
$(srctree)/lib/lwip/lwip-external/contrib/examples/tftp/tftp_example.h
$(obj)/tftp_example.h
+
+obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
+obj-$(CONFIG_CMD_TFTPBOOT) += lwip-tftp.o
+
diff --git a/lib/lwip/apps/tftp/lwip-tftp.c
b/lib/lwip/apps/tftp/lwip-tftp.c
new file mode 100644
index 00..511d82e600
--- /dev/null
+++ b/lib/lwip/apps/tftp/lwip-tftp.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * (C) Copyright 2023 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+
+#include "lwip/apps/tftp_client.h"
+#include "lwip/apps/tftp_server.h"
+#include
+
+#include
+
+#include "../../../lwip/ulwip.h"
+
+#if LWIP_UDP
+
+static ulong daddr;
+static ulong size;
+
+static void *tftp_open(const char *fname, const char *mode, u8_t
is_write)
+{
+ LWIP_UNUSED_ARG(mode);
+ return NULL;
+}
+
+static void tftp_close(void *handle)
+{
+ printf("\ndone\n");
+ printf("Bytes transferred = %ld (0x%lx hex)\n", size, size);
Can you replace all the printf occurences with log_ ?
+
+ env_set_ulong("filesize", size);
+ ulwip_exit(0);
+}
+
+static int tftp_read(void *handle, void *buf, int bytes)
+{
+ return 0;
+}
+
+static int tftp_write(void *handle, struct pbuf *p)
+{
+ struct pbuf *q;
+
+ for (q = p; q != NULL; q = q->next) {
+ memcpy((void *)daddr, q->payload, q->len);
+ /* printf("downloaded chunk size %d, to addr 0x%lx\n",
q->len, daddr); */
Remove all those debug comments on the next version
+ daddr += q->len;
+ size += q->len;
+ printf("#");
+ }
+
+ return 0;
+}
+
+/* For TFTP client only */
+static void tftp_error(void *handle, int err, const char *msg, int size)
+{
+ char message[100];
+
+ LWIP_UNUSED_ARG(handle);
+
+ memset(message, 0, sizeof(message));
+ MEMCPY(message, msg, LWIP_MIN(sizeof(message)-1, (size_t)size));
Why aren't we using the native memcpy?
+
+ printf("TFTP error: %d (%s)", err, message);
+}
+
+static const struct tftp_context tftp = {
+ tftp_open,
+ tftp_close,
+ tftp_read,
+ tftp_write,
+ tftp_error
+};
+
+int lwip_tftp(ulong addr, char *fname)
+{
+ void *f = (void *)0x1; /*fake handle*/
If it's fake can't it just be NULL? What does 'fake' mean? is that safe to
be passed around the LWIP APIs?
Here I reuse a tftp example from lwIP. f here is a file handle to write
output. I do write to memory and do not use this value.
But there is a check that his value can not be NULL. So something needs to
be passed here to not do modifications to
the example code.
Sorry I did not have the time to follow all your patches here throgouhly
enough. However, if things like this come up, please also do not
hesitate to come to us (lwip developers) with ideas to make our code
more easily integratable into target applications (like U-Boot here).
As I said before (to Maxim in a private mail I think), I think it would
be best to start targeting this integration based on lwIP's master
branch, so modifications in the upstream lwIP sources would be possible
to make this work neatly.
Regards,
Simon
+ err_t err;
+ ip_addr_t srv;
+ int ret;
+ char *server_ip;
+
+ if (!fname || addr == 0)
+ return CMD_RET_FAILURE;
+
+ size = 0;
+ daddr = addr;
+ server_ip = env_get("serverip");
+ if (!server_ip) {
+ printf("error: serverip variable has to be set\n");
+
Re: [PATCHv6 09/14] net/lwip: implement lwIP port to U-Boot
Hi all,
could you please remove the lwip-devel list from CC? I am interested in these
mails, but the more you dive into U-Boot specific things here, the less people
on our lwip list will be interested in this topic.
Thanks,
Simon
Am 18. August 2023 14:53:43 MESZ schrieb Maxim Uvarov :
>On Wed, 16 Aug 2023 at 15:01, Ilias Apalodimas
>wrote:
>
>> On Mon, Aug 14, 2023 at 07:32:48PM +0600, Maxim Uvarov wrote:
>> > Implement network lwIP interface connected to the U-boot.
>> > Keep original file structure widely used fro lwIP ports.
>> > (i.e. port/if.c port/sys-arch.c).
>>
>> What the patch does is obvious. Try to describe *why* we need this
>>
>> >
>> > Signed-off-by: Maxim Uvarov
>> > ---
>> > net/eth-uclass.c | 8 +
>> > net/lwip/port/if.c| 260 ++
>> > net/lwip/port/include/arch/cc.h | 39
>> > net/lwip/port/include/arch/sys_arch.h | 56 ++
>> > net/lwip/port/include/limits.h| 0
>> > net/lwip/port/sys-arch.c | 20 ++
>> > 6 files changed, 383 insertions(+)
>> > create mode 100644 net/lwip/port/if.c
>> > create mode 100644 net/lwip/port/include/arch/cc.h
>> > create mode 100644 net/lwip/port/include/arch/sys_arch.h
>> > create mode 100644 net/lwip/port/include/limits.h
>> > create mode 100644 net/lwip/port/sys-arch.c
>> >
>> > diff --git a/net/eth-uclass.c b/net/eth-uclass.c
>> > index c393600fab..6625f6d8a5 100644
>> > --- a/net/eth-uclass.c
>> > +++ b/net/eth-uclass.c
>> > @@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
>> > struct eth_device_priv {
>> > enum eth_state_t state;
>> > bool running;
>> > + ulwip ulwip;
>> > };
>> >
>> > /**
>> > @@ -347,6 +348,13 @@ int eth_init(void)
>> > return ret;
>> > }
>> >
>> > +struct ulwip *eth_lwip_priv(struct udevice *current)
>> > +{
>> > + struct eth_device_priv *priv = dev_get_uclass_priv(current);
>> > +
>> > + return &priv->ulwip;
>> > +}
>> > +
>> > void eth_halt(void)
>> > {
>> > struct udevice *current;
>> > diff --git a/net/lwip/port/if.c b/net/lwip/port/if.c
>> > new file mode 100644
>> > index 00..625a9c10bf
>> > --- /dev/null
>> > +++ b/net/lwip/port/if.c
>> > @@ -0,0 +1,260 @@
>> > +// SPDX-License-Identifier: GPL-2.0
>> > +
>> > +/*
>> > + * (C) Copyright 2023 Linaro Ltd.
>> > + */
>> > +
>> > +#include
>> > +#include
>> > +#include
>> > +#include "lwip/debug.h"
>> > +#include "lwip/arch.h"
>> > +#include "netif/etharp.h"
>> > +#include "lwip/stats.h"
>> > +#include "lwip/def.h"
>> > +#include "lwip/mem.h"
>> > +#include "lwip/pbuf.h"
>> > +#include "lwip/sys.h"
>> > +#include "lwip/netif.h"
>> > +#include "lwip/ethip6.h"
>> > +
>> > +#include "lwip/ip.h"
>> > +
>> > +#define IFNAME0 'e'
>> > +#define IFNAME1 '0'
>>
>> Why is this needed and how was 'e0' chosen?
>> Dont we have a device name in the udevice struct?
>>
>>
>If we assume that we have lwip netif on top of an active U-Boot eth device,
>then it can be any name.
>
> /** descriptive abbreviation */
>
> char name[2];
>
>./net/lwip/lwip-external/contrib/examples/ethernetif/ethernetif.c:#define
>IFNAME0 'e'
>./net/lwip/lwip-external/contrib/examples/ethernetif/ethernetif.c:#define
>IFNAME1 'n'
>./net/lwip/lwip-external/contrib/ports/unix/port/netif/tapif.c:#define
>IFNAME0 't'
>./net/lwip/lwip-external/contrib/ports/unix/port/netif/tapif.c:#define
>IFNAME1 'p'
>./net/lwip/lwip-external/contrib/ports/unix/port/netif/vdeif.c:#define
>IFNAME0 'v'
>./net/lwip/lwip-external/contrib/ports/unix/port/netif/vdeif.c:#define
>IFNAME1 'd'
>./net/lwip/lwip-external/contrib/ports/win32/pcapif.c:#define IFNAME0
>'e'
>./net/lwip/lwip-external/contrib/ports/win32/pcapif.c:#define IFNAME1
>'0'
>./net/lwip/lwip-external/src/netif/bridgeif.c:#define IFNAME0 'b'
>./net/lwip/lwip-external/src/netif/bridgeif.c:#define IFNAME1 'r'
>./net/lwip/port/if.c:#define IFNAME0 'u'
>./net/lwip/port/if.c:#define IFNAME1 '0'
>
>
>
>> > +
>> > +static struct pbuf *low_level_input(struct netif *netif);
>> > +
>> > +int ulwip_enabled(void)
>> > +{
>> > + struct ulwip *ulwip;
>> > +
>> > + ulwip = eth_lwip_priv(eth_get_dev());
>>
>> eth_get_dev() can return NULL. There are various locations of this call
>> that needs fixing
>>
>
>
>ok.
>
>
>>
>> > + return ulwip->init_done;
>> > +}
>> > +
>> > +
>> > +struct ulwip_if {
>> > +};
>>
>> Why the forward declaration?
>>
>> > +
>> > +#define LWIP_PORT_INIT_NETMASK(addr) IP4_ADDR((addr), 255, 255, 255, 0)
>>
>> Why are we limiting the netmask to a class C network?
>>
>>
>that can be completely removed.
>
>
>> > +
>> > +void ulwip_poll(void)
>> > +{
>> > + struct pbuf *p;
>> > + int err;
>> > + struct netif *netif = netif_get_by_index(1);
>>
>> First of all netif can be NULL. Apart from that always requesting index 1
>> feels wrong. We should do something similar to eth_get_dev() and get the
>> *active* device correlation to an index
>>
>>
>I expect that it will
Re: [PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function
On 02.04.2020 21:49, Simon Glass wrote: Hi Marek, On Thu, 2 Apr 2020 at 13:45, Marek Vasut wrote: On 4/2/20 8:50 PM, Simon Glass wrote: Hi. Hi, [...] I suspect we could change this, so that device_ofdata_to_platdata() first calls itself on its parent. I can think of various reasons why this change might be desirable. I think this is how it worked before already. Well effectively, yes, because ofdata and probe were joined together. Simon, do you have plan to fix this DM core issue ? I'm not sure it definitely should be changed. But I'll do a patch and see how it looks. Do I understand it correctly that the patch 82de42fa14682d408da935adfb0f935354c5008f actually completely breaks SoCFPGA ? Then I would say this is a release blocker ? Yes. A10 SPL won't boot at all. It crashes during the clock manager setup. This came in right at the beginning of the cycle. I thought the purpose of the 3-month cycle was to allow time to test? It was ... altera ? I do plan to try out changing the behaviour to read a parent's ofdata before the child, but I am not comfortable adding such a major change just before a release. It could have any number of ill effects. Can you update the clock driver? E.g. you could move some of the code from socfpga_a10_ofdata_to_platdata() to a probe() method? Can we revert the patch which broke arria10 instead ? It did work before, so who knows how many other ill side effects there are ... No, sorry, we need to fix Altera. Other boards have fixed driver bugs exposed by the patch. BTW what is a good Altera board to get that doesn't cost too much? A problem here might be that you'd need to have a gen5, an A10 and a stratix board to find all problems... Regards, Simon Regards, Simon
Re: [PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function
On 02.04.2020 21:54, Marek Vasut wrote: On 4/2/20 9:53 PM, Simon Goldschmidt wrote: On 02.04.2020 21:49, Simon Glass wrote: Hi Marek, On Thu, 2 Apr 2020 at 13:45, Marek Vasut wrote: On 4/2/20 8:50 PM, Simon Glass wrote: Hi. Hi, [...] I suspect we could change this, so that device_ofdata_to_platdata() first calls itself on its parent. I can think of various reasons why this change might be desirable. I think this is how it worked before already. Well effectively, yes, because ofdata and probe were joined together. Simon, do you have plan to fix this DM core issue ? I'm not sure it definitely should be changed. But I'll do a patch and see how it looks. Do I understand it correctly that the patch 82de42fa14682d408da935adfb0f935354c5008f actually completely breaks SoCFPGA ? Then I would say this is a release blocker ? Yes. A10 SPL won't boot at all. It crashes during the clock manager setup. This came in right at the beginning of the cycle. I thought the purpose of the 3-month cycle was to allow time to test? It was ... altera ? I do plan to try out changing the behaviour to read a parent's ofdata before the child, but I am not comfortable adding such a major change just before a release. It could have any number of ill effects. Can you update the clock driver? E.g. you could move some of the code from socfpga_a10_ofdata_to_platdata() to a probe() method? Can we revert the patch which broke arria10 instead ? It did work before, so who knows how many other ill side effects there are ... No, sorry, we need to fix Altera. Other boards have fixed driver bugs exposed by the patch. BTW what is a good Altera board to get that doesn't cost too much? A problem here might be that you'd need to have a gen5, an A10 and a stratix board to find all problems... And agilex too ... Hmm, I thought we would try and keep stratix and agilex more close than gen5/A10... I even don't have any non-gen5 boards myself here, so I cannot even test those, either. But in the end, yes, it would be a good thing to have all those boards execute basic tests at least after rc1 has been tagged. I wonder if OSADL could help out here, given they already have a broad range of boards testing linux-rt already. Or do we have a separate hardware area for this? Regards, Simon
Re: [PATCH 3/3] arm: socfpga: arria10: Enable cache driver in SPL
Am 06.04.2020 um 11:18 schrieb Ley Foon Tan:
> Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
> to enable cache driver in SPL.
>
> This fixed error below in SPL:
> cache controller driver NOT found!
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 4
> configs/socfpga_arria10_defconfig| 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> index 0db358cf1f2b..6ff1ea6e5eb7 100644
> --- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -73,6 +73,10 @@
> reset-names = "i2c";
> };
>
> +&L2 {
> + u-boot,dm-pre-reloc;
> +};
> +
> &l4_mp_clk {
> u-boot,dm-pre-reloc;
> };
> diff --git a/configs/socfpga_arria10_defconfig
> b/configs/socfpga_arria10_defconfig
> index ca34457ddd16..875031a77e3a 100644
> --- a/configs/socfpga_arria10_defconfig
> +++ b/configs/socfpga_arria10_defconfig
> @@ -22,6 +22,7 @@ CONFIG_VERSION_VARIABLE=y
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_ENV_SUPPORT=y
> CONFIG_SPL_FPGA_SUPPORT=y
> +CONFIG_SPL_CACHE=y
Can you select or default this in Kconfig if it's required for all
Arria10 boards (even if we only have one right now)?
Regards,
Simon
> CONFIG_CMD_ASKENV=y
> CONFIG_CMD_GREPENV=y
> # CONFIG_CMD_FLASH is not set
>
Re: [PATCH v2 3/3] arm: socfpga: arria10: Enable cache driver in SPL
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan wrote:
>
> Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
> to enable cache driver in SPL.
>
> This fixed error below in SPL:
> cache controller driver NOT found!
>
> Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
>
> ---
> v2: Enable SPL_CACHE in Kconfig instead of defconfig.
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 4
> arch/arm/mach-socfpga/Kconfig| 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> index 0db358cf1f2b..6ff1ea6e5eb7 100644
> --- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -73,6 +73,10 @@
> reset-names = "i2c";
> };
>
> +&L2 {
> + u-boot,dm-pre-reloc;
> +};
> +
> &l4_mp_clk {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 38d6c1b2ba32..a3699e82a19e 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -46,6 +46,7 @@ config TARGET_SOCFPGA_ARRIA10
> bool
> select SPL_ALTERA_SDRAM
> select SPL_BOARD_INIT if SPL
> + select SPL_CACHE if SPL
> select CLK
> select SPL_CLK if SPL
> select DM_I2C
> --
> 2.19.0
>
Re: [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan wrote:
>
> Move Uboot specific properties to *u-boot.dtsi files.
> Preparation to sync Arria 10 device tree from Linux.
>
> Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++
> arch/arm/dts/socfpga_arria10.dtsi | 28
> .../arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 17 +++
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 27
> .../socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 46 +++
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 37 --
> 6 files changed, 186 insertions(+), 92 deletions(-)
> create mode 100644 arch/arm/dts/socfpga_arria10-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> new file mode 100644
> index ..c637b100738a
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2014, 2020, Intel Corporation
> + */
> +
> +/ {
> + chosen {
> + tick-timer = &timer2;
> + u-boot,dm-pre-reloc;
> + };
> +
> + memory@0 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + soc {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&clkmgr {
> + u-boot,dm-pre-reloc;
> +
> + clocks {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&cb_intosc_hs_div2_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&cb_intosc_ls_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&f2s_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&i2c0 {
> + reset-names = "i2c";
> +};
> +
> +&i2c1 {
> + reset-names = "i2c";
> +};
> +
> +&i2c2 {
> + reset-names = "i2c";
> +};
> +
> +&i2c3 {
> + reset-names = "i2c";
> +};
> +
> +&i2c4 {
> + reset-names = "i2c";
> +};
> +
> +&l4_mp_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&l4_sp_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&l4_sys_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&main_periph_ref_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&main_pll {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&main_noc_base_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&noc_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&osc1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&peri_noc_base_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&periph_pll {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&porta {
> + bank-name = "porta";
> +};
> +
> +&portb {
> + bank-name = "portb";
> +};
> +
> +&portc {
> + bank-name = "portc";
> +};
> +
> +&rst {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sysmgr {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&timer2 {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi
> b/arch/arm/dts/socfpga_arria10.dtsi
> index cc529bcd1156..c8cd5a84b8a8 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -21,11 +21,6 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - chosen {
> - tick-timer = &timer2;
> - u-boot,dm-pre-reloc;
> - };
> -
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -60,7 +55,6 @@
> device_type = "soc";
> interrupt-parent = <&intc>;
> ranges;
> - u-boot,dm-pre-reloc;
>
> amba {
> compatible = "simple-bus";
> @@ -99,35 +93,29 @@
> clkmgr: clkmgr@ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
> - u-boot,dm-pre-reloc;
>
> clocks {
> #add
Re: [PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan wrote:
>
> Update these 3 files from Linux:.
> - socfpga_arria10.dtsi (Commit ID c1459a9d7e92)
> - socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b)
> - socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f)
>
> Change in socfpga_arria10.dtsi:
> - Add clkmgr label, so that can reference to it in u-boot.dtsi.
>
> Change in socfpga_arria10-u-boot.dtsi:
> - Add compatible and altr,sysmgr-syscon for uboot.
>
> Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
>
> ---
> v2: Update commit ID in description.
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 15
> arch/arm/dts/socfpga_arria10.dtsi| 90 ++--
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 43 +++---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 16 +---
> 4 files changed, 108 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> index c637b100738a..0db358cf1f2b 100644
> --- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -38,6 +38,21 @@
> u-boot,dm-pre-reloc;
> };
>
> +&gmac0 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> +};
> +
> +&gmac1 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> +};
> +
> +&gmac2 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
> +};
> +
> &i2c0 {
> reset-names = "i2c";
> };
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi
> b/arch/arm/dts/socfpga_arria10.dtsi
> index c8cd5a84b8a8..a598c7554266 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -1,17 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0
> /*
> * Copyright Altera Corporation (C) 2014. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms and conditions of the GNU General Public License,
> - * version 2, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along
> with
> - * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> #include
> @@ -79,6 +68,8 @@
> #dma-requests = <32>;
> clocks = <&l4_main_clk>;
> clock-names = "apb_pclk";
> + resets = <&rst DMA_RESET>, <&rst
> DMA_OCP_RESET>;
> + reset-names = "dma", "dma-ocp";
> };
> };
>
> @@ -377,13 +368,28 @@
> clk-gate = <0xC8 11>;
> };
>
> - nand_clk: nand_clk {
> + nand_x_clk: nand_x_clk {
> #clock-cells = <0>;
> compatible =
> "altr,socfpga-a10-gate-clk";
> clocks = <&l4_mp_clk>;
> clk-gate = <0xC8 10>;
> };
>
> + nand_ecc_clk: nand_ecc_clk {
> + #clock-cells = <0>;
> + compatible =
> "altr,socfpga-a10-gate-clk";
> + clocks = <&nand_x_clk>;
> + clk-gate = <0xC8 10>;
> + };
> +
> + nand_clk: nand_clk {
> + #clock-cells = <0>;
> + compati
Re: [PATCH v4 17/20] spl: nor: add lzma decompression support for legacy image
Sorry if it seems I ignored this mail yesterday, I just found it now :) On Wed, Feb 12, 2020 at 10:05 AM Stefan Roese wrote: > > On 12.02.20 09:57, Weijie Gao wrote: > > > > >> And more general: why do we need to code this in every loader? I think it > >> would > >> be preferrable to have the loader load the binary data and do the > >> decompression > >> (and entry_point assignment) in a central place so that all loaders can > >> benefit > >> from compression. As it is now, we are duplicating code when implementing > >> LZMA > >> in the next loader. > > I agree with Simon, that it would make sense to move this code into a > even more generic location, so that other "loaders" can also use this > feature. I know, that I suggested to add it here and I think we can > make this move into the common SPL interface at a later point, after > this patch set has been integrated. My concern is that we add poor code now and that cleanup at a "later point" just gets forgotten. To me, this patch looks like another "get the stuff I need in fast" thing, without thinking about overall code quality. Yes it might be more work to do it properly, but in my opinion, the result will be code that is easier to maintain in the long run. Regards, Simon > > > This feature is originally designed for the case that u-boot is stored > > in a small capacity storage device, mostly NOR flashes, and the space > > reserved for u-boot is very small. Most loaders (MMC, NAND, SATA, ...) > > do not need this at all. > > Yes and no. As you pointed out, it might be faster to load and > decompress a smaller U-Boot proper image than just loading a bigger > image. So other platforms might very well take advantage of this > feature. And size increase is always a big issue in modern U-Boot. So a > smaller image is always welcome. ;) > > Thanks, > Stefan
Re: [PATCH v4 17/20] spl: nor: add lzma decompression support for legacy image
On Thu, Feb 13, 2020 at 3:53 AM Weijie Gao wrote:
>
> On Wed, 2020-02-12 at 11:18 +0100, Simon Goldschmidt wrote:
> > On Wed, Feb 12, 2020 at 9:57 AM Weijie Gao wrote:
> > >
> > > On Wed, 2020-02-12 at 09:22 +0100, Simon Goldschmidt wrote:
> > > > On Wed, Feb 12, 2020 at 8:49 AM Weijie Gao
> > > > wrote:
> > > > >
> > > > > This patch adds support for decompressing LZMA compressed u-boot
> > > > > payload in
> > > > > legacy uImage format.
> > > > >
> > > > > Using this patch together with u-boot-lzma.img is useful for NOR
> > > > > flashes as
> > > > > they can reduce the size and load time of u-boot payload.
> > > > >
> > > > > Reviewed-by: Stefan Roese
> > > > > Signed-off-by: Weijie Gao
> > > > > ---
> > > > > Changes since v3: none
> > > > > ---
> > > > > common/spl/spl_nor.c | 59
> > > > >
> > > > > 1 file changed, 54 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
> > > > > index b1e79b9ded..7c81fb28f6 100644
> > > > > --- a/common/spl/spl_nor.c
> > > > > +++ b/common/spl/spl_nor.c
> > > > > @@ -4,8 +4,19 @@
> > > > > */
> > > > >
> > > > > #include
> > > > > +#include
> > > > > #include
> > > > >
> > > > > +#if IS_ENABLED(CONFIG_SPL_LZMA)
> > > >
> > > > Is this guard really necessary? What happens without it?
> > >
> > > Actually nothing will happen.
> >
> > So can you drop it?
>
> Already dropped in v5.
Which v5? Oh, I see you sent a v5 just about 2 hours after v4?
That's way too fast to have a discussion about a version.
>
> >
> > >
> > > >
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#endif
> > > > > +
> > > > > +#ifndef CONFIG_SYS_BOOTM_LEN
> > > > > +#define CONFIG_SYS_BOOTM_LEN (8 << 20)
> > > > > +#endif
> > > >
> > > > This looks strange. I think we should have a central place where this
> > > > is defined
> > > > to a default value. As it is now, you are adding the 3rd place where
> > > > this is
> > > > defined to a "fallback" value, each with a different value.
> > >
> > > This is copied from common/bootm.c. It does exist in two files:
> > > common/bootm.c and common/spl/spl_fit.c.
> >
> > Exactly. It is copied. Yet another duplication, which is bad.
> > And it is not even copied 1:1, as those two files define a different default
> > value and you define yet another different default value.
>
> Actually the same value. from common/bootm.c, 0x80 = (8 << 20).
Same value, different code. Still ugly and hard to maintain to have this
code copied (*and* not copied literally, even if the resulting value is the
same).
>
> >
> > >
> > > >
> > > > > +
> > > > > static ulong spl_nor_load_read(struct spl_load_info *load, ulong
> > > > > sector,
> > > > >ulong count, void *buf)
> > > > > {
> > > > > @@ -27,6 +38,9 @@ static int spl_nor_load_image(struct spl_image_info
> > > > > *spl_image,
> > > > > int ret;
> > > > > __maybe_unused const struct image_header *header;
> > > > > __maybe_unused struct spl_load_info load;
> > > > > + __maybe_unused SizeT lzma_len;
> > > > > + struct image_header hdr;
> > > > > + uintptr_t dataptr;
> > > > >
> > > > > /*
> > > > > * Loading of the payload to SDRAM is done with skipping of
> > > > > @@ -107,14 +121,49 @@ static int spl_nor_load_image(struct
> > > > > spl_image_info *spl_image,
> > > > >
> > > > > spl_nor_get_uboot_base());
> > > > > }
> > > > >
> > > > > - ret = spl_parse_image_header(spl_image,
> > > > > - (const struct image_header
> > > > > *)spl_nor_get_uboot_
Re: [PATCH v5 00/20] Refactor the architecture parts of mt7628
On Wed, Feb 12, 2020 at 10:43 AM Weijie Gao wrote: > > This patch series are divided into two parts: > > The main part is to rewrite the whole architecture code of mt7628: > * Lock parts of the d-cache for initial stack so the rest of the code can > be reimplemented in C. > * Memory controller & DDR initialization have been fully written to support > detecting DDR size automatically. > * DDR calibration has also been reimplemented with a clear logic. > * Implemented a new sysreset driver to take advantage of the reset > controller so we can drop the use of syscon-based sysreset to reduce size. > > The second part is to add SPL support for mt7628: > * With SPL enabled we can build the ROM-bootable and RAM-bootable binary > simultaneously, and we can drop RAM boot related configs and defconfig > files. > * Generate compressed u-boot.bin image for SPL to reduce size of final > combined binary. > * Enable DM support for SPL for a more flexible device probing. > * Add a demo board (mt7628_rfb) aims at router application. > > Changes since v2: > * Dropped a patch which removes unused parts of mt7628a.dtsi > * Move lzma decompression support to common spl_nor.c > * Move u-boot,dm-pre-reloc to u-boot-mt7628.dtsi > > Changes since v3: > * Rebased on newest master branch > * Add a test for binman etype u-boot-lzma-img to make sure binman passes 100% > code coverage > * Use u-boot-with-spl.bin for SPL-enabled output file > * Remove unused code from spl_nor loader. No changes for v5 (since v4)? Regards, Simon > > Weijie Gao (20): > mips: add support to restore exception vector base before booting > linux > mips: mtmips: add predefined i-cache/d-cache size and linesize > mips: add an option to support initialize SRAM for initial stack > mips: start.S: avoid overwriting outside gd when clearing global data > in stack > sysreset: add reset controller based reboot driver > mips: mtmips: make use of sysreset-resetctrl for mt7628 soc > configs: enable CONFIG_RESTORE_EXCEPTION_VECTOR_BASE for all mtmips > boards > mips: add a mtmips-specific field to architecture-specific global data > mips: add a option to support not reserving malloc space on initial > stack > mips: mtmips: rewrite lowlevel codes of mt7628 > dts: mtmips: add alternative pinmux node for uart2 > mips: enable support for appending dtb to spl binary > mips: add an option to enable u_boot_list section for SPL loaders in > u-boot-spl.lds > lib: enable lzma decompression support for SPL build > Makefile: add support to generate LZMA compressed u-boot image > tools: binman: add etype file for u-boot-lzma-img > spl: nor: add lzma decompression support for legacy image > mips: mtmips: add SPL support > mips: mtmips: enable SPL for all boards > mips: mtmips: add support for mt7628-rfb > > Makefile | 19 + > arch/mips/Kconfig | 66 > arch/mips/cpu/start.S | 16 +- > arch/mips/cpu/u-boot-spl.lds | 4 +- > arch/mips/dts/Makefile| 1 + > arch/mips/dts/mediatek,mt7628-rfb.dts | 67 > arch/mips/dts/mt7628-u-boot.dtsi | 56 +++ > arch/mips/dts/mt7628a.dtsi| 17 +- > arch/mips/include/asm/global_data.h | 3 + > arch/mips/include/asm/u-boot-mips.h | 2 + > arch/mips/lib/bootm.c | 3 + > arch/mips/lib/traps.c | 19 + > arch/mips/mach-mtmips/Kconfig | 135 +++ > arch/mips/mach-mtmips/Makefile| 8 +- > arch/mips/mach-mtmips/cpu.c | 58 +--- > arch/mips/mach-mtmips/ddr_cal.c | 211 +++ > arch/mips/mach-mtmips/ddr_calibrate.c | 309 - > arch/mips/mach-mtmips/ddr_init.c | 194 +++ > arch/mips/mach-mtmips/include/mach/ddr.h | 52 +++ > arch/mips/mach-mtmips/include/mach/mc.h | 180 ++ > arch/mips/mach-mtmips/include/mach/serial.h | 13 + > arch/mips/mach-mtmips/lowlevel_init.S | 328 -- > arch/mips/mach-mtmips/mt7628/Makefile | 6 + > arch/mips/mach-mtmips/mt7628/ddr.c| 173 + > arch/mips/mach-mtmips/mt7628/init.c | 109 ++ > arch/mips/mach-mtmips/mt7628/lowlevel_init.S | 161 + > arch/mips/mach-mtmips/mt7628/mt7628.h | 104 ++ > arch/mips/mach-mtmips/mt7628/serial.c | 34 ++ > arch/mips/mach-mtmips/mt76xx.h| 32 -- > arch/mips/mach-mtmips/spl.c | 44 +++ > board/gardena/smart-gateway-mt7688/board.c| 2 + > board/mediatek/mt7628/Kconfig | 12 + > board/mediatek/mt7628/MAINTAINERS | 7 + > board/mediatek/mt7628/Makefile| 3 + > board/mediatek/mt7628/board.c | 8 + > common/spl/spl_nor.c
Re: [PATCH v5 17/20] spl: nor: add lzma decompression support for legacy image
On Wed, Feb 12, 2020 at 10:46 AM Weijie Gao wrote:
>
> This patch adds support for decompressing LZMA compressed u-boot payload in
> legacy uImage format.
>
> Using this patch together with u-boot-lzma.img is useful for NOR flashes as
> they can reduce the size and load time of u-boot payload.
>
> Reviewed-by: Stefan Roese
> Signed-off-by: Weijie Gao
> ---
> Changes since v3: removed unused code. add description for cache flushing
This is v5. What has changed since v4?
> ---
> common/spl/spl_nor.c | 51 +++-
> 1 file changed, 46 insertions(+), 5 deletions(-)
>
> diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
> index b1e79b9ded..b8e133e7b6 100644
> --- a/common/spl/spl_nor.c
> +++ b/common/spl/spl_nor.c
> @@ -4,8 +4,17 @@
> */
>
> #include
> +#include
> #include
>
> +#include
> +#include
> +#include
> +
> +#ifndef CONFIG_SYS_BOOTM_LEN
> +#define CONFIG_SYS_BOOTM_LEN (8 << 20)
> +#endif
> +
> static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector,
>ulong count, void *buf)
> {
> @@ -27,6 +36,9 @@ static int spl_nor_load_image(struct spl_image_info
> *spl_image,
> int ret;
> __maybe_unused const struct image_header *header;
> __maybe_unused struct spl_load_info load;
> + __maybe_unused SizeT lzma_len;
> + struct image_header hdr;
> + uintptr_t dataptr;
>
> /*
> * Loading of the payload to SDRAM is done with skipping of
> @@ -107,14 +119,43 @@ static int spl_nor_load_image(struct spl_image_info
> *spl_image,
> spl_nor_get_uboot_base());
> }
>
> - ret = spl_parse_image_header(spl_image,
> - (const struct image_header
> *)spl_nor_get_uboot_base());
> + /* Payload image may not be aligned, so copy it for safety. */
> + memcpy(&hdr, (void *)spl_nor_get_uboot_base(), sizeof(hdr));
> + ret = spl_parse_image_header(spl_image, &hdr);
> if (ret)
> return ret;
>
> - memcpy((void *)(unsigned long)spl_image->load_addr,
> - (void *)(spl_nor_get_uboot_base() + sizeof(struct
> image_header)),
> - spl_image->size);
> + dataptr = spl_nor_get_uboot_base() + sizeof(struct image_header);
> +
> + switch (image_get_comp(&hdr)) {
> + case IH_COMP_NONE:
> + memmove((void *)(unsigned long)spl_image->load_addr,
> + (void *)dataptr, spl_image->size);
> + break;
> +#if IS_ENABLED(CONFIG_SPL_LZMA)
> + case IH_COMP_LZMA:
> + lzma_len = CONFIG_SYS_BOOTM_LEN;
> +
> + ret = lzmaBuffToBuffDecompress((void *)spl_image->load_addr,
> + &lzma_len, (void *)dataptr,
> + spl_image->size);
Is using CONFIG_SYS_BOOTM_LEN correct here at all? The name says it is used for
bootm but now it is used for SPL loading U-Boot as well. How do we know this is
the available memory size for both use cases? (And no, you're not adding this,
it is being used in spl_fit.c already. Still, I'm not sure this is correct.)
> +
> + if (ret) {
> + printf("LZMA decompression error: %d\n", ret);
> + return ret;
> + }
> +
> + spl_image->size = lzma_len;
> + break;
> +#endif
> + default:
> + debug("Compression method %s is not supported\n",
> + genimg_get_comp_short_name(image_get_comp(&hdr)));
> + return -EINVAL;
> + }
> +
> + /* Flush instruction cache */
Is this "add description for cache flushing" mentioned in the log above? I can
see from the function name that you're flushing cache. Only I still don't see
why this is necessary here (but not in the rest of the code where SPL starts a
U-Boot image).
Regards,
Simon
> + flush_cache((unsigned long)spl_image->load_addr, spl_image->size);
>
> return 0;
> }
> --
> 2.17.1
Re: [PATCH v4 17/20] spl: nor: add lzma decompression support for legacy image
On Thu, Feb 13, 2020 at 8:53 AM Stefan wrote: > > Hi Simon, > > On 13.02.20 08:40, Simon Goldschmidt wrote: > > Sorry if it seems I ignored this mail yesterday, I just found it now :) > > > > On Wed, Feb 12, 2020 at 10:05 AM Stefan Roese wrote: > >> > >> On 12.02.20 09:57, Weijie Gao wrote: > >> > >> > >> > >>>> And more general: why do we need to code this in every loader? I think > >>>> it would > >>>> be preferrable to have the loader load the binary data and do the > >>>> decompression > >>>> (and entry_point assignment) in a central place so that all loaders can > >>>> benefit > >>>> from compression. As it is now, we are duplicating code when > >>>> implementing LZMA > >>>> in the next loader. > >> > >> I agree with Simon, that it would make sense to move this code into a > >> even more generic location, so that other "loaders" can also use this > >> feature. I know, that I suggested to add it here and I think we can > >> make this move into the common SPL interface at a later point, after > >> this patch set has been integrated. > > > > My concern is that we add poor code now and that cleanup at a "later point" > > just gets forgotten. > > I understand. > > > To me, this patch looks like another "get the stuff I need in fast" thing, > > without thinking about overall code quality. Yes it might be more work to > > do it properly, but in my opinion, the result will be code that is easier to > > maintain in the long run. > > I fully agree. But I already pushed Weijie to make many enhancements to > the code and I fear that this work gets just too complex (time > consuming) right now. As this type of generalization is not restricted > on this new lzma implementation, but will very likely touch other > features as well. > > So again, I'm still okay with adding this feature for spi_nor only right > now. But if Weijie volunteers to move it to a even more generic > location, that would be very welcome of course. ;) Ok, I'm not the one in charge to decide if it's ok to merge this code. Regards, Simon > > Thanks, > Stefan
Re: [PATCH v5 00/20] Refactor the architecture parts of mt7628
On Thu, Feb 13, 2020 at 9:42 AM Weijie Gao wrote: > > On Thu, 2020-02-13 at 08:48 +0100, Simon Goldschmidt wrote: > > On Wed, Feb 12, 2020 at 10:43 AM Weijie Gao wrote: > > > > > > This patch series are divided into two parts: > > > > > > The main part is to rewrite the whole architecture code of mt7628: > > > * Lock parts of the d-cache for initial stack so the rest of the code can > > > be reimplemented in C. > > > * Memory controller & DDR initialization have been fully written to > > > support > > > detecting DDR size automatically. > > > * DDR calibration has also been reimplemented with a clear logic. > > > * Implemented a new sysreset driver to take advantage of the reset > > > controller so we can drop the use of syscon-based sysreset to reduce > > > size. > > > > > > The second part is to add SPL support for mt7628: > > > * With SPL enabled we can build the ROM-bootable and RAM-bootable binary > > > simultaneously, and we can drop RAM boot related configs and defconfig > > > files. > > > * Generate compressed u-boot.bin image for SPL to reduce size of final > > > combined binary. > > > * Enable DM support for SPL for a more flexible device probing. > > > * Add a demo board (mt7628_rfb) aims at router application. > > > > > > Changes since v2: > > > * Dropped a patch which removes unused parts of mt7628a.dtsi > > > * Move lzma decompression support to common spl_nor.c > > > * Move u-boot,dm-pre-reloc to u-boot-mt7628.dtsi > > > > > > Changes since v3: > > > * Rebased on newest master branch > > > * Add a test for binman etype u-boot-lzma-img to make sure binman passes > > > 100% > > > code coverage > > > * Use u-boot-with-spl.bin for SPL-enabled output file > > > * Remove unused code from spl_nor loader. > > > > No changes for v5 (since v4)? > > v5 is based on v3, for replacing v4. Because v4 has an obvious mistake. > Modifying based on v3 is more clear than on v4. Hm, ok, you probably should have mentioned that somewhere. I got confused. Regards, Simon > > > > > Regards, > > Simon > > > > > > > > Weijie Gao (20): > > > mips: add support to restore exception vector base before booting > > > linux > > > mips: mtmips: add predefined i-cache/d-cache size and linesize > > > mips: add an option to support initialize SRAM for initial stack > > > mips: start.S: avoid overwriting outside gd when clearing global data > > > in stack > > > sysreset: add reset controller based reboot driver > > > mips: mtmips: make use of sysreset-resetctrl for mt7628 soc > > > configs: enable CONFIG_RESTORE_EXCEPTION_VECTOR_BASE for all mtmips > > > boards > > > mips: add a mtmips-specific field to architecture-specific global data > > > mips: add a option to support not reserving malloc space on initial > > > stack > > > mips: mtmips: rewrite lowlevel codes of mt7628 > > > dts: mtmips: add alternative pinmux node for uart2 > > > mips: enable support for appending dtb to spl binary > > > mips: add an option to enable u_boot_list section for SPL loaders in > > > u-boot-spl.lds > > > lib: enable lzma decompression support for SPL build > > > Makefile: add support to generate LZMA compressed u-boot image > > > tools: binman: add etype file for u-boot-lzma-img > > > spl: nor: add lzma decompression support for legacy image > > > mips: mtmips: add SPL support > > > mips: mtmips: enable SPL for all boards > > > mips: mtmips: add support for mt7628-rfb > > > > > > Makefile | 19 + > > > arch/mips/Kconfig | 66 > > > arch/mips/cpu/start.S | 16 +- > > > arch/mips/cpu/u-boot-spl.lds | 4 +- > > > arch/mips/dts/Makefile| 1 + > > > arch/mips/dts/mediatek,mt7628-rfb.dts | 67 > > > arch/mips/dts/mt7628-u-boot.dtsi | 56 +++ > > > arch/mips/dts/mt7628a.dtsi| 17 +- > > > arch/mips/include/asm/global_data.h | 3 + > > > arch/mips/include/asm/u-boot-mips.h | 2 + > > > arch/mips/lib/bootm.c | 3 + > > > arch/mips/lib/traps.c | 19 + > > > arch/mips/mach-mtm
Re: [PATCH 10/33] mtd: Rename free() to rfree()
On Wed, Feb 12, 2020 at 6:14 PM Simon Glass wrote: > > Hi Masahiro, > > On Wed, 12 Feb 2020 at 06:14, Masahiro Yamada wrote: > > > > On Mon, Jan 13, 2020 at 4:08 AM Simon Glass wrote: > > > > > > This function name conflicts with our desire to #define free() to > > > something else on sandbox. Since it deals with resources, rename it to > > > rfree(). > > > > > > Signed-off-by: Simon Glass > > > > > > I noticed this commit was merged recently. > > > > Now 'free' is a reserved keyword > > you cannot use in U-Boot. > > > > > > Commit cc92c3c thru cf23c7c are horrible. > > > > > > Commit cfda60f should have used > > 'static inline' instead of #define. > > > > I cannot believe it. > > Are you sure you understand the problem I was trying to solve? I am > using dlmalloc's existing means of adding a prefix, but I'm sure we > could change it to another way. > > If we define malloc() as dlmalloc() in dlmalloc.c, then we could add a > declaration in dlmalloc.h that uses static inline to convert calls to > malloc() to call dlmalloc(). Then anything that doesn't include > malloc.h would still call the C library malloc(). Is that what you are > thinking? There is no "malloc()" in dlmalloc.c. It is called "mALLOc()" and by defining USE_DL_PREFIX, you already have converted that to be linked as "dlmalloc()". I think there should be no difference in who calls what when converting your defines to static inline functions. And yes, I also dislike the other patches that remove all occurrences of 'free'. I think without knowing the backgrounds of your patches, that just looks strange. Regards, Simon > > I did look at using a link script instead but it is pretty messy. > > What do you mean by 'free' being a reserved keyword? Where? So is > 'rfree' a good substitute or do you suggest something else? > > Regards, > Simon
Re: [PATCH 1/2] ARM: socfpga: Permit overriding the default timer frequency
Am 15.02.2020 um 15:02 schrieb Marek Vasut: > The default timer rate may be different than 25 MHz, permit overriding > the default rate in board configuration file. Ultimatelly, this should > be properly handled by a clock driver, however that is not available > on Gen5 yet. Sigh, yes, I still haven't found the time to fight those size problems I have... :-( > > Signed-off-by: Marek Vasut > Cc: Ley Foon Tan > Cc: Simon Goldschmidt > --- > include/configs/socfpga_common.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > index 8d10469e7c..8c5dcfa57c 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -98,8 +98,10 @@ Just above this line, there's this comment: "This timer uses eosc1, whose clock frequency is fixed at any condition". While I'm ok with the change below, it does look a bit funny to make this overriable if it's "fixed at any condition". Could you elaborate on this? Do we need to change the comment? Regards, Simon > #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS > #define CONFIG_SYS_TIMER_COUNTS_DOWN > #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) > +#ifndef CONFIG_SYS_TIMER_RATE > #define CONFIG_SYS_TIMER_RATE2500 > #endif > +#endif > > /* > * L4 Watchdog >
Re: [PATCH 1/2] ARM: socfpga: Permit overriding the default timer frequency
On Sat, Feb 15, 2020 at 10:40 PM Marek Vasut wrote: > > On 2/15/20 8:39 PM, Simon Goldschmidt wrote: > > Am 15.02.2020 um 15:02 schrieb Marek Vasut: > >> The default timer rate may be different than 25 MHz, permit overriding > >> the default rate in board configuration file. Ultimatelly, this should > >> be properly handled by a clock driver, however that is not available > >> on Gen5 yet. > > > > Sigh, yes, I still haven't found the time to fight those size problems I > > have... :-( > > > >> > >> Signed-off-by: Marek Vasut > >> Cc: Ley Foon Tan > >> Cc: Simon Goldschmidt > >> --- > >> include/configs/socfpga_common.h | 2 ++ > >> 1 file changed, 2 insertions(+) > >> > >> diff --git a/include/configs/socfpga_common.h > >> b/include/configs/socfpga_common.h > >> index 8d10469e7c..8c5dcfa57c 100644 > >> --- a/include/configs/socfpga_common.h > >> +++ b/include/configs/socfpga_common.h > >> @@ -98,8 +98,10 @@ > > > > Just above this line, there's this comment: "This timer uses eosc1, > > whose clock frequency is fixed at any condition". > > > > While I'm ok with the change below, it does look a bit funny to make > > this overriable if it's "fixed at any condition". Could you elaborate on > > this? Do we need to change the comment? > > The comment is probably wrong, since you can connect the SoCFPGA > external oscillator input to any applicable xtal ? Right. Could you delete that comment then with this patch to prevent confusion? Regards, Simon
Re: [PATCH V2 1/2] ARM: socfpga: Permit overriding the default timer frequency
Am 17.02.2020 um 18:30 schrieb Marek Vasut: > The default timer rate may be different than 25 MHz, permit overriding > the default rate in board configuration file. Ultimatelly, this should > be properly handled by a clock driver, however that is not available > on Gen5 yet. > > Signed-off-by: Marek Vasut > Cc: Ley Foon Tan > Cc: Simon Goldschmidt Reviewed-by: Simon Goldschmidt > --- > V2: Drop misleading comment > --- > include/configs/socfpga_common.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > index 8d10469e7c..54a43569dc 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -94,12 +94,13 @@ > * L4 OSC1 Timer 0 > */ > #ifndef CONFIG_TIMER > -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ > #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS > #define CONFIG_SYS_TIMER_COUNTS_DOWN > #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) > +#ifndef CONFIG_SYS_TIMER_RATE > #define CONFIG_SYS_TIMER_RATE2500 > #endif > +#endif > > /* > * L4 Watchdog >
Re: [PATCH v4 0/5] usb: host: dwc2: use driver model for PHY and CLOCK
On Tue, Feb 18, 2020 at 6:53 PM Marek Vasut wrote: > > On 2/18/20 9:34 AM, Patrick Delaunay wrote: > > > > In this serie I update the DWC2 host driver to use the device tree > > information and the associated PHY and CLOCK drivers when they are > > availables. > > > > The V4 is rebased on latest master (v2020.04-rc2). > > CI-Tavis build is OK: > > https://travis-ci.org/patrickdelaunay/u-boot/builds/651479714 > > > > NB: CI-Travis build was OK for all target after V3: > > https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 > > As in V2, I cause the warnings for some boards: > > drivers/usb/host/built-in.o: In function `dwc2_usb_remove': > > drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' > > > > I test this serie on stm32mp157c-ev1 board, with PHY and CLK > > support > > > > The U-CLASS are provided by: > > - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c > > - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c > > - RESET by RCC reset driver = drivers/reset/stm32-reset.c > > > > And I activate the configuration > > +CONFIG_USB_DWC2=y > > Simon, can you test this on SOCFPGA ? I can test if it probes, but I don't have anything running on that USB port the socfpga_socrates board has. Would that be enought to test? Regards, Simon > > [...]
[PATCH 0/8] malloc: implement USE_DL_PREFIX using inline functions
Commit cfda60f99ae2 ("sandbox: Use a prefix for all allocation functions")
introduced preprocessor macros for malloc/free etc.
This is bad practice as it essentially makes 'free' a reserved keyword and
resulted in quite a bit of renaming to avoid that reserved keyword.
A better solution is to define the allocation functions as 'static inline'.
This should go in before the release, as it's a regression not seen before
the last release.
A side-effect is that exports.h may not declare malloc/free. I'm not really
sure if this is correct, but for sandbox, it should probably be ok?
Simon Goldschmidt (8):
malloc: implement USE_DL_PREFIX via inline functions
Revert "mtd: Rename free() to rfree()"
Revert "dma: Rename free() to rfree()"
Revert "clk: Rename free() to rfree()"
Revert "gpio: Rename free() to rfree()"
Revert "reset: Rename free() to rfree()"
Revert "power-domain: Rename free() to rfree()"
Revert "mailbox: Rename free() to rfree()"
drivers/clk/clk-ti-sci.c | 2 +-
drivers/clk/clk-uclass.c | 4 +-
drivers/clk/clk_sandbox.c | 2 +-
drivers/clk/tegra/tegra-car-clk.c | 2 +-
drivers/dma/dma-uclass.c | 4 +-
drivers/dma/sandbox-dma-test.c| 4 +-
drivers/dma/ti/k3-udma.c | 4 +-
drivers/gpio/gpio-rcar.c | 2 +-
drivers/gpio/gpio-uclass.c| 8 ++--
drivers/mailbox/k3-sec-proxy.c| 2 +-
drivers/mailbox/mailbox-uclass.c | 4 +-
drivers/mailbox/sandbox-mbox.c| 2 +-
drivers/mailbox/stm32-ipcc.c | 2 +-
drivers/mailbox/tegra-hsp.c | 2 +-
drivers/mtd/mtdcore.c | 4 +-
drivers/mtd/nand/raw/denali.c | 2 +-
drivers/mtd/nand/spi/core.c | 2 +-
drivers/mtd/nand/spi/gigadevice.c | 2 +-
drivers/mtd/nand/spi/macronix.c | 2 +-
drivers/mtd/nand/spi/micron.c | 2 +-
drivers/mtd/nand/spi/winbond.c| 2 +-
drivers/power/domain/bcm6328-power-domain.c | 2 +-
.../power/domain/imx8-power-domain-legacy.c | 2 +-
drivers/power/domain/imx8-power-domain.c | 2 +-
drivers/power/domain/imx8m-power-domain.c | 2 +-
drivers/power/domain/meson-ee-pwrc.c | 2 +-
drivers/power/domain/meson-gx-pwrc-vpu.c | 2 +-
drivers/power/domain/mtk-power-domain.c | 2 +-
drivers/power/domain/power-domain-uclass.c| 2 +-
drivers/power/domain/sandbox-power-domain.c | 2 +-
drivers/power/domain/tegra186-power-domain.c | 2 +-
drivers/power/domain/ti-sci-power-domain.c| 2 +-
drivers/reset/reset-bcm6345.c | 2 +-
drivers/reset/reset-hisilicon.c | 2 +-
drivers/reset/reset-hsdk.c| 2 +-
drivers/reset/reset-imx7.c| 2 +-
drivers/reset/reset-mediatek.c| 2 +-
drivers/reset/reset-meson.c | 2 +-
drivers/reset/reset-mtmips.c | 2 +-
drivers/reset/reset-rockchip.c| 2 +-
drivers/reset/reset-socfpga.c | 2 +-
drivers/reset/reset-sunxi.c | 2 +-
drivers/reset/reset-ti-sci.c | 2 +-
drivers/reset/reset-uclass.c | 2 +-
drivers/reset/reset-uniphier.c| 2 +-
drivers/reset/sandbox-reset.c | 2 +-
drivers/reset/sti-reset.c | 2 +-
drivers/reset/stm32-reset.c | 2 +-
drivers/reset/tegra-car-reset.c | 2 +-
drivers/reset/tegra186-reset.c| 2 +-
include/_exports.h| 2 +
include/asm-generic/gpio.h| 2 +-
include/clk-uclass.h | 4 +-
include/dma-uclass.h | 4 +-
include/exports.h | 2 +
include/linux/mtd/mtd.h | 4 +-
include/mailbox-uclass.h | 4 +-
include/malloc.h | 44 ---
include/power-domain-uclass.h | 4 +-
include/reset-uclass.h| 4 +-
60 files changed, 105 insertions(+), 87 deletions(-)
--
2.20.1
[PATCH 1/8] malloc: implement USE_DL_PREFIX via inline functions
Commit cfda60f99ae2 ("sandbox: Use a prefix for all allocation functions")
introduced preprocessor macros for malloc/free etc.
This is bad practice as it essentially makes 'free' a reserved keyword and
resulted in quite a bit of renaming to avoid that reserved keyword.
A better solution is to define the allocation functions as 'static inline'.
As a side effect, exports.h must not export malloc/free for sandbox.
Signed-off-by: Simon Goldschmidt
---
A side-effect is that exports.h may not declare malloc/free. I'm not really
sure if this is correct, but for sandbox, it should probably be ok?
include/_exports.h | 2 ++
include/exports.h | 2 ++
include/malloc.h | 44 +---
3 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/include/_exports.h b/include/_exports.h
index 0dee05f077..acfbf97c17 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -22,9 +22,11 @@
EXPORT_FUNC(dummy, void, install_hdlr, void)
EXPORT_FUNC(dummy, void, free_hdlr, void)
#endif
+#ifndef CONFIG_SANDBOX
EXPORT_FUNC(malloc, void *, malloc, size_t)
#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
EXPORT_FUNC(free, void, free, void *)
+#endif
#endif
EXPORT_FUNC(udelay, void, udelay, unsigned long)
EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long)
diff --git a/include/exports.h b/include/exports.h
index cbd16fc518..5d161824c8 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -25,10 +25,12 @@ void puts(const char*);
int printf(const char* fmt, ...);
void install_hdlr(int, interrupt_handler_t, void*);
void free_hdlr(int);
+#ifndef CONFIG_SANDBOX
void *malloc(size_t);
#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
void free(void*);
#endif
+#endif
void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
int vprintf(const char *, va_list);
diff --git a/include/malloc.h b/include/malloc.h
index f66c2e8617..50d4873b08 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -897,21 +897,6 @@ void malloc_simple_info(void);
# define pvALLOc dlpvalloc
# define mALLINFo dlmallinfo
# define mALLOPt dlmallopt
-
-/* Ensure that U-Boot actually uses these too */
-#define calloc dlcalloc
-#define free(ptr) dlfree(ptr)
-#define malloc(x) dlmalloc(x)
-#define memalign dlmemalign
-#define realloc dlrealloc
-#define valloc dlvalloc
-#define pvalloc dlpvalloc
-#define mallinfo() dlmallinfo()
-#define mallopt dlmallopt
-#define malloc_trim dlmalloc_trim
-#define malloc_usable_size dlmalloc_usable_size
-#define malloc_stats dlmalloc_stats
-
# else /* USE_DL_PREFIX */
# define cALLOccalloc
# define fREe free
@@ -966,6 +951,35 @@ voidmalloc_stats();
int mALLOPt();
struct mallinfo mALLINFo();
# endif
+
+# ifdef USE_DL_PREFIX
+/* Ensure that U-Boot actually uses the redefined functions: */
+static inline void *calloc(size_t n, size_t elem_size)
+{
+ return dlcalloc(n, elem_size);
+}
+
+static inline void free(void *ptr) { dlfree(ptr); }
+static inline void *malloc(size_t bytes) { return dlmalloc(bytes); }
+static inline void *memalign(size_t alignment, size_t bytes)
+{
+ return dlmemalign(alignment, bytes);
+}
+
+static inline void *realloc(void *oldmem, size_t bytes)
+{
+ return dlrealloc(oldmem, bytes);
+}
+
+static inline void *valloc(size_t bytes) { return dlvalloc(bytes); }
+static inline void *pvalloc(size_t bytes) { return dlpvalloc(bytes); }
+static inline struct mallinfo mallinfo(void) { return dlmallinfo(); }
+static inline int mallopt(int param_number, int value)
+{
+ return dlmallopt(param_number, value);
+}
+# endif
+
#endif
#pragma GCC visibility pop
--
2.20.1
[PATCH 3/8] Revert "dma: Rename free() to rfree()"
This reverts commit aae95882232a24ee49c89d0356febf3685a87c8a.
Signed-off-by: Simon Goldschmidt
---
drivers/dma/dma-uclass.c | 4 ++--
drivers/dma/sandbox-dma-test.c | 4 ++--
drivers/dma/ti/k3-udma.c | 4 ++--
include/dma-uclass.h | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index 9d5a7fc796..68e17ed1f9 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -123,10 +123,10 @@ int dma_free(struct dma *dma)
debug("%s(dma=%p)\n", __func__, dma);
- if (!ops->rfree)
+ if (!ops->free)
return 0;
- return ops->rfree(dma);
+ return ops->free(dma);
}
int dma_enable(struct dma *dma)
diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c
index 234a7d2134..e8c809fa64 100644
--- a/drivers/dma/sandbox-dma-test.c
+++ b/drivers/dma/sandbox-dma-test.c
@@ -89,7 +89,7 @@ static int sandbox_dma_request(struct dma *dma)
return 0;
}
-static int sandbox_dma_rfree(struct dma *dma)
+static int sandbox_dma_free(struct dma *dma)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
@@ -230,7 +230,7 @@ static const struct dma_ops sandbox_dma_ops = {
.transfer = sandbox_dma_transfer,
.of_xlate = sandbox_dma_of_xlate,
.request= sandbox_dma_request,
- .rfree = sandbox_dma_rfree,
+ .free = sandbox_dma_free,
.enable = sandbox_dma_enable,
.disable= sandbox_dma_disable,
.send = sandbox_dma_send,
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f274100f32..d6eb6d9339 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1553,7 +1553,7 @@ static int udma_request(struct dma *dma)
return 0;
}
-static int udma_rfree(struct dma *dma)
+static int udma_free(struct dma *dma)
{
struct udma_dev *ud = dev_get_priv(dma->dev);
struct udma_chan *uc;
@@ -1848,7 +1848,7 @@ static const struct dma_ops udma_ops = {
.transfer = udma_transfer,
.of_xlate = udma_of_xlate,
.request= udma_request,
- .rfree = udma_rfree,
+ .free = udma_free,
.enable = udma_enable,
.disable= udma_disable,
.send = udma_send,
diff --git a/include/dma-uclass.h b/include/dma-uclass.h
index 340437acc1..a1d9d26ac5 100644
--- a/include/dma-uclass.h
+++ b/include/dma-uclass.h
@@ -58,14 +58,14 @@ struct dma_ops {
*/
int (*request)(struct dma *dma);
/**
-* rfree - Free a previously requested dma.
+* free - Free a previously requested dma.
*
* This is the implementation of the client dma_free() API.
*
* @dma: The DMA to free.
* @return 0 if OK, or a negative error code.
*/
- int (*rfree)(struct dma *dma);
+ int (*free)(struct dma *dma);
/**
* enable() - Enable a DMA Channel.
*
--
2.20.1
[PATCH 7/8] Revert "power-domain: Rename free() to rfree()"
This reverts commit 4f51188e47921b17e6b3ce9606c8e71234c9f2df.
Signed-off-by: Simon Goldschmidt
---
drivers/power/domain/bcm6328-power-domain.c | 2 +-
drivers/power/domain/imx8-power-domain-legacy.c | 2 +-
drivers/power/domain/imx8-power-domain.c| 2 +-
drivers/power/domain/imx8m-power-domain.c | 2 +-
drivers/power/domain/meson-ee-pwrc.c| 2 +-
drivers/power/domain/meson-gx-pwrc-vpu.c| 2 +-
drivers/power/domain/mtk-power-domain.c | 2 +-
drivers/power/domain/power-domain-uclass.c | 2 +-
drivers/power/domain/sandbox-power-domain.c | 2 +-
drivers/power/domain/tegra186-power-domain.c| 2 +-
drivers/power/domain/ti-sci-power-domain.c | 2 +-
include/power-domain-uclass.h | 4 ++--
12 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/power/domain/bcm6328-power-domain.c
b/drivers/power/domain/bcm6328-power-domain.c
index a6426bee27..e261d22b50 100644
--- a/drivers/power/domain/bcm6328-power-domain.c
+++ b/drivers/power/domain/bcm6328-power-domain.c
@@ -63,7 +63,7 @@ static const struct udevice_id bcm6328_power_domain_ids[] = {
};
struct power_domain_ops bcm6328_power_domain_ops = {
- .rfree = bcm6328_power_domain_free,
+ .free = bcm6328_power_domain_free,
.off = bcm6328_power_domain_off,
.on = bcm6328_power_domain_on,
.request = bcm6328_power_domain_request,
diff --git a/drivers/power/domain/imx8-power-domain-legacy.c
b/drivers/power/domain/imx8-power-domain-legacy.c
index 6f01a60b34..f489083f2d 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -297,7 +297,7 @@ static const struct udevice_id imx8_power_domain_ids[] = {
struct power_domain_ops imx8_power_domain_ops = {
.request = imx8_power_domain_request,
- .rfree = imx8_power_domain_free,
+ .free = imx8_power_domain_free,
.on = imx8_power_domain_on,
.off = imx8_power_domain_off,
.of_xlate = imx8_power_domain_of_xlate,
diff --git a/drivers/power/domain/imx8-power-domain.c
b/drivers/power/domain/imx8-power-domain.c
index 571146e19d..eaf8635899 100644
--- a/drivers/power/domain/imx8-power-domain.c
+++ b/drivers/power/domain/imx8-power-domain.c
@@ -74,7 +74,7 @@ static const struct udevice_id imx8_power_domain_ids[] = {
struct power_domain_ops imx8_power_domain_ops_v2 = {
.request = imx8_power_domain_request,
- .rfree = imx8_power_domain_free,
+ .free = imx8_power_domain_free,
.on = imx8_power_domain_on,
.off = imx8_power_domain_off,
};
diff --git a/drivers/power/domain/imx8m-power-domain.c
b/drivers/power/domain/imx8m-power-domain.c
index 5b6467cda7..48a3fca6bd 100644
--- a/drivers/power/domain/imx8m-power-domain.c
+++ b/drivers/power/domain/imx8m-power-domain.c
@@ -122,7 +122,7 @@ static const struct udevice_id imx8m_power_domain_ids[] = {
struct power_domain_ops imx8m_power_domain_ops = {
.request = imx8m_power_domain_request,
- .rfree = imx8m_power_domain_free,
+ .free = imx8m_power_domain_free,
.on = imx8m_power_domain_on,
.off = imx8m_power_domain_off,
.of_xlate = imx8m_power_domain_of_xlate,
diff --git a/drivers/power/domain/meson-ee-pwrc.c
b/drivers/power/domain/meson-ee-pwrc.c
index 7082c80bfa..f09bc03811 100644
--- a/drivers/power/domain/meson-ee-pwrc.c
+++ b/drivers/power/domain/meson-ee-pwrc.c
@@ -354,7 +354,7 @@ static int meson_ee_pwrc_of_xlate(struct power_domain
*power_domain,
}
struct power_domain_ops meson_ee_pwrc_ops = {
- .rfree = meson_ee_pwrc_free,
+ .free = meson_ee_pwrc_free,
.off = meson_ee_pwrc_off,
.on = meson_ee_pwrc_on,
.request = meson_ee_pwrc_request,
diff --git a/drivers/power/domain/meson-gx-pwrc-vpu.c
b/drivers/power/domain/meson-gx-pwrc-vpu.c
index 12cdfcdd1f..8381cb226d 100644
--- a/drivers/power/domain/meson-gx-pwrc-vpu.c
+++ b/drivers/power/domain/meson-gx-pwrc-vpu.c
@@ -271,7 +271,7 @@ static int meson_pwrc_vpu_of_xlate(struct power_domain
*power_domain,
}
struct power_domain_ops meson_gx_pwrc_vpu_ops = {
- .rfree = meson_pwrc_vpu_free,
+ .free = meson_pwrc_vpu_free,
.off = meson_pwrc_vpu_off,
.on = meson_pwrc_vpu_on,
.request = meson_pwrc_vpu_request,
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
index 3ff7ca1bef..dcf33678d7 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -398,7 +398,7 @@ static const struct udevice_id mtk_power_domain_ids[] = {
};
struct power_domain_ops mtk_power_domain_ops = {
- .rfree = scpsys_power_free,
+ .free = scpsys_power_free,
.off = scpsys_power_off,
.on = scpsys_power_on,
.request = scpsys_power_request,
diff --git a/drivers/power/domain/power-domain-uclass.c
b/drivers/power/domain/power-domain-uclass.c
index d9c623b56e
[PATCH 4/8] Revert "clk: Rename free() to rfree()"
This reverts commit fb8c0d595f1ad83bee5dd398b59b0ee16d8d15a9.
Signed-off-by: Simon Goldschmidt
---
drivers/clk/clk-ti-sci.c | 2 +-
drivers/clk/clk-uclass.c | 4 ++--
drivers/clk/clk_sandbox.c | 2 +-
drivers/clk/tegra/tegra-car-clk.c | 2 +-
include/clk-uclass.h | 4 ++--
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/clk-ti-sci.c
index 82241d9f3f..e272003d30 100644
--- a/drivers/clk/clk-ti-sci.c
+++ b/drivers/clk/clk-ti-sci.c
@@ -206,7 +206,7 @@ static const struct udevice_id ti_sci_clk_of_match[] = {
static struct clk_ops ti_sci_clk_ops = {
.of_xlate = ti_sci_clk_of_xlate,
.request = ti_sci_clk_request,
- .rfree = ti_sci_clk_free,
+ .free = ti_sci_clk_free,
.get_rate = ti_sci_clk_get_rate,
.set_rate = ti_sci_clk_set_rate,
.set_parent = ti_sci_clk_set_parent,
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 71878474eb..24353fae53 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -426,10 +426,10 @@ int clk_free(struct clk *clk)
return 0;
ops = clk_dev_ops(clk->dev);
- if (!ops->rfree)
+ if (!ops->free)
return 0;
- return ops->rfree(clk);
+ return ops->free(clk);
}
ulong clk_get_rate(struct clk *clk)
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 768fbb7c52..7059979606 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -108,7 +108,7 @@ static struct clk_ops sandbox_clk_ops = {
.enable = sandbox_clk_enable,
.disable= sandbox_clk_disable,
.request= sandbox_clk_request,
- .rfree = sandbox_clk_free,
+ .free = sandbox_clk_free,
};
static int sandbox_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/tegra/tegra-car-clk.c
b/drivers/clk/tegra/tegra-car-clk.c
index 6083f14e75..1f0e2dc95b 100644
--- a/drivers/clk/tegra/tegra-car-clk.c
+++ b/drivers/clk/tegra/tegra-car-clk.c
@@ -81,7 +81,7 @@ static int tegra_car_clk_disable(struct clk *clk)
static struct clk_ops tegra_car_clk_ops = {
.request = tegra_car_clk_request,
- .rfree = tegra_car_clk_free,
+ .free = tegra_car_clk_free,
.get_rate = tegra_car_clk_get_rate,
.set_rate = tegra_car_clk_set_rate,
.enable = tegra_car_clk_enable,
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index dac42dab36..e76d98e2f6 100644
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -53,14 +53,14 @@ struct clk_ops {
*/
int (*request)(struct clk *clock);
/**
-* rfree - Free a previously requested clock.
+* free - Free a previously requested clock.
*
* This is the implementation of the client clk_free() API.
*
* @clock: The clock to free.
* @return 0 if OK, or a negative error code.
*/
- int (*rfree)(struct clk *clock);
+ int (*free)(struct clk *clock);
/**
* get_rate() - Get current clock rate.
*
--
2.20.1
[PATCH 2/8] Revert "mtd: Rename free() to rfree()"
This reverts commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0.
Signed-off-by: Simon Goldschmidt
---
drivers/mtd/mtdcore.c | 4 ++--
drivers/mtd/nand/raw/denali.c | 2 +-
drivers/mtd/nand/spi/core.c | 2 +-
drivers/mtd/nand/spi/gigadevice.c | 2 +-
drivers/mtd/nand/spi/macronix.c | 2 +-
drivers/mtd/nand/spi/micron.c | 2 +-
drivers/mtd/nand/spi/winbond.c| 2 +-
include/linux/mtd/mtd.h | 4 ++--
8 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index f8d3f4d246..4567e5eb7a 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -1180,10 +1180,10 @@ int mtd_ooblayout_free(struct mtd_info *mtd, int
section,
if (!mtd || section < 0)
return -EINVAL;
- if (!mtd->ooblayout || !mtd->ooblayout->rfree)
+ if (!mtd->ooblayout || !mtd->ooblayout->free)
return -ENOTSUPP;
- return mtd->ooblayout->rfree(mtd, section, oobfree);
+ return mtd->ooblayout->free(mtd, section, oobfree);
}
EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index f51d3e25c7..550fb7c771 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -1160,7 +1160,7 @@ static int denali_ooblayout_free(struct mtd_info *mtd,
int section,
static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
.ecc = denali_ooblayout_ecc,
- .rfree = denali_ooblayout_free,
+ .free = denali_ooblayout_free,
};
static int denali_multidev_fixup(struct denali_nand_info *denali)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index cd624ec6ae..5e3704e4d0 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1023,7 +1023,7 @@ static int spinand_noecc_ooblayout_free(struct mtd_info
*mtd, int section,
static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
.ecc = spinand_noecc_ooblayout_ecc,
- .rfree = spinand_noecc_ooblayout_free,
+ .free = spinand_noecc_ooblayout_free,
};
static int spinand_init(struct spinand_device *spinand)
diff --git a/drivers/mtd/nand/spi/gigadevice.c
b/drivers/mtd/nand/spi/gigadevice.c
index 0b228dcb5b..4c8bb1e12d 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -104,7 +104,7 @@ static int gd5fxgq4xexxg_ecc_get_status(struct
spinand_device *spinand,
static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout = {
.ecc = gd5fxgq4xexxg_ooblayout_ecc,
- .rfree = gd5fxgq4xexxg_ooblayout_free,
+ .free = gd5fxgq4xexxg_ooblayout_free,
};
static const struct spinand_info gigadevice_spinand_table[] = {
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
index 67d092be2c..2948e2ea41 100644
--- a/drivers/mtd/nand/spi/macronix.c
+++ b/drivers/mtd/nand/spi/macronix.c
@@ -48,7 +48,7 @@ static int mx35lfxge4ab_ooblayout_free(struct mtd_info *mtd,
int section,
static const struct mtd_ooblayout_ops mx35lfxge4ab_ooblayout = {
.ecc = mx35lfxge4ab_ooblayout_ecc,
- .rfree = mx35lfxge4ab_ooblayout_free,
+ .free = mx35lfxge4ab_ooblayout_free,
};
static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 687306e33e..718c4b42ca 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -64,7 +64,7 @@ static int mt29f2g01abagd_ooblayout_free(struct mtd_info
*mtd, int section,
static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = {
.ecc = mt29f2g01abagd_ooblayout_ecc,
- .rfree = mt29f2g01abagd_ooblayout_free,
+ .free = mt29f2g01abagd_ooblayout_free,
};
static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index 6ede98c85d..b05cd70457 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -60,7 +60,7 @@ static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int
section,
static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
.ecc = w25m02gv_ooblayout_ecc,
- .rfree = w25m02gv_ooblayout_free,
+ .free = w25m02gv_ooblayout_free,
};
static int w25m02gv_select_target(struct spinand_device *spinand,
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 1b9151714c..ceffd994de 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -129,8 +129,8 @@ struct mtd_oob_region {
struct mtd_ooblayout_ops {
int (*ecc)(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobecc);
- int (*rfree)(struct mtd_info *mtd, int section,
-struct mtd_oob_region *oobfree);
+ int (*free)(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree);
};
/*
--
2.20.1
[PATCH 5/8] Revert "gpio: Rename free() to rfree()"
This reverts commit 093152f275e036e54d48b3d9fc0adbc1ca4cc5b0.
Signed-off-by: Simon Goldschmidt
---
drivers/gpio/gpio-rcar.c | 2 +-
drivers/gpio/gpio-uclass.c | 8
include/asm-generic/gpio.h | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 9dc4cd6042..25bbbcde4b 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -130,7 +130,7 @@ static int rcar_gpio_free(struct udevice *dev, unsigned
offset)
static const struct dm_gpio_ops rcar_gpio_ops = {
.request= rcar_gpio_request,
- .rfree = rcar_gpio_free,
+ .free = rcar_gpio_free,
.direction_input= rcar_gpio_direction_input,
.direction_output = rcar_gpio_direction_output,
.get_value = rcar_gpio_get_value,
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 0a22441d38..90fbed455b 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -364,8 +364,8 @@ int _dm_gpio_free(struct udevice *dev, uint offset)
uc_priv = dev_get_uclass_priv(dev);
if (!uc_priv->name[offset])
return -ENXIO;
- if (gpio_get_ops(dev)->rfree) {
- ret = gpio_get_ops(dev)->rfree(dev, offset);
+ if (gpio_get_ops(dev)->free) {
+ ret = gpio_get_ops(dev)->free(dev, offset);
if (ret)
return ret;
}
@@ -1043,8 +1043,8 @@ static int gpio_post_bind(struct udevice *dev)
if (!reloc_done) {
if (ops->request)
ops->request += gd->reloc_off;
- if (ops->rfree)
- ops->rfree += gd->reloc_off;
+ if (ops->free)
+ ops->free += gd->reloc_off;
if (ops->direction_input)
ops->direction_input += gd->reloc_off;
if (ops->direction_output)
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 05777e6afe..d6cf18744f 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -248,7 +248,7 @@ int gpio_xlate_offs_flags(struct udevice *dev, struct
gpio_desc *desc,
*/
struct dm_gpio_ops {
int (*request)(struct udevice *dev, unsigned offset, const char *label);
- int (*rfree)(struct udevice *dev, unsigned int offset);
+ int (*free)(struct udevice *dev, unsigned offset);
int (*direction_input)(struct udevice *dev, unsigned offset);
int (*direction_output)(struct udevice *dev, unsigned offset,
int value);
--
2.20.1
[PATCH 8/8] Revert "mailbox: Rename free() to rfree()"
This reverts commit cc92c3cc68a9053f53b2814e9233d86553cc998e.
Signed-off-by: Simon Goldschmidt
---
drivers/mailbox/k3-sec-proxy.c | 2 +-
drivers/mailbox/mailbox-uclass.c | 4 ++--
drivers/mailbox/sandbox-mbox.c | 2 +-
drivers/mailbox/stm32-ipcc.c | 2 +-
drivers/mailbox/tegra-hsp.c | 2 +-
include/mailbox-uclass.h | 4 ++--
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index a560209f03..0546752f5f 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -293,7 +293,7 @@ static int k3_sec_proxy_recv(struct mbox_chan *chan, void
*data)
struct mbox_ops k3_sec_proxy_mbox_ops = {
.of_xlate = k3_sec_proxy_of_xlate,
.request = k3_sec_proxy_request,
- .rfree = k3_sec_proxy_free,
+ .free = k3_sec_proxy_free,
.send = k3_sec_proxy_send,
.recv = k3_sec_proxy_recv,
};
diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
index 291f5c218e..f408f05cf9 100644
--- a/drivers/mailbox/mailbox-uclass.c
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -106,8 +106,8 @@ int mbox_free(struct mbox_chan *chan)
debug("%s(chan=%p)\n", __func__, chan);
- if (ops->rfree)
- return ops->rfree(chan);
+ if (ops->free)
+ return ops->free(chan);
return 0;
}
diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c
index 25e23eb05b..0f09dfa951 100644
--- a/drivers/mailbox/sandbox-mbox.c
+++ b/drivers/mailbox/sandbox-mbox.c
@@ -88,7 +88,7 @@ static const struct udevice_id sandbox_mbox_ids[] = {
struct mbox_ops sandbox_mbox_mbox_ops = {
.request = sandbox_mbox_request,
- .rfree = sandbox_mbox_free,
+ .free = sandbox_mbox_free,
.send = sandbox_mbox_send,
.recv = sandbox_mbox_recv,
};
diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c
index 13e642ab70..c58d9fa001 100644
--- a/drivers/mailbox/stm32-ipcc.c
+++ b/drivers/mailbox/stm32-ipcc.c
@@ -154,7 +154,7 @@ static const struct udevice_id stm32_ipcc_ids[] = {
struct mbox_ops stm32_ipcc_mbox_ops = {
.request = stm32_ipcc_request,
- .rfree = stm32_ipcc_free,
+ .free = stm32_ipcc_free,
.send = stm32_ipcc_send,
.recv = stm32_ipcc_recv,
};
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 60f6a38321..00fc3972f9 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -176,7 +176,7 @@ static const struct udevice_id tegra_hsp_ids[] = {
struct mbox_ops tegra_hsp_mbox_ops = {
.of_xlate = tegra_hsp_of_xlate,
.request = tegra_hsp_request,
- .rfree = tegra_hsp_free,
+ .free = tegra_hsp_free,
.send = tegra_hsp_send,
.recv = tegra_hsp_recv,
};
diff --git a/include/mailbox-uclass.h b/include/mailbox-uclass.h
index 3c60c76506..e0618aad97 100644
--- a/include/mailbox-uclass.h
+++ b/include/mailbox-uclass.h
@@ -49,14 +49,14 @@ struct mbox_ops {
*/
int (*request)(struct mbox_chan *chan);
/**
-* rfree - Free a previously requested channel.
+* free - Free a previously requested channel.
*
* This is the implementation of the client mbox_free() API.
*
* @chan: The channel to free.
* @return 0 if OK, or a negative error code.
*/
- int (*rfree)(struct mbox_chan *chan);
+ int (*free)(struct mbox_chan *chan);
/**
* send - Send a message over a mailbox channel
*
--
2.20.1
[PATCH 6/8] Revert "reset: Rename free() to rfree()"
This reverts commit 94474b25c3a60a746bf641a975c3db239dae29b9.
Signed-off-by: Simon Goldschmidt
---
drivers/reset/reset-bcm6345.c | 2 +-
drivers/reset/reset-hisilicon.c | 2 +-
drivers/reset/reset-hsdk.c | 2 +-
drivers/reset/reset-imx7.c | 2 +-
drivers/reset/reset-mediatek.c | 2 +-
drivers/reset/reset-meson.c | 2 +-
drivers/reset/reset-mtmips.c| 2 +-
drivers/reset/reset-rockchip.c | 2 +-
drivers/reset/reset-socfpga.c | 2 +-
drivers/reset/reset-sunxi.c | 2 +-
drivers/reset/reset-ti-sci.c| 2 +-
drivers/reset/reset-uclass.c| 2 +-
drivers/reset/reset-uniphier.c | 2 +-
drivers/reset/sandbox-reset.c | 2 +-
drivers/reset/sti-reset.c | 2 +-
drivers/reset/stm32-reset.c | 2 +-
drivers/reset/tegra-car-reset.c | 2 +-
drivers/reset/tegra186-reset.c | 2 +-
include/reset-uclass.h | 4 ++--
19 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c
index c1f1e7f70b..f26582479e 100644
--- a/drivers/reset/reset-bcm6345.c
+++ b/drivers/reset/reset-bcm6345.c
@@ -53,7 +53,7 @@ static int bcm6345_reset_request(struct reset_ctl *rst)
}
struct reset_ops bcm6345_reset_reset_ops = {
- .rfree = bcm6345_reset_free,
+ .free = bcm6345_reset_free,
.request = bcm6345_reset_request,
.rst_assert = bcm6345_reset_assert,
.rst_deassert = bcm6345_reset_deassert,
diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c
index a678b8f745..54a254f9cb 100644
--- a/drivers/reset/reset-hisilicon.c
+++ b/drivers/reset/reset-hisilicon.c
@@ -73,7 +73,7 @@ static int hisi_reset_of_xlate(struct reset_ctl *rst,
static const struct reset_ops hisi_reset_reset_ops = {
.of_xlate = hisi_reset_of_xlate,
.request = hisi_reset_request,
- .rfree = hisi_reset_free,
+ .free = hisi_reset_free,
.rst_assert = hisi_reset_assert,
.rst_deassert = hisi_reset_deassert,
};
diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c
index f9a432a7a2..213d6c87be 100644
--- a/drivers/reset/reset-hsdk.c
+++ b/drivers/reset/reset-hsdk.c
@@ -81,7 +81,7 @@ static int hsdk_reset_noop(struct reset_ctl *rst_ctl)
static const struct reset_ops hsdk_reset_ops = {
.request= hsdk_reset_noop,
- .rfree = hsdk_reset_noop,
+ .free = hsdk_reset_noop,
.rst_assert = hsdk_reset_noop,
.rst_deassert = hsdk_reset_reset,
};
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index a61855e9ed..59d7088c9f 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -273,7 +273,7 @@ static int imx7_reset_request(struct reset_ctl *rst)
static const struct reset_ops imx7_reset_reset_ops = {
.request = imx7_reset_request,
- .rfree = imx7_reset_free,
+ .free = imx7_reset_free,
.rst_assert = imx7_reset_assert,
.rst_deassert = imx7_reset_deassert,
};
diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c
index 6d17f52ac7..0680abbe28 100644
--- a/drivers/reset/reset-mediatek.c
+++ b/drivers/reset/reset-mediatek.c
@@ -57,7 +57,7 @@ static int mediatek_reset_deassert(struct reset_ctl
*reset_ctl)
struct reset_ops mediatek_reset_ops = {
.request = mediatek_reset_request,
- .rfree = mediatek_reset_free,
+ .free = mediatek_reset_free,
.rst_assert = mediatek_reset_assert,
.rst_deassert = mediatek_reset_deassert,
};
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 70f96355b3..180780061e 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -63,7 +63,7 @@ static int meson_reset_deassert(struct reset_ctl *reset_ctl)
struct reset_ops meson_reset_ops = {
.request = meson_reset_request,
- .rfree = meson_reset_free,
+ .free = meson_reset_free,
.rst_assert = meson_reset_assert,
.rst_deassert = meson_reset_deassert,
};
diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c
index 677de0a6f9..5df95f1324 100644
--- a/drivers/reset/reset-mtmips.c
+++ b/drivers/reset/reset-mtmips.c
@@ -46,7 +46,7 @@ static int mtmips_reset_deassert(struct reset_ctl *reset_ctl)
static const struct reset_ops mtmips_reset_ops = {
.request= mtmips_reset_request,
- .rfree = mtmips_reset_free,
+ .free = mtmips_reset_free,
.rst_assert = mtmips_reset_assert,
.rst_deassert = mtmips_reset_deassert,
};
diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
index 100afc8103..a4dc103951 100644
--- a/drivers/reset/reset-rockchip.c
+++ b/drivers/reset/reset-rockchip.c
@@ -77,7 +77,7 @@ static int rockchip_reset_deassert(struct reset_ctl
*reset_ctl)
struct reset_ops rockchip_reset_ops = {
.request = rockchip_reset_request,
- .rfree = rockchip_reset_free,
+ .free
Re: [PATCH v2 06/21] configs: socfpga: Enable FIT image loading with ATF support
Am 20.02.2020 um 17:45 schrieb Marek Vasut: > On 2/20/20 3:15 AM, Ang, Chee Hong wrote: >>> On 2/19/20 1:25 PM, chee.hong@intel.com wrote: From: Chee Hong Ang SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new boot flow with ATF support is as follow: SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux) Signed-off-by: Chee Hong Ang --- configs/socfpga_agilex_defconfig| 8 +++- configs/socfpga_stratix10_defconfig | 8 +++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 693a774..0065ff0 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_TEXT_BASE=0x20 >>> >>> Why did the text base change ? >> This defconfig support ATF. >> ATF will occupy from this address range (0x1000) >> U-Boot now starts at 0x20. > > Then please document it in the commit message. Or even better, could we have 2 defconfigs, one for ATF, one for non-ATF? That way, we get build coverage that this still works. Regards, Simon > CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 @@ -10,10 +10,16 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its" CONFIG_BOOTDELAY=5 +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y >>> >>> Is legacy image support really needed ? >> Let me check. Will get rid of this if it's not needed. Thanks. > > Thanks >
Re: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)
Ang, Chee Hong schrieb am Sa., 22. Feb. 2020,
06:30:
> > From: Chee Hong Ang
> >
> > Allow clock manager driver to access the System Manager's Boot Scratch
> > Register 0 in non-secure mode (EL2) on SoC 64bits platform.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> > arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
> > 2 files changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
> b/arch/arm/mach-
> > socfpga/clock_manager_agilex.c
> > index 4ee2b7b..e5a0998 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
> >
> > u32 cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(socfpga_get_sysmgr_addr() +
> > - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > }
> >
> > void cm_print_clock_quick_summary(void)
> > diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-
> > socfpga/clock_manager_s10.c
> > index 05e4212..02578cc 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> > @@ -9,6 +9,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >
> > unsigned int cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(socfpga_get_sysmgr_addr() +
> > - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > }
> >
> > unsigned int cm_get_spi_controller_clk_hz(void)
> > --
> > 2.7.4
> SPL reads the clock info from handoff table (OCRAM) and write
> the clock info into the System Manager's boot scratch register.
> U-Boot proper will read from the System Manager's boot scratch
> register to get the clock info in case the handoff table (OCRAM)
> is no longer available.
> After some investigations, the handoff table in OCRAM should be preserved
> for warm boot. In other words, this handoff table should be left untouched.
> SPL and U-Boot should directly read the clock info from handoff table in
> OCRAM.
> Therefore, U-Boot proper no longer need to read the clock info from
> System Manager's boot scratch register (secure zone) from non-secure world
> (EL2).
>
I don't think that's a good idea: for security reasons, SPL memory should
not be accessible from EL2 if it is required/used for the next reboot.
Regards,
Simon
Re: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)
Ang, Chee Hong schrieb am Mo., 24. Feb. 2020,
10:12:
>
>
>
>
> *From:* Ang, Chee Hong
> *Sent:* Saturday, February 22, 2020 6:00 PM
> *To:* Simon Goldschmidt
> *Cc:* U-Boot Mailing List ; Marek Vasut <
> ma...@denx.de>; See, Chin Liang ; Tan, Ley Foon
> ; Westergreen, Dalon ;
> Gong, Richard
> *Subject:* RE: [PATCH v2 11/21] arm: socfpga: Secure register access for
> clock manager (SoC 64bits)
>
>
>
> Ang, Chee Hong schrieb am Sa., 22. Feb. 2020,
> 06:30:
>
> > From: Chee Hong Ang
> >
> > Allow clock manager driver to access the System Manager's Boot Scratch
> > Register 0 in non-secure mode (EL2) on SoC 64bits platform.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> > arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
> > 2 files changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
> b/arch/arm/mach-
> > socfpga/clock_manager_agilex.c
> > index 4ee2b7b..e5a0998 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
> >
> > u32 cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(socfpga_get_sysmgr_addr() +
> > - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > }
> >
> > void cm_print_clock_quick_summary(void)
> > diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-
> > socfpga/clock_manager_s10.c
> > index 05e4212..02578cc 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> > @@ -9,6 +9,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >
> > unsigned int cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(socfpga_get_sysmgr_addr() +
> > - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > }
> >
> > unsigned int cm_get_spi_controller_clk_hz(void)
> > --
> > 2.7.4
> >SPL reads the clock info from handoff table (OCRAM) and write
> >the clock info into the System Manager's boot scratch register.
> >U-Boot proper will read from the System Manager's boot scratch
> >register to get the clock info in case the handoff table (OCRAM)
> >is no longer available.
> >After some investigations, the handoff table in OCRAM should be preserved
> >for warm boot. In other words, this handoff table should be left
> untouched.
> >SPL and U-Boot should directly read the clock info from handoff table in
> OCRAM.
> >Therefore, U-Boot proper no longer need to read the clock info from
> >System Manager's boot scratch register (secure zone) from non-secure
> world (EL2).
>
>
>
> >I don't think that's a good idea: for security reasons, SPL memory should
> not be accessible from EL2 if it is required/used for the next reboot.
>
> >
>
> >Regards,
>
> >Simon
>
> Right. I think I will have to go for proper high-level API in ATF for EL2
> to query the clock frequency:
>
> INTEL_SIP_SMC_CLK_GET_QSPI
>
>
>
> I found out System Manager is read only in EL2 and read/write in EL3.
>
> Will drop this patch.
>
> No change required since it only read back from System Manager’s registers.
>
So reading these registers is allowed in EL2? I would have expected all
access is blocked? Is this specified somewhere, or will it be?
Regards,
Simon
>
Re: [PATCH] spi: cadence-qspi: Move ref clock calculation to probe
Vignesh Raghavendra schrieb am Mi., 26. Feb. 2020, 08:29:
> +Simon who converted driver to use clk_get* APIs
>
> On 24/02/20 12:40 pm, Pratyush Yadav wrote:
> > "assigned-clock-parents" and "assigned-clock-rates" DT properties take
> > effect only after ofdata_to_platdata() when clk_set_defaults() is called
> > in device_probe(). Therefore clk get rate() would return a wrong value
> > in ofdata_to_platdata() when compared with probe. Hence it needs to be
> > moved to probe.
> >
> > Tested on u-boot-ti/next.
> >
>
> Acked-by: Vignesh Raghavendra
>
Fine by me. I actually moved it there after someone requested me to :-) I
first had it in the set_rate function...
Acked-by: Simon Goldschmidt
>
> Regards
> Vignesh
>
> > Signed-off-by: Pratyush Yadav
> > ---
> > drivers/spi/cadence_qspi.c | 33 +
> > 1 file changed, 17 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> > index 83b114ffe7..994a5948f1 100644
> > --- a/drivers/spi/cadence_qspi.c
> > +++ b/drivers/spi/cadence_qspi.c
> > @@ -166,11 +166,28 @@ static int cadence_spi_probe(struct udevice *bus)
> > {
> > struct cadence_spi_platdata *plat = bus->platdata;
> > struct cadence_spi_priv *priv = dev_get_priv(bus);
> > + struct clk clk;
> > int ret;
> >
> > priv->regbase = plat->regbase;
> > priv->ahbbase = plat->ahbbase;
> >
> > + if (plat->ref_clk_hz == 0) {
> > + ret = clk_get_by_index(bus, 0, &clk);
> > + if (ret) {
> > +#ifdef CONFIG_CQSPI_REF_CLK
> > + plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
> > +#else
> > + return ret;
> > +#endif
> > + } else {
> > + plat->ref_clk_hz = clk_get_rate(&clk);
> > + clk_free(&clk);
> > + if (IS_ERR_VALUE(plat->ref_clk_hz))
> > + return plat->ref_clk_hz;
> > + }
> > + }
> > +
> > ret = reset_get_bulk(bus, &priv->resets);
> > if (ret)
> > dev_warn(bus, "Can't get reset: %d\n", ret);
> > @@ -268,8 +285,6 @@ static int cadence_spi_ofdata_to_platdata(struct
> udevice *bus)
> > {
> > struct cadence_spi_platdata *plat = bus->platdata;
> > ofnode subnode;
> > - struct clk clk;
> > - int ret;
> >
> > plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
> > plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
> > @@ -305,20 +320,6 @@ static int cadence_spi_ofdata_to_platdata(struct
> udevice *bus)
> > plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns",
> 20);
> > plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns",
> 20);
> >
> > - ret = clk_get_by_index(bus, 0, &clk);
> > - if (ret) {
> > -#ifdef CONFIG_CQSPI_REF_CLK
> > - plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
> > -#else
> > - return ret;
> > -#endif
> > - } else {
> > - plat->ref_clk_hz = clk_get_rate(&clk);
> > - clk_free(&clk);
> > - if (IS_ERR_VALUE(plat->ref_clk_hz))
> > - return plat->ref_clk_hz;
> > - }
> > -
> > debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
> > __func__, plat->regbase, plat->ahbbase, plat->max_hz,
> > plat->page_size);
> >
>
>
>
Re: [PATCH v2 10/21] arm: socfpga: Add secure register access helper functions for SoC 64bits
Ang, Chee Hong schrieb am Fr., 28. Feb. 2020, 03:53: > > > On 2/24/20 3:21 AM, Ang, Chee Hong wrote: > > > [...] > > > > > > > Currently, we have like 20+ secure registers allowed access by > > > > drivers running in non-secure mode (U-Boot proper / Linux). > > > > I don't think we want to define and maintain those high level > > > > interfaces for each of those secure register accesses in ATF and > U-Boot. > > > > > > See above. > > > >>> OK. Then these secure access register should be set up in SPL > (EL3). > > > >>> U-Boot drivers shouldn't access them at all because the driver may > > > >>> be running in SPL(EL3) and in U-Boot proper (EL2) too. > > > >>> I can take a look at those drivers accessing secure registers and > > > >>> try to move/decouple those secure access from U-Boot drivers to > > > >>> SPL > > > >>> (EL3) then we no longer need those secure register access > functions. > > > >> > > > >> I think that would be great, no ? > > > > Since the SDMMC/DWMAC drivers read the device tree to configure the > > > > behaviour of the hardware via the secure registers. I think it > > > > should still be part of the driver instead of configuring the > > > > hardware in different places. I have proposed using ATF's high-level > > > > APIs to achieve this > > > when the driver is running in EL2. > > > > I have already proposed this in other email threads. > > > > Are you OK with this approach ? > > > > > > I think something more high level might be a good idea here. > > What do you mean by 'more high level' ? > > We handle this in SPL (EL3) ? > > > > Since you are the author of this 'drivers/net/dwmac_socfpga.c': > > https://gitlab.denx.de/u-boot/u- > > boot/blob/master/drivers/net/dwmac_socfpga.c#L101 > > https://gitlab.denx.de/u-boot/u- > > boot/blob/master/arch/arm/dts/socfpga_stratix10.dtsi#L98 > > > > Your driver selects the PHY interface (RGMII/RMII and etc) using the > following > > register (part of System Manager): > > https://www.intel.com/content/www/us/en/programmable/hps/stratix- > > 10/hps.html#topic/jng1505406892594.html > > > > I personally think this PHY interface select for EMACx shouldn't be part > of > > System Manager. > > I don't see the security benefits here by making this PHY interface > select as > > 'secure zone' register. > > > > Same applies to DW MMC driver as well: > > https://gitlab.denx.de/u-boot/u- > > boot/blob/master/drivers/mmc/socfpga_dw_mmc.c#L60 > > > > It sets the following register in System Manager (secure zone) to > configure the > > SDMMC clocks: > > https://www.intel.com/content/www/us/en/programmable/hps/stratix- > > 10/hps.html#topic/gil1505406886282.html > > > > Don't you think these things should be part of driver itself as what we > are doing > > now instead of removing these from drivers and place them in SPL (EL3)? > > These 2 drivers that access the system manager: > drivers/mmc/socfpga_dw_mmc.c > - MMC driver access System Manager's 'SDMMC' register to set clock phase > > https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/topic/gil1505406886282.html > > drivers/net/dwmac_socfpga.c > - MAC driver access System Manager's 'EMACx' registers to set MAC's PHY > interface: > > https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html#topic/jng1505406892594.html > > Gen5/Arria10/Stratix10 & Agilex all using these drivers. > They do not cause any issue in Gen5/Arria10 because there is no 'secure > zone' in System Manager. > For Stratix10 & Agilex, it has issue with U-Boot proper running in EL2. > > I don't think is good idea to separate those System Manager access from > these 2 drivers and move them to SPL as they are shared by all SOCFPGA > platforms. > > I think the proper way to resolve this is we add a new System Manager > driver under 'drivers/misc'. > The device type should be 'UCLASS_MISC'. I have a pending patchset that adds such a sysmgr driver at least for gen5. I haven't published it yet because the whole series as one makes gen5 SRAM overlow, but maybe that part can be split out... Regards, Simon Then we make changes to those drivers (SDMMC/MAC) to access the System > Manager through the System Manager driver by using 'misc_read(dev...)' & > 'misc_write(dev...)' > The System Manager driver should decide whether to access those 'secure > zone' registers directly in EL3 or making SMC call to ATF to access the > System Manager if it's running in EL2. > > Linux has similar MAC driver running in EL1 (non-secure) accessing System > Manager: > > https://elixir.bootlin.com/linux/v5.5/source/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c#L302 > > Linux MAC driver access System Manager via this 'altr,system_manager' > driver: > > https://elixir.bootlin.com/linux/v5.5/source/drivers/mfd/altera-sysmgr.c#L44 > System Manager driver will make SMC/PSCI call to ATF to access the System > Manager's registers. >
Re: DE1-SoC Board Config
Am 02.03.2020 um 01:39 schrieb Jack Frye:
> I am trying to build uboot-socfpga for Terasic DE1-SoC board (Cyclone V),
> booting from SDMMC. I am unable to get u-boot to program the FPGA.
First question: which version of U-Boot are you using? Upstream sources
or Altera sources?
> I am following this guide from RocketBoards.
> https://rocketboards.org/foswiki/Documentation/BuildingBootloader
> with a few addenda. I have successfully built the u-boot-with_spl.sfp file
> using the configuration socfpga_cyclone5_defconfig.
>
> I added
> #define CONFIG_BOOTCOMMAND "run callscript"
> to socfpga_cyclone5_socsdk.h
>
> I also added
> #define CONFIG_EXTRA_ENV_SETTINGS \
> "scriptfile=u-boot.scr" "\0" \
> "fpgadata=0x200" "\0" \
> "callscript=fatload mmc 0:1 $fpgadata $scriptfile;" \
> "source $fpgadata" "\0"
> to socfpga_common.h
>
> My u-boot script contains the commands
> echo --- Programming FPGA ---
> # load rbf from FAT partition into memory
> fatload mmc 0:1 ${fpgadata} output_file.rbf;
> # program FPGA
> fpga load 0 ${fpgadata} ${filesize};
> # enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges
> bridge enable;
>
> When I reach this part of the script, I am seeing
> 7007204 bytes read in 366 ms (18.3 MiB/s)
> Command ‘load’ failed: Error -6
That "-6" is not an error code. The code here invalidly returns negative
numbers instead of error codes.
Anyway, the function returning this is fpgamgr_program_poll_initphase()
and it says that FPGA does not enter init phase or user mode after
programming.
Have you tried to execute the steps manually? If so, how long does the
"fpga load" command execute?
Have you tried listing memory contents (or using crc32) after loading
the rbf to see if it is correct?
>
> I have scoured the internet for answers and posted on RocketBoards forums,
> but no one seems to be able to diagnose the problem. Those who have assisted
> me have commented they were able to perform this operation using older
> versions of the tools. The big difference I understand is that now the SOCEDS
> builds the preloader into u-boot using the filter_qts script. I wonder if
> there may be some bug or compatibility issue here.
I'm not sure fpga programming depends on the handoff files...
Regards,
Simon
>
> I have also tried using socfpga_de1_soc_defconfig, but I do not see any
> console output when I boot.
>
Re: [PATCH v4 1/5] dm: clk: add stub when CONFIG_CLK is desactivated
Am 18.02.2020 um 09:34 schrieb Patrick Delaunay:
> Add stub for functions clk_...() when CONFIG_CLK is desactivated.
>
> This patch avoids compilation issues for driver using these API
> without protection (#if CONFIG_IS_ENABLED(CLK))
>
> For example, before this patch we have undefined reference to
> `clk_disable_bulk') for code:
> clk_disable_bulk(&priv->clks);
> clk_release_bulk(&priv->clks);
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v4:
> - Add stub for all functions using 'struct clk' or 'struct clk_bulk'
> after remarks on v3
>
> Changes in v3:
> - Add stub for clk_disable_bulk
>
> Changes in v2: None
>
> include/clk.h | 101 +++---
> 1 file changed, 88 insertions(+), 13 deletions(-)
>
> diff --git a/include/clk.h b/include/clk.h
> index 3336301815..1fb415ddc8 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -312,6 +312,7 @@ static inline int clk_release_bulk(struct clk_bulk *bulk)
> return clk_release_all(bulk->clks, bulk->count);
> }
>
> +#if CONFIG_IS_ENABLED(CLK)
> /**
> * clk_request - Request a clock by provider-specific ID.
> *
> @@ -433,19 +434,6 @@ int clk_disable_bulk(struct clk_bulk *bulk);
> */
> bool clk_is_match(const struct clk *p, const struct clk *q);
>
> -int soc_clk_dump(void);
> -
> -/**
> - * clk_valid() - check if clk is valid
> - *
> - * @clk: the clock to check
> - * @return true if valid, or false
> - */
> -static inline bool clk_valid(struct clk *clk)
> -{
> - return clk && !!clk->dev;
> -}
> -
> /**
> * clk_get_by_id() - Get the clock by its ID
> *
> @@ -465,6 +453,93 @@ int clk_get_by_id(ulong id, struct clk **clkp);
> * @return true on binded, or false on no
> */
> bool clk_dev_binded(struct clk *clk);
> +
> +#else /* CONFIG_IS_ENABLED(CLK) */
> +
> +static inline int clk_request(struct udevice *dev, struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_free(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline ulong clk_get_rate(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline struct clk *clk_get_parent(struct clk *clk)
> +{
> + return (struct clk *)-ENOSYS;
This should use ERR_PTR() to care for platforms defining
CONFIG_ERR_PTR_OFFSET.
> +}
> +
> +static inline long long clk_get_parent_rate(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline ulong clk_set_rate(struct clk *clk, ulong rate)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_enable(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_enable_bulk(struct clk_bulk *bulk)
> +{
> + return bulk && bulk->count == 0 ? 0 : -ENOSYS;
For this test to work, someone would need to set bulk->count to 0. This
is normally done by clk_get_bulk(), but you defined it to only return an
error.
I guess it works for you because all clk_bulk objects you use are from
the heap (which is currently zeroed out in U-Boot) or if they are on the
stack, you have if/else code that doesn't bring you here. Still it seems
wrong.
Regards,
Simon
> +}
> +
> +static inline int clk_disable(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_disable_bulk(struct clk_bulk *bulk)
> +{
> + return bulk && bulk->count == 0 ? 0 : -ENOSYS;
> +}
> +
> +static inline bool clk_is_match(const struct clk *p, const struct clk *q)
> +{
> + return false;
> +}
> +
> +static inline int clk_get_by_id(ulong id, struct clk **clkp)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline bool clk_dev_binded(struct clk *clk)
> +{
> + return false;
> +}
> +#endif /* CONFIG_IS_ENABLED(CLK) */
> +
> +/**
> + * clk_valid() - check if clk is valid
> + *
> + * @clk: the clock to check
> + * @return true if valid, or false
> + */
> +static inline bool clk_valid(struct clk *clk)
> +{
> + return clk && !!clk->dev;
> +}
> +
> +int soc_clk_dump(void);
> +
> #endif
>
> #define clk_prepare_enable(clk) clk_enable(clk)
>
Re: [PATCH v4 2/5] usb: host: dwc2: add phy support
Am 18.02.2020 um 09:35 schrieb Patrick Delaunay:
> Use generic phy to initialize the PHY associated to the
> DWC2 device and available in the device tree.
>
> This patch don't added dependency because when CONFIG_PHY
> is not activated, the generic PHY function are stubbed.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - update dev_err
> - update commit message
> - change dev_err to dev_dbg for PHY function call
> - treat dwc2_shutdown_phy error
>
> drivers/usb/host/dwc2.c | 66 +
> 1 file changed, 66 insertions(+)
>
> diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> index e4efaf1e59..5e7ffaddd9 100644
> --- a/drivers/usb/host/dwc2.c
> +++ b/drivers/usb/host/dwc2.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -37,6 +38,7 @@ struct dwc2_priv {
> #ifdef CONFIG_DM_REGULATOR
> struct udevice *vbus_supply;
> #endif
> + struct phy phy;
> #else
> uint8_t *aligned_buffer;
> uint8_t *status_buffer;
> @@ -1322,13 +1324,71 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice
> *dev)
> return 0;
> }
>
> +static int dwc2_setup_phy(struct udevice *dev)
> +{
> + struct dwc2_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + ret = generic_phy_get_by_index(dev, 0, &priv->phy);
> + if (ret) {
> + if (ret != -ENOENT) {
Could you invert this logic and add a comment like "no PHY" or something?
> + dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
> + return ret;
> + }
> + return 0;
> + }
> +
> + ret = generic_phy_init(&priv->phy);
> + if (ret) {
> + dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
> + return ret;
> + }
> +
> + ret = generic_phy_power_on(&priv->phy);
> + if (ret) {
> + dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
> + generic_phy_exit(&priv->phy);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int dwc2_shutdown_phy(struct udevice *dev)
> +{
> + struct dwc2_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + if (!generic_phy_valid(&priv->phy))
A comment saying that this is for platforms without a phy driver would
be nice.
Other than that:
Reviewed-by: Simon Goldschmidt
> + return 0;
> +
> + ret = generic_phy_power_off(&priv->phy);
> + if (ret) {
> + dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
> + return ret;
> + }
> +
> + ret = generic_phy_exit(&priv->phy);
> + if (ret) {
> + dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int dwc2_usb_probe(struct udevice *dev)
> {
> struct dwc2_priv *priv = dev_get_priv(dev);
> struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
> + int ret;
>
> bus_priv->desc_before_addr = true;
>
> + ret = dwc2_setup_phy(dev);
> + if (ret)
> + return ret;
> +
> return dwc2_init_common(dev, priv);
> }
>
> @@ -1341,6 +1401,12 @@ static int dwc2_usb_remove(struct udevice *dev)
> if (ret)
> return ret;
>
> + ret = dwc2_shutdown_phy(dev);
> + if (ret) {
> + dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
> + return ret;
> + }
> +
> dwc2_uninit_common(priv->regs);
>
> reset_release_bulk(&priv->resets);
>
Re: [PATCH v4 3/5] usb: host: dwc2: add clk support
Am 18.02.2020 um 09:35 schrieb Patrick Delaunay:
> Add support for clock with driver model.
>
> This patch don't added dependency because when CONFIG_CLK
> is not activated the clk function are stubbed.
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Goldschmidt
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> drivers/usb/host/dwc2.c | 30 +-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> index 5e7ffaddd9..d56d0e61b5 100644
> --- a/drivers/usb/host/dwc2.c
> +++ b/drivers/usb/host/dwc2.c
> @@ -5,14 +5,15 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -39,6 +40,7 @@ struct dwc2_priv {
> struct udevice *vbus_supply;
> #endif
> struct phy phy;
> + struct clk_bulk clks;
> #else
> uint8_t *aligned_buffer;
> uint8_t *status_buffer;
> @@ -1377,6 +1379,26 @@ static int dwc2_shutdown_phy(struct udevice *dev)
> return 0;
> }
>
> +static int dwc2_clk_init(struct udevice *dev)
> +{
> + struct dwc2_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + ret = clk_get_bulk(dev, &priv->clks);
> + if (ret == -ENOSYS || ret == -ENOENT)
> + return 0;
> + if (ret)
> + return ret;
> +
> + ret = clk_enable_bulk(&priv->clks);
> + if (ret) {
> + clk_release_bulk(&priv->clks);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int dwc2_usb_probe(struct udevice *dev)
> {
> struct dwc2_priv *priv = dev_get_priv(dev);
> @@ -1385,6 +1407,10 @@ static int dwc2_usb_probe(struct udevice *dev)
>
> bus_priv->desc_before_addr = true;
>
> + ret = dwc2_clk_init(dev);
> + if (ret)
> + return ret;
> +
> ret = dwc2_setup_phy(dev);
> if (ret)
> return ret;
> @@ -1410,6 +1436,8 @@ static int dwc2_usb_remove(struct udevice *dev)
> dwc2_uninit_common(priv->regs);
>
> reset_release_bulk(&priv->resets);
> + clk_disable_bulk(&priv->clks);
> + clk_release_bulk(&priv->clks);
>
> return 0;
> }
>
Re: [PATCH v4 0/5] usb: host: dwc2: use driver model for PHY and CLOCK
Am 19.02.2020 um 08:27 schrieb Simon Goldschmidt: > On Tue, Feb 18, 2020 at 6:53 PM Marek Vasut wrote: >> >> On 2/18/20 9:34 AM, Patrick Delaunay wrote: >>> >>> In this serie I update the DWC2 host driver to use the device tree >>> information and the associated PHY and CLOCK drivers when they are >>> availables. >>> >>> The V4 is rebased on latest master (v2020.04-rc2). >>> CI-Tavis build is OK: >>> https://travis-ci.org/patrickdelaunay/u-boot/builds/651479714 >>> >>> NB: CI-Travis build was OK for all target after V3: >>> https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 >>> As in V2, I cause the warnings for some boards: >>> drivers/usb/host/built-in.o: In function `dwc2_usb_remove': >>> drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' >>> >>> I test this serie on stm32mp157c-ev1 board, with PHY and CLK >>> support >>> >>> The U-CLASS are provided by: >>> - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c >>> - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c >>> - RESET by RCC reset driver = drivers/reset/stm32-reset.c >>> >>> And I activate the configuration >>> +CONFIG_USB_DWC2=y >> >> Simon, can you test this on SOCFPGA ? > > I can test if it probes, but I don't have anything running on that USB port > the socfpga_socrates board has. Would that be enought to test? Tested the whole series on socfpga_socrates by instantiating the driver. Shows the same behaviour as before (I still have no OTG cable to test attaching a storage device). Regards, Simon > > Regards, > Simon > >> >> [...]
[PATCH] net: phy: fix autoneg timeout
Recently, genphy_update_link() has been changed to use a 50ms polling
interval instead of the previous 1ms. However, the timeout to give up
waiting for a link remained unchanged, calculating the iterations.
As a result, PHY_ANEG_TIMEOUT now specifies "multiples of 50ms" instead
of just to be a number of milliseconds.
Fix this by dividing PHY_ANEG_TIMEOUT by 50 in this loop. This gets us
back to a 4 seconds timeout for the default value (instead of 200s).
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Signed-off-by: Simon Goldschmidt
---
This should be applied before the next release as it fixes a regression
of v2020.01!
drivers/net/phy/phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 80a7664e49..5cf9c165b6 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -244,7 +244,7 @@ int genphy_update_link(struct phy_device *phydev)
/*
* Timeout reached ?
*/
- if (i > PHY_ANEG_TIMEOUT) {
+ if (i > (PHY_ANEG_TIMEOUT / 50)) {
printf(" TIMEOUT !\n");
phydev->link = 0;
return -ETIMEDOUT;
--
2.20.1
Re: [PATCH 2/8] Revert "mtd: Rename free() to rfree()"
Am 19.02.2020 um 21:04 schrieb Fabio Estevam: > On Wed, Feb 19, 2020 at 4:40 PM Simon Goldschmidt > wrote: >> >> This reverts commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0. > > You missed to explain the reason for the revert. Yes, I'll fix that in v2. Regards, Simon
Re: [PATCH 1/8] malloc: implement USE_DL_PREFIX via inline functions
Am 20.02.2020 um 04:05 schrieb Simon Glass:
> On Wed, 19 Feb 2020 at 12:39, Simon Goldschmidt
> wrote:
>>
>> Commit cfda60f99ae2 ("sandbox: Use a prefix for all allocation functions")
>> introduced preprocessor macros for malloc/free etc.
>>
>> This is bad practice as it essentially makes 'free' a reserved keyword and
>> resulted in quite a bit of renaming to avoid that reserved keyword.
>>
>> A better solution is to define the allocation functions as 'static inline'.
>>
>> As a side effect, exports.h must not export malloc/free for sandbox.
>>
>> Signed-off-by: Simon Goldschmidt
>> ---
>>
>> A side-effect is that exports.h may not declare malloc/free. I'm not really
>> sure if this is correct, but for sandbox, it should probably be ok?
>
> Is it possible to fix this? E.g. don't use inline for these two
> functions on sandbox?
Not using inline for sandbox for these two is *not* an option as these
two are exactly the ones offending globally known names.
I guess we have to know what we want here: what is exports.h meant for?
To me it looks like it is meant for "U-Boot API" applications to link
against. If so, why is it included in U-Boot sources (in over 20 files)?
I guess one solution would be to move (or copy) the DL prefix handling
into exports.h and _exports.h so that applications linking with
exports.h implicily call dlmalloc/dlfree, not malloc/free (which would
be the OS versions for sandbox).
I'll try to prepare v2 in that direction, but I'm still not unsure since
exports.h is included in internal U-Boot code.
Regards,
Simon
>
>>
>> include/_exports.h | 2 ++
>> include/exports.h | 2 ++
>> include/malloc.h | 44 +---
>> 3 files changed, 33 insertions(+), 15 deletions(-)
>
> Reviewed-by: Simon Glass
>
Re: [PATCH] net: phy: fix autoneg timeout
On Thu, Mar 5, 2020 at 5:40 AM Stefan Roese wrote:
>
> Hi Simon,
>
> On 04.03.20 21:12, Simon Goldschmidt wrote:
> > Recently, genphy_update_link() has been changed to use a 50ms polling
> > interval instead of the previous 1ms. However, the timeout to give up
> > waiting for a link remained unchanged, calculating the iterations.
> >
> > As a result, PHY_ANEG_TIMEOUT now specifies "multiples of 50ms" instead
> > of just to be a number of milliseconds.
> >
> > Fix this by dividing PHY_ANEG_TIMEOUT by 50 in this loop. This gets us
> > back to a 4 seconds timeout for the default value (instead of 200s).
> >
> > Fixes: net: phy: Increase link up delay in genphy_update_link()
> > ("27c3f70f3b50")
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > This should be applied before the next release as it fixes a regression
> > of v2020.01!
> >
> > drivers/net/phy/phy.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> > index 80a7664e49..5cf9c165b6 100644
> > --- a/drivers/net/phy/phy.c
> > +++ b/drivers/net/phy/phy.c
> > @@ -244,7 +244,7 @@ int genphy_update_link(struct phy_device *phydev)
> > /*
> >* Timeout reached ?
> >*/
> > - if (i > PHY_ANEG_TIMEOUT) {
> > + if (i > (PHY_ANEG_TIMEOUT / 50)) {
> > printf(" TIMEOUT !\n");
> > phydev->link = 0;
> > return -ETIMEDOUT;
> >
>
> A similar fix from Andre for this is queued for this for quite some
> time now:
>
> https://patchwork.ozlabs.org/patch/1217524/
Right. I thought I remembered a patch but hadn't found it...
I'll drop this one then.
Regards,
Simon
>
> Joe or Tom, could you please take this one?
>
> Thanks,
> Stefan
Re: [PATCH] net: phy: Fix overlong PHY timeout
On Fri, Feb 21, 2020 at 5:33 PM Matthias Brugger wrote:
>
> Hi Joe,
>
> On 30/01/2020 12:00, Matthias Brugger wrote:
> >
> >
> > On 03/01/2020 23:08, Andre Przywara wrote:
> >> Commit 27c3f70f3b50 ("net: phy: Increase link up delay in
> >> genphy_update_link()") increased the per-iteration waiting time from
> >> 1ms to 50ms, without adjusting the timeout counter. This lead to the
> >> timeout increasing from the typical 4 seconds to over three minutes.
> >>
> >> Adjust the timeout counter evaluation by that factor of 50 to bring the
> >> timeout back to the intended value.
> >>
> >> Signed-off-by: Andre Przywara
A "Fixes:" tag would have been nice...
Anyway:
Tested-by: Simon Goldschmidt
> >
> > I tested this on RPi4 with the genet patches on top. Now the timeout is
> > reasonable :)
> >
> > Tested-by: Matthias Brugger
> >
>
> Friedly reminder, are you planning to take this fix for v2020.04?
Yes, please! This timeout is really annoying right now!
Regards,
Simon
>
> Regards,
> Matthias
>
> >> ---
> >> drivers/net/phy/phy.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> >> index 80a7664e49..5cf9c165b6 100644
> >> --- a/drivers/net/phy/phy.c
> >> +++ b/drivers/net/phy/phy.c
> >> @@ -244,7 +244,7 @@ int genphy_update_link(struct phy_device *phydev)
> >> /*
> >> * Timeout reached ?
> >> */
> >> -if (i > PHY_ANEG_TIMEOUT) {
> >> +if (i > (PHY_ANEG_TIMEOUT / 50)) {
> >> printf(" TIMEOUT !\n");
> >> phydev->link = 0;
> >> return -ETIMEDOUT;
> >>
>
Re: [PATCH v5 1/5] dm: clk: add stub when CONFIG_CLK is deactivated
On Fri, Mar 6, 2020 at 11:01 AM Patrick Delaunay
wrote:
>
> Add stub for functions clk_...() when CONFIG_CLK is deactivated.
>
> This patch avoids compilation issues for driver using these API
> without protection (#if CONFIG_IS_ENABLED(CLK))
>
> For example, before this patch we have undefined reference to
> `clk_disable_bulk') for code:
> clk_disable_bulk(&priv->clks);
> clk_release_bulk(&priv->clks);
>
> The bulk stub set and test bulk->count to avoid error for the sequence:
>
> clk_get_bulk(dev, &priv->bulk);
>
> if (clk_enable(&priv>bulk))
> return -EIO;
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v5:
> - use ERR_PTR in clk_get_parent()
> - force bulk->count = 0 in clk_get_bulk to avoid issue
> for next call of clk_enable_bulk / clk_enable_bulk
I wonder if this is correct. I think it only produces additional code. If you
always set bulk->count to 0, the enable code will never fail.
However, the enable function should never be executed as enable returns an
error. I can imagine the *disable* function could be called, but the return
value of this function is currently only handled in clk_sandbox_test.c...
Wouldn't it work to just remove all checks for bulk->count and let *all*
redefined functions return a constant (success or failure)? That would help
to keep the code small.
Looking at linux, clock disable functions have *no* return value that needs
to be checked, clock enable functions return success when compiled without
clock support.
Regards,
Simon
> - update commit message
>
> Changes in v4:
> - Add stub for all functions using 'struct clk' or 'struct clk_bulk'
> after remarks on v3
>
> Changes in v3:
> - Add stub for clk_disable_bulk
>
> Changes in v2: None
>
> include/clk.h | 104 +++---
> 1 file changed, 91 insertions(+), 13 deletions(-)
>
> diff --git a/include/clk.h b/include/clk.h
> index 3336301815..ca8f1cfec7 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -9,6 +9,7 @@
> #define _CLK_H_
>
> #include
> +#include
> #include
> #include
>
> @@ -249,6 +250,8 @@ static inline int clk_get_by_index(struct udevice *dev,
> int index,
>
> static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
> {
> + if (bulk)
> + bulk->count = 0;
> return -ENOSYS;
> }
>
> @@ -312,6 +315,7 @@ static inline int clk_release_bulk(struct clk_bulk *bulk)
> return clk_release_all(bulk->clks, bulk->count);
> }
>
> +#if CONFIG_IS_ENABLED(CLK)
> /**
> * clk_request - Request a clock by provider-specific ID.
> *
> @@ -433,19 +437,6 @@ int clk_disable_bulk(struct clk_bulk *bulk);
> */
> bool clk_is_match(const struct clk *p, const struct clk *q);
>
> -int soc_clk_dump(void);
> -
> -/**
> - * clk_valid() - check if clk is valid
> - *
> - * @clk: the clock to check
> - * @return true if valid, or false
> - */
> -static inline bool clk_valid(struct clk *clk)
> -{
> - return clk && !!clk->dev;
> -}
> -
> /**
> * clk_get_by_id() - Get the clock by its ID
> *
> @@ -465,6 +456,93 @@ int clk_get_by_id(ulong id, struct clk **clkp);
> * @return true on binded, or false on no
> */
> bool clk_dev_binded(struct clk *clk);
> +
> +#else /* CONFIG_IS_ENABLED(CLK) */
> +
> +static inline int clk_request(struct udevice *dev, struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_free(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline ulong clk_get_rate(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline struct clk *clk_get_parent(struct clk *clk)
> +{
> + return ERR_PTR(-ENOSYS);
> +}
> +
> +static inline long long clk_get_parent_rate(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline ulong clk_set_rate(struct clk *clk, ulong rate)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_enable(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_enable_bulk(struct clk_bulk *bulk)
> +{
> + return bulk && bulk->count == 0 ? 0 : -ENOSYS;
> +}
> +
> +static inline int clk_disable(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_disable_bulk(struct clk_bulk *bulk)
> +{
> + return bulk && bulk->count == 0 ? 0 : -ENOSYS;
> +}
> +
> +static inline bool clk_is_match(const struct clk *p, const struct clk *q)
> +{
> + return false;
> +}
> +
> +static inline int clk_get_by_id(ulong id, struct clk **clkp)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline bool clk_dev_binded(struct clk *clk)
> +{
> + return false;
> +}
> +#endif /* CONFIG_IS_ENABLED(CLK) */
> +
> +/**
> + * clk_valid() - check if clk is valid
> + *
> + * @clk: the clock to check
> + * @return true if valid, or false
> + */
> +static inline bool clk_valid(struct clk *clk)
> +{
Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut wrote: > > On 3/9/20 9:50 AM, Ley Foon Tan wrote: > > On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen > > wrote: > >> > >> I am reading through this thread, and want to point out that it is not > >> that the > >> FPGA bridge need be actively used in the fpga, but > >> rather that this port be configured in the FPGA configuration. This is an > >> important distinction, ecery FPGA design that > >> instantiates the HPS does configure the F2S Bridge. it drives select pins, > >> control pins, data pins, etc, on the interface to known values, > >> and so the apply can always be done as all SoC FPGA designs have the soc > >> instantiated. If someone boots the arm, and uses an > >> FPGA design without having the soc instantiated, it may then cause issues, > >> but i > >> would argue that is not a supported use > >> in the first place. > >> > >> --dalon > >> > > > > I can reproduce the issue if without setting applycfg bit. Access to > > F2sdram interface will cause system hang. > > > > From the Cyclone 5 Soc datasheet: > > applycfg - Write with this bit set to apply all the settings loaded in > > SDR registers to the memory interface. This bit is write-only and > > always returns 0 if read. > > > > Software should set applycfg bit if change any register under SDR > > register range. SW is allowed to set this bit multiple times, the only > > condition is SDRAM need to be idle. > > My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > > change the sequence to below: > > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > > socfpga_sdram_apply_static_cfg(); > > > > Marek and Simon, are you okay with this? If yes, I will submit patch for > > this. > > The problem was that this was causing weird sporadic hangs on Gen5, > which is why it was removed. So until there is an explanation for those > hangs, I'm not really OK with this. These sporadic hangs you saw were on devices without an FPGA image directly accessing the SDRAM ports, right? > > Maybe the application of static config should happen in SPL, before the > DRAM is running, or something like that ? Thinking this further, limiting it to applying in SPL is not a good idea since that prevents us from implementing different FPGA images/configs by loading a config later in the boot (i.e. in U-Boot from a FIT-image). Would it work to make setting this optional, i.e. only write the bit if an FPGA config actually uses these ports? Then it couldn't lead to problems on other hardware... Regards, Simon
Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
On Mon, Mar 9, 2020 at 3:15 PM Marek Vasut wrote: > > On 3/9/20 3:10 PM, Simon Goldschmidt wrote: > > On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut wrote: > >> > >> On 3/9/20 9:50 AM, Ley Foon Tan wrote: > >>> On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen > >>> wrote: > >>>> > >>>> I am reading through this thread, and want to point out that it is not > >>>> that the > >>>> FPGA bridge need be actively used in the fpga, but > >>>> rather that this port be configured in the FPGA configuration. This is > >>>> an > >>>> important distinction, ecery FPGA design that > >>>> instantiates the HPS does configure the F2S Bridge. it drives select > >>>> pins, > >>>> control pins, data pins, etc, on the interface to known values, > >>>> and so the apply can always be done as all SoC FPGA designs have the soc > >>>> instantiated. If someone boots the arm, and uses an > >>>> FPGA design without having the soc instantiated, it may then cause > >>>> issues, but i > >>>> would argue that is not a supported use > >>>> in the first place. > >>>> > >>>> --dalon > >>>> > >>> > >>> I can reproduce the issue if without setting applycfg bit. Access to > >>> F2sdram interface will cause system hang. > >>> > >>> From the Cyclone 5 Soc datasheet: > >>> applycfg - Write with this bit set to apply all the settings loaded in > >>> SDR registers to the memory interface. This bit is write-only and > >>> always returns 0 if read. > >>> > >>> Software should set applycfg bit if change any register under SDR > >>> register range. SW is allowed to set this bit multiple times, the only > >>> condition is SDRAM need to be idle. > >>> My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > >>> change the sequence to below: > >>> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > >>> socfpga_sdram_apply_static_cfg(); > >>> > >>> Marek and Simon, are you okay with this? If yes, I will submit patch for > >>> this. > >> > >> The problem was that this was causing weird sporadic hangs on Gen5, > >> which is why it was removed. So until there is an explanation for those > >> hangs, I'm not really OK with this. > > > > These sporadic hangs you saw were on devices without an FPGA image directly > > accessing the SDRAM ports, right? > > Yes > > >> Maybe the application of static config should happen in SPL, before the > >> DRAM is running, or something like that ? > > > > Thinking this further, limiting it to applying in SPL is not a good idea > > since > > that prevents us from implementing different FPGA images/configs by loading > > a > > config later in the boot (i.e. in U-Boot from a FIT-image). > > Well, but later we have SDRAM running and we cannot make it go idle, can we? > > > Would it work to make setting this optional, i.e. only write the bit if an > > FPGA > > config actually uses these ports? Then it couldn't lead to problems on other > > hardware... > > Can you make SDRAM bus really idle ? >From the CPU side, that should work, no? Of course you have to make sure no other peripheraly (including FPGA!) are using the RAM. And if this would be an explicit command, people needing this could experiment with it - and hopefully give better hints as to what's going wrong if we *do* see problems again. Regards, Simon
Re: [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager driver
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> From: Chee Hong Ang
>
> This driver (misc uclass) handle the read/write access to
> System Manager. For 64 bits platforms, processor needs to be
> in secure mode to has write access to most of the System Manager's
> registers (except boot scratch registers). When the processor is
> running in EL2 (non-secure), this driver will invoke the SMC call
> to ATF to perform write access to the System Manager's registers.
> All other drivers that require access to System Manager should
> go through this driver.
>
> Signed-off-by: Chee Hong Ang
> ---
> drivers/misc/Makefile| 1 +
> drivers/misc/altera_sysmgr.c | 115
> +++
> 2 files changed, 116 insertions(+)
> create mode 100644 drivers/misc/altera_sysmgr.c
>
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index 2b843de..9fa2411 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -29,6 +29,7 @@ endif
> endif
> obj-$(CONFIG_ALI152X) += ali512x.o
> obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
> +obj-$(CONFIG_ARCH_SOCFPGA) += altera_sysmgr.o
> obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
> obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
> obj-$(CONFIG_DS4510) += ds4510.o
> diff --git a/drivers/misc/altera_sysmgr.c b/drivers/misc/altera_sysmgr.c
> new file mode 100644
> index 000..b36ecae
> --- /dev/null
> +++ b/drivers/misc/altera_sysmgr.c
I think this file should have something in the name specifying it is for
s10/agilex. I will post a misc/sysmgr for gen5 that needs a specific
name, too
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Intel Corporation
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define IS_OUT_OF_SYSMGR(addr, range) ((addr) > (range))
> +
> +struct altera_sysmgr_priv {
> + fdt_addr_t base_addr;
> + fdt_addr_t base_size;
> +};
> +
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> +static int secure_write32(u32 val, fdt_addr_t addr)
> +{
> + int ret;
> + u64 args[2];
> +
> + args[0] = (u64)addr;
> + args[1] = val;
> + ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
Hmm, so you're just using misc_ops to still issue generic writes. From
the discussion with Marek in the last version, I would have thought you
wanted to create a higher level API instead of still tunnelling reads
and writes?
In my gen5 series to abstract the gen5 sysmgr, I have used 'ioctl' and
'call' from misc_ops to have an API.
Regards,
Simon
> + if (ret)
> + return -EIO;
> +
> + return 0;
> +}
> +#endif
> +
> +static int write32(u32 val, fdt_addr_t addr)
> +{
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> + return secure_write32(val, addr);
> +#else
> + writel(val, addr);
> +
> + return 0;
> +#endif
> +}
> +
> +static int altera_sysmgr_read(struct udevice *dev,
> + int offset, void *buf, int size)
> +{
> + struct altera_sysmgr_priv *priv = dev_get_priv(dev);
> + fdt_addr_t addr = priv->base_addr + offset;
> +
> + if (IS_OUT_OF_SYSMGR(addr, priv->base_addr + priv->base_size - size))
> + return -EINVAL;
> +
> + if (size != sizeof(u32))
> + return -EIO;
> +
> + *(u32 *)buf = readl(addr);
> +
> + return 0;
> +}
> +
> +static int altera_sysmgr_write(struct udevice *dev, int offset,
> + const void *buf, int size)
> +{
> + struct altera_sysmgr_priv *priv = dev_get_priv(dev);
> + fdt_addr_t addr = priv->base_addr + offset;
> +
> + if (IS_OUT_OF_SYSMGR(addr, priv->base_addr + priv->base_size - size))
> + return -EINVAL;
> +
> + if (size != sizeof(u32))
> + return -EIO;
> +
> + return write32(*(u32 *)buf, addr);
> +}
> +
> +static int altera_sysmgr_probe(struct udevice *dev)
> +{
> + struct altera_sysmgr_priv *priv = dev_get_priv(dev);
> + fdt_addr_t addr;
> + fdt_size_t size;
> +
> + addr = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &size);
> +
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + priv->base_addr = addr;
> + priv->base_size = size;
> +
> + return 0;
> +}
> +
> +static const struct misc_ops altera_sysmgr_ops = {
> + .read = altera_sysmgr_read,
> + .write = altera_sysmgr_write,
> +};
> +
> +static const struct udevice_id altera_sysmgr_ids[] = {
> + { .compatible = "altr,sys-mgr" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(altera_sysmgr) = {
> + .name = "altr,sys-mgr",
> + .id = UCLASS_MISC,
> + .of_match = altera_sysmgr_ids,
> + .priv_auto_alloc_size = sizeof(struct altera_sysmgr_priv),
> + .probe = altera_sysmgr_probe,
> + .ops= &altera_sysmgr_ops,
> +};
>
Re: [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager driver
Am 10.03.2020 um 17:42 schrieb Ang, Chee Hong:
>> -Original Message-
>> From: Simon Goldschmidt
>> Sent: Wednesday, March 11, 2020 12:17 AM
>> To: Ang, Chee Hong
>> Cc: u-boot@lists.denx.de; Marek Vasut ; See, Chin Liang
>> ; Tan, Ley Foon ;
>> Westergreen, Dalon ; Gong, Richard
>>
>> Subject: Re: [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager
>> driver
>>
>> Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
>>> From: Chee Hong Ang
>>>
>>> This driver (misc uclass) handle the read/write access to System
>>> Manager. For 64 bits platforms, processor needs to be in secure mode
>>> to has write access to most of the System Manager's registers (except
>>> boot scratch registers). When the processor is running in EL2
>>> (non-secure), this driver will invoke the SMC call to ATF to perform
>>> write access to the System Manager's registers.
>>> All other drivers that require access to System Manager should go
>>> through this driver.
>>>
>>> Signed-off-by: Chee Hong Ang
>>> ---
>>> drivers/misc/Makefile| 1 +
>>> drivers/misc/altera_sysmgr.c | 115
>>> +++
>>> 2 files changed, 116 insertions(+)
>>> create mode 100644 drivers/misc/altera_sysmgr.c
>>>
>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
>>> 2b843de..9fa2411 100644
>>> --- a/drivers/misc/Makefile
>>> +++ b/drivers/misc/Makefile
>>> @@ -29,6 +29,7 @@ endif
>>> endif
>>> obj-$(CONFIG_ALI152X) += ali512x.o
>>> obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
>>> +obj-$(CONFIG_ARCH_SOCFPGA) += altera_sysmgr.o
>>> obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
>>> obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
>>> obj-$(CONFIG_DS4510) += ds4510.o
>>> diff --git a/drivers/misc/altera_sysmgr.c
>>> b/drivers/misc/altera_sysmgr.c new file mode 100644 index
>>> 000..b36ecae
>>> --- /dev/null
>>> +++ b/drivers/misc/altera_sysmgr.c
>>
>> I think this file should have something in the name specifying it is for
>> s10/agilex.
>> I will post a misc/sysmgr for gen5 that needs a specific name, too
> Gen5/A10/S10/Agilex are using same DW MMC/MAC drivers and these drivers
> access system manager.
> Therefore, this driver is enabled for all platforms. Gen5/A10, S10/Agilex all
> are using it.
Ah, I missed that part of the series. I'm still reading it. Making gen5
use misc_read/misc_write seems a bit strange, but I can't think of a
better way right now, either...
> Can I know what does your gen5 sysmgr driver do ?
I moved "pin init", "freezereq" and "get fpga ID" there to have less
ad-hoc code in the main SPL file...
The series where it's in targets moving as much as I can to DM drivers.
Sadly, I still haven't found a way to make it fit into the gen5 SRAM,
which is why I haven't posted it, yet...
> I can change the name to avoid conflict but Gen5 will have 2 sysmgr drivers
> for different purposes.
> Are you OK with that ?
Hmm, I don't think that will work. That would mean binding 2 drivers to
one ofnode. I can split the gen5 driver later and implement read/write
like it's needed if this one gets applied as is.
>>
>>> @@ -0,0 +1,115 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright (C) 2020 Intel Corporation */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +#define IS_OUT_OF_SYSMGR(addr, range) ((addr) > (range))
>>> +
>>> +struct altera_sysmgr_priv {
>>> + fdt_addr_t base_addr;
>>> + fdt_addr_t base_size;
>>> +};
>>> +
>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) static int
>>> +secure_write32(u32 val, fdt_addr_t addr) {
>>> + int ret;
>>> + u64 args[2];
>>> +
>>> + args[0] = (u64)addr;
>>> + args[1] = val;
>>> + ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
>>
>> Hmm, so you're just using misc_ops to still issue generic writes. From the
>> discussion with Marek in the last version, I would have thought you wanted to
>> create a higher level API instead of still tunnelling reads and writes?
>>
>> In my gen5 series to abstract the gen5 sysmgr, I have used
Re: [PATCH v4 00/21] Enable ARM Trusted Firmware for U-Boot
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> From: "Ang, Chee Hong"
>
> v4 changes:
> [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager
> - Add System Manager driver (UCLASS_MISC) to handle secure access for SoC64
>
> [PATCH v4 13/21] mmc: dwmmc: socfpga: MMC driver access System Manager via
> 'altera_sysmgr'
> - DW MMC driver access System Manager via the System Manager driver
>
> [PATCH v4 14/21] arch: arm: socfpga: Add 'altr,sysmgr-syscon' for MMC
> - DW MMC driver get DRVSEL & SMPLSEL clock settings from device tree
>
> [PATCH v4 15/21] net: designware: socfpga: MAC driver access System via
> 'altera_sysmgr'
> - DW MAC driver access System Manager via the System Manager driver
>
> v3:
> https://lists.denx.de/pipermail/u-boot/2020-February/400986.html
>
> These patchsets have dependency on:
> https://lists.denx.de/pipermail/u-boot/2019-September/384906.html
>
> Chee Hong Ang (21):
> configs: agilex: Remove CONFIG_OF_EMBED
> arm: socfpga: add fit source file for pack itb with ATF
> arm: socfpga: Add function for checking description from FIT image
> arm: socfpga: Load FIT image with ATF support
> arm: socfpga: Override 'lowlevel_init' to support ATF
> configs: socfpga: Enable FIT image loading with ATF support
> arm: socfpga: Disable "spin-table" method for booting Linux
> arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
> arm: socfpga: Define SMC function identifiers for PSCI SiP services
> arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> misc: altera_sysmgr: Add Altera System Manager driver
> arch: arm: socfpga: Enable driver model for misc drivers.
> mmc: dwmmc: socfpga: MMC driver access System Manager via
> 'altera_sysmgr'
> arch: arm: socfpga: Add 'altr,sysmgr-syscon' for MMC node in device
> tree
> net: designware: socfpga: MAC driver access System Manager via
> 'altera_sysmgr'
> arm: socfpga: Add ATF support for Reset Manager driver
> arm: socfpga: stratix10: Initialize timer in SPL
> arm: socfpga: Add ATF support to query FPGA configuration status
> arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
> arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> mbox_reset_cold()
> configs: socfpga: Add defconfig for Agilex and Stratix 10 without ATF
> support
Are you sure building all previously existing defconfigs keeps working
with every single commit here? If not, that would break 'git bisect' in
the future...
I have the feeling that things might be broken in between - escpecially
since you're adding the 'old' "without ATF" defconfig in the last patch.
I think it would make more sense to keep the old defconfig name, keep it
building correctly throughout this series and add a "with ATF" defconfig
at the end. That way, you ensure existing usages keep working.
Regards,
Simon
>
> arch/arm/Kconfig | 2 +
> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 1 +
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
> arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 1 +
> arch/arm/dts/socfpga_cyclone5.dtsi | 1 +
> arch/arm/dts/socfpga_stratix10.dtsi| 1 -
> arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 7 +
> arch/arm/dts/socfpga_stratix10_socdk.dts | 2 -
> arch/arm/mach-socfpga/Kconfig | 2 -
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/board.c | 10 +
> arch/arm/mach-socfpga/include/mach/misc.h | 3 +
> arch/arm/mach-socfpga/lowlevel_init_64.S | 81 +
> arch/arm/mach-socfpga/mailbox_s10.c| 4 +
> arch/arm/mach-socfpga/misc_s10.c | 121 ++-
> arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
> arch/arm/mach-socfpga/timer_s10.c | 3 +-
> board/altera/soc64/its/fit_spl_atf.its | 52 +++
> configs/socfpga_agilex_defconfig | 8 +-
> ...lex_defconfig => socfpga_agilex_nofw_defconfig} | 2 +-
> configs/socfpga_stratix10_defconfig| 7 +-
> ..._defconfig => socfpga_stratix10_nofw_defconfig} | 2 +-
> drivers/fpga/stratix10.c | 141 +++-
> drivers/misc/Makefile | 1 +
> drivers/misc/altera_sysmgr.c | 115 ++
> drivers/mmc/socfpga_dw_mmc.c | 63 +++-
> drivers/net/dwmac_socfpga.c| 37 +-
> include/configs/socfpga_soc64_common.h | 4 +
> include/linux/intel-smc.h | 393
> +
> 29 files changed, 955 insertions(+), 122 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S
> create mode 100644 board/altera/soc64/its/fit_spl_atf.its
> copy configs/{socfpga_agilex_defconfig => socfpga_agilex_nofw_defconf
Re: [PATCH v4 12/21] arch: arm: socfpga: Enable driver model for misc drivers.
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com: > From: Chee Hong Ang > > Enable this misc driver model for 'altera_sysmgr' driver for > socfpga platforms. > > Signed-off-by: Chee Hong Ang > --- > arch/arm/Kconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 8d9f7fc..4ee8ae0 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -937,9 +937,11 @@ config ARCH_SOCFPGA > select DM > select DM_SERIAL > select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > + select MISC Please don't 'select' this. You prevent building smaller configs that don't need it. Please use 'imply' instead. > select OF_CONTROL > select SPL_DM_RESET if DM_RESET > select SPL_DM_SERIAL > + select SPL_DRIVERS_MISC_SUPPORT Especially this one makes gen5 SPL uneccessary large. Regards, Simon > select SPL_LIBCOMMON_SUPPORT > select SPL_LIBGENERIC_SUPPORT > select SPL_NAND_SUPPORT if SPL_NAND_DENALI >
Re: [PATCH v4 14/21] arch: arm: socfpga: Add 'altr, sysmgr-syscon' for MMC node in device tree
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> From: Chee Hong Ang
>
> In device tree for all socfpga platforms, a phandle to System Manager
> ('altr,sysmgr-syscon') is needed for MMC node to enable the MMC driver
> to configure the SDMMC's clock phase shift via System Manager driver
> (altera_sysmgr).
> This phandle specifies the offset of the SDMCC control register in
> System Manager, start of bit field for drvsel and start of bit field
> for smplsel.
>
> Signed-off-by: Chee Hong Ang
> ---
> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi| 1 +
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
> arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi| 1 +
> arch/arm/dts/socfpga_cyclone5.dtsi | 1 +
> arch/arm/dts/socfpga_stratix10.dtsi | 1 -
> arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 7 +++
> arch/arm/dts/socfpga_stratix10_socdk.dts | 2 --
This looks strange. I would have expected you add the 'syscon' entry to
the base dtsi files (and to the ones in Linux, too, btw). But you're
adding it to "-u-boot.dtsi" files, too. Why?
Regards,
Simon
> 7 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> index 1908be4..56fd7d9 100644
> --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> @@ -34,6 +34,7 @@
> &mmc {
> drvsel = <3>;
> smplsel = <0>;
> + altr,sysmgr-syscon = <&sysmgr 0x28 0 4>;
> u-boot,dm-pre-reloc;
> };
>
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index d6b6c2d..887673b 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -44,6 +44,7 @@
> cap-sd-highspeed;
> broken-cd;
> bus-width = <4>;
> + altr,sysmgr-syscon = <&sysmgr 0x28 0 4>;
> };
>
> &eccmgr {
> diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
> index dfaff4c..d2189f1 100644
> --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
> @@ -20,6 +20,7 @@
> };
>
> &mmc {
> + altr,sysmgr-syscon = <&sysmgr 0x108 0 3>;
> u-boot,dm-pre-reloc;
> };
>
> diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi
> b/arch/arm/dts/socfpga_cyclone5.dtsi
> index 319a71e..c309681 100644
> --- a/arch/arm/dts/socfpga_cyclone5.dtsi
> +++ b/arch/arm/dts/socfpga_cyclone5.dtsi
> @@ -23,6 +23,7 @@
> bus-width = <4>;
> cap-mmc-highspeed;
> cap-sd-highspeed;
> + altr,sysmgr-syscon = <&sysmgr 0x108 0 3>;
> };
>
> sysmgr@ffd08000 {
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
> b/arch/arm/dts/socfpga_stratix10.dtsi
> index a8e61cf..9c89065 100755
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -228,7 +228,6 @@
> interrupts = <0 96 4>;
> fifo-depth = <0x400>;
> resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
> - u-boot,dm-pre-reloc;
> status = "disabled";
> };
>
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> index a903040..ca91b40 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> @@ -28,6 +28,13 @@
> u-boot,dm-pre-reloc;
> };
>
> +&mmc {
> + drvsel = <3>;
> + smplsel = <0>;
> + altr,sysmgr-syscon = <&sysmgr 0x28 0 4>;
> + u-boot,dm-pre-reloc;
> +};
> +
> &sysmgr {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> b/arch/arm/dts/socfpga_stratix10_socdk.dts
> index b7b48a5..ff6e1b2 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk.dts
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -91,8 +91,6 @@
> cap-mmc-highspeed;
> broken-cd;
> bus-width = <4>;
> - drvsel = <3>;
> - smplsel = <0>;
> };
>
> &qspi {
>
Re: [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager driver
Am 10.03.2020 um 17:42 schrieb Ang, Chee Hong:
>> -Original Message-
>> From: Simon Goldschmidt
>> Sent: Wednesday, March 11, 2020 12:17 AM
>> To: Ang, Chee Hong
>> Cc: u-boot@lists.denx.de; Marek Vasut ; See, Chin Liang
>> ; Tan, Ley Foon ;
>> Westergreen, Dalon ; Gong, Richard
>>
>> Subject: Re: [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager
>> driver
>>
>> Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
>>> From: Chee Hong Ang
>>>
>>> This driver (misc uclass) handle the read/write access to System
>>> Manager. For 64 bits platforms, processor needs to be in secure mode
>>> to has write access to most of the System Manager's registers (except
>>> boot scratch registers). When the processor is running in EL2
>>> (non-secure), this driver will invoke the SMC call to ATF to perform
>>> write access to the System Manager's registers.
>>> All other drivers that require access to System Manager should go
>>> through this driver.
>>>
>>> Signed-off-by: Chee Hong Ang
>>> ---
>>> drivers/misc/Makefile| 1 +
>>> drivers/misc/altera_sysmgr.c | 115
>>> +++
>>> 2 files changed, 116 insertions(+)
>>> create mode 100644 drivers/misc/altera_sysmgr.c
>>>
>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
>>> 2b843de..9fa2411 100644
>>> --- a/drivers/misc/Makefile
>>> +++ b/drivers/misc/Makefile
>>> @@ -29,6 +29,7 @@ endif
>>> endif
>>> obj-$(CONFIG_ALI152X) += ali512x.o
>>> obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
>>> +obj-$(CONFIG_ARCH_SOCFPGA) += altera_sysmgr.o
>>> obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
>>> obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
>>> obj-$(CONFIG_DS4510) += ds4510.o
>>> diff --git a/drivers/misc/altera_sysmgr.c
>>> b/drivers/misc/altera_sysmgr.c new file mode 100644 index
>>> 000..b36ecae
>>> --- /dev/null
>>> +++ b/drivers/misc/altera_sysmgr.c
>>
>> I think this file should have something in the name specifying it is for
>> s10/agilex.
>> I will post a misc/sysmgr for gen5 that needs a specific name, too
> Gen5/A10/S10/Agilex are using same DW MMC/MAC drivers and these drivers
> access system manager.
> Therefore, this driver is enabled for all platforms. Gen5/A10, S10/Agilex all
> are using it.
> Can I know what does your gen5 sysmgr driver do ?
> I can change the name to avoid conflict but Gen5 will have 2 sysmgr drivers
> for different purposes.
> Are you OK with that ?
>>
>>> @@ -0,0 +1,115 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright (C) 2020 Intel Corporation */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +#define IS_OUT_OF_SYSMGR(addr, range) ((addr) > (range))
>>> +
>>> +struct altera_sysmgr_priv {
>>> + fdt_addr_t base_addr;
>>> + fdt_addr_t base_size;
>>> +};
>>> +
>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) static int
>>> +secure_write32(u32 val, fdt_addr_t addr) {
>>> + int ret;
>>> + u64 args[2];
>>> +
>>> + args[0] = (u64)addr;
>>> + args[1] = val;
>>> + ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
>>
>> Hmm, so you're just using misc_ops to still issue generic writes. From the
>> discussion with Marek in the last version, I would have thought you wanted to
>> create a higher level API instead of still tunnelling reads and writes?
Any response to this?
Thanks,
Simon
>>
>> In my gen5 series to abstract the gen5 sysmgr, I have used 'ioctl' and
>> 'call' from
>> misc_ops to have an API.
>>
>> Regards,
>> Simon
>>
>>> + if (ret)
>>> + return -EIO;
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +static int write32(u32 val, fdt_addr_t addr) { #if
>>> +!defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
>>> + return secure_write32(val, addr);
>>> +#else
>>> + writel(val, addr);
>>> +
>>> + return 0;
>>> +#endif
>>> +}
>>> +
>>> +static int altera_sysmgr_read(struct ude
Re: [PATCH v6 4/5] usb: host: dwc2: force reset assert
Am 10.03.2020 um 11:09 schrieb Patrick Delaunay:
> Assert reset before deassert in dwc2_reset;
> this patch solve issues when the DWC2 registers are already
> initialized with value incompatible with host mode.
>
> Force a hardware reset of the IP reset all the DWC2 registers at
> default value, the host driver start with a clean state
> (Core Soft reset doen in dwc_otg_core_reset is not enought
> to reset all register).
>
> The error can occurs in U-Boot when DWC2 device gadget driver
> force device mode (called by ums or dfu command, before to execute
> the usb start command).
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Goldschmidt
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - add clk_disable_bulk in dwc2_usb_remove
>
> drivers/usb/host/dwc2.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> index b1b79d0a18..640ae3e730 100644
> --- a/drivers/usb/host/dwc2.c
> +++ b/drivers/usb/host/dwc2.c
> @@ -1151,6 +1151,8 @@ static int dwc2_reset(struct udevice *dev)
> return ret;
> }
>
> + /* force reset to clear all IP register */
> + reset_assert_bulk(&priv->resets);
> ret = reset_deassert_bulk(&priv->resets);
> if (ret) {
> reset_release_bulk(&priv->resets);
>
Re: [PATCH v6 1/5] dm: clk: add stub when CONFIG_CLK is deactivated
Am 10.03.2020 um 11:09 schrieb Patrick Delaunay:
> Add stub for functions clk_...() when CONFIG_CLK is deactivated.
>
> This patch avoids compilation issues for driver using these API
> without protection (#if CONFIG_IS_ENABLED(CLK))
>
> For example, before this patch we have undefined reference to
> `clk_disable_bulk') for code:
> clk_disable_bulk(&priv->clks);
> clk_release_bulk(&priv->clks);
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Goldschmidt
> ---
>
> Changes in v6:
> - return success in stub for clk_free/clk_enable/clk_disable/
> clk_enable_bulk/clk_disable_bulk
>
> Changes in v5:
> - use ERR_PTR in clk_get_parent()
> - force bulk->count = 0 in clk_get_bulk to avoid issue
> for next call of clk_enable_bulk / clk_enable_bulk
> - update commit message
>
> Changes in v4:
> - Add stub for all functions using 'struct clk' or 'struct clk_bulk'
> after remarks on v3
>
> Changes in v3:
> - Add stub for clk_disable_bulk
>
> Changes in v2: None
>
> include/clk.h | 102 +++---
> 1 file changed, 89 insertions(+), 13 deletions(-)
>
> diff --git a/include/clk.h b/include/clk.h
> index 3336301815..60c4b7d075 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -9,6 +9,7 @@
> #define _CLK_H_
>
> #include
> +#include
> #include
> #include
>
> @@ -312,6 +313,7 @@ static inline int clk_release_bulk(struct clk_bulk *bulk)
> return clk_release_all(bulk->clks, bulk->count);
> }
>
> +#if CONFIG_IS_ENABLED(CLK)
> /**
> * clk_request - Request a clock by provider-specific ID.
> *
> @@ -433,19 +435,6 @@ int clk_disable_bulk(struct clk_bulk *bulk);
> */
> bool clk_is_match(const struct clk *p, const struct clk *q);
>
> -int soc_clk_dump(void);
> -
> -/**
> - * clk_valid() - check if clk is valid
> - *
> - * @clk: the clock to check
> - * @return true if valid, or false
> - */
> -static inline bool clk_valid(struct clk *clk)
> -{
> - return clk && !!clk->dev;
> -}
> -
> /**
> * clk_get_by_id() - Get the clock by its ID
> *
> @@ -465,6 +454,93 @@ int clk_get_by_id(ulong id, struct clk **clkp);
> * @return true on binded, or false on no
> */
> bool clk_dev_binded(struct clk *clk);
> +
> +#else /* CONFIG_IS_ENABLED(CLK) */
> +
> +static inline int clk_request(struct udevice *dev, struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_free(struct clk *clk)
> +{
> + return 0;
> +}
> +
> +static inline ulong clk_get_rate(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline struct clk *clk_get_parent(struct clk *clk)
> +{
> + return ERR_PTR(-ENOSYS);
> +}
> +
> +static inline long long clk_get_parent_rate(struct clk *clk)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline ulong clk_set_rate(struct clk *clk, ulong rate)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline int clk_enable(struct clk *clk)
> +{
> + return 0;
> +}
> +
> +static inline int clk_enable_bulk(struct clk_bulk *bulk)
> +{
> + return 0;
> +}
> +
> +static inline int clk_disable(struct clk *clk)
> +{
> + return 0;
> +}
> +
> +static inline int clk_disable_bulk(struct clk_bulk *bulk)
> +{
> + return 0;
> +}
> +
> +static inline bool clk_is_match(const struct clk *p, const struct clk *q)
> +{
> + return false;
> +}
> +
> +static inline int clk_get_by_id(ulong id, struct clk **clkp)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline bool clk_dev_binded(struct clk *clk)
> +{
> + return false;
> +}
> +#endif /* CONFIG_IS_ENABLED(CLK) */
> +
> +/**
> + * clk_valid() - check if clk is valid
> + *
> + * @clk: the clock to check
> + * @return true if valid, or false
> + */
> +static inline bool clk_valid(struct clk *clk)
> +{
> + return clk && !!clk->dev;
> +}
> +
> +int soc_clk_dump(void);
> +
> #endif
>
> #define clk_prepare_enable(clk) clk_enable(clk)
>
Re: [PATCH 1/1] fit: check return value of fit_image_get_data_size()
On Wed, Mar 11, 2020 at 9:51 PM Heinrich Schuchardt wrote:
>
> GCC-10 reports:
>
> In file included from tools/common/image-fit.c:1:
> include/image.h: In function ‘fit_image_get_data_and_size’:
> ./tools/../common/image-fit.c:1015:9: warning: ‘len’ may be used
> uninitialized in this function [-Wmaybe-uninitialized]
> 1015 | *size = len;
> | ~~^
> ./tools/../common/image-fit.c:996:6: note: ‘len’ was declared here
> 996 | int len;
> | ^~~
>
> Add the missing check of the return value of fit_image_get_data_size().
>
> Fixes: c3c863880479 ("add FIT data-position & data-offset property support")
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Simon Goldschmidt
> ---
> common/image-fit.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/common/image-fit.c b/common/image-fit.c
> index f3bb00c98a..4435bc4f1d 100644
> --- a/common/image-fit.c
> +++ b/common/image-fit.c
> @@ -1011,8 +1011,10 @@ int fit_image_get_data_and_size(const void *fit, int
> noffset,
> if (external_data) {
> debug("External Data\n");
> ret = fit_image_get_data_size(fit, noffset, &len);
> - *data = fit + offset;
> - *size = len;
> + if (!ret) {
> + *data = fit + offset;
> + *size = len;
> + }
> } else {
> ret = fit_image_get_data(fit, noffset, data, size);
> }
> --
> 2.25.1
>
Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: > > > On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: >> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: >> [...] >> >> (thanks for fixing your mailer :)) >> The problem was that this was causing weird sporadic hangs on Gen5, which is why it was removed. So until there is an explanation for those hangs, I'm not really OK with this. >>> >>> These sporadic hangs you saw were on devices without an FPGA image >>> directly >>> accessing the SDRAM ports, right? >> >> Yes >> Maybe the application of static config should happen in SPL, before the DRAM is running, or something like that ? >>> >>> Thinking this further, limiting it to applying in SPL is not a good >>> idea >>> since >>> that prevents us from implementing different FPGA images/configs by >>> loading a >>> config later in the boot (i.e. in U-Boot from a FIT-image). >> >> Well, but later we have SDRAM running and we cannot make it go idle, >> can >> we? >> >>> >>> Unfortunately the sdram cfg apply must occur AFTER the fpga is >>> configured. This >>> is because the FPGA drives configuration bits, around the interfaces >>> datawidth >>> for example, that are used in setting up the dram interface. I believe the >>> intent is for the command to only run when the ridge enable function is >>> called. >> >> So that's one part of the fix -- only run this apply_static_cfg if the >> bitstream uses the F2S bridge. > > actually, the restriction is to apply this only if the FPGA is configured, > whether the bridge is used is irrelevant. you can further restrict this > to only when the bridge is used, but to me that means devicetree entries > or something to determine whether it is used. In my opinion, we need an FPGA-specific devicetree (or something similar) to describe the FPGA image, anyway. Today, too much configuration is applied at compile time (or when programming SPL to flash at latest) - there's currently no way to switch peripherals to FPGA for one image but not for another, for example. Worse: if you enable bridges but there's no slave attached, the CPU can be stuck. That would need to be described with the FPGA image as well. Regards, Simon > >> >>> Would it work to make setting this optional, i.e. only write the bit >>> if >>> an FPGA >>> config actually uses these ports? Then it couldn't lead to problems >>> on >>> other >>> hardware... >> >> Can you make SDRAM bus really idle ? > > From the CPU side, that should work, no? Of course you have to make sure > no > other peripheraly (including FPGA!) are using the RAM. > > And if this would be an explicit command, people needing this could > experiment with it - and hopefully give better hints as to what's going > wrong > if we *do* see problems again. Maybe altera has something hidden somewhere in the bus tunables ? :) >>> >>> The only trick i am aware of, and Ley Foon, please comment, is isolating >>> relevant code to the caches before executing. >> >> How do you make sure some DMA doesn't do something funny or some pending >> write doesn't trigger DRAM write ? There is more than the CPU that can >> access the DRAM and cause bus traffic. > > True, and it is unclear how we could ensure there is absolutely no traffic. > > --dalon > >
Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Am 16.03.2020 um 20:06 schrieb Marek Vasut: > On 3/16/20 8:04 PM, Simon Goldschmidt wrote: >> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: >>> >>> >>> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: >>>> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: >>>> [...] >>>> >>>> (thanks for fixing your mailer :)) >>>> >>>>>>>>>> The problem was that this was causing weird sporadic hangs on >>>>>>>>>> Gen5, >>>>>>>>>> which is why it was removed. So until there is an explanation for >>>>>>>>>> those >>>>>>>>>> hangs, I'm not really OK with this. >>>>>>>>> >>>>>>>>> These sporadic hangs you saw were on devices without an FPGA image >>>>>>>>> directly >>>>>>>>> accessing the SDRAM ports, right? >>>>>>>> >>>>>>>> Yes >>>>>>>> >>>>>>>>>> Maybe the application of static config should happen in SPL, >>>>>>>>>> before >>>>>>>>>> the >>>>>>>>>> DRAM is running, or something like that ? >>>>>>>>> >>>>>>>>> Thinking this further, limiting it to applying in SPL is not a good >>>>>>>>> idea >>>>>>>>> since >>>>>>>>> that prevents us from implementing different FPGA images/configs by >>>>>>>>> loading a >>>>>>>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>>>>>> >>>>>>>> Well, but later we have SDRAM running and we cannot make it go idle, >>>>>>>> can >>>>>>>> we? >>>>>>>> >>>>> >>>>> Unfortunately the sdram cfg apply must occur AFTER the fpga is >>>>> configured. This >>>>> is because the FPGA drives configuration bits, around the interfaces >>>>> datawidth >>>>> for example, that are used in setting up the dram interface. I believe >>>>> the >>>>> intent is for the command to only run when the ridge enable function is >>>>> called. >>>> >>>> So that's one part of the fix -- only run this apply_static_cfg if the >>>> bitstream uses the F2S bridge. >>> >>> actually, the restriction is to apply this only if the FPGA is configured, >>> whether the bridge is used is irrelevant. you can further restrict this >>> to only when the bridge is used, but to me that means devicetree entries >>> or something to determine whether it is used. >> >> In my opinion, we need an FPGA-specific devicetree (or something >> similar) to describe the FPGA image, anyway. > > Like a DTO ? > >> Today, too much >> configuration is applied at compile time (or when programming SPL to >> flash at latest) - there's currently no way to switch peripherals to >> FPGA for one image but not for another, for example. > > Yes > >> Worse: if you enable bridges but there's no slave attached, the CPU can >> be stuck. That would need to be described with the FPGA image as well. > > Can you propose a patch ? In corona times and with kids now at home, I don't know if I can soon :-( Regards, Simon
Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Am 16.03.2020 um 20:55 schrieb Dalon L Westergreen: > > > On Mon, 2020-03-16 at 20:06 +0100, Marek Vasut wrote: >> On 3/16/20 8:04 PM, Simon Goldschmidt wrote: >>> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: >>>> >>>> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: >>>>> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: >>>>> [...] >>>>> >>>>> (thanks for fixing your mailer :)) >>>>> >>>>>>>>>>> The problem was that this was causing weird sporadic hangs >>>>>>>>>>> on >>>>>>>>>>> Gen5, >>>>>>>>>>> which is why it was removed. So until there is an >>>>>>>>>>> explanation for >>>>>>>>>>> those >>>>>>>>>>> hangs, I'm not really OK with this. >>>>>>>>>> >>>>>>>>>> These sporadic hangs you saw were on devices without an FPGA >>>>>>>>>> image >>>>>>>>>> directly >>>>>>>>>> accessing the SDRAM ports, right? >>>>>>>>> >>>>>>>>> Yes >>>>>>>>> >>>>>>>>>>> Maybe the application of static config should happen in SPL, >>>>>>>>>>> before >>>>>>>>>>> the >>>>>>>>>>> DRAM is running, or something like that ? >>>>>>>>>> >>>>>>>>>> Thinking this further, limiting it to applying in SPL is not a >>>>>>>>>> good >>>>>>>>>> idea >>>>>>>>>> since >>>>>>>>>> that prevents us from implementing different FPGA >>>>>>>>>> images/configs by >>>>>>>>>> loading a >>>>>>>>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>>>>>>> >>>>>>>>> Well, but later we have SDRAM running and we cannot make it go >>>>>>>>> idle, >>>>>>>>> can >>>>>>>>> we? >>>>>>>>> >>>>>> >>>>>> Unfortunately the sdram cfg apply must occur AFTER the fpga is >>>>>> configured. This >>>>>> is because the FPGA drives configuration bits, around the interfaces >>>>>> datawidth >>>>>> for example, that are used in setting up the dram interface. I >>>>>> believe the >>>>>> intent is for the command to only run when the ridge enable function >>>>>> is >>>>>> called. >>>>> >>>>> So that's one part of the fix -- only run this apply_static_cfg if the >>>>> bitstream uses the F2S bridge. >>>> >>>> actually, the restriction is to apply this only if the FPGA is configured, >>>> whether the bridge is used is irrelevant. you can further restrict this >>>> to only when the bridge is used, but to me that means devicetree entries >>>> or something to determine whether it is used. >>> >>> In my opinion, we need an FPGA-specific devicetree (or something >>> similar) to describe the FPGA image, anyway. >> >> Like a DTO ? > > DTOs are how i suggest solving this in linux, so i would assume a dto would > be best here too. Yes. That DTO should be beside the FPGA image, either in a FIT image or just loaded separately. It should contain pin settings, bridge settings etc. However, to ensure the bus is idle, we still would have to limit applying that config bit to before RAM is set up, so quite early in SPL, right? I cannot see how that would work, given the limit of 64K. Plus it's kind of a bad boot flow to configure the FPGA before even starting U-Boot... Regards, Simon > >> >>> Today, too much >>> configuration is applied at compile time (or when programming SPL to >>> flash at latest) - there's currently no way to switch peripherals to >>> FPGA for one image but not for another, for example. >> >> Yes >> >>> Worse: if you enable bridges but there's no slave attached, the CPU can >>> be stuck. That would need to be described with the FPGA image as well. >> >> Can you propose a patch ? >> >
Re: [U-Boot] [PATCH v4 2/4] arm: socfpga: Convert reset manager from struct to defines
On Wed, Oct 30, 2019 at 10:48 AM Ley Foon Tan wrote: > > On Tue, Oct 29, 2019 at 6:31 PM Simon Goldschmidt > wrote: > > > > > > > > Ley Foon Tan schrieb am Di., 29. Okt. 2019, 11:16: > >> > >> On Fri, Oct 25, 2019 at 5:37 PM Simon Goldschmidt > >> wrote: > >> > > >> > On Fri, Oct 25, 2019 at 11:17 AM Ley Foon Tan > >> > wrote: > >> > > > >> > > On Wed, Oct 23, 2019 at 2:11 AM Simon Goldschmidt > >> > > wrote: > >> > > > > >> > > > Am 10.10.2019 um 09:37 schrieb Ley Foon Tan: > >> > > > > Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct > >> > > > > to defines. > >> > > > > > >> > > > > Change to get reset manager base address from DT node instead of > >> > > > > using > >> > > > > #define. > >> > > > > > >> > > > > Signed-off-by: Ley Foon Tan > >> > > > > > >> > > > > --- > >> > > > > v4: > >> > > > > - Update commit message about get base address from DT node. > >> > > > > > >> > > > > v3: > >> > > > > - Remove "No functional change" in commit description. > >> > > > > > >> > > > > v2: > >> > > > > - Get base address from DT > >> > > > > - Revert to use writel(), readl(), setbits_le32() and > >> > > > > clrbits_le32(). > >> > > > > - Add prefix to defines. > >> > > > > --- > >> > > > > arch/arm/mach-socfpga/include/mach/misc.h | 1 + > >> > > > > .../mach-socfpga/include/mach/reset_manager.h | 2 + > >> > > > > .../include/mach/reset_manager_arria10.h | 43 > >> > > > > - > >> > > > > .../include/mach/reset_manager_gen5.h | 22 - > >> > > > > .../include/mach/reset_manager_s10.h | 33 ++--- > >> > > > > arch/arm/mach-socfpga/misc.c | 32 + > >> > > > > arch/arm/mach-socfpga/misc_gen5.c | 7 ++- > >> > > > > arch/arm/mach-socfpga/reset_manager_arria10.c | 47 > >> > > > > ++- > >> > > > > arch/arm/mach-socfpga/reset_manager_gen5.c| 28 +-- > >> > > > > arch/arm/mach-socfpga/reset_manager_s10.c | 34 +++--- > >> > > > > arch/arm/mach-socfpga/spl_a10.c | 7 ++- > >> > > > > arch/arm/mach-socfpga/spl_gen5.c | 12 ++--- > >> > > > > arch/arm/mach-socfpga/spl_s10.c | 12 +++-- > >> > > > > drivers/sysreset/sysreset_socfpga.c | 6 +-- > >> > > > > 14 files changed, 137 insertions(+), 149 deletions(-) > >> > > > > > >> > > > > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h > >> > > > > b/arch/arm/mach-socfpga/include/mach/misc.h > >> > > > > index 27d0b6a370..a29b049742 100644 > >> > > > > --- a/arch/arm/mach-socfpga/include/mach/misc.h > >> > > > > +++ b/arch/arm/mach-socfpga/include/mach/misc.h > >> > > > > @@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void); > >> > > > > > >> > > > > void do_bridge_reset(int enable, unsigned int mask); > >> > > > > void socfpga_pl310_clear(void); > >> > > > > +void socfpga_get_manager_addr(void); > >> > > > > > >> > > > > #endif /* _MISC_H_ */ > >> > > > > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h > >> > > > > b/arch/arm/mach-socfpga/include/mach/reset_manager.h > >> > > > > index 6ad037e325..a5b6931350 100644 > >> > > > > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h > >> > > > > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h > >> > > > > @@ -6,6 +6,8 @@ > >> > > > > #ifndef _RESET_MANAGER_H_ > >> > > > > #define _RESET_MANAGER_H_ > >> > > > > > >> > > > > +extern phys_addr_t socfpga_rstmgr_base; > &g
Re: [U-Boot] [PATCH 1/1] net: avoid address-of-packed-member error
Am 04.11.2019 um 20:34 schrieb Heinrich Schuchardt:
struct ip_udp_hdr is naturally packed. There is no point in adding a
__packed attribute. With the attribute the network stack does not compile
using GCC 9.2.1:
Is this commit message correct? In lwIP, we *do* need to pack all these
network header structs as they can come in unaligned. Especially the IP
header is normally 16-bit aligned if the incoming Ethernet frame is
32-bit aligned (which is a must for many DMA engines).
This is also the reason why the below code works, I guess: it is rarely
totally unaligned, but nearly always at least 16-bit aligned, so
dereferencing the checksum pointer as aligned u16 just works.
Nevertheless, the code is formally wrong and your patch is correct. I
just don't like the commit message saying 'packed' is not required.
net/net.c: In function ‘net_process_received_packet’:
net/net.c:1288:23: error: taking address of packed member of ‘struct
ip_udp_hdr’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
1288 |sumptr = (ushort *)&(ip->udp_src);
| ^~
Unfortunately there was a bug in GCC 7.1 which required __packed here.
So let's avoid the error by using a uchar pointer instead of an u16
pointer.
Signed-off-by: Heinrich Schuchardt
---
net/net.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/net/net.c b/net/net.c
index ded86e7456..e6f6d2cb45 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1274,7 +1274,7 @@ void net_process_received_packet(uchar *in_packet, int
len)
#ifdef CONFIG_UDP_CHECKSUM
if (ip->udp_xsum != 0) {
ulong xsum;
- ushort *sumptr;
+ uchar *sumptr;
ushort sumlen;
xsum = ip->ip_p;
@@ -1285,13 +1285,11 @@ void net_process_received_packet(uchar *in_packet, int
len)
xsum += (ntohl(ip->ip_dst.s_addr) >> 0) & 0x;
sumlen = ntohs(ip->udp_len);
- sumptr = (ushort *)&(ip->udp_src);
+ sumptr = (uchar *)&ip->udp_src;
while (sumlen > 1) {
- ushort sumdata;
-
- sumdata = *sumptr++;
- xsum += ntohs(sumdata);
+ xsum += (sumptr[0] << 8) + sumptr[1];
Do we need a comment here stating why we have an open-coded copy of
ntohs? That could keep us from getting this bug back in the future...
Regards,
Simon
+ sumptr += 2;
sumlen -= 2;
}
if (sumlen > 0) {
--
2.24.0.rc1
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Re: [U-Boot] [PATCHv2 0/4] support remote system update on Intel Stratix10 SoC
Am 30.10.2019 um 21:34 schrieb richard.g...@linux.intel.com: From: Richard Gong This is 2nd submission of Intel Remote System Update patches. Ok, so what has changed since v1? You'd normally add a changelog (ideally to both this cover-letter and to each patch). Have a look at patman in tools/patman, that allows you to create those changelogs more easily. The Intel Remote System Update (RSU) provides a way for users to update the QSPI configuration bitstream of a Intel Stratix10 SoC device with significantly reduced risk of corrupting the bitstream storage and bricking the system. The patchset adds RSU support which allows user to perform a complete set of RSU operations via provided console commands. The patches have reviewed by other colleagues at Intel. Richard Gong (4): arm: socfpga: stratix10: add RSU mailbox support drivers: firmware: add RSU support for Stratix10 SoC dirvers: firmware: add console commands for RSU support arm: socfpga: stratix10: add environment variables for RSU support arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 36 +- arch/arm/mach-socfpga/mailbox_s10.c | 79 ++ Do you have plans to move this code to drivers/mailbox? arch/arm/mach-socfpga/misc_s10.c |9 + drivers/firmware/Kconfig | 11 + drivers/firmware/Makefile|1 + drivers/firmware/rsu.c | 662 ++ drivers/firmware/rsu_ll_qspi.c | 1050 ++ drivers/firmware/rsu_misc.c | 817 + drivers/firmware/rsu_s10.c | 874 ++ Ok, so you started to add this "RSU" as a driver, that's probably fine (sorry I did not find the time to review that, yet). However, I think you'd need a more specific name, probably including 'intel' or something to make this more clear. I'll hope to find the time to review the rest this week. Regards, Simon include/intel/rsu.h | 291 ++ include/intel/rsu_ll.h | 72 ++ include/intel/rsu_misc.h | 60 ++ include/intel/rsu_s10.h | 46 + 13 files changed, 3998 insertions(+), 10 deletions(-) create mode 100644 drivers/firmware/rsu.c create mode 100644 drivers/firmware/rsu_ll_qspi.c create mode 100644 drivers/firmware/rsu_misc.c create mode 100644 drivers/firmware/rsu_s10.c create mode 100644 include/intel/rsu.h create mode 100644 include/intel/rsu_ll.h create mode 100644 include/intel/rsu_misc.h create mode 100644 include/intel/rsu_s10.h ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] net: avoid address-of-packed-member error
Tom Rini schrieb am Mo., 4. Nov. 2019, 22:15: > On Mon, Nov 04, 2019 at 09:28:51PM +0100, Simon Goldschmidt wrote: > > Am 04.11.2019 um 20:34 schrieb Heinrich Schuchardt: > > > struct ip_udp_hdr is naturally packed. There is no point in adding a > > > __packed attribute. With the attribute the network stack does not > compile > > > using GCC 9.2.1: > > > > Is this commit message correct? In lwIP, we *do* need to pack all these > > network header structs as they can come in unaligned. Especially the IP > > header is normally 16-bit aligned if the incoming Ethernet frame is > 32-bit > > aligned (which is a must for many DMA engines). > > > > This is also the reason why the below code works, I guess: it is rarely > > totally unaligned, but nearly always at least 16-bit aligned, so > > dereferencing the checksum pointer as aligned u16 just works. > > > > Nevertheless, the code is formally wrong and your patch is correct. I > just > > don't like the commit message saying 'packed' is not required. > > Perhaps we should fix the underlying code problem then? Or does that > men "rewrite the whole file" ? > This patch fixes the code problem. If there are more problems: any assignment to an u16 pointer from an address of a packed struct issues a warning (provided that appropriate warning settings are used). If we fix all of these warnings (e.g. like we do here, by using alignment agnostic byte accesses), we should be good. I just think the misleading commit message should be fixed before giving my RB. Regards, Simon > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/1] net: avoid address-of-packed-member error
On Tue, Nov 5, 2019 at 2:52 PM Tom Rini wrote: > > On Tue, Nov 05, 2019 at 12:48:19PM +0100, Heinrich Schuchardt wrote: > > > sandbox_defconfig does not compile using GCC 9.2.1: > > > > net/net.c: In function ‘net_process_received_packet’: > > net/net.c:1288:23: error: taking address of packed member of ‘struct > > ip_udp_hdr’ may result in an unaligned pointer value > > [-Werror=address-of-packed-member] > > 1288 |sumptr = (ushort *)&(ip->udp_src); > > | ^~ > > > > Avoid the error by using a u8 pointer instead of an u16 pointer and > > in-lining ntohs(). > > > > Simplify the checksumming of the last message byte. > > > > Signed-off-by: Heinrich Schuchardt > > --- > > v2: > > reword commit message > > add a comment > > simplify checksumming of last byte > > If I follow what Simon was saying yesterday, the whole message framing > is wrong. The problem isn't that gcc 9.2 is showing a warning, the > problem is that gcc 9.2 is showing that we have a problem (in terms of > what can/can't happen in real life networking terms), which you're > correcting. Simon, can you please suggest a commit message here if > you're still not quite happy, as you understand the underlying problem > well it seems. Thanks! Well, we do have an error and GCC 9.2 shows this. I don't know why other versions don't issue this warning. This new commit message might still concentrate too much on the GCC version, but I think it's ok. I just wanted to prevent someone reading this in the future and taking it as a hint that the attribute 'packed' can be removed (which in turn might procude bugs on some platforms). So: Reviewed-by: Simon Goldschmidt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/3] drivers: reset: Add a managed API to get reset controllers from the DT
Am 05.11.2019 um 17:33 schrieb Simon Glass: Hi Jean-Jacques, On Mon, 4 Nov 2019 at 08:41, Jean-Jacques Hiblot wrote: On 30/10/2019 02:48, Simon Glass wrote: On Mon, 30 Sep 2019 at 10:15, Jean-Jacques Hiblot wrote: Add managed functions to get a reset_ctl from the device-tree, based on a name or an index. Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl) from the device-tree. When the device is unbound, the reset controllers are automatically released and the data structure is freed. Signed-off-by: Jean-Jacques Hiblot --- drivers/reset/reset-uclass.c | 116 +- include/reset.h | 135 ++- 2 files changed, 247 insertions(+), 4 deletions(-) Reviewed-by: Simon Glass I really don't like these ERR_PTR returns. I suppose they make the code easier to port, and we can be sure that pointers will not be in the last 4KB of address space? It seems rather unlikely because the returned pointer points to actual RAM allocated from the heap. On most platforms I've worked with, the top of the address space is not dedicated to memory. Most != all: on socfpga, the internal SRAM is at the end of the address spcae. In SPL, this means the last 4K cannot be used. However, that shouldn't keep us from porting ERR_PTR returns from Linux code. Yes that's my comfort. If ever the need to fix this arises it could done by tweaking the macros to use another unused address space. Not easily without doing something platform-specific, as someone else is currently pushing. That "someone else" would be me. Sadly, I did not get any response: https://patchwork.ozlabs.org/project/uboot/list/?series=137880 Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] spi: cadence_qspi: Move to spi-mem framework
Hi Vignesh,
On Thu, Oct 17, 2019 at 2:31 PM Vignesh Raghavendra wrote:
>
> Hi Simon,
>
> On 17/10/19 4:50 PM, Simon Goldschmidt wrote:
> > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
> >>
> >> Current Cadence QSPI driver has few limitations. It assumes all read
> >> operations to be in Quad mode and thus does not support SFDP parsing.
> >> Also, adding support for new mode such as Octal mode would not be
> >> possible with current configuration. Therefore move the driver over to
> >> spi-mem
> >> framework. This has added advantage that driver can be used to support
> >> SPI NAND memories too.
> >> Hence, move driver over to new spi-mem APIs.
> >>
> >> Please note that this gets rid of mode bit setting done when
> >> CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
> >> that config option.
> >
> > I just have tried this on an socfgpa cylone5 board with an mt25ql256a, but
> > it does not seem to work: when leaving spi-rx-bus-width and spi-tx-bus-width
> > at 4 in my devicetree, SFDP parsing works, but reading data afterwards
> > produces invalid results (I haven't tested what's wrong there).
> >
>
> Thanks for testing!
>
> spi-tx-bus-width = 4 was not supported before so I haven't added support
> for that mode in this series. That change will be a separate series.
>
> Could you try with spi-tx-bus-width = 1 and spi-rx-bus-width = 4 and see
> if that works?
>
> If that does not work then could you disable SFDP parsing (but keep
> spi-rx-bus-width = 4) and see if that works. This should narrow down
> whether SFDP parsing is broken or if driver has an issue.
Sorry, I still haven't found the time at work to test this. I'll keep trying.
Keeping that aside, if this driver is converted to spi-mem, is there any
chance of getting this into SPL while not getting standard SPI drivers in?
On socfpga, I have a standard SPI driver (designware_spi) enabled but that
results in both the cadence_qspi and designware_spi being included in SPL aside
well when boot-from-SPI is enabled.
Does that somehow change when cadence_qspi is an spi-mem driver?
Thanks,
Simon
>
> Regards
> Vignesh
>
> > It works as expected when not parsing SFDP or setting the bus-width to 1.
> > So the change itself probably works, but SFDP parsing is broken?
> >
> > I did the tests with this applied first:
> > https://patchwork.ozlabs.org/project/uboot/list/?series=135505
> >
> > Regards,
> > Simon
> >
> >
> >>
> >> Signed-off-by: Vignesh Raghavendra
> >> ---
> >> drivers/spi/cadence_qspi.c | 136 +
> >> drivers/spi/cadence_qspi.h | 9 +--
> >> drivers/spi/cadence_qspi_apb.c | 124 --
> >> 3 files changed, 91 insertions(+), 178 deletions(-)
> >>
> >> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> >> index e2e54cd27723..673a2e9a6c4c 100644
> >> --- a/drivers/spi/cadence_qspi.c
> >> +++ b/drivers/spi/cadence_qspi.c
> >> @@ -10,6 +10,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >> #include
> >> #include "cadence_qspi.h"
> >>
> >> @@ -34,12 +35,21 @@ static int cadence_spi_write_speed(struct udevice
> >> *bus, uint hz)
> >> return 0;
> >> }
> >>
> >> +static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
> >> +{
> >> + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
> >> + SPI_MEM_OP_NO_ADDR,
> >> + SPI_MEM_OP_NO_DUMMY,
> >> + SPI_MEM_OP_DATA_IN(len, idcode,
> >> 1));
> >> +
> >> + return cadence_qspi_apb_command_read(reg_base, &op);
> >> +}
> >> +
> >> /* Calibration sequence to determine the read data capture delay register
> >> */
> >> static int spi_calibration(struct udevice *bus, uint hz)
> >> {
> >> struct cadence_spi_priv *priv = dev_get_priv(bus);
> >> void *base = priv->regbase;
> >> - u8 opcode_rdid = 0x9F;
> >> unsigned int idcode = 0, temp = 0;
> >> int err = 0, i, range_lo = -1, range_hi = -1;
> >>
> >> @@ -53,8 +63,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
> >> cadence_qspi_apb_controller_enable(base);
&g
Re: [U-Boot] [PATCH v5 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
On Thu, Nov 7, 2019 at 9:33 AM Marek Vasut wrote:
>
> On 11/7/19 4:31 AM, Ley Foon Tan wrote:
> > On Thu, Nov 7, 2019 at 10:49 AM Marek Vasut wrote:
> >>
> >> On 11/7/19 3:10 AM, Ley Foon Tan wrote:
> >> [...]
> >>> diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>> b/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>> index 322c858c4b..d55460755f 100644
> >>> --- a/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>> +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>> @@ -10,6 +10,10 @@
> >>> };
> >>> };
> >>>
> >>> +&clkmgr {
> >>> + u-boot,dm-pre-reloc;
> >>> +};
> >>> +
> >>> &rst {
> >>> u-boot,dm-pre-reloc;
> >>> };
> >>> @@ -17,3 +21,7 @@
> >>> &sdr {
> >>> u-boot,dm-pre-reloc;
> >>> };
> >>> +
> >>> +&sysmgr {
> >>> + u-boot,dm-pre-reloc;
> >>> +};
> >>
> >> Gen5 doesn't have any clock driver, so does it really make sense to
> >> retain the clkmgr node in SPL now ? Seems like this only grows the SPL
> >> size with no benefit.
> >>
> > But, we need to get clkmgr base address from DT even we don't have
> > clock driver for it.
> > So, clkmgr needs enable in SPL.
Plus gen5 will have get clock manager soon ;-)
Regards,
Simon
>
> Ah, I see, thanks for clarifying.
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Re: [U-Boot] [PATCH v5 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
On Thu, Nov 7, 2019 at 9:40 AM Marek Vasut wrote:
>
> On 11/7/19 9:36 AM, Simon Goldschmidt wrote:
> > On Thu, Nov 7, 2019 at 9:33 AM Marek Vasut wrote:
> >>
> >> On 11/7/19 4:31 AM, Ley Foon Tan wrote:
> >>> On Thu, Nov 7, 2019 at 10:49 AM Marek Vasut wrote:
> >>>>
> >>>> On 11/7/19 3:10 AM, Ley Foon Tan wrote:
> >>>> [...]
> >>>>> diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>>>> b/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>>>> index 322c858c4b..d55460755f 100644
> >>>>> --- a/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>>>> +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>>>> @@ -10,6 +10,10 @@
> >>>>> };
> >>>>> };
> >>>>>
> >>>>> +&clkmgr {
> >>>>> + u-boot,dm-pre-reloc;
> >>>>> +};
> >>>>> +
> >>>>> &rst {
> >>>>> u-boot,dm-pre-reloc;
> >>>>> };
> >>>>> @@ -17,3 +21,7 @@
> >>>>> &sdr {
> >>>>> u-boot,dm-pre-reloc;
> >>>>> };
> >>>>> +
> >>>>> +&sysmgr {
> >>>>> + u-boot,dm-pre-reloc;
> >>>>> +};
> >>>>
> >>>> Gen5 doesn't have any clock driver, so does it really make sense to
> >>>> retain the clkmgr node in SPL now ? Seems like this only grows the SPL
> >>>> size with no benefit.
> >>>>
> >>> But, we need to get clkmgr base address from DT even we don't have
> >>> clock driver for it.
> >>> So, clkmgr needs enable in SPL.
> >
> > Plus gen5 will have get clock manager soon ;-)
>
> Keep in mind we're already in -rc1 , so that's for next release.
Right, that's in the gen5 DM series for next. I just wanted to say it's
ok to add this here because we'll need it anyway soon.
Regards,
Simon
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Re: [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
Am 03.10.2019 um 14:59 schrieb Marek Vasut: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers accordingly, no functional change. The S10 enables the WDT only in SPL, but does not enable it in U-Boot itself, hence disable it in the config again. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Jagan Teki Cc: Ley Foon Tan Cc: Philipp Tomisch Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Simon Goldschmidt --- V2: Use non-DM watchdog in SPL on S10 --- configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 7 +++ include/configs/socfpga_common.h | 3 --- include/configs/socfpga_stratix10_socdk.h | 6 -- scripts/config_whitelist.txt | 1 - 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index ad83f50032..462082b67b 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -56,3 +56,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 96f806ab5f..03c43fa8b9 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -91,3 +91,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index a66a9bcbe2..6fd9b0a177 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,6 +36,13 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver. +config DESIGNWARE_WATCHDOG + bool "Designware watchdog timer support" + select HW_WATCHDOG + help + Enable this to support Designware Watchdog Timer IP, present e.g. + on Altera SoCFPGA SoCs. + config WDT bool "Enable driver model for watchdog timer drivers" depends on DM diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index b11fe021a7..32b9131be0 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -104,12 +104,9 @@ /* * L4 Watchdog */ -#ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASESOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 3 -#endif /* * MMC Driver diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 7b55dd14da..353e08f982 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -162,14 +162,16 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #ifdef CONFIG_SPL_BUILD #define CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG +#else +#undef CONFIG_HW_WATCHDOG +#undef CONFIG_DESIGNWARE_WATCHDOG +#endif #define CONFIG_DW_WDT_BASESOCFPGA_L4WD0_ADDRESS #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) #endif #define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 -#endif /* * SPL memory layout diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b18eab1707..839eda8c0f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -320,7 +320,6 @@ CONFIG_DEFAULT_IMMR CONFIG_DEF_HWCONFIG CONFIG_DELAY_ENVIRONMENT CONFIG_DESIGNWARE_ETH -CONFIG_DESIGNWARE_WATCHDOG CONFIG_DEVELOP CONFIG_DEVICE_TREE_LIST CONFIG_DFU_ALT ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
Am 03.10.2019 um 14:59 schrieb Marek Vasut:
Convert the designware watchdog timer driver to DM and add DT probing
support. Perform minor coding style clean up, like drop superfluous
braces. There ought to be no functional change.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Jagan Teki
Cc: Ley Foon Tan
Cc: Philipp Tomisch
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
V2: - Support both DM and non-DM probing
- Fix watchdog stop handling by setting CR bit
---
configs/socfpga_stratix10_defconfig | 2 +
configs/socfpga_vining_fpga_defconfig | 1 +
drivers/watchdog/Kconfig | 2 +-
drivers/watchdog/designware_wdt.c | 122 ++
include/configs/socfpga_stratix10_socdk.h | 1 +
5 files changed, 104 insertions(+), 24 deletions(-)
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_defconfig
index 462082b67b..752fa545bd 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -57,3 +57,5 @@ CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_vining_fpga_defconfig
b/configs/socfpga_vining_fpga_defconfig
index 03c43fa8b9..def7a3eca7 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -91,4 +91,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_WDT=y
CONFIG_DESIGNWARE_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 6fd9b0a177..bfb91af947 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -38,7 +38,7 @@ config ULP_WATCHDOG
config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"
- select HW_WATCHDOG
+ select HW_WATCHDOG if !WDT
help
Enable this to support Designware Watchdog Timer IP, present e.g.
on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
index c668567c66..a7b735979a 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -4,7 +4,8 @@
*/
#include
-#include
+#include
+#include
#include
#include
@@ -17,46 +18,51 @@
#define DW_WDT_CR_RMOD_VAL0x00
#define DW_WDT_CRR_RESTART_VAL0x76
+struct designware_wdt_priv {
+ void __iomem*base;
+};
+
/*
* Set the watchdog time interval.
* Counter is 32 bit.
*/
-static int designware_wdt_settimeout(unsigned int timeout)
+static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
+unsigned int timeout)
{
signed int i;
/* calculate the timeout range value */
- i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
- if (i > 15)
- i = 15;
- if (i < 0)
- i = 0;
+ i = log_2_n_round_up(timeout * clk_khz) - 16;
+ i = clamp(i, 0, 15);
+
+ writel(i | (i << 4), base + DW_WDT_TORR);
- writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
return 0;
}
-static void designware_wdt_enable(void)
+static void designware_wdt_enable(void __iomem *base)
{
- writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
- (0x1 << DW_WDT_CR_EN_OFFSET)),
- (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
+ BIT(DW_WDT_CR_EN_OFFSET),
+ base + DW_WDT_CR);
}
-static unsigned int designware_wdt_is_enabled(void)
+static unsigned int designware_wdt_is_enabled(void __iomem *base)
{
- unsigned long val;
- val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
- return val & 0x1;
+ return readl(base + DW_WDT_CR) & BIT(0);
}
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
+static void designware_wdt_reset_common(void __iomem *base)
{
- if (designware_wdt_is_enabled())
+ if (designware_wdt_is_enabled(base))
/* restart the watchdog counter */
- writel(DW_WDT_CRR_RESTART_VAL,
- (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+ writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
+}
+
+#if !CONFIG_IS_ENABLED(WDT)
+void hw_watchdog_reset(void)
+{
+ designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
}
void hw_watchdog_init(void)
@@ -64,10 +70,80 @@ void hw_watchdog_init(void)
/* reset to disable the watchdog */
hw_watchdog_reset();
/* set timer in miliseconds */
- designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
+ designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
+
Re: [U-Boot] [PATCH v2 0/4] usb: host: dwc2: use driver model for PHY and CLOCK
Marek Vasut schrieb am Fr., 8. Nov. 2019, 16:46: > On 11/8/19 3:47 PM, Patrick Delaunay wrote: > > > > In this serie I update the DWC2 host driver to use the device tree > > information and the associated PHY and CLOCK drivers when they are > > available. > > I'm kinda on the fence whether to add it into current release or not. > The patches look generally OK to me. > > Ley, Simon, can you check this on SoCFPGA ? > Gmm, so can try, but I don't have a working setup with USB peripherals attached... I do have USB on the socrates, but currently no cable to connect anything... I could test it to see if I can get the same result saying no attached devices are found, that would mean probing still works correctly... Regards, Simon Bin, can you give it a once-over ? > > If this looks OK to you, I will add it. > > [...] > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: cadence_qspi: support DM_CLK
Vignesh Raghavendra schrieb am So., 10. Nov. 2019, 12:41:
> Hi Simon,
>
> On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
> > From: Simon Goldschmidt
> >
> > Support loading clk speed via DM instead of requiring ad-hoc code.
> >
> > Signed-off-by: Simon Goldschmidt
> > Signed-off-by: Simon Goldschmidt
> > ---
> [...]
> > @@ -22,12 +23,29 @@ static int cadence_spi_write_speed(struct udevice
> *bus, uint hz)
> > {
> > struct cadence_spi_platdata *plat = bus->platdata;
> > struct cadence_spi_priv *priv = dev_get_priv(bus);
> > + unsigned int ref_clk_hz;
> > + struct clk clk;
> > + int ret;
> > +
> > + ret = clk_get_by_index(bus, 0, &clk);
> > + if (ret) {
> > +#ifdef CONFIG_CQSPI_REF_CLK
> > + ref_clk_hz = CONFIG_CQSPI_REF_CLK;
> > +#else
> > + return ret;
> > +#endif
> > + } else {
> > + ref_clk_hz = clk_get_rate(&clk);
> > + clk_free(&clk);
> > + if (IS_ERR_VALUE(ref_clk_hz))
> > + return ref_clk_hz;
> > + }
> >
>
> Can this be moved to probe function instead? cadence_spi_write_speed()
> is called multiple times from spi_calibration() and doing
> clk_get_by_index() and clk_get_rate() each time seems to be additional
> overhead.
>
Sure, that would indeed be better.
Regards,
Simon
> Regards
> Vignesh
>
>
> > cadence_qspi_apb_config_baudrate_div(priv->regbase,
> > - CONFIG_CQSPI_REF_CLK, hz);
> > + ref_clk_hz, hz);
> >
> > /* Reconfigure delay timing if speed is changed. */
> > - cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
> > + cadence_qspi_apb_delay(priv->regbase, ref_clk_hz, hz,
> > plat->tshsl_ns, plat->tsd2d_ns,
> > plat->tchsh_ns, plat->tslch_ns);
> >
> >
>
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Re: [U-Boot] [PATCH] env: Access Environment in SPI flashes before relocation
Heiko Schocher schrieb am Sa., 9. Nov. 2019, 05:02:
> Enable the new Kconfig option ENV_SPI_EARLY if you want
> to use Environment in SPI flash before relocation.
> Call env_init() and than you can use env_get_f() for
> accessing Environment variables.
>
> Signed-off-by: Heiko Schocher
>
> ---
> travis build:
> https://travis-ci.org/hsdenx/u-boot-test/builds/609101712
>
> env/Kconfig | 8
> env/sf.c| 109
> 2 files changed, 117 insertions(+)
>
> diff --git a/env/Kconfig b/env/Kconfig
> index bc03816bc8..f2e1e1ba87 100644
> --- a/env/Kconfig
> +++ b/env/Kconfig
> @@ -370,6 +370,14 @@ config ENV_SPI_MODE
> Value of the SPI work mode for environment.
> See include/spi.h for value.
>
> +config ENV_SPI_EARLY
> + bool "Access Environment in SPI flashes before relocation"
> + depends on ENV_IS_IN_SPI_FLASH
> + help
> + Enable this if you want to use Environment in SPI flash
> + before relocation. Call env_init() and than you can use
> + env_get_f() for accessing Environment variables.
> +
> config ENV_IS_IN_UBI
> bool "Environment in a UBI volume"
> depends on !CHAIN_OF_TRUST
> diff --git a/env/sf.c b/env/sf.c
> index 590d0cedd8..c4dd7dc611 100644
> --- a/env/sf.c
> +++ b/env/sf.c
> @@ -308,6 +308,113 @@ static int env_sf_init(void)
> }
> #endif
>
> +#if defined(CONFIG_ENV_SPI_EARLY)
> +static int env_sf_init_early(void)
> +{
> + int ret;
> + int read1_fail;
> + int crc1_ok;
> +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
> + int crc2_ok;
> + int read2_fail;
> +#endif
> +
> + /*
> +* if malloc is not ready yet, we cannot use
> +* this part yet.
> +*/
> + if (!gd->malloc_limit)
> + return -ENOENT;
> +
> + env_t *tmp_env2 = NULL;
> + env_t *tmp_env1;
> +
> + tmp_env1 = (env_t *)memalign(ARCH_DMA_MINALIGN,
> + CONFIG_ENV_SIZE);
> +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
> + tmp_env2 = (env_t *)memalign(ARCH_DMA_MINALIGN,
> + CONFIG_ENV_SIZE);
> +#endif
> + if (!tmp_env1 || !tmp_env2)
> + goto out;
> +
> + ret = setup_flash_device();
> + if (ret)
> + goto out;
> +
> + read1_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET,
> + CONFIG_ENV_SIZE, tmp_env1);
> + crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) ==
> + tmp_env1->crc;
> +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
> + read2_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET_REDUND,
> + CONFIG_ENV_SIZE, tmp_env2);
> + crc2_ok = crc32(0, tmp_env2->data, ENV_SIZE) ==
> + tmp_env2->crc;
> + if (read1_fail && read2_fail) {
> + goto err_read;
> + } else if (!read1_fail && read2_fail) {
> + if (!crc1_ok)
> + goto err_read;
> + gd->env_valid = ENV_VALID;
> + } else if (read1_fail && !read2_fail) {
> + if (!crc2_ok)
> + goto err_read;
> + gd->env_valid = ENV_REDUND;
> + } else {
> + /* both environments read */
> + if (!crc1_ok && !crc2_ok) {
> + goto err_read;
> + } else if (crc1_ok && !crc2_ok) {
> + gd->env_valid = ENV_VALID;
> + } else if (!crc1_ok && crc2_ok) {
> + gd->env_valid = ENV_REDUND;
> + } else {
> + /* both ok - check serial */
> + if (tmp_env1->flags == 255 && tmp_env2->flags == 0)
> + gd->env_valid = ENV_REDUND;
> + else if (tmp_env2->flags == 255 && tmp_env1->flags
> == 0)
> + gd->env_valid = ENV_VALID;
> + else if (tmp_env1->flags > tmp_env2->flags)
> + gd->env_valid = ENV_VALID;
> + else if (tmp_env2->flags > tmp_env1->flags)
> + gd->env_valid = ENV_REDUND;
> + else /* flags are equal - almost impossible */
> + gd->env_valid = ENV_VALID;
> + }
> + }
> + if (gd->env_valid == ENV_VALID)
> + gd->env_addr = (unsigned long)&tmp_env1->data;
> + else
> + gd->env_addr = (unsigned long)&tmp_env2->data;
> +
> +#else
> + if (read1_fail)
> + goto err_read;
> +
> + /* check crc */
> + if (!crc1_ok)
> + goto err_read;
> +
> + /* if valid -> this is our env */
> + gd->env_valid = ENV_VALID;
> + gd->env_addr = tmp_env1;
> +#endif
> +
> + return 0;
> +err_read:
> + spi_flash_free(env_flash);
> + env_flash = NULL
Re: [U-Boot] [PATCH v2 0/4] usb: host: dwc2: use driver model for PHY and CLOCK
On Sat, Nov 9, 2019 at 4:46 PM Patrick Delaunay wrote: > > Hi Marek, > > My ci travis build is failing after the last updates (raspberry pi). I am > testing a update with sub for clk disable bulk function: > > https://github.com/patrickdelaunay/u-boot/commit/1d053dd96e6623d02b84654398655a5563ccfdcb > > Now buikd is ok: > https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 > > I will push it after the Week end (tuesday). With that additional change, it seems to build and work for me (same error message saying USB "Port not available" than without this patch). Regards, Simon > > Sorry. > > Patrick. > > > > Le ven. 8 nov. 2019 à 16:55, Simon Goldschmidt > a écrit : >> >> Marek Vasut schrieb am Fr., 8. Nov. 2019, 16:46: >> >> > On 11/8/19 3:47 PM, Patrick Delaunay wrote: >> > > >> > > In this serie I update the DWC2 host driver to use the device tree >> > > information and the associated PHY and CLOCK drivers when they are >> > > available. >> > >> > I'm kinda on the fence whether to add it into current release or not. >> > The patches look generally OK to me. >> > >> > Ley, Simon, can you check this on SoCFPGA ? >> > >> >> Gmm, so can try, but I don't have a working setup with USB peripherals >> attached... I do have USB on the socrates, but currently no cable to >> connect anything... >> >> I could test it to see if I can get the same result saying no attached >> devices are found, that would mean probing still works correctly... >> >> Regards, >> Simon >> >> Bin, can you give it a once-over ? >> > >> > If this looks OK to you, I will add it. >> > >> > [...] >> > >> ___ >> U-Boot mailing list >> U-Boot@lists.denx.de >> https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: cadence_qspi: support DM_CLK
Vignesh Raghavendra schrieb am Mo., 11. Nov. 2019, 05:22:
>
>
> On 10/11/19 5:11 PM, Vignesh Raghavendra wrote:
> > Hi Simon,
> >
> > On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
> >> From: Simon Goldschmidt
> >>
> >> Support loading clk speed via DM instead of requiring ad-hoc code.
> >>
> >> Signed-off-by: Simon Goldschmidt
> >> Signed-off-by: Simon Goldschmidt
> >> ---
> > [...]
> >> @@ -22,12 +23,29 @@ static int cadence_spi_write_speed(struct udevice
> *bus, uint hz)
> >> {
> >> struct cadence_spi_platdata *plat = bus->platdata;
> >> struct cadence_spi_priv *priv = dev_get_priv(bus);
> >> +unsigned int ref_clk_hz;
> >> +struct clk clk;
> >> +int ret;
> >> +
> >> +ret = clk_get_by_index(bus, 0, &clk);
> >> +if (ret) {
> >> +#ifdef CONFIG_CQSPI_REF_CLK
>
> We also could get rid of CONFIG_CQSPI_REF_CLK altogether. Instead pass
> frequency from DT or platdata using "clock-frequency" property like
> serial drivers do, assuming all platforms now use DT or platdata (all TI
> platforms using this driver support DT).
> But that can be done in a separate patch series...
>
My next step for socfpga is to provide a DM_CLK driver, so that would
remove the need for this define altogether (for that platform).
Regards,
Simon
>
> >> +ref_clk_hz = CONFIG_CQSPI_REF_CLK;
> >> +#else
> >> +return ret;
> >> +#endif
> >> +} else {
> >> +ref_clk_hz = clk_get_rate(&clk);
> >> +clk_free(&clk);
> >> +if (IS_ERR_VALUE(ref_clk_hz))
> >> +return ref_clk_hz;
> >> +}
> >>
> [...]
>
> --
> Regards
> Vignesh
>
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Re: [U-Boot] [PATCH] env: Access Environment in SPI flashes before relocation
On Mon, Nov 11, 2019 at 7:15 AM Heiko Schocher wrote:
>
> Hello Simon,
>
> Am 10.11.2019 um 15:51 schrieb Simon Goldschmidt:
> >
> >
> > Heiko Schocher mailto:h...@denx.de>> schrieb am Sa., 9. Nov.
> > 2019, 05:02:
> >
> > Enable the new Kconfig option ENV_SPI_EARLY if you want
> > to use Environment in SPI flash before relocation.
> > Call env_init() and than you can use env_get_f() for
> > accessing Environment variables.
> >
> > Signed-off-by: Heiko Schocher mailto:h...@denx.de>>
> >
> > ---
> > travis build:
> > https://travis-ci.org/hsdenx/u-boot-test/builds/609101712
> >
> > env/Kconfig | 8
> > env/sf.c| 109
> > 2 files changed, 117 insertions(+)
> >
> > diff --git a/env/Kconfig b/env/Kconfig
> > index bc03816bc8..f2e1e1ba87 100644
> > --- a/env/Kconfig
> > +++ b/env/Kconfig
> > @@ -370,6 +370,14 @@ config ENV_SPI_MODE
> >Value of the SPI work mode for environment.
> >See include/spi.h for value.
> >
> > +config ENV_SPI_EARLY
> > + bool "Access Environment in SPI flashes before relocation"
> > + depends on ENV_IS_IN_SPI_FLASH
> > + help
> > + Enable this if you want to use Environment in SPI flash
> > + before relocation. Call env_init() and than you can use
> > + env_get_f() for accessing Environment variables.
> > +
> > config ENV_IS_IN_UBI
> > bool "Environment in a UBI volume"
> > depends on !CHAIN_OF_TRUST
> > diff --git a/env/sf.c b/env/sf.c
> > index 590d0cedd8..c4dd7dc611 100644
> > --- a/env/sf.c
> > +++ b/env/sf.c
> > @@ -308,6 +308,113 @@ static int env_sf_init(void)
> [...]
> >
> >
> > Sorry I haven't looked at the file in detail yet, but doesn't this
> > duplicate quite a lot of env
> > decision code?
>
> Yes, correct, I take a look to remove this duplication ...
>
> Hmm... just detected when booting with invalid environment in spi nor flash,
> that the board selects correct the default environment (before relocation)
> but I see in U-Boot commandshell:
>
> => printenv
>
> Environment size: 1/12283 bytes
> =>
>
> and even worser, saveenv never calls the save function for the spi nor...
> it seems, the reason is:
>
> diff --git a/env/env.c b/env/env.c
> index 9237bb9c74..6faef1136d 100644
> --- a/env/env.c
> +++ b/env/env.c
> @@ -189,7 +189,7 @@ int env_load(void)
> if (!drv->load)
> continue;
>
> - if (!env_has_inited(drv->location))
> + if (env_has_inited(drv->location))
> continue;
>
> printf("Loading Environment from %s... ", drv->name);
>
> With this change, all is fine again. This seems a bug to me ... but wonder
> why this does not pop up on other boards ... what do you think?
I don't think I really get what your problem is, yet. But the code above looks
correct: only call load/save/erase on env drivers that have successfully been
initialized via env_init.
Regards,
Simon
>
> bye,
> Heiko
>
> >
> > Regards,
> > Simon
> >
> > +
> > U_BOOT_ENV_LOCATION(sf) = {
> > .location = ENVL_SPI_FLASH,
> > ENV_NAME("SPI Flash")
> > @@ -317,5 +424,7 @@ U_BOOT_ENV_LOCATION(sf) = {
> > #endif
> > #if defined(INITENV) && defined(CONFIG_ENV_ADDR)
> > .init = env_sf_init,
> > +#elif defined(CONFIG_ENV_SPI_EARLY)
> > + .init = env_sf_init_early,
> > #endif
> > };
> > --
> > 2.21.0
> >
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
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[U-Boot] [PATCH] spl: fix stack usage check if gd is not initialized
Most platforms do not set up gd->start_addr_sp in SPL. Since this is
required for CONFIG_SPL_SYS_REPORT_SACK_F_USAGE to work correctly, set
up gd->start_addr_sp in SPL to the value passed to
board_init_f_init_reserve if it is not set yet.
Fixes: d8c0332031 ("spl: implement stack usage check")
Signed-off-by: Simon Goldschmidt
---
common/init/board_init.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/common/init/board_init.c b/common/init/board_init.c
index e52106966d..3bc7994586 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -18,6 +18,19 @@ __weak void arch_setup_gd(struct global_data *gd_ptr)
}
#endif /* !CONFIG_X86 && !CONFIG_ARM */
+/**
+ * This function is called from board_init_f_init_reserve to set up
+ * gd->start_addr_sp for stack protection if not already set otherwise
+ */
+__weak void board_init_f_init_stack_protection_addr(ulong base)
+{
+#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)
+ /* set up stack pointer for stack usage if not set yet */
+ if (!gd->start_addr_sp)
+ gd->start_addr_sp = base;
+#endif
+}
+
/**
* This function is called after the position of the initial stack is
* determined in gd->start_addr_sp. Boards can override it to set up
@@ -129,6 +142,10 @@ void board_init_f_init_reserve(ulong base)
#if !defined(CONFIG_ARM)
arch_setup_gd(gd_ptr);
#endif
+
+ if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
+ board_init_f_init_stack_protection_addr(base);
+
/* next alloc will be higher by one GD plus 16-byte alignment */
base += roundup(sizeof(struct global_data), 16);
--
2.20.1
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[U-Boot] [PATCH v3] spi: cadence_qspi: support DM_CLK
Support loading clk speed via DM instead of requiring ad-hoc code.
Signed-off-by: Simon Goldschmidt
---
Changes in v3:
- load ref_clk_hz only once in cadence_spi_ofdata_to_platdata instead
of loading it every time in cadence_spi_write_speed
Changes in v2:
- check return value of clk_get_rate for error
drivers/spi/cadence_qspi.c | 21 +++--
drivers/spi/cadence_qspi.h | 1 +
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index e2e54cd277..8fd23a7702 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct udevice *bus,
uint hz)
struct cadence_spi_priv *priv = dev_get_priv(bus);
cadence_qspi_apb_config_baudrate_div(priv->regbase,
-CONFIG_CQSPI_REF_CLK, hz);
+plat->ref_clk_hz, hz);
/* Reconfigure delay timing if speed is changed. */
- cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
+ cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
plat->tshsl_ns, plat->tsd2d_ns,
plat->tchsh_ns, plat->tslch_ns);
@@ -294,6 +295,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
*bus)
{
struct cadence_spi_platdata *plat = bus->platdata;
ofnode subnode;
+ struct clk clk;
+ int ret;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
@@ -325,6 +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
*bus)
plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret) {
+#ifdef CONFIG_CQSPI_REF_CLK
+ plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#else
+ return ret;
+#endif
+ } else {
+ plat->ref_clk_hz = clk_get_rate(&clk);
+ clk_free(&clk);
+ if (IS_ERR_VALUE(plat->ref_clk_hz))
+ return plat->ref_clk_hz;
+ }
+
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
plat->page_size);
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 20cceca239..99dee75bbd 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -16,6 +16,7 @@
#define CQSPI_READ_CAPTURE_MAX_DELAY 16
struct cadence_spi_platdata {
+ unsigned intref_clk_hz;
unsigned intmax_hz;
void*regbase;
void*ahbbase;
--
2.20.1
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Re: [U-Boot] [PATCH v3] spi: cadence_qspi: support DM_CLK
On Tue, Nov 12, 2019 at 9:59 AM Tan, Ley Foon wrote:
>
>
>
> > -Original Message-
> > From: Simon Goldschmidt
> > Sent: Tuesday, November 12, 2019 5:43 AM
> > To: Jagan Teki
> > Cc: Marek Vasut ; Tan, Ley Foon
> > ; Vignesh Raghavendra ; Simon
> > Goldschmidt ; u-boot@lists.denx.de
> > Subject: [PATCH v3] spi: cadence_qspi: support DM_CLK
> >
> > Support loading clk speed via DM instead of requiring ad-hoc code.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > Changes in v3:
> > - load ref_clk_hz only once in cadence_spi_ofdata_to_platdata instead
> > of loading it every time in cadence_spi_write_speed
> >
> > Changes in v2:
> > - check return value of clk_get_rate for error
> >
> > drivers/spi/cadence_qspi.c | 21 +++--
> > drivers/spi/cadence_qspi.h | 1 +
> > 2 files changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index
> > e2e54cd277..8fd23a7702 100644
> > --- a/drivers/spi/cadence_qspi.c
> > +++ b/drivers/spi/cadence_qspi.c
> > @@ -5,6 +5,7 @@
> > */
> >
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct udevice
> > *bus, uint hz)
> > struct cadence_spi_priv *priv = dev_get_priv(bus);
> >
> > cadence_qspi_apb_config_baudrate_div(priv->regbase,
> > - CONFIG_CQSPI_REF_CLK, hz);
> > + plat->ref_clk_hz, hz);
> >
> > /* Reconfigure delay timing if speed is changed. */
> > - cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
> > + cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
> > plat->tshsl_ns, plat->tsd2d_ns,
> > plat->tchsh_ns, plat->tslch_ns);
> >
> > @@ -294,6 +295,8 @@ static int cadence_spi_ofdata_to_platdata(struct
> > udevice *bus) {
> > struct cadence_spi_platdata *plat = bus->platdata;
> > ofnode subnode;
> > + struct clk clk;
> > + int ret;
> >
> > plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
> > plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); @@ -325,6
> > +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
> > plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns",
> > 20);
> > plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns",
> > 20);
> >
> Did you compile this with platform without clock DM before? Eg: Stratix10.
> You need add check for CONFIG_CLK enabled to call clock DM functions here.
Unless I'm mistaken, those functions are prototyped when CLK is not enabled:
https://elixir.bootlin.com/u-boot/latest/source/include/clk.h#L172
That should be enough, no? And yes, I did test this on the current state of
gen5 which does not have a CLK driver, yet.
Regards,
Simon
>
> Regards
> Ley Foon
>
> > + ret = clk_get_by_index(bus, 0, &clk);
> > + if (ret) {
> > +#ifdef CONFIG_CQSPI_REF_CLK
> > + plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; #else
> > + return ret;
> > +#endif
> > + } else {
> > + plat->ref_clk_hz = clk_get_rate(&clk);
> > + clk_free(&clk);
> > + if (IS_ERR_VALUE(plat->ref_clk_hz))
> > + return plat->ref_clk_hz;
> > + }
> > +
> > debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-
> > size=%d\n",
> > __func__, plat->regbase, plat->ahbbase, plat->max_hz,
> > plat->page_size);
> > diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index
> > 20cceca239..99dee75bbd 100644
> > --- a/drivers/spi/cadence_qspi.h
> > +++ b/drivers/spi/cadence_qspi.h
> > @@ -16,6 +16,7 @@
> > #define CQSPI_READ_CAPTURE_MAX_DELAY 16
> >
> > struct cadence_spi_platdata {
> > + unsigned intref_clk_hz;
> > unsigned intmax_hz;
> > void*regbase;
> > void*ahbbase;
> > --
> > 2.20.1
>
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Re: [U-Boot] [PATCH v3] spi: cadence_qspi: support DM_CLK
On Tue, Nov 12, 2019 at 10:22 AM Vignesh Raghavendra wrote:
>
>
>
> On 12/11/19 2:44 PM, Simon Goldschmidt wrote:
> > On Tue, Nov 12, 2019 at 9:59 AM Tan, Ley Foon
> > wrote:
> >>
> >>
> >>
> >>> -Original Message-
> >>> From: Simon Goldschmidt
> >>> Sent: Tuesday, November 12, 2019 5:43 AM
> >>> To: Jagan Teki
> >>> Cc: Marek Vasut ; Tan, Ley Foon
> >>> ; Vignesh Raghavendra ; Simon
> >>> Goldschmidt ; u-boot@lists.denx.de
> >>> Subject: [PATCH v3] spi: cadence_qspi: support DM_CLK
> >>>
> >>> Support loading clk speed via DM instead of requiring ad-hoc code.
> >>>
> >>> Signed-off-by: Simon Goldschmidt
> >>> ---
> >>>
> >>> Changes in v3:
> >>> - load ref_clk_hz only once in cadence_spi_ofdata_to_platdata instead
> >>> of loading it every time in cadence_spi_write_speed
> >>>
> >>> Changes in v2:
> >>> - check return value of clk_get_rate for error
> >>>
> >>> drivers/spi/cadence_qspi.c | 21 +++--
> >>> drivers/spi/cadence_qspi.h | 1 +
> >>> 2 files changed, 20 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index
> >>> e2e54cd277..8fd23a7702 100644
> >>> --- a/drivers/spi/cadence_qspi.c
> >>> +++ b/drivers/spi/cadence_qspi.c
> >>> @@ -5,6 +5,7 @@
> >>> */
> >>>
> >>> #include
> >>> +#include
> >>> #include
> >>> #include
> >>> #include
> >>> @@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct udevice
> >>> *bus, uint hz)
> >>> struct cadence_spi_priv *priv = dev_get_priv(bus);
> >>>
> >>> cadence_qspi_apb_config_baudrate_div(priv->regbase,
> >>> - CONFIG_CQSPI_REF_CLK, hz);
> >>> + plat->ref_clk_hz, hz);
> >>>
> >>> /* Reconfigure delay timing if speed is changed. */
> >>> - cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
> >>> + cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
> >>> plat->tshsl_ns, plat->tsd2d_ns,
> >>> plat->tchsh_ns, plat->tslch_ns);
> >>>
> >>> @@ -294,6 +295,8 @@ static int cadence_spi_ofdata_to_platdata(struct
> >>> udevice *bus) {
> >>> struct cadence_spi_platdata *plat = bus->platdata;
> >>> ofnode subnode;
> >>> + struct clk clk;
> >>> + int ret;
> >>>
> >>> plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
> >>> plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); @@ -325,6
> >>> +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
> >>> plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns",
> >>> 20);
> >>> plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns",
> >>> 20);
> >>>
> >> Did you compile this with platform without clock DM before? Eg: Stratix10.
> >> You need add check for CONFIG_CLK enabled to call clock DM functions here.
> >
> > Unless I'm mistaken, those functions are prototyped when CLK is not enabled:
> >
> > https://elixir.bootlin.com/u-boot/latest/source/include/clk.h#L172
> >
>
> But, unfortunately, such stub does not exists for clk_get_rate().
> So on platforms w/o CONFIG_CLK set:
>
> arm-linux-gnueabihf-ld.bfd: drivers/spi/built-in.o: in function
> `cadence_spi_probe':
> /home/a0132425/workspace/u-boot/drivers/spi/cadence_qspi.c:184: undefined
> reference to `clk_get_rate'
> Makefile:1647: recipe for target 'u-boot' failed
> make: *** [u-boot] Error 1
So why did it compile for me? Probably because the linker knows it doesn't
need 'clk_get_rate' since this branch will never be executed?
Regards,
Simon
>
> Regards
> Vignesh
>
> > That should be enough, no? And yes, I did test this on the current state of
> > gen5 which does not have a CLK driver, yet.
> >
> > Regards,
> > Simon
> >
> >>
> >> Regards
> >> Ley Foon
> >>
> >>> + ret = clk_get
Re: [U-Boot] [PATCH v3 1/5] dm: clk: add stub for clk_disable_bulk when CONFIG_CLK is desactivated
Patrick Delaunay schrieb am Di., 12. Nov. 2019,
10:42:
> Add stub for clk_disable_bulk() when CONFIG_CLK is desactivated.
>
> That avoid compilation issue (undefined reference to
> `clk_disable_bulk') for code:
>
> clk_disable_bulk(&priv->clks);
> clk_release_bulk(&priv->clks);
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v3:
> - Add stub for clk_disable_bulk
>
> Changes in v2: None
>
> include/clk.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/clk.h b/include/clk.h
> index a5ee53d94a..6f0b0fe4bc 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -379,7 +379,11 @@ int clk_disable(struct clk *clk);
> * by clk_get_bulk().
> * @return zero on success, or -ve error code.
> */
> + #if CONFIG_IS_ENABLED(CLK)
> int clk_disable_bulk(struct clk_bulk *bulk);
> +#else
> +inline int clk_disable_bulk(struct clk_bulk *bulk) { return 0; }
> +#endif
>
Doing this inline at this place seems quite different than what is done for
the other functions?
Regards,
Simon
> /**
> * clk_is_match - check if two clk's point to the same hardware clock
> --
> 2.17.1
>
>
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Re: [U-Boot] [PATCH v3] spi: cadence_qspi: support DM_CLK
On Tue, Nov 12, 2019 at 10:30 AM Tan, Ley Foon wrote:
>
>
>
> > -Original Message-
> > From: Simon Goldschmidt
> > Sent: Tuesday, November 12, 2019 5:27 PM
> > To: Vignesh Raghavendra
> > Cc: Tan, Ley Foon ; Jagan Teki
> > ; Marek Vasut ; u-
> > b...@lists.denx.de
> > Subject: Re: [PATCH v3] spi: cadence_qspi: support DM_CLK
> >
> > On Tue, Nov 12, 2019 at 10:22 AM Vignesh Raghavendra
> > wrote:
> > >
> > >
> > >
> > > On 12/11/19 2:44 PM, Simon Goldschmidt wrote:
> > > > On Tue, Nov 12, 2019 at 9:59 AM Tan, Ley Foon
> > wrote:
> > > >>
> > > >>
> > > >>
> > > >>> -Original Message-
> > > >>> From: Simon Goldschmidt
> > > >>> Sent: Tuesday, November 12, 2019 5:43 AM
> > > >>> To: Jagan Teki
> > > >>> Cc: Marek Vasut ; Tan, Ley Foon
> > > >>> ; Vignesh Raghavendra ;
> > > >>> Simon Goldschmidt ;
> > > >>> u-boot@lists.denx.de
> > > >>> Subject: [PATCH v3] spi: cadence_qspi: support DM_CLK
> > > >>>
> > > >>> Support loading clk speed via DM instead of requiring ad-hoc code.
> > > >>>
> > > >>> Signed-off-by: Simon Goldschmidt
> > > >>> ---
> > > >>>
> > > >>> Changes in v3:
> > > >>> - load ref_clk_hz only once in cadence_spi_ofdata_to_platdata instead
> > > >>> of loading it every time in cadence_spi_write_speed
> > > >>>
> > > >>> Changes in v2:
> > > >>> - check return value of clk_get_rate for error
> > > >>>
> > > >>> drivers/spi/cadence_qspi.c | 21 +++--
> > > >>> drivers/spi/cadence_qspi.h | 1 +
> > > >>> 2 files changed, 20 insertions(+), 2 deletions(-)
> > > >>>
> > > >>> diff --git a/drivers/spi/cadence_qspi.c
> > > >>> b/drivers/spi/cadence_qspi.c index
> > > >>> e2e54cd277..8fd23a7702 100644
> > > >>> --- a/drivers/spi/cadence_qspi.c
> > > >>> +++ b/drivers/spi/cadence_qspi.c
> > > >>> @@ -5,6 +5,7 @@
> > > >>> */
> > > >>>
> > > >>> #include
> > > >>> +#include
> > > >>> #include
> > > >>> #include
> > > >>> #include
> > > >>> @@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct
> > > >>> udevice *bus, uint hz)
> > > >>> struct cadence_spi_priv *priv = dev_get_priv(bus);
> > > >>>
> > > >>> cadence_qspi_apb_config_baudrate_div(priv->regbase,
> > > >>> - CONFIG_CQSPI_REF_CLK, hz);
> > > >>> + plat->ref_clk_hz, hz);
> > > >>>
> > > >>> /* Reconfigure delay timing if speed is changed. */
> > > >>> - cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK,
> > hz,
> > > >>> + cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
> > > >>> plat->tshsl_ns, plat->tsd2d_ns,
> > > >>> plat->tchsh_ns, plat->tslch_ns);
> > > >>>
> > > >>> @@ -294,6 +295,8 @@ static int
> > > >>> cadence_spi_ofdata_to_platdata(struct
> > > >>> udevice *bus) {
> > > >>> struct cadence_spi_platdata *plat = bus->platdata;
> > > >>> ofnode subnode;
> > > >>> + struct clk clk;
> > > >>> + int ret;
> > > >>>
> > > >>> plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
> > > >>> plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); @@
> > > >>> -325,6
> > > >>> +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct
> > > >>> +udevice *bus)
> > > >>> plat->tchsh_ns = ofnode_read_u32_default(subnode,
> > > >>> "cdns,tchsh-ns", 20);
> > > >>> plat->tslch_ns = ofnode_read_u32_default(subnode,
> > > >>> "cdns,tslch-ns", 20);
> > > >>>
> > &g
Re: [U-Boot] [PATCH v3] spi: cadence_qspi: support DM_CLK
On Tue, Nov 12, 2019 at 12:40 PM Vignesh Raghavendra wrote:
>
>
>
> On 12/11/19 4:57 PM, Simon Goldschmidt wrote:
> > On Tue, Nov 12, 2019 at 10:30 AM Tan, Ley Foon
> > wrote:
> >>
> [...]
> >>>> But, unfortunately, such stub does not exists for clk_get_rate().
> >>>> So on platforms w/o CONFIG_CLK set:
> >>>>
> >>>> arm-linux-gnueabihf-ld.bfd: drivers/spi/built-in.o: in function
> >>> `cadence_spi_probe':
> >>>> /home/a0132425/workspace/u-boot/drivers/spi/cadence_qspi.c:184:
> >>> undefined reference to `clk_get_rate'
> >>>> Makefile:1647: recipe for target 'u-boot' failed
> >>>> make: *** [u-boot] Error 1
> >>>
> >>> So why did it compile for me? Probably because the linker knows it doesn't
> >>> need 'clk_get_rate' since this branch will never be executed?
> >> Maybe you can try compile from clean build. Run "make mrproper" before
> >> compile.
> >
> > Of course I did that, and I just did it again. It *does* compile.
> >
> > Can anyone tell me a config/setup where it doesn't compile? Or does
> > this complain only come from reading the sources?
> >
>
> I see above error with k2g_evm_defconfig and compiler is:
Ok, just tested that config and it works for me :-(
>
> arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture
> 8.3-2019.03 (arm-rel-8.36)) 8.3.0
I'm using 6.3.0 from debian stretch, but have also tested my patch
with newest Ubuntu (which has a 9.x cross compiler).
So while I think that difference is disturbing, Maybe it's really best
to inline-define all clock functions as you mentioned to Patrick
in the other thread...
Regards,
Simon
>
> Regards
> Vignesh
>
>
> > Regards,
> > Simon
> >
> >>
> >> Regards
> >> Ley Foon
> >>>
> >>> Regards,
> >>> Simon
> >>>
> >>>>
> >>>> Regards
> >>>> Vignesh
> >>>>
> >>>>> That should be enough, no? And yes, I did test this on the current
> >>>>> state of
> >>>>> gen5 which does not have a CLK driver, yet.
> >>>>>
> >>>>> Regards,
> >>>>> Simon
> >>>>>
> >>>>>>
> >>>>>> Regards
> >>>>>> Ley Foon
> >>>>>>
> >>>>>>> + ret = clk_get_by_index(bus, 0, &clk);
> >>>>>>> + if (ret) {
> >>>>>>> +#ifdef CONFIG_CQSPI_REF_CLK
> >>>>>>> + plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; #else
> >>>>>>> + return ret;
> >>>>>>> +#endif
> >>>>>>> + } else {
> >>>>>>> + plat->ref_clk_hz = clk_get_rate(&clk);
> >>>>>>> + clk_free(&clk);
> >>>>>>> + if (IS_ERR_VALUE(plat->ref_clk_hz))
> >>>>>>> + return plat->ref_clk_hz;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-
> >>>>>>> size=%d\n",
> >>>>>>> __func__, plat->regbase, plat->ahbbase, plat->max_hz,
> >>>>>>> plat->page_size);
> >>>>>>> diff --git a/drivers/spi/cadence_qspi.h
> >>>>>>> b/drivers/spi/cadence_qspi.h index 20cceca239..99dee75bbd 100644
> >>>>>>> --- a/drivers/spi/cadence_qspi.h
> >>>>>>> +++ b/drivers/spi/cadence_qspi.h
> >>>>>>> @@ -16,6 +16,7 @@
> >>>>>>> #define CQSPI_READ_CAPTURE_MAX_DELAY 16
> >>>>>>>
> >>>>>>> struct cadence_spi_platdata {
> >>>>>>> + unsigned intref_clk_hz;
> >>>>>>> unsigned intmax_hz;
> >>>>>>> void*regbase;
> >>>>>>> void*ahbbase;
> >>>>>>> --
> >>>>>>> 2.20.1
> >>>>>>
>
> --
> Regards
> Vignesh
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[U-Boot] [PATCH 1/2] usb: composite: fix possible alignment issues
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting two functions to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off-by: Simon Goldschmidt
---
drivers/usb/gadget/composite.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 618a7d5016..cfc9512caa 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -12,8 +12,16 @@
#define USB_BUFSIZ 4096
+/* Helper type for accessing packed u16 pointers */
+typedef struct { __le16 val; } __packed __le16_packed;
+
static struct usb_composite_driver *composite;
+static inline void le16_add_cpu_packed(__le16_packed *var, u16 val)
+{
+ var->val = cpu_to_le16(le16_to_cpu(var->val) + val);
+}
+
/**
* usb_add_function() - add a function to a configuration
* @config: the configuration
@@ -480,20 +488,20 @@ done:
* the host side.
*/
-static void collect_langs(struct usb_gadget_strings **sp, __le16 *buf)
+static void collect_langs(struct usb_gadget_strings **sp, void *buf)
{
const struct usb_gadget_strings *s;
u16 language;
- __le16 *tmp;
+ __le16_packed *tmp;
while (*sp) {
s = *sp;
language = cpu_to_le16(s->language);
- for (tmp = buf; *tmp && tmp < &buf[126]; tmp++) {
- if (*tmp == language)
+ for (tmp = buf; tmp->val && tmp < &buf[126]; tmp++) {
+ if (tmp->val == language)
goto repeat;
}
- *tmp++ = language;
+ tmp->val = language;
repeat:
sp++;
}
@@ -705,7 +713,8 @@ static int bos_desc(struct usb_composite_dev *cdev)
*/
usb_ext = cdev->req->buf + le16_to_cpu(bos->wTotalLength);
bos->bNumDeviceCaps++;
- le16_add_cpu(&bos->wTotalLength, USB_DT_USB_EXT_CAP_SIZE);
+ le16_add_cpu_packed((__le16_packed *)&bos->wTotalLength,
+ USB_DT_USB_EXT_CAP_SIZE);
usb_ext->bLength = USB_DT_USB_EXT_CAP_SIZE;
usb_ext->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
usb_ext->bDevCapabilityType = USB_CAP_TYPE_EXT;
@@ -721,7 +730,8 @@ static int bos_desc(struct usb_composite_dev *cdev)
ss_cap = cdev->req->buf + le16_to_cpu(bos->wTotalLength);
bos->bNumDeviceCaps++;
- le16_add_cpu(&bos->wTotalLength, USB_DT_USB_SS_CAP_SIZE);
+ le16_add_cpu_packed((__le16_packed *)&bos->wTotalLength,
+ USB_DT_USB_SS_CAP_SIZE);
ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE;
ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE;
--
2.20.1
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[U-Boot] [PATCH 2/2] usb: dwc2: fix possible alignment issues
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting dwc2_fifo_read to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off-by: Simon Goldschmidt
---
drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 7eb632d3b1..dba221dad0 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -731,7 +731,7 @@ static int write_fifo_ep0(struct dwc2_ep *ep, struct
dwc2_request *req)
return 0;
}
-static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max)
+static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
{
invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
@@ -1285,7 +1285,7 @@ static void dwc2_ep0_setup(struct dwc2_udc *dev)
nuke(ep, -EPROTO);
/* read control req from fifo (8 bytes) */
- dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8);
+ dwc2_fifo_read(ep, usb_ctrl, 8);
debug_cond(DEBUG_SETUP != 0,
"%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
--
2.20.1
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Re: [U-Boot] [PATCH v6 2/4] arm: socfpga: Convert reset manager from struct to defines
Am 08.11.2019 um 03:38 schrieb Ley Foon Tan:
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Call to socfpga_get_rstmgr_addr() function, instead of access to global
variable directly.
- Update socfpga_get_base_addr() to return error code, instead of return 0.
v5:
- Change macro values with 0x** format.
v4:
- Update commit message about get base address from DT node.
v3:
- Remove "No functional change" in commit description.
v2:
- Get base address from DT
- Revert to use writel(), readl(), setbits_le32() and clrbits_le32().
- Add prefix to defines.
---
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
.../mach-socfpga/include/mach/reset_manager.h | 2 +
.../include/mach/reset_manager_arria10.h | 43
.../include/mach/reset_manager_gen5.h | 22 -
.../include/mach/reset_manager_s10.h | 33 ++---
arch/arm/mach-socfpga/misc.c | 41
arch/arm/mach-socfpga/misc_gen5.c | 7 ++-
arch/arm/mach-socfpga/reset_manager_arria10.c | 49 ++-
arch/arm/mach-socfpga/reset_manager_gen5.c| 28 +--
arch/arm/mach-socfpga/reset_manager_s10.c | 35 ++---
arch/arm/mach-socfpga/spl_a10.c | 7 ++-
arch/arm/mach-socfpga/spl_gen5.c | 14 +++---
arch/arm/mach-socfpga/spl_s10.c | 12 +++--
drivers/sysreset/sysreset_socfpga.c | 6 +--
14 files changed, 150 insertions(+), 150 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 27d0b6a370..7310fd4c3a 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
+void socfpga_get_managers_addr(void);
#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6ad037e325..96052d94b4 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -6,6 +6,8 @@
#ifndef _RESET_MANAGER_H_
#define _RESET_MANAGER_H_
+phys_addr_t socfpga_get_rstmgr_addr(void);
+
void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 6623ebee65..22e4eb33de 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
void socfpga_reset_deassert_osc1wd0(void);
int socfpga_bridges_reset(void);
-struct socfpga_reset_manager {
- u32 stat;
- u32 ramstat;
- u32 miscstat;
- u32 ctrl;
- u32 hdsken;
- u32 hdskreq;
- u32 hdskack;
- u32 counts;
- u32 mpumodrst;
- u32 per0modrst;
- u32 per1modrst;
- u32 brgmodrst;
- u32 sysmodrst;
- u32 coldmodrst;
- u32 nrstmodrst;
- u32 dbgmodrst;
- u32 mpuwarmmask;
- u32 per0warmmask;
- u32 per1warmmask;
- u32 brgwarmmask;
- u32 syswarmmask;
- u32 nrstwarmmask;
- u32 l3warmmask;
- u32 tststa;
- u32 tstscratch;
- u32 hdsktimeout;
- u32 hmcintr;
- u32 hmcintren;
- u32 hmcintrens;
- u32 hmcintrenr;
- u32 hmcgpout;
- u32 hmcgpin;
-};
+#define RSTMGR_A10_STATUS 0x00
+#define RSTMGR_A10_CTRL0x0c
+#define RSTMGR_A10_MPUMODRST 0x20
+#define RSTMGR_A10_PER0MODRST 0x24
+#define RSTMGR_A10_PER1MODRST 0x28
+#define RSTMGR_A10_BRGMODRST 0x2c
+#define RSTMGR_A10_SYSMODRST 0x30
+
+#define RSTMGR_CTRLRSTMGR_A10_CTRL
/*
* SocFPGA Arria10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index f4dcb14623..d108eac1e2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -11,19 +11,15 @@
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
-struct socfpga_reset_manager {
- u32 status;
- u32 ctrl;
-
Re: [U-Boot] [PATCH v6 3/4] arm: socfpga: Convert system manager from struct to defines
Am 08.11.2019 um 03:38 schrieb Ley Foon Tan:
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Call to socfpga_get_sysmgr_addr() function, instead of access to global
variable directly.
v5:
- Change macro value to 0x** format.
v4:
- Update commit message about get base address from DT node.
v3:
- Remove "No functional change" in commit description.
v2:
- Revert to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
arch/arm/mach-socfpga/clock_manager_s10.c | 4 +-
.../include/mach/system_manager.h | 2 +
.../include/mach/system_manager_arria10.h | 94 +++--
.../include/mach/system_manager_gen5.h| 123 +++-
.../include/mach/system_manager_s10.h | 184 +++---
arch/arm/mach-socfpga/mailbox_s10.c | 6 +-
arch/arm/mach-socfpga/misc.c | 10 +
arch/arm/mach-socfpga/misc_arria10.c | 11 +-
arch/arm/mach-socfpga/misc_gen5.c | 26 ++-
arch/arm/mach-socfpga/misc_s10.c | 9 +-
arch/arm/mach-socfpga/reset_manager_arria10.c | 24 +--
arch/arm/mach-socfpga/reset_manager_gen5.c| 9 +-
arch/arm/mach-socfpga/reset_manager_s10.c | 20 +-
arch/arm/mach-socfpga/scan_manager.c | 6 +-
arch/arm/mach-socfpga/spl_a10.c | 5 +-
arch/arm/mach-socfpga/spl_gen5.c | 12 +-
arch/arm/mach-socfpga/spl_s10.c | 12 +-
arch/arm/mach-socfpga/system_manager_gen5.c | 42 ++--
arch/arm/mach-socfpga/system_manager_s10.c| 42 ++--
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 13 +-
drivers/ddr/altera/sdram_gen5.c | 12 +-
drivers/ddr/altera/sdram_s10.c| 6 +-
drivers/fpga/socfpga_arria10.c| 7 +-
drivers/fpga/socfpga_gen5.c | 4 +-
drivers/mmc/socfpga_dw_mmc.c | 6 +-
25 files changed, 267 insertions(+), 422 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 3ba2a00c02..88817030ab 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -14,8 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/*
* function to write the bypass register which requires a poll of the
@@ -351,7 +349,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
unsigned int cm_get_qspi_controller_clk_hz(void)
{
- return readl(&sysmgr_regs->boot_scratch_cold0);
+ return readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD0);
}
unsigned int cm_get_spi_controller_clk_hz(void)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 7e76df74b7..7f05029a67 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -6,6 +6,8 @@
#ifndef _SYSTEM_MANAGER_H_
#define _SYSTEM_MANAGER_H_
+phys_addr_t socfpga_get_sysmgr_addr(void);
+
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
#include
#else
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
index 14052b957c..e4fc6d2e55 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -6,73 +6,33 @@
#ifndef _SYSTEM_MANAGER_ARRIA10_H_
#define _SYSTEM_MANAGER_ARRIA10_H_
-struct socfpga_system_manager {
- u32 siliconid1;
- u32 siliconid2;
- u32 wddbg;
- u32 bootinfo;
- u32 mpu_ctrl_l2_ecc;
- u32 _pad_0x14_0x1f[3];
- u32 dma;
- u32 dma_periph;
- u32 sdmmcgrp_ctrl;
- u32 sdmmc_l3master;
- u32 nand_bootstrap;
- u32 nand_l3master;
- u32 usb0_l3master;
- u32 usb1_l3master;
- u32 emac_global;
- u32 emac[3];
- u32 _pad_0x50_0x5f[4];
- u32 fpgaintf_en_global;
- u32 fpgaintf_en_0;
- u32 fpgaintf_en_1;
- u32 fpgaintf_en_2;
- u32 fpgaintf_en_3;
- u32 _pad_0x74_0x7f[3];
- u32 noc_addr_remap_value;
- u32 noc_addr_remap_set;
- u32 noc_addr_remap_clear;
- u32 _pad_0x8c_0x8f;
- u32 ecc_intmask_value;
- u32 ecc_intmask_set;
- u32 ecc_intmask_clr;
- u32 ecc_intstatus_serr;
- u32 ecc_intstatus_derr;
- u32 mpu_status_l2_ecc;
- u32 mpu_clear_l2
Re: [U-Boot] [PATCH v6 4/4] arm: socfpga: Convert clock manager from struct to defines
Am 08.11.2019 um 03:38 schrieb Ley Foon Tan:
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Call to socfpga_get_clkmgr_addr() function, instead of access to global
variable directly.
v5:
- Change macro value to 0x** format.
v4:
- Update commit message about get base address from DT node.
v3:
- Remove "No functional change" in commit description.
v2:
- Revert to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
arch/arm/mach-socfpga/clock_manager.c | 14 +-
arch/arm/mach-socfpga/clock_manager_arria10.c | 155 +++--
arch/arm/mach-socfpga/clock_manager_gen5.c| 211 +
arch/arm/mach-socfpga/clock_manager_s10.c | 213 ++
.../mach-socfpga/include/mach/clock_manager.h | 2 +
.../include/mach/clock_manager_arria10.h | 133 +--
.../include/mach/clock_manager_gen5.h | 112 -
.../include/mach/clock_manager_s10.h | 115 --
arch/arm/mach-socfpga/misc.c | 10 +
drivers/mmc/socfpga_dw_mmc.c | 11 +-
10 files changed, 501 insertions(+), 475 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c
b/arch/arm/mach-socfpga/clock_manager.c
index 9f3c643df8..dbb10ecb68 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,18 +10,17 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
void cm_wait_for_lock(u32 mask)
{
u32 inter_val;
u32 retry = 0;
do {
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
- inter_val = readl(&clock_manager_base->inter) & mask;
+ inter_val = readl(socfpga_get_clkmgr_addr() +
+ CLKMGR_INTER) & mask;
#else
- inter_val = readl(&clock_manager_base->stat) & mask;
+ inter_val = readl(socfpga_get_clkmgr_addr() +
+ CLKMGR_STAT) & mask;
#endif
/* Wait for stable lock */
if (inter_val == mask)
@@ -36,8 +35,9 @@ void cm_wait_for_lock(u32 mask)
/* function to poll in the fsm busy bit */
int cm_wait_for_fsm(void)
{
- return wait_for_bit_le32(&clock_manager_base->stat,
-CLKMGR_STAT_BUSY, false, 2, false);
+ return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
+CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 2,
+false);
}
int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 334a79fd9c..392f2eb915 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct
mainpll_cfg *main_cfg,
return 0;
}
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
/* calculate the intended main VCO frequency based on handoff */
static unsigned int cm_calc_handoff_main_vco_clk_hz
(struct mainpll_cfg *main_cfg)
@@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
writel((main_cfg->vco1_denom <<
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
- &clock_manager_base->main_pll.vco1);
+ socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
- main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
+ main_cfg->vco1_numer,
+ socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
}
@@ -579,14 +577,18 @@ static void cm_pll_ramp_periph(struct mainpll_cfg
*main_cfg,
/* execute the ramping here */
for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
- writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
- cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
- &clock_manager_base->per_pll.vco1);
+ writel((per_cfg->vco1_denom <<
+
Re: [U-Boot] [PATCH v6 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
Move Stratix10 and Agilex clock manager common code to new header file.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Move #include to top of header file.
v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
.../include/mach/clock_manager_s10.h | 16 +++--
.../include/mach/clock_manager_soc64.h| 23 +++
2 files changed, 26 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 13eb23569c..e710aa2f94 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -1,12 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2019 Intel Corporation
*
*/
#ifndef _CLOCK_MANAGER_S10_
#define _CLOCK_MANAGER_S10_
+#include
+
/* Clock speed accessors */
unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
@@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(void);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-const unsigned int cm_get_intosc_clk_hz(void);
-const unsigned int cm_get_fpga_clk_hz(void);
-
-#define CLKMGR_EOSC1_HZ2500
-#define CLKMGR_INTOSC_HZ 46000
-#define CLKMGR_FPGA_CLK_HZ 5000
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
struct cm_config {
/* main group */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
new file mode 100644
index 00..3b4bb62ca5
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_SOC64_
+#define _CLOCK_MANAGER_SOC64_
+
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ2500
+#define CLKMGR_INTOSC_HZ 46000
+#define CLKMGR_FPGA_CLK_HZ 5000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+#endif /* _CLOCK_MANAGER_SOC64_ */
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan: CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Remove unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. --- arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h index 3b4bb62ca5..71fbaa7667 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h @@ -13,9 +13,7 @@ const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); const unsigned int cm_get_intosc_clk_hz(void); const unsigned int cm_get_fpga_clk_hz(void); -#define CLKMGR_EOSC1_HZ 2500 -#define CLKMGR_INTOSC_HZ 46000 -#define CLKMGR_FPGA_CLK_HZ 5000 +#define CLKMGR_INTOSC_HZ 4 /* Clock configuration accessors */ const struct cm_config * const cm_get_default_config(void); ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 13/19] ddr: altera: Restructure Stratix 10 SDRAM driver
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Remove compatible "intel,sdr-ctl-agilex" from this patch.
v3:
- Change sdram_common.* to sdram_soc64.*
---
drivers/ddr/altera/Makefile | 2 +-
drivers/ddr/altera/sdram_s10.c| 296 +
drivers/ddr/altera/sdram_s10.h| 148 +
drivers/ddr/altera/sdram_soc64.c | 303 ++
.../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 70 ++--
5 files changed, 340 insertions(+), 479 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_soc64.c
copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%)
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 341ac0d73b..eb8da13b7d 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -9,5 +9,5 @@
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
endif
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index d7e6371ddb..fcab3ae3e4 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -14,28 +14,14 @@
#include "sdram_s10.h"
#include
#include
-#include
#include
#include
#include
-struct altera_sdram_priv {
- struct ram_info info;
- struct reset_ctl_bulk resets;
-};
-
-struct altera_sdram_platdata {
- void __iomem *hmc;
- void __iomem *ddr_sch;
- void __iomem *iomhc;
-};
-
DECLARE_GLOBAL_DATA_PTR;
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
-#define PGTABLE_OFF 0x4000
-
/* The followring are the supported configurations */
u32 ddr_config[] = {
/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -62,28 +48,6 @@ u32 ddr_config[] = {
DDR_CONFIG(1, 4, 10, 17),
};
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
- return readl(plat->iomhc + reg);
-}
-
-static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
- return readl(plat->hmc + reg);
-}
-
-static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
- u32 data, u32 reg)
-{
- return writel(data, plat->hmc + reg);
-}
-
-static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
- u32 reg)
-{
- return writel(data, plat->ddr_sch + reg);
-}
-
int match_ddr_conf(u32 ddr_conf)
{
int i;
@@ -95,193 +59,12 @@ int match_ddr_conf(u32 ddr_conf)
return 0;
}
-static int emif_clear(struct altera_sdram_platdata *plat)
-{
- hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
-
- return wait_for_bit_le32((const void *)(plat->hmc +
-RSTHANDSHAKESTAT),
-DDR_HMC_RSTHANDSHAKE_MASK,
-false, 1000, false);
-}
-
-static int emif_reset(struct altera_sdram_platdata *plat)
-{
- u32 c2s, s2c, ret;
-
- c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
- s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
-
- debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
- c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
- hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
- hmc_readl(plat, DRAMSTS));
-
- if (s2c && emif_clear(plat)) {
- printf("DDR: emif_clear() failed\n");
- return -1;
- }
-
- debug("DDR: Triggerring emif reset\n");
- hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
-
- /* if seq2core[3] = 0, we are good */
- ret = wait_for_bit_le32((const void *)(plat->hmc +
-RSTHANDSHAKESTAT),
-DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-false, 1000, false);
- if (ret) {
- printf("DDR: failed to get ack from EMIF\n");
- return ret;
- }
-
- ret = emif_clear(plat);
- if (ret) {
- printf("DDR: emif_clear() failed\n");
- return ret;
- }
-
- debug("DDR: %s triggered successly\n", __func__);
- return 0;
-}
-
-static int poll_hmc_clock_status(void)
-{
- return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_HMC_CLK),
-
Re: [U-Boot] [PATCH v6 17/19] arm: dts: agilex: Add base dtsi and devkit dts
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
Add device tree files for Agilex SoC platform.
Based on Linux Commit ID4b36daf9ada30.
Based on? Why is this not a copy of the Linux devicetree files? The
single difference should be in *-u-boot.dtsi. Being like this, I don't
know what good it is to add the Linux commit ID if the files are
obviously different... :-(
Regards,
Simon
Signed-off-by: Ley Foon Tan
---
v6:
- Use new macro names from agilex-clock.h.
v5:
- Add CCU DT node.
v4:
- Add u-boot,dm-pre-reloc to sysmgr node.
v3:
- Fixed bank 1 memory alias base address to 0x28000.
- Rename STRATIX10_*_CLK to SOCFPGA_SOC64_*_CLK.
- Include socfpga-soc64-clock.h
- Change to "intel,sdr-ctl-agilex" for SDRAM node.
v2:
- Add clock property to device node.
- Change memory size to 8GB
- Enable i2c1
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_agilex.dtsi | 500 ++
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 79 +++
arch/arm/dts/socfpga_agilex_socdk.dts | 138 +
4 files changed, 718 insertions(+)
create mode 100644 arch/arm/dts/socfpga_agilex.dtsi
create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47978e7685..d90ad835a4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -319,6 +319,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) +=\
+ socfpga_agilex_socdk.dtb\
socfpga_arria5_socdk.dtb\
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
new file mode 100644
index 00..9e578a0108
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+/dts-v1/;
+#include
+#include
+#include
+
+/ {
+ compatible = "intel,socfpga-agilex";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 120 8>,
+<0 121 8>,
+<0 122 8>,
+<0 123 8>;
+ interrupt-affinity = <&cpu0>,
+<&cpu1>,
+<&cpu2>,
+<&cpu3>;
+ interrupt-parent = <&intc>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ intc: intc@fffc1000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0xfffc1000 0x0 0x1000>,
+ <0x0 0xfffc2000 0x0 0x2000>,
+ <0x0 0xfffc4000 0x0 0x2000>,
+ <0x0 0xfffc6000 0x0 0x2000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+ ranges = <0 0 0 0x>;
+
+ ccu: cache-controller@f700 {
+ compatible = "arteris,ncore-ccu";
+ reg = <0xf700 0x100900>;
+ };
+
+ clkmgr: clock-controller@ffd1 {
+ compatible = "intel,agilex-clkmgr";
+ reg = <0xffd1 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gmac0: eth
Re: [U-Boot] [PATCH v6 19/19] arm: socfpga: agilex: Enable Agilex SoC build
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan: Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Include socfpga_soc64_common.h. v5: - Enable NCORE_CACHE v3: - Disable CONFIG_USE_TINY_PRINTF v2: - Remove IC_CLK define, use clock DM method to get i2c clock - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is enabled. --- arch/arm/Kconfig | 4 +- arch/arm/mach-socfpga/Kconfig | 16 +++ arch/arm/mach-socfpga/Makefile | 9 configs/socfpga_agilex_defconfig | 58 ++ include/configs/socfpga_agilex_socdk.h | 15 +++ 5 files changed, 100 insertions(+), 2 deletions(-) create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 include/configs/socfpga_agilex_socdk.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 629c5e8c2d..723bd5c619 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -905,7 +905,7 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_STRATIX10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL @@ -917,7 +917,7 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SPL_SERIAL_SUPPORT select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index fc0a54214f..922442a31f 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -26,6 +26,15 @@ config SYS_TEXT_BASE default 0x0140 if TARGET_SOCFPGA_ARRIA10 default 0x0140 if TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_AGILEX + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select ARMV8_SPIN_TABLE + select CLK + select NCORE_CACHE + select SPL_CLK if SPL + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -72,6 +81,10 @@ choice prompt "Altera SOCFPGA board select" optional +config TARGET_SOCFPGA_AGILEX_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex)" + select TARGET_SOCFPGA_AGILEX + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -148,6 +162,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -165,6 +180,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 81b6ffc675..418f543b20 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -41,6 +41,14 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += mailbox_s10.o +obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += system_manager_s10.o +obj-y += timer_s10.o +obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_pll_config_s10.o endif ifdef CONFIG_SPL_BUILD @@ -59,6 +67,7 @@ obj-y += firewall.o obj-y += spl_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += firewall.o obj-y += spl_agilex.o endif endif diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig new file mode 100644 index 00..c221500155 --- /dev/null +++ b/configs/socfpga_agilex_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONF
Re: [U-Boot] [PULL] u-boot-socfpga/master
On Fri, Nov 15, 2019 at 10:35 AM Marek Vasut wrote: > > The following changes since commit 3ff1ff3ff76c15efe0451309af084ee6c096c583: > > Merge branch '2019-11-12-migrate-SYS_REDUNDAND_ENVIRONMENT' > (2019-11-12 13:40:58 -0500) > > are available in the Git repository at: > > git://git.denx.de/u-boot-socfpga.git master > > for you to fetch changes up to 155bf0a09b9b9538f3ef8dc244094e1a45e9e281: > > spi: cadence_qspi: support DM_CLK (2019-11-13 15:47:08 +0100) > > > Ley Foon Tan (2): > arm: dts: Stratix10: Fix memory node address and size cells > configs: Stratix10: Disable CONFIG_SPL_USE_TINY_PRINTF > > Simon Goldschmidt (4): > ddr: socfpga: gen5: constify altera_gen5_sdram_ops > socfpga: fix include guard in misc.h (arch vs. global) > timer: dw-apb: add reset handling > spi: cadence_qspi: support DM_CLK Sorry to interfere here, but Vignesh had a comment on this one and I sent v3 (what you have is v1 or v2- sorrry I wasn't aware of that). Since Vignesh claims v3 does still not compile for k2g_evm_defconfig (although I cannot reproduce that error) , we should probably defer this patch until I have checked that Travis builds it correctly. Regards, Simon > > arch/arm/dts/socfpga_stratix10_socdk.dts | 2 ++ > arch/arm/mach-socfpga/include/mach/misc.h | 6 +++--- > configs/socfpga_stratix10_defconfig | 1 + > drivers/ddr/altera/sdram_gen5.c | 2 +- > drivers/spi/cadence_qspi.c| 22 -- > drivers/timer/dw-apb-timer.c | 18 +- > 6 files changed, 44 insertions(+), 7 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
