The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block itself.
Use the already existing SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor laurentiu.tu
check is based on
the PCI controller's version register.
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Cc: York Sun york...@freescale.com
---
Based on: git://git.denx.de/u-boot-mpc85xx.git master
arch/powerpc/cpu/mpc85xx/liodn.c | 25
the reg' property.
If we don't do this, last half of the cpu nodes
will have broken clock-frequency values.
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Cc: York Sun york...@freescale.com
---
Based on: git://git.denx.de/u-boot-mpc85xx.git master
arch/powerpc/cpu/mpc85xx/fdt.c |5
SoCs were changed to use the new compatible:
T1023/4, T1040, T2080/1, T4240, B4860.
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
---
depends on https://patchwork.ozlabs.org/patch/403532/
arch/powerpc/cpu/mpc85xx/b4860_ids.c | 4 ++--
arch/powerpc/cpu/mpc85xx/p2041_ids.c | 4
On 11/24/2014 06:57 PM, York Sun wrote:
On 11/23/2014 11:30 PM, Joakim Tjernlund wrote:
York Sun york...@freescale.com wrote on 2014/10/24 18:02:03:
On 10/24/2014 08:39 AM, Joakim Tjernlund wrote:
Booting my t1042 I get:
Loading Ramdisk to 2e639000, end 2cc4 ... OK
Loading Device Tree
On 11/26/2014 10:55 AM, Joakim Tjernlund wrote:
Laurentiu Tudor b10...@freescale.com wrote on 2014/11/25 09:49:22:
On 11/24/2014 06:57 PM, York Sun wrote:
On 11/23/2014 11:30 PM, Joakim Tjernlund wrote:
York Sun york...@freescale.com wrote on 2014/10/24 18:02:03:
On 10/24/2014 08:39 AM
Offsets were overlaping, causing pamu access violations in
hypervised scenarios.
Signed-off-by: Cristian Sovaiala cristian.sovai...@freescale.com
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Reviewed-by: Fleming Andrew-AFLEMING aflem...@freescale.com
Reviewed-by: Sun Yusong-R58495
For B4 the LIODN register for PCIe is in PCIe address space and not in
GUTs
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Laurentiu Tudor laurentiu.tu
Hi York,
> -Original Message-
> From: York Sun
> Sent: Thursday, June 28, 2018 6:18 PM
>
> On 06/28/2018 02:42 AM, Laurentiu Tudor wrote:
> > Add config defines with the sata, edma and qdma register block
> > base addresses. Also white list the newly introdu
Add support for ICID setting of qman portals and
the required device tree fixups.
Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h | 23
Add infrastructure for ICID setup and device tree
fixup on ARM platforms. This include basic ICID setup
for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 111 ++
.../arm
Add support for ICID setting of fman ports and
the required device tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl-layerscape/fsl_icid.h
QMAN_BAR{E} register setup was disabled on ARM platforms,
however the register does need to be set. Add code that
sets it up on ARMs.
Signed-off-by: Laurentiu Tudor
---
drivers/misc/fsl_portals.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/misc
Add a define with a value for the missing debug stream ID.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
b/arch/arm/include/asm/arch
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm
add the actual infrastructure for ICID setup, qman
portal and fman ICID configuration.
Changes in v2:
- drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/7]
Laurentiu Tudor (7):
armv8: fsl-layerscape: add missing register blocks base address
defines
armv8: ls1046a: advertise
Add defines for the edma and qdma register block base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch
Hi Bharat,
Thanks for the review! Comments inline.
On 03.07.2018 16:38, Bharat Bhushan wrote:
>
>
>> -Original Message-
>> From: upstream-release-boun...@linux.freescale.net [mailto:upstream-
>> release-boun...@linux.freescale.net] On Behalf Of Laurentiu Tudor
u-boot@lists.denx.de; Prabhakar Kushwaha
>>> ; York Sun
>>> Cc: Bharat Bhushan ; Horia Geanta
>>> ; Laurentiu Tudor
>>> Subject: [PATCH v5 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device
>>> tree
>>>
>>> From: Laurentiu Tudor
From: Laurentiu Tudor
This patch series adds the required devices setup and device tree
fixups for SMMU enablement on NXP LS1046A chips. The approach taken
tries to mimic the implementation of PAMU LIODN setup on booke powerpc.
First 4 patches contain some fixes and add some missing bits
From: Laurentiu Tudor
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h
From: Laurentiu Tudor
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14 +++
.../asm/arch-fsl-layerscape/fsl_icid.h| 25
From: Laurentiu Tudor
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110
From: Laurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
Add defines for the edma and qdma register block base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b
From: Laurentiu Tudor
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Signed-off-by: Laurentiu Tudor
---
arch
From: Laurentiu Tudor
Add a define with a value for the missing debug stream ID.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
b/arch
From: Laurentiu Tudor
Add support for ICID setting of fman ports and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl
Hi Horia,
Thanks for having a look. Comments inline.
On 25.07.2018 20:55, Horia Geanta wrote:
> On 7/24/2018 5:05 PM, laurentiu.tu...@nxp.com wrote:
>> From: Laurentiu Tudor
>>
>> Add support for SEC ICID configuration and apply it for ls1046a.
>> Also add code to mak
From: Laurentiu Tudor
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110
From: Laurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
Add defines for the edma and qdma register block base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b
From: Laurentiu Tudor
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Signed-off-by: Laurentiu Tudor
---
arch
From: Laurentiu Tudor
Add support for ICID setting of fman ports and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl
From: Laurentiu Tudor
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14 +++
.../asm/arch-fsl-layerscape/fsl_icid.h| 25
From: Laurentiu Tudor
This patch series adds the required devices setup and device tree
fixups for SMMU enablement on NXP LS1046A chips. The approach taken
tries to mimic the implementation of PAMU LIODN setup on booke powerpc.
First 4 patches contain some fixes and add some missing bits
From: Laurentiu Tudor
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h
From: Laurentiu Tudor
Add a define with a value for the missing debug stream ID.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
b/arch
Hi Bharat,
> -Original Message-
> From: Bharat Bhushan
> >
> > On 7/31/2018 5:53 PM, laurentiu.tu...@nxp.com wrote:
> > > From: Laurentiu Tudor
> > >
> > > Add support for SEC ICID configuration and apply it for ls1046a.
> > >
Hi Horia,
> -Original Message-
> From: Horia Geanta
>
> On 7/31/2018 5:53 PM, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > Add support for SEC ICID configuration and apply it for ls1046a.
> > Also add code to make the necessary de
From: Laurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Reviewed-by: Bharat Bhushan
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm
From: Laurentiu Tudor
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.
Reviewed-by: Bharat Bhushan
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl
From: Laurentiu Tudor
Add support for ICID setting of fman ports and the required device
tree fixups.
Reviewed-by: Bharat Bhushan
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30
From: Laurentiu Tudor
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Reviewed-by: Bharat Bhushan
Signed-off
From: Laurentiu Tudor
Add a define with a value for the missing debug stream ID.
Reviewed-by: Bharat Bhushan
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Reviewed-by: Horia Geantă
Reviewed-by: Bharat Bhushan
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14
From: Laurentiu Tudor
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h
From: Laurentiu Tudor
Add defines for the edma and qdma register block base addresses.
Reviewed-by: Bharat Bhushan
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
This patch series adds the required devices setup and device tree
fixups for SMMU enablement on NXP LS1046A chips. The approach taken
tries to mimic the implementation of PAMU LIODN setup on booke powerpc.
First 4 patches contain some fixes and add some missing bits
From: Laurentiu Tudor
This patch series adds the required devices setup and device tree
fixups for SMMU enablement on NXP LS1046A chips. The approach taken
tries to mimic the implementation of PAMU LIODN setup on booke powerpc.
First 4 patches contain some fixes and add some missing bits
From: Laurentiu Tudor
Add defines for the edma and qdma register block base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b
From: Laurentiu Tudor
Add support for ICID setting of fman ports and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl
From: Laurentiu Tudor
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14 +++
.../asm/arch-fsl-layerscape/fsl_icid.h| 25
From: Laurentiu Tudor
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h
From: Laurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
Add a define with a value for the missing debug stream ID.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
b/arch
From: Laurentiu Tudor
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Signed-off-by: Laurentiu Tudor
---
arch
From: Laurentiu Tudor
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110
Hi York,
> From: York Sun
> Sent: Wednesday, August 8, 2018 7:23 PM
>
> On 08/08/2018 02:05 AM, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > This patch series adds the required devices setup and device tree
> > fixups for SMMU enablemen
From: Laurentiu Tudor
Add define for quiccengine register block base address.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm
From: Laurentiu Tudor
This patch builds on the already existing LS1046A SMMU enablement
infrastructure to add the required device setup and device tree
fixups for enabling SMMU on LS1043A SoCs.
Laurentiu Tudor (4):
armv8: fsl-layerscape: add missing qe base address define
armv8: ls1043a
From: Laurentiu Tudor
Reuse the existing ICID setup code done for LS1046A smmu enablement
and add the equivalent setup for LS1043A chips.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 90
From: Laurentiu Tudor
Enable support for ICID setup of qman portals and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
drivers/misc/fsl_portals.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc
From: Laurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
This patch series adds the required devices setup and device tree
fixups for SMMU enablement on LS1046A chips. The approach taken tries
to mimic the implementation of PAMU LIODN setup on booke powerpc.
First 4 patches contain some fixes and add some missing bits & pi
From: Laurentiu Tudor
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110
From: Laurentiu Tudor
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h
From: Laurentiu Tudor
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.
Also included in this patch, while adding the new required JR
defines sanitize the preexisting ones by dropping the CONFIG_
prefixes.
Signed-off
From: Laurentiu Tudor
Add defines for the edma and qdma register block base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b
From: Laurentiu Tudor
Add support for ICID setting of fman ports and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl
From: Laurentiu Tudor
Add a define with a value for the missing debug stream ID.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
b/arch
From: Laurentiu Tudor
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Signed-off-by: Laurentiu Tudor
---
arch
Hi Bharat,
On 10.07.2018 08:14, Bharat Bhushan wrote:
>
>
>> -Original Message-----
>> From: Laurentiu Tudor
>> Sent: Monday, July 9, 2018 6:42 PM
>> To: Bharat Bhushan ; York Sun
>> ; Prabhakar Kushwaha
>> ; u-boot@lists.denx.de
>> Subject:
Hi Bharat,
On 09.07.2018 15:13, Bharat Bhushan wrote:
>
>
>> -Original Message-----
>> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
>> Sent: Wednesday, July 4, 2018 7:44 PM
>> To: York Sun ; Prabhakar Kushwaha
>> ; u-boot@lists.denx.de
>
Hi Bharat,
On 09.07.2018 15:06, Bharat Bhushan wrote:
>
>
>> -Original Message-----
>> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
>> Sent: Wednesday, July 4, 2018 7:44 PM
>> To: York Sun ; Prabhakar Kushwaha
>> ; u-boot@lists.denx.de
>
Hi Bharat,
On 09.07.2018 15:21, Bharat Bhushan wrote:
>
>
>> -Original Message-----
>> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
>> Sent: Wednesday, July 4, 2018 7:44 PM
>> To: York Sun ; Prabhakar Kushwaha
>> ; u-boot@lists.denx.de
>
add the actual infrastructure for ICID setup, qman
portal and fman ICID configuration.
Changes in v3:
- cleaner QMAN_BAR setup
- moved SoC specific bits from generic ICID arch setup to board code
Changes in v2:
- drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/7]
Laurentiu Tudo
Add infrastructure for ICID setup and device tree
fixup on ARM platforms. This include basic ICID setup
for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 111 ++
.../arm
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch
Add support for ICID setting of qman portals and
the required device tree fixups.
Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h | 23
Add defines for the edma and qdma register block base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch
Add a define with a value for the missing debug stream ID.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
b/arch/arm/include/asm/arch
Add support for ICID setting of fman ports and
the required device tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl-layerscape/fsl_icid.h
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm
Hi Bharat,
Thanks for the review! Comments inline.
On 03.07.2018 17:09, Bharat Bhushan wrote:
>
>
>> -Original Message-
>> From: upstream-release-boun...@linux.freescale.net [mailto:upstream-
>> release-boun...@linux.freescale.net] On Behalf Of Laurentiu Tudor
Add infrastructure for ICID setup and device tree
fixup on ARM platforms. This include basic ICID setup
for several devices.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 111 ++
.../arm
Add support for ICID setting of fman ports and
the required device tree fixups.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
.../asm/arch-fsl-layerscape/fsl_icid.h
QMAN_BAR{E} register setup was disabled on ARM platforms,
however the register does need to be set. Add code that
sets it up on ARMs.
Signed-off-by: Laurentiu Tudor
---
drivers/misc/fsl_portals.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/misc
Add a define with a value for the missing debug stream ID.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
b/arch/arm/include/asm/arch
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm
Add config defines with the sata, edma and qdma register block
base addresses. Also white list the newly introduced defines.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +++
scripts/config_whitelist.txt | 3 +++
2 files
add the actual infrastructure for ICID setup, qman
portal and fman ICID configuration.
Laurentiu Tudor (7):
armv8: fsl-layerscape: add configs for missing register blocks
addresses
armv8: ls1046a: advertise QMan v3 in configuration
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
a
Add support for ICID setting of qman portals and
the required device tree fixups.
Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor
---
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
.../asm/arch-fsl-layerscape/fsl_portals.h | 23
From: Laurentiu Tudor
The ICIDs for the qdma device are not configured through SCFG but
through some registers found in the actual device register block.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h| 6 +-
arch/arm/include/asm/arch-fsl
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3",
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3",
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3",
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
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