The SPI and NAND board variants never went into production.
Drop those board variants.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/Makefile | 2 -
arch/arm/dts/am335x-brppt1-nand.dts | 374 ---
arch/arm/dts/am335x-brppt1-spi.dts | 377
Drop board variants that were never produced, fix the SPL loader,
and update environment.
Bernhard Messerklinger (5):
brppt1: Remove unused board variants
brppt1: Fix SPL boot stage
brppt1: Cleanup device tree
include: configs: brppt1: Fix commit 0ea4fc4dcf90
brppt1: Update
* Remove unnecessary device tree nodes which are not needed in
U-Boot directly.
* Move all U-Boot specific device tree properties to u-boot dtsi.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi | 32
arch/arm/dts/am335x-brppt1-mmc.dts | 201
tbaddr} and configuration script at
${cfgaddr} to ensure proper boot in warm restart case.
Signed-off-by: Bernhard Messerklinger
---
configs/brppt1_mmc_defconfig | 4 +++-
include/configs/brppt1.h | 18 --
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/c
drivers are dropped.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi | 80 ++
configs/brppt1_mmc_defconfig | 2 +-
2 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/am335x-brppt1-mmc-u-boot.dts
se
of this, cfgscr is not allowed to destroy the previously loaded device
tree otherwise cfgscr will fail.
This patch moves the device trees invalidation on warm restart to the
PREBOOT cmd to fix that issue.
Fixes: 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr")
Sig
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter
update.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_bindings.c| 28 +++
.../asm/arch-apollolake/fsp_bindings.h| 1 +
2 files changed, 29 insertions(+)
diff --git
This patch set adds new paramters and functions to allow full
configuration of the latest FSP MR6 release.
Bernhard Messerklinger (2):
x86: apl: fsp_bindings: Add support for u64 parameters
arch: x86: apl: Update FSP parameters
arch/x86/cpu/apollolake/fsp_bindings.c| 51
Add missing parameters to support full configuration of the latest FSP
MR6 release.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_bindings.c| 23 +++
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 5 +++-
.../asm/arch-apollolake/fsp/fsp_s_upd.h
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
Reviewed-by: Simon Glass
Tested on coral:
Tested-by: Simon Glass
---
Changes in v4:
Fix comment alignment
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c
into FSP-M and FSP-S
Fix #if defined macro for FSP-S path to reduce SPL size
Changes in v2:
Integration of the review comments
Fix swizzle size bug
Bernhard Messerklinger (3):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Use devicetree for FSP-M configuration
macro for FSP-S path to reduce SPL size
Changes in v2:
Integration of the review comments
Fix swizzle size bug
Bernhard Messerklinger (3):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Use devicetree for FSP-M configuration
arch: x86: apl: Use devicetree for
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++---
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/x86/cpu/apoll
: Bernhard Messerklinger
---
Changes in v2:
Integration of the review comments
Fix swizzle size bug
arch/x86/cpu/apollolake/Makefile |1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 1803 +
arch/x86/cpu/apollolake/fsp_m.c | 169 +-
arch/x86/cpu
ructures
[1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html
[2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html
Changes in v2:
Integration of the review comments
Fix swizzle size bug
Bernhard Messerklinger (2):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++---
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x8
Hi Simon,
>Hi Bernhard,
>
>On Thu, 30 Apr 2020 at 03:16, Bernhard Messerklinger
> wrote:
>>
>> A the moment the FSP configuration is a mix of hard coded values
>and
>> devicetree properties.
>> This patch makes FSP-M and FSP-S full configurable from devicetr
Hi Simon,
>Hi Bernhard,
>
>On Thu, 30 Apr 2020 at 03:16, Bernhard Messerklinger
> wrote:
>>
>> Only load VBT if it's present in the u-boot.rom.
>>
>
>I think you can drop the RFC from this series. The approach seems
>good to me.
>
>Also, what AP
: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/Makefile |1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 2096 +
arch/x86/cpu/apollolake/fsp_m.c | 164 +-
arch/x86/cpu/apollolake/fsp_s.c | 382 +--
arch/x86/dts
Hi Bin, Simon,
>
>Move FSP-M configuration to the device-tree like it's already done
>for
>other SoCs (Baytrail).
>
>Signed-off-by: Bernhard Messerklinger
>
>---
>With this patch I moved the FSP-M configuration to the device-tree
>based
>on the Baytrai
eries.
This series is superseded by:
"Move FSP configuration to devicetree" [1]
[1]: https://lists.denx.de/pipermail/u-boot/2020-April/409505.html
>Changes in v2:
>Remove FSP-M binding file
>
>Bernhard Messerklinger (2):
> arch: x86: apl: Only load VBT if CONFIG_HAVE_V
ructures
[1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html
[2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html
Bernhard Messerklinger (2):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Use devicetree for FSP configuration
arc
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 17cf1
Hi Simon,
>
>Hi Bernhard,
>
>On Mon, 20 Apr 2020 at 07:11, Bernhard Messerklinger
> wrote:
>>
>> Hi Simon,
>>
>> >Hi Bernhard,
>> >
>> >On Tue, 14 Apr 2020 at 03:26, Bernhard Messerklinger
>> > wrote:
>> >>
Hi Simon,
>Hi Bernhard,
>
>On Tue, 14 Apr 2020 at 03:26, Bernhard Messerklinger
> wrote:
>>
>> Move FSP-S configuration to the device-tree like it's already done
>for
>> other SoCs (Baytrail).
>>
>> Signed-off-by: Bernhard Messerklinger
>
>
This patch series moves the configuration of FPS-S for Apollo Lake
based SoCs from the code to the device-tree.
This is similar to the previous patch series for FSP-M.
If wanted, I can also send FSP-M and FSP-S patch as a single series.
Changes in v2:
Remove FSP-M binding file
Bernhard
Move FSP-S configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
Changes in v2:
Remove FSP-M binding file
arch/x86/cpu/apollolake/fsp_s.c | 1070 +++--
arch/x86/dts/chromebook_cora
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fs
This patch series moves the configuration of FPS-S for Apollo Lake
based SoCs from the code to the device-tree.
This is similar to the previous patch series for FSP-M.
Bernhard Messerklinger (2):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Read FSP-S
Move FSP-S configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 1070 +++--
arch/x86/dts/chromebook_coral.dts | 35 +-
.../asm/arch-apollolak
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 1f22c
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
With this patch I moved the FSP-M configuration to the device-tree based
on the Baytrail boards.
Changes in v3:
Added doc binding file
Added fspm pref
Hi Bin,
>Hi Bernhard,
>
>On Mon, Mar 30, 2020 at 4:25 PM Bernhard Messerklinger
> wrote:
>>
>> Hi Bin,
>>
>> >Hi Bernhard,
>> >
>> >On Mon, Mar 30, 2020 at 3:35 PM Bernhard Messerklinger
>> > wrote:
>> >>
>>
Hi Bin,
>Hi Bernhard,
>
>On Mon, Mar 30, 2020 at 3:35 PM Bernhard Messerklinger
> wrote:
>>
>> Hi Simon, Bin,
>>
>> I am facing problems with the PCI enumeration at SPL loader stage.
>> On our HW we have PCIe x2 port connected to a FPGA. Since SPL does
Hi Simon,
>>> With this patch I moved the fsp-m configuration to the device-tree
>>> based on the baytrail boards.
>>> I have tried to build it so that only entries that differ from the
>>> default configuration need to be added. As a minimum the ddr
>>> configuration must be present.
>>> If you l
Hi Simon, Bin,
I am facing problems with the PCI enumeration at SPL loader stage.
On our HW we have PCIe x2 port connected to a FPGA. Since SPL does pci
enumeration before FSP-S has been called the enumeration of the second port of
the pci x2 connection causes the system to hang.
In my configurat
Hi Simon,
>> With this patch I moved the fsp-m configuration to the device-tree
>> based on the baytrail boards.
>> I have tried to build it so that only entries that differ from the
>> default configuration need to be added. As a minimum the ddr
>> configuration must be present.
>> If you like th
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytaril).
Signed-off-by: Bernhard Messerklinger
---
With this patch I moved the fsp-m configuration to the device-tree based
on the baytrail boards.
I have tried to build it so that only entries that differ
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytaril).
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_m.c | 337 +++---
arch/x86/dts/chromebook_coral.dts | 35 ++
.../asm/arch-apollolak
: Bernhard Messerklinger
---
This patch is a revised version of the patch "arm: imx6: configure NoC on
i.MX6DQP" from the original author Filip Brozovic .
It takes care of the review notes for the original patch.
patchwork: https://patchwork.ozlabs.org/patch/670208/
mail-archive: https://lis
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
---
This
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
---
This
-"U-Boot" schrieb: -
> Hi Stefano, Filip,
>
> I found this patch on the mailing list:
> https://patchwork.ozlabs.org/patch/670208/
>
> As far as I can see this patch never made it to mainline.
> I have tested and reviewed the patch and it works for me.
> With this patch my i.MX6QP DDR3
Hi Stefano, Filip,
I found this patch on the mailing list:
https://patchwork.ozlabs.org/patch/670208/
As far as I can see this patch never made it to mainline.
I have tested and reviewed the patch and it works for me.
With this patch my i.MX6QP DDR3 NoC configuration works fine.
What is the cur
With the introduction of the new spi-mem model operations changed
slightly. The new spi-mem operations make things a bit easier to
handle for ich-spi flash interface. This patch converts the ich-spi
driver by using spi-mem operations.
Signed-off-by: Bernhard Messerklinger
---
Changes in v4
message a little bit
Changes in v3:
- update erase op code handling to work with latest master
spi-nor driver
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 267 +-
drivers/spi/ich.h | 9 +-
2 files changed, 100 insertions(+), 176
Hello Bin,
> Von: "Bin Meng"
> An: "Simon Glass" , "Bernhard Messerklinger"
> , "Vignesh Raghavendra"
> , "U-Boot Mailing List"
> Kopie: "Bernhard Messerklinger"
> Datum: 07/28/2019 01:31 PM
> Betreff: [PATCH
With the introduction of the new spi-mem model operations changed
slightly, which broke the ich-spi driver. The new spi-mem operations
make things a bit easier to handle for ich flash interface. This patch
makes ich-spi work again by using spi-mem operations.
Signed-off-by: Bernhard Messerklinger
Add check if exec_op is set before calling it.
At the moment it is called unconditionally, which leads to a crash if it
is not set correctly.
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/spi-mem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi
Reviewed-by: Bernhard Messerklinger
Tested-by: Bernhard Messerklinger
Von:Anssi Hannula
An: u-boot@lists.denx.de, Bernhard Messerklinger
Kopie: Hannes Schmelzer
Datum: 02/27/2019 11:56 AM
Betreff:[PATCH v2] fs: fat: fix reading non-cluster-aligned root
directory
A
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does in arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.
Signed-off-by: Bernhard Messerklinger
---
I hope this patch won't break other x86 board.
I only can test it with APL board.
Changes
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.
Signed-off-by: Bernhard Messerklinger
---
I hope this patch won't break other x86 board.
I only can test it with APL board.
Changes
> > > > > > Are you saying that if doing cpu_mhz_from_cpuid() you can't
get
> > > > > > correct frequency? Can you investigate why your core crystal
clock
> > is
> > > > > > always zero?
> > > > >
> > > > > Yes, this has to be investigated.
> > > > >
> > > > > > Can we do it something like VLV2?
Hi Andy,
> Von: Bin Meng
> An: Andy Shevchenko ,
> Kopie: Bernhard Messerklinger automation.com>, U-Boot Mailing List
> Datum: 25.11.2018 15:50
> Betreff: Re: [U-Boot] [PATCH] x86: tsc: Add support for APL soc
>
> Hi Andy,
>
> On Sun, Nov 25, 2018 at 10:
Hi Bin,
> Missing commit message
I will fix this.
>
> APL means ApolloLake? Could you please spell it out?
I will fix this.
>
> > Signed-off-by: Bernhard Messerklinger automation.com>
> > ---
> >
> > drivers/timer/tsc_timer.c | 2 ++
> > 1 file
Hi Anssi,
I tested your patch because i faced the same problem.
But I need an addition to your patch to get everything to work.
Since for fat12/16 the sect_to_clust() calculation is always a negative
value
the division through the cluster size with an odd negative value cuts the
rest.
With the
> Von: Bernhard Messerklinger/Eggelsberg/AT/B&R
> An: Jagan Teki ,
> Kopie: Jagan Teki , U-Boot-Denx
> Datum: 04.09.2018 10:54
> Betreff: Antwort: Re: [U-Boot] [PATCH] spi: mxc_spi: Fix chipselect
> with DM_SPI in SPL
>
> Hi Jagan,
>
> it's
Signed-off-by: Bernhard Messerklinger
---
drivers/timer/tsc_timer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index da7c812908..b2a982812a 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -64,6 +64,8
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 7 +++
drivers/spi/ich.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index d84bbdb2e5..4ec107d323 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -213,6 +213,10 @@ static
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 168 +-
drivers/spi/ich.h | 46 -
2 files changed, 178 insertions(+), 36 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 03531a8c0c..d84bbdb2e5 100644
works with CONFIG_DM_SPI.
Would you prefer to add CONFIG_SPL_DM_SPI as configuration parameter?
Bernhard
Von:Jagan Teki
An: Bernhard Messerklinger ,
Kopie: U-Boot-Denx , Jagan Teki
Datum: 03.09.2018 18:33
Betreff:Re: [U-Boot] [PATCH] spi: mxc_spi: Fix chipselect with
DM_SPI in SPL
Since CONFIG_IS_ENABLED(DM_SPI) is not working in SPL because
CONFIG_SPL_DM_SPI is not defined we should go with #ifdef CONFIG_DM_SPI.
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/mxc_spi.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff
Signed-off-by: Bernhard Messerklinger
---
drivers/serial/serial_mxc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4f1f822c58..e586c18cf0 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -339,6
thing.
Regards,
Bernhard
On Thu, Mar 22, 2018 at 10:06 AM, Bin Meng wrote:
> Hi,
>
> On Thu, Feb 15, 2018 at 3:59 PM, Bernhard Messerklinger
> wrote:
>> Since memory banks may not be located behind each other we need to add
>> them separately.
>>
>&
Use dm_pci_map_bar function for BAR mapping. This has the advantage
of clearing BAR flags and and only accepting mapped memory.
Signed-off-by: Bernhard Messerklinger
---
drivers/mmc/pci_mmc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/pci_mmc.c b
Do a explicit check for CONFIG_SYS_BIG_ENDIAN and
CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both
are undefined (x86).
Signed-off-by: Bernhard Messerklinger
---
drivers/serial/ns16550.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/serial
Since memory banks may not be located behind each other we need to add
them separately.
Signed-off-by: Bernhard Messerklinger
---
drivers/pci/pci-uclass.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
Fix commit f1bcad22dd19 ("net: e1000: add support for writing to
EEPROM").
Signed-off-by: Bernhard Messerklinger
---
drivers/net/e1000.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 8316854bc1..5cc54efe48 10
ed address).
To avoid this we tell the compiler to always align this scratchpad to a
word aligned address.
Signed-off-by: Bernhard Messerklinger
---
cmd/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/fdt.c b/cmd/fdt.c
index d7654b2c4f..aa9cb4b3c1 100644
--- a/cmd/f
_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS0
/* USB Ethernet Configs */
#define CONFIG_USBD_HS
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01"
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:ef
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