Pull Request: Please pull u-boot-socfpga-next-20240415
Dear Tom, Please pull the SoCFPGA changes for next from u-boot-socfpga, containing: 1. Add option to reprogram FPGA every reboot, enable this as default in chameleonv3 defconfig. 2. Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG, so the driver can be built when CONFIG_SPL_SOCFPGA_DT_REG is set in defconfig. Build-tested on SoC64 & SoC32 boards. Best regards, Tien Fong The following changes since commit b03b49046af5dfca599d2ce8f0aafed89b97aa91: Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2024-04-14 15:58:31 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-socfpga.git tags/u-boot-socfpga-next-20240415 for you to fetch changes up to 27ed98d491521a637f2b4468ac021511294f897f: drivers: misc: Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG (2024-04-15 11:16:06 +0800) Michał Barnaś (2): arm: socfpga: arria10: add option to reprogram the FPGA every reboot chameleonv3: set in defconfig for FPGA to reprogram every reboot Wan Yee Lau (1): drivers: misc: Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG arch/arm/mach-socfpga/Kconfig | 8 arch/arm/mach-socfpga/spl_a10.c | 8 ++-- configs/socfpga_chameleonv3_defconfig | 1 + drivers/misc/Makefile | 2 +- 4 files changed, 16 insertions(+), 3 deletions(-)
RE: [PATCH v3 2/2] chameleonv3: set in defconfig for FPGA to reprogramevery reboot
> -Original Message- > From: U-Boot On Behalf Of "Michal > Barnas" > Sent: Wednesday, March 20, 2024 2:18 AM > To: u-boot@lists.denx.de > Cc: "Michał Barnaś" ; "Marcel Ziswiler" > ; "Martyn Welch" > ; "Paweł Anikiel" ; > "Simon Glass" ; "Svyatoslav Ryhel" > ; "Tom Rini" > Subject: [PATCH v3 2/2] chameleonv3: set in defconfig for FPGA to > reprogramevery reboot > > Set CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM as > enabled in chameleon v3 board's defconfig. > > Signed-off-by: Michał Barnaś > --- > > Changes in v3: > - Update defconfig to use renamed Kconfig > > configs/socfpga_chameleonv3_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/socfpga_chameleonv3_defconfig > b/configs/socfpga_chameleonv3_defconfig > index 6ea61ca6ea..7506aa8d32 100644 > --- a/configs/socfpga_chameleonv3_defconfig > +++ b/configs/socfpga_chameleonv3_defconfig > @@ -7,6 +7,7 @@ > CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" > CONFIG_SPL_TEXT_BASE=0xFFE0 > CONFIG_SPL_DRIVERS_MISC=y > CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y > +CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM=y > CONFIG_SPL_FS_FAT=y > CONFIG_FIT=y > CONFIG_SPL_FIT=y Reviewed-by: Tien Fong Chee Regards Tien Fong
RE: [PATCH v3 1/2] arm: socfpga: arria10: add option to reprogram the FPGA every reboot
> -Original Message-
> From: Michał Barnaś
> Sent: Wednesday, March 20, 2024 2:18 AM
> To: u-boot@lists.denx.de
> Cc: Michał Barnaś ; Dinh Nguyen
> ; Marek Vasut ; Simon Glass
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Tom Rini
> Subject: [PATCH v3 1/2] arm: socfpga: arria10: add option to reprogram the
> FPGA every reboot
>
> Add Kconfig that enables FPGA reprogramming with warm boot on Arria 10.
> This option allows to change the bitstream on the filesystem and apply
> changes with warm reboot without the need for a power cycle.
>
> Signed-off-by: Michał Barnaś
> ---
>
> Changes in v3:
> - Rebase on current master branch
> - Drop the TARGET_ prefix in Kconfig
> - Remove #ifdefs and use IS_ENABLED
>
> Changes in v2:
> - Rebase on current master branch
>
> arch/arm/mach-socfpga/Kconfig | 8
> arch/arm/mach-socfpga/spl_a10.c | 8 ++--
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig index 114d243812..a89bd8ca58 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -80,6 +80,14 @@ config TARGET_SOCFPGA_ARRIA10
> imply FPGA_SOCFPGA
> imply SPL_USE_TINY_PRINTF
>
> +config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
> + bool "Always reprogram Arria 10 FPGA"
> + depends on TARGET_SOCFPGA_ARRIA10
> + help
> + Arria 10 FPGA is only programmed during the cold boot.
> + This option forces the FPGA to be reprogrammed every reboot,
> + allowing to change the bitstream and apply it with warm reboot.
> +
> config TARGET_SOCFPGA_CYCLONE5
> bool
> select TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-
> socfpga/spl_a10.c index 9edbbf4a29..3981d2d4f1 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -122,7 +122,10 @@ void spl_board_init(void)
> arch_early_init_r();
>
> /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
> - if (is_fpgamgr_user_mode()) {
> + if
> ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
> + is_regular_boot_valid()) ||
> +
> (!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
> + is_fpgamgr_user_mode())) {
> ret = config_pins(gd->fdt_blob, "shared");
> if (ret)
> return;
> @@ -130,7 +133,8 @@ void spl_board_init(void)
> ret = config_pins(gd->fdt_blob, "fpga");
> if (ret)
> return;
> - } else if (!is_fpgamgr_early_user_mode()) {
> + } else if
> (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) ||
> +!is_fpgamgr_early_user_mode()) {
> /* Program IOSSM(early IO release) or full FPGA */
> fpgamgr_program(buf, FPGA_BUFSIZ, 0);
>
> --
> 2.44.0.291.gc1ea87d7ee-goog
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH v1 1/1] [U-Boot] drivers: misc: Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG
> -Original Message-
> From: Lau, Wan Yee
> Sent: Thursday, March 28, 2024 2:24 PM
> To: u-boot@lists.denx.de
> Cc: Chee, Tien Fong ; Chong, Teik Heng
> ; Marek ; Hea, Kok Kiang
>
> Subject: [PATCH v1 1/1] [U-Boot] drivers: misc: Fixes: Rename
> CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG
>
> From: Wan Yee Lau
>
> Commit 3f190c55a4211215914126b74357344342329943
> ("drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA")
>
> This commit rename CONFIG_SPL_SOCFPGA_SEC_REG to
> CONFIG_SPL_SOCFPGA_DT_REG in Makefile.
>
> Signed-off-by: Wan Yee Lau
> ---
> drivers/misc/Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> 1522f6c3b7..5bb1b315cd 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -90,4 +90,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
> obj-$(CONFIG_ESM_K3) += k3_esm.o
> obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
> obj-$(CONFIG_SL28CPLD) += sl28cpld.o
> -obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o
> +obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o
> --
> 2.25.1
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: Pull Request: SoCFPGA changes for efi-2024-04-rc5
> -Original Message- > From: Tom Rini > Sent: Monday, March 18, 2024 8:29 PM > To: Chee, Tien Fong > Cc: u-boot@lists.denx.de; Vasut, Marek ; Hea, Kok Kiang > ; Lim, Jit Loon ; Lau, Wan > Yee > Subject: Re: Pull Request: SoCFPGA changes for efi-2024-04-rc5 > > On Mon, Mar 18, 2024 at 07:17:24AM +, Chee, Tien Fong wrote: > > > Dear Tom, > > > > Please pull the SoCFPGA changes for master from u-boot-socfpga, thanks. > > > > Best regards, > > Tien Fong > > > > The following changes since commit > 86fd291a7990af84e96808f48eff2219dd4ef496: > > > > Merge tag 'efi-2024-04-rc5' of > > https://source.denx.de/u-boot/custodians/u-boot-efi (2024-03-13 > > 20:39:46 -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-socfpga.git > > 386fca68960994ece0d9da8a69a14495b5f1aedf > > > > for you to fetch changes up to > 386fca68960994ece0d9da8a69a14495b5f1aedf: > > > > arch: arm: Agilex5 enablement (2024-03-18 14:45:47 +0800) > > > > > > Jit Loon Lim (1): > > arch: arm: Agilex5 enablement > > > > Wan Yee Lau (1): > > drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA > > Please rebase this on top of the current next branch, and use a tag rather > than commit hash for me to pull. A short summary of the changes, either in > the tag or pull request email itself would be appreciated as well. Thanks. Noted. > > -- > Tom
Pull Request: Please pull u-boot-socfpga-next-20240319
Dear Tom, Please pull the SoCFPGA changes for next from u-boot-socfpga, containing: 1. A new driver in the misc to register setting from device tree. This also provides user a clean interface and all register settings are centralized in one place, device tree. 1. Enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Build-tested on SoC64 boards, boot tested on some of them. Best regards, Tien Fong The following changes since commit 86fd291a7990af84e96808f48eff2219dd4ef496: Merge tag 'efi-2024-04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-03-13 20:39:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-socfpga.git tags/u-boot-socfpga-next-20240319 for you to fetch changes up to 386fca68960994ece0d9da8a69a14495b5f1aedf: arch: arm: Agilex5 enablement (2024-03-18 14:45:47 +0800) Jit Loon Lim (1): arch: arm: Agilex5 enablement Wan Yee Lau (1): drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA arch/arm/Kconfig | 6 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 71 +++ arch/arm/dts/socfpga_agilex5.dtsi | 575 ++ arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 124 + arch/arm/dts/socfpga_agilex5_socdk.dts | 163 +++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- arch/arm/mach-socfpga/Kconfig | 19 +- arch/arm/mach-socfpga/Makefile | 14 +- arch/arm/mach-socfpga/board.c | 56 ++- arch/arm/mach-socfpga/clock_manager_agilex5.c | 89 arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 38 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 +- arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h | 12 + arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 25 +- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 59 ++- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 1 - board/intel/agilex5-socdk/MAINTAINERS | 8 + configs/socfpga_agilex5_defconfig | 116 + doc/device-tree-bindings/misc/socfpga_dtreg.txt| 80 drivers/clk/altera/Makefile| 1 + drivers/clk/altera/clk-agilex5.c | 745 + drivers/clk/altera/clk-agilex5.h | 284 +++ drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/socfpga_dtreg.c | 115 + include/configs/socfpga_agilex5_socdk.h| 12 + include/configs/socfpga_soc64_common.h | 143 +- include/dt-bindings/clock/agilex5-clock.h | 71 +++ include/dt-bindings/reset/altr,rst-mgr-agx5.h | 80 31 files changed, 2922 insertions(+), 37 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h create mode 100644 board/intel/agilex5-socdk/MAINTAINERS create mode 100644 configs/socfpga_agilex5_defconfig create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt create mode 100644 drivers/clk/altera/clk-agilex5.c create mode 100644 drivers/clk/altera/clk-agilex5.h create mode 100644 drivers/misc/socfpga_dtreg.c create mode 100644 include/configs/socfpga_agilex5_socdk.h create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h
Pull Request: SoCFPGA changes for efi-2024-04-rc5
Dear Tom, Please pull the SoCFPGA changes for master from u-boot-socfpga, thanks. Best regards, Tien Fong The following changes since commit 86fd291a7990af84e96808f48eff2219dd4ef496: Merge tag 'efi-2024-04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-03-13 20:39:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-socfpga.git 386fca68960994ece0d9da8a69a14495b5f1aedf for you to fetch changes up to 386fca68960994ece0d9da8a69a14495b5f1aedf: arch: arm: Agilex5 enablement (2024-03-18 14:45:47 +0800) Jit Loon Lim (1): arch: arm: Agilex5 enablement Wan Yee Lau (1): drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA arch/arm/Kconfig | 6 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 71 +++ arch/arm/dts/socfpga_agilex5.dtsi | 575 +++ arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 124 +++ arch/arm/dts/socfpga_agilex5_socdk.dts | 163 +++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 ++-- arch/arm/mach-socfpga/Kconfig | 19 +- arch/arm/mach-socfpga/Makefile | 14 +- arch/arm/mach-socfpga/board.c | 56 - arch/arm/mach-socfpga/clock_manager_agilex5.c | 89 arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 38 +++- arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 +- arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h | 12 ++ arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 25 ++- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 59 +- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 1 - board/intel/agilex5-socdk/MAINTAINERS | 8 + configs/socfpga_agilex5_defconfig | 116 +++ doc/device-tree-bindings/misc/socfpga_dtreg.txt| 80 +++ drivers/clk/altera/Makefile| 1 + drivers/clk/altera/clk-agilex5.c | 745 ++ drivers/clk/altera/clk-agilex5.h | 284 + drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/socfpga_dtreg.c | 115 +++ include/configs/socfpga_agilex5_socdk.h| 12 ++ include/configs/socfpga_soc64_common.h | 143 - include/dt-bindings/clock/agilex5-clock.h | 71 +++ include/dt-bindings/reset/altr,rst-mgr-agx5.h | 80 +++ 31 files changed, 2922 insertions(+), 37 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h create mode 100644 board/intel/agilex5-socdk/MAINTAINERS create mode 100644 configs/socfpga_agilex5_defconfig create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt create mode 100644 drivers/clk/altera/clk-agilex5.c create mode 100644 drivers/clk/altera/clk-agilex5.h create mode 100644 drivers/misc/socfpga_dtreg.c create mode 100644 include/configs/socfpga_agilex5_socdk.h create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h
RE: [PATCH v4 1/1] arch: arm: Agilex5 enablement
Hi, > -Original Message- > From: Lim, Jit Loon > Sent: Tuesday, March 12, 2024 10:01 PM > To: u-boot@lists.denx.de > Cc: Jagan Teki ; Marek ; > Simon ; Chee, Tien Fong > ; Hea, Kok Kiang ; > Maniyam, Dinesh ; Ng, Boon Khai > ; Yuslaimi, Alif Zakuan > ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun ; Bin > Meng > Subject: [PATCH v4 1/1] arch: arm: Agilex5 enablement > > This patch is to enable Agilex5 platform for Intel > product. Changes, modification and new files are > created for board, dts, configs and makefile to > create the base for Agilex5. > > Signed-off-by: Jit Loon Lim > > --- > Changes v3 -> v4: > - Update defined to is_enabled > Changes v2 -> v3: > - Added FPGA 240G DDR region > Changes v1 -> v2: > - fixed git auto merge issue > --- > arch/arm/Kconfig | 4 +- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 71 ++ > arch/arm/dts/socfpga_agilex5.dtsi | 575 ++ > .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 133 > arch/arm/dts/socfpga_agilex5_socdk.dts| 163 > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 38 +- > arch/arm/mach-socfpga/Kconfig | 19 +- > arch/arm/mach-socfpga/Makefile| 14 +- > arch/arm/mach-socfpga/board.c | 56 +- > arch/arm/mach-socfpga/clock_manager_agilex5.c | 89 +++ > .../include/mach/base_addr_soc64.h| 38 +- > .../mach-socfpga/include/mach/clock_manager.h | 4 +- > .../include/mach/clock_manager_agilex5.h | 12 + > .../mach-socfpga/include/mach/handoff_soc64.h | 31 +- > .../mach-socfpga/include/mach/mailbox_s10.h | 1 + > arch/arm/mach-socfpga/mmu-arm64_s10.c | 59 +- > board/intel/agilex5-socdk/MAINTAINERS | 8 + > configs/socfpga_agilex5_defconfig | 116 +++ > drivers/clk/altera/Makefile | 1 + > drivers/clk/altera/clk-agilex5.c | 743 ++ > drivers/clk/altera/clk-agilex5.h | 284 +++ > include/configs/socfpga_agilex5_socdk.h | 12 + > include/configs/socfpga_soc64_common.h| 143 +++- > include/dt-bindings/clock/agilex5-clock.h | 71 ++ > include/dt-bindings/reset/altr,rst-mgr-agx5.h | 80 ++ > 26 files changed, 2730 insertions(+), 36 deletions(-) > create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts > create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c > create mode 100644 arch/arm/mach- > socfpga/include/mach/clock_manager_agilex5.h > create mode 100644 board/intel/agilex5-socdk/MAINTAINERS > create mode 100644 configs/socfpga_agilex5_defconfig > create mode 100644 drivers/clk/altera/clk-agilex5.c > create mode 100644 drivers/clk/altera/clk-agilex5.h > create mode 100644 include/configs/socfpga_agilex5_socdk.h > create mode 100644 include/dt-bindings/clock/agilex5-clock.h > create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index fde85dc0d5..6df805f44c 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config COUNTER_FREQUENCY > ROCKCHIP_RK3288 || ROCKCHIP_RK322X || > ROCKCHIP_RK3036 > default 2500 if ARCH_LX2160A || ARCH_LX2162A || > ARCH_LS1088A > default 1 if ARCH_ZYNQMP > + default 2 if ARCH_SOCFPGA && ARM64 && > TARGET_SOCFPGA_AGILEX5 > default 0 > help > For platforms with ARMv8-A and ARMv7-A which features a system > @@ -1124,7 +1125,8 @@ config ARCH_SOCFPGA > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select SYSRESET > select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 > + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 > && \ > + TARGET_SOCFPGA_SOC64 > imply CMD_DM > imply CMD_MTDPARTS > imply CRC32_VERIFY > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index d9725030d5..2b4f896ad2 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -548,6 +548,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += > thunderx-88xx.dtb > > dtb-$(CONFIG_ARCH_SOCFPGA) +=\ > socfpga_agilex_socdk.dtb
RE: [PATCH v3 v3 1/1] arch: arm: Agilex5 enablement
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Monday, March 11, 2024 9:52 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun ; Bin
> Meng
> Subject: [PATCH v3 v3 1/1] arch: arm: Agilex5 enablement
>
> This patch is to enable Agilex5 platform for Intel
> product. Changes, modification and new files are
> created for board, dts, configs and makefile to
> create the base for Agilex5.
>
> Signed-off-by: Jit Loon Lim
>
> Changes v2 -> v3:
> - Added FPGA 240G DDR region
> Changes v1 -> v2:
> - fixed git auto merge issue
> ---
> arch/arm/Kconfig | 4 +-
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 71 ++
> arch/arm/dts/socfpga_agilex5.dtsi | 575 ++
> .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 133
> arch/arm/dts/socfpga_agilex5_socdk.dts| 163
> arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 38 +-
> arch/arm/mach-socfpga/Kconfig | 19 +-
> arch/arm/mach-socfpga/Makefile| 14 +-
> arch/arm/mach-socfpga/board.c | 56 +-
> arch/arm/mach-socfpga/clock_manager_agilex5.c | 89 +++
> .../include/mach/base_addr_soc64.h| 38 +-
> .../mach-socfpga/include/mach/clock_manager.h | 4 +-
> .../include/mach/clock_manager_agilex5.h | 12 +
> .../mach-socfpga/include/mach/handoff_soc64.h | 31 +-
> .../mach-socfpga/include/mach/mailbox_s10.h | 1 +
> arch/arm/mach-socfpga/mmu-arm64_s10.c | 59 +-
> board/intel/agilex5-socdk/MAINTAINERS | 8 +
> configs/socfpga_agilex5_defconfig | 116 +++
> drivers/clk/altera/Makefile | 1 +
> drivers/clk/altera/clk-agilex5.c | 743 ++
> drivers/clk/altera/clk-agilex5.h | 284 +++
> include/configs/socfpga_agilex5_socdk.h | 12 +
> include/configs/socfpga_soc64_common.h| 143 +++-
> include/dt-bindings/clock/agilex5-clock.h | 71 ++
> include/dt-bindings/reset/altr,rst-mgr-agx5.h | 80 ++
> 26 files changed, 2730 insertions(+), 36 deletions(-)
> create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi
> create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts
> create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c
> create mode 100644 arch/arm/mach-
> socfpga/include/mach/clock_manager_agilex5.h
> create mode 100644 board/intel/agilex5-socdk/MAINTAINERS
> create mode 100644 configs/socfpga_agilex5_defconfig
> create mode 100644 drivers/clk/altera/clk-agilex5.c
> create mode 100644 drivers/clk/altera/clk-agilex5.h
> create mode 100644 include/configs/socfpga_agilex5_socdk.h
> create mode 100644 include/dt-bindings/clock/agilex5-clock.h
> create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h
>
[...]
> diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> new file mode 100644
> index 00..a24b0482bb
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2024 Intel Corporation
> + */
> +
> +#include "socfpga_agilex5-u-boot.dtsi"
> +
> +/{
> + aliases {
> + spi0 =
> + freeze_br0 = _controller;
> + };
[...]
> +
> +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
Using IS_enabled()
> +_0_blob {
> + filename = "arch/arm/dts/socfpga_agilex5_socdk.dtb";
> +};
[...]
Best regards
Tien Fong
RE: [RESEND v2 1/1] arch: arm: Agilex5 enablement
Hi Jit loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Thursday, March 7, 2024 12:42 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun ; Bin
> Meng
> Subject: [RESEND v2 1/1] arch: arm: Agilex5 enablement
>
> This patch is to enable Agilex5 platform for Intel
> product. Changes, modification and new files are
> created for board, dts, configs and makefile to
> create the base for Agilex5.
>
> Signed-off-by: Jit Loon Lim
>
> ---
> Changes v1 -> v2:
> - fixed git auto merge issue
> ---
[...]
> --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
> +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2016-2018 Intel Corporation
> + * Copyright (C) 2016-2024 Intel Corporation
> *
> */
>
> @@ -10,6 +10,62 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
> +static struct mm_region socfpga_agilex5_mem_map[] = {
> + {
> + /* OCRAM 512KB */
> + .virt = 0xUL,
> + .phys = 0xUL,
> + .size = 0x0008UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE,
> + }, {
> + /* DEVICE */
> + .virt = 0x10808000UL,
> + .phys = 0x10808000UL,
> + .size = 0x0F7F8000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> + }, {
> + /* FPGA 1.5GB */
> + .virt = 0x2000UL,
> + .phys = 0x2000UL,
> + .size = 0x6000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> + }, {
> + /* FPGA 15GB */
> + .virt = 0x44000UL,
> + .phys = 0x44000UL,
> + .size = 0x3C000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> + }, {
> + /* FPGA 240GB */
> + .virt = 0x44UL,
> + .phys = 0x44UL,
> + .size = 0x3E8000UL,
This size is not 240GB, please correct it.
[...]
Best regards,
Tien Fong
RE: [RESEND v2 1/1] arch: arm: Agilex5 enablement
Hi, > -Original Message- > From: Lim, Jit Loon > Sent: Thursday, March 7, 2024 12:42 AM > To: u-boot@lists.denx.de > Cc: Jagan Teki ; Marek ; > Simon ; Chee, Tien Fong > ; Hea, Kok Kiang ; > Maniyam, Dinesh ; Ng, Boon Khai > ; Yuslaimi, Alif Zakuan > ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun ; Bin > Meng > Subject: [RESEND v2 1/1] arch: arm: Agilex5 enablement > > This patch is to enable Agilex5 platform for Intel > product. Changes, modification and new files are > created for board, dts, configs and makefile to > create the base for Agilex5. > > Signed-off-by: Jit Loon Lim > > --- > Changes v1 -> v2: > - fixed git auto merge issue > --- > arch/arm/Kconfig | 4 +- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 71 ++ > arch/arm/dts/socfpga_agilex5.dtsi | 575 ++ > .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 134 > arch/arm/dts/socfpga_agilex5_socdk.dts| 163 > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 38 +- > arch/arm/mach-socfpga/Kconfig | 19 +- > arch/arm/mach-socfpga/Makefile| 14 +- > arch/arm/mach-socfpga/board.c | 56 +- > arch/arm/mach-socfpga/clock_manager_agilex5.c | 89 +++ > .../include/mach/base_addr_soc64.h| 38 +- > .../mach-socfpga/include/mach/clock_manager.h | 4 +- > .../include/mach/clock_manager_agilex5.h | 12 + > .../mach-socfpga/include/mach/handoff_soc64.h | 31 +- > .../mach-socfpga/include/mach/mailbox_s10.h | 1 + > arch/arm/mach-socfpga/mmu-arm64_s10.c | 59 +- > board/intel/agilex5-socdk/MAINTAINERS | 8 + > configs/socfpga_agilex5_defconfig | 116 +++ > drivers/clk/altera/Makefile | 1 + > drivers/clk/altera/clk-agilex5.c | 743 ++ > drivers/clk/altera/clk-agilex5.h | 284 +++ > include/configs/socfpga_agilex5_socdk.h | 12 + > include/configs/socfpga_soc64_common.h| 143 +++- > include/dt-bindings/clock/agilex5-clock.h | 71 ++ > include/dt-bindings/reset/altr,rst-mgr-agx5.h | 80 ++ > 26 files changed, 2731 insertions(+), 36 deletions(-) > create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts > create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c > create mode 100644 arch/arm/mach- > socfpga/include/mach/clock_manager_agilex5.h > create mode 100644 board/intel/agilex5-socdk/MAINTAINERS > create mode 100644 configs/socfpga_agilex5_defconfig > create mode 100644 drivers/clk/altera/clk-agilex5.c > create mode 100644 drivers/clk/altera/clk-agilex5.h > create mode 100644 include/configs/socfpga_agilex5_socdk.h > create mode 100644 include/dt-bindings/clock/agilex5-clock.h > create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index fde85dc0d5..6df805f44c 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config COUNTER_FREQUENCY > ROCKCHIP_RK3288 || ROCKCHIP_RK322X || > ROCKCHIP_RK3036 > default 2500 if ARCH_LX2160A || ARCH_LX2162A || > ARCH_LS1088A > default 1 if ARCH_ZYNQMP > + default 2 if ARCH_SOCFPGA && ARM64 && > TARGET_SOCFPGA_AGILEX5 > default 0 > help > For platforms with ARMv8-A and ARMv7-A which features a system > @@ -1124,7 +1125,8 @@ config ARCH_SOCFPGA > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select SYSRESET > select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 > + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && > \ > + TARGET_SOCFPGA_SOC64 > imply CMD_DM > imply CMD_MTDPARTS > imply CRC32_VERIFY > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index d9725030d5..2b4f896ad2 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -548,6 +548,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += > thunderx-88xx.dtb > > dtb-$(CONFIG_ARCH_SOCFPGA) +=\ > socfpga_agilex_socdk.dtb\ > + socfpga_agilex5_socdk.dtb \ > socfpga_arria5_secu1.dtb
RE: [PATCH 1/2] arm: socfpga: arria10: add option to reprogram the FPGA every reboot
> -Original Message-
> From: Michał Barnaś
> Sent: Thursday, February 22, 2024 11:21 PM
> To: u-boot@lists.denx.de
> Cc: Michał Barnaś ; Dinh Nguyen
> ; Marek Vasut ; Simon Glass
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Tom Rini
> Subject: [PATCH 1/2] arm: socfpga: arria10: add option to reprogram the
> FPGA every reboot
>
> Add Kconfig that enables FPGA reprogramming with warm boot on Arria 10.
> This option allows to change the bitstream on the filesystem and apply
> changes with warm reboot without the need for a power cycle.
>
> Signed-off-by: Michał Barnaś
> ---
>
> arch/arm/mach-socfpga/Kconfig | 8
> arch/arm/mach-socfpga/spl_a10.c | 8
> 2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig index 114d243812..89303f1f16 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -80,6 +80,14 @@ config TARGET_SOCFPGA_ARRIA10
> imply FPGA_SOCFPGA
> imply SPL_USE_TINY_PRINTF
>
> +config TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
> + bool "Always reprogram Arria 10 FPGA"
> + depends on TARGET_SOCFPGA_ARRIA10
> + help
> + Arria 10 FPGA is only programmed during the cold boot.
> + This option forces the FPGA to be reprogrammed every reboot,
> + allowing to change the bitstream and apply it with warm reboot.
> +
> config TARGET_SOCFPGA_CYCLONE5
> bool
> select TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-
> socfpga/spl_a10.c index 9edbbf4a29..d5d3327a42 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -122,7 +122,11 @@ void spl_board_init(void)
> arch_early_init_r();
>
> /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
> +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
> + if (is_regular_boot_valid()) {
> +#else
> if (is_fpgamgr_user_mode()) {
> +#endif
> ret = config_pins(gd->fdt_blob, "shared");
> if (ret)
> return;
> @@ -130,7 +134,11 @@ void spl_board_init(void)
> ret = config_pins(gd->fdt_blob, "fpga");
> if (ret)
> return;
> +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
> + } else {
> +#else
> } else if (!is_fpgamgr_early_user_mode()) {
> +#endif
> /* Program IOSSM(early IO release) or full FPGA */
> fpgamgr_program(buf, FPGA_BUFSIZ, 0);
>
> --
> 2.44.0.rc1.240.g4c46232300-goog
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH 0/2] arm: socfpga: arria10: allow to reprogram FPGA with warm reboot
> -Original Message- > From: Michał Barnaś > Sent: Thursday, February 29, 2024 9:49 PM > To: Dinh Nguyen > Cc: u-boot@lists.denx.de; Marcel Ziswiler ; > Marek Vasut ; Martyn Welch > ; Paweł Anikiel ; Simon > Glass ; Simon Goldschmidt > ; Svyatoslav Ryhel > ; Chee, Tien Fong ; Tom > Rini > Subject: Re: [PATCH 0/2] arm: socfpga: arria10: allow to reprogram FPGA with > warm reboot > > On Thu, Feb 29, 2024 at 2:03 PM Dinh Nguyen wrote: > > > > > > > > On 2/22/24 09:20, Michał Barnaś wrote: > > > > > > By default, the board requires power cycle (cold boot) to program > > > the FPGA with bitstream. This change adds Kconfig that allows to > > > enable reprogramming the FPGA with every boot. This makes the update > > > process of the bitstream on the filesystem to be applied with simple > > > system reboot. > > > > > > > > > > If we want to enable the reprogramming on every boot, would it make > > sense to just do it and not even bother with the Kconfig option? > > > > Dinh > > The FPGA programming part takes quite a long time, so it increases the > reboot time significantly. > I don't think that everyone needs the reprogramming to happen every time. > We need that because our boards are closed in the lab and the power is not > easily accessible, so in case of update to the bitstream, we should be able to > remotely update it with a pure warm reboot. > So I thought that this should be set by Kconfig to not bother other users with > longer reboot times. > > Michał Reprogram should be avoided when FPGA already in user mode, this is for FPGA boot first use case. Full reprogram is slow in SPL, because very small buffer in this small OCRAM can only be used to process the full RBF. Since this is an optional configuration, I don't see any issue with these changes. Tien Fong
RE: [PATCH v1 1/1] arch:arm: Agilex5 enablement
Hi, > -Original Message- > From: Lim, Jit Loon > Sent: Tuesday, February 20, 2024 10:36 PM > To: u-boot@lists.denx.de > Cc: Jagan Teki ; Marek ; > Simon ; Chee, Tien Fong > ; Hea, Kok Kiang ; > Maniyam, Dinesh ; Ng, Boon Khai > ; Yuslaimi, Alif Zakuan > ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun ; Bin > Meng > Subject: [PATCH v1 1/1] arch:arm: Agilex5 enablement > > This patch is to enable Agilex5 platform for Intel product. Changes, > modification and new files are created for board, dts, configs and makefile to > create the base for Agilex5. > > Signed-off-by: Jit Loon Lim > --- > arch/arm/Kconfig | 9 +- > arch/arm/dts/Makefile | 32 + > .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 11 +- > arch/arm/dts/socfpga_agilex5_socdk.dts| 67 +- > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 2 +- > arch/arm/mach-socfpga/Kconfig | 125 +- > arch/arm/mach-socfpga/Makefile| 99 +- > arch/arm/mach-socfpga/board.c | 2 - > .../include/mach/base_addr_soc64.h| 16 +-- > board/intel/agilex5-socdk/MAINTAINERS | 2 + > board/intel/agilex5-socdk/Makefile| 2 +- > board/intel/agilex5-socdk/socfpga.c | 2 +- > configs/socfpga_agilex5_defconfig | 33 - > include/configs/socfpga_agilex5_socdk.h | 2 +- > include/configs/socfpga_soc64_common.h| 40 +- > 15 files changed, 63 insertions(+), 381 deletions(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > 43d5ad346f..c8d91669da 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,7 +28,7 @@ config COUNTER_FREQUENCY > ROCKCHIP_RK3288 || ROCKCHIP_RK322X || > ROCKCHIP_RK3036 > default 2500 if ARCH_LX2160A || ARCH_LX2162A || > ARCH_LS1088A > default 1 if ARCH_ZYNQMP > - default 4 if ARCH_SOCFPGA && ARM64 This patch is not based on latest U-Boot main branch https://source.denx.de/u-boot/u-boot.git, no such code in current main branch. > + default 2 if ARCH_SOCFPGA && ARM64 && > TARGET_SOCFPGA_AGILEX5 > default 0 > help > For platforms with ARMv8-A and ARMv7-A which features a system > @@ -1088,14 +1088,14 @@ config ARCH_SNAPDRAGON > select SPMI > imply CMD_DM > > -config ARCH_SOCFPGA Why remove this? > - bool "Altera SOCFPGA family" > +bool "Altera SOCFPGA family" Why to change this? > select ARCH_EARLY_INIT_R > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 > select ARM64 if TARGET_SOCFPGA_SOC64 > select CPU_V7A if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select DM > select DM_SERIAL > + select GICV2 > select GPIO_EXTRA_HEADER > select ENABLE_ARM_SOC_BOOT0_HOOK if > TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > select OF_CONTROL > @@ -1109,7 +1109,7 @@ config ARCH_SOCFPGA > select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 > select SPL_SERIAL > select SPL_SYSRESET > - select SPL_WATCHDOG > + select SPL_WATCHDOG if !TARGET_SOCFPGA_AGILEX5 This can be removed, watchdog is supported in Agilex5 > select SUPPORT_SPL > select SYS_NS16550 > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 @@ -1123,6 +1123,7 @@ config > ARCH_SOCFPGA > imply DM_SPI > imply DM_SPI_FLASH > imply FAT_WRITE > + imply MTD > imply SPL > imply SPL_DM > imply SPL_DM_SPI > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > 90d933a9ae..646f4feaf7 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -543,37 +543,7 @@ dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517- > evm.dtb > dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb > > dtb-$(CONFIG_ARCH_SOCFPGA) +=\ > - socfpga_agilex_n6010.dtb\ > - socfpga_agilex_socdk.dtb\ > - socfpga_agilex_socdk_nand.dtb \ > - socfpga_agilex_socdk_qspi.dtb \ > - socfpga_agilex5_socdk.dtb \ > - socfpga_agilex5_emu.dtb \ > - socfpga_agilex7m_socdk.dtb \ > - socfpga_agilex7m_socdk_nand.dtb \ > - socfpga_arria5_secu1.dtb\ > - socfpga_arria5_socdk.dtb\ > -
RE: [PATCH v2 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
> -Original Message-
> From: Lau, Wan Yee
> Sent: Monday, February 5, 2024 11:47 AM
> To: u-boot@lists.denx.de
> Cc: Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Chong, Teik Heng
> Subject: [PATCH v2 1/1] drivers: misc: Add socfpga_dtreg driver for Intel
> SoCFPGA
>
> From: Wan Yee Lau
>
> Add socfpga_dtreg driver enablement for Intel SoCFPGA.
>
> Signed-off-by: Wan Yee Lau
> ---
> Changes for v2:
> - Rearranged header file in socfpga_drteg.c, moved lower.
>
> arch/arm/Kconfig | 2 +
> .../misc/socfpga_dtreg.txt| 74 +++
> drivers/misc/Kconfig | 7 ++
> drivers/misc/Makefile | 1 +
> drivers/misc/socfpga_dtreg.c | 117 ++
> 5 files changed, 201 insertions(+)
> create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
> create mode 100644 drivers/misc/socfpga_dtreg.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index
> 531b081de9..6087345eb8 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1092,6 +1092,8 @@ config ARCH_SOCFPGA
> select SPL_LIBGENERIC_SUPPORT
> select SPL_OF_CONTROL
> select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
> + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
> + select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
> select SPL_SERIAL
> select SPL_SYSRESET
> select SPL_WATCHDOG
> diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-
> tree-bindings/misc/socfpga_dtreg.txt
> new file mode 100644
> index 00..6057f792b9
> --- /dev/null
> +++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
> @@ -0,0 +1,74 @@
> +* Firewall and privilege register settings in device tree
> +
> +Required properties:
> +
> +
> +- compatible: should contain "intel,socfpga-dtreg"
> +- reg: Physical base address and size of block register.
> +- intel,offset-settings: 32-bit offset address of block register,
> + followed by 32-bit value settings and
> + the masking bits, only masking bit
> + set to 1 allows modification.
> +
> +The device tree node which describes secure and privilege register
> +access configuration in compile time.
> +
> +Most of these registers are expected to work except for the case which
> +some registers configuration are required for granting access to some
> +other registers, for example CCU registers have to be properly
> +configured before allowing register configuration access to fpga2sdram
> +firewall as shown in below example.
> +
> +Some registers depend on runtime data for proper configuration are
> +expected to be part of driver that generating these data for example
> +configuration for soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register
> +depend on DDR size parsed from memory device tree node.
> +
> +Please refer details of tested examples below for both fpga2sdram and
> +QoS configuration with default reset value and the comments.
> +
> +Example:
> +
> +
> +Configuration for multiple dtreg node support in device tree:
> +
> + socfpga_dtreg0: socfpga-dtreg0 {
> + compatible = "intel,socfpga-dtreg";
> + #address-cells = <1>;
> +#size-cells = <1>;
> + bootph-all;
> +
> +coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
> + reg = <0xf7100200 0x0014>;
> +intel,offset-settings =
> + /* Disable ocram security at CCU for
> non secure
> access */
> +<0x004 0x8000 0xe007>,
> +<0x008 0x8000 0xe007>,
> +<0x00c 0x8000 0xe007>,
> +<0x010 0x8000 0xe007>;
> +bootph-all;
> +};
> +};
> +
> + socfpga_dtreg1: socfpga-dtreg1 {
> + compatible = "intel,socfpga-dtreg";
> + #address-cells = <1>;
> +#size-cells = <1>;
> + bootph-all;
> +
> +soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f802 {
> +reg = <0xf802 0x001c>;
> +intel,offset-settings =
> +
RE: [PATCH 1/1] socfpga_de1_soc: Specify Uart clock in dts
> -Original Message-
> From: U-Boot On Behalf Of "Alexander
> Daum"
> Sent: Wednesday, January 4, 2023 5:11 AM
> To: u-boot@lists.denx.de
> Cc: "Alexander Daum"
> Subject: [PATCH 1/1] socfpga_de1_soc: Specify Uart clock in dts
>
> UART output was broken since commit c402e8170245 ("dts: arm: socfpga:
> merge gen5 devicetrees from linux"), when uart clocks where removed from
> socfpga.dtsi
>
> This patch specifies the uart clock for DE1-SoC board.
>
> Signed-off-by: Alexander Daum
> ---
> arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
> b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
> index ff1e61e0cb..f4935d0689 100644
> --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
> @@ -76,6 +76,7 @@
>
> {
> u-boot,dm-pre-reloc;
> + clock-frequency = <1>;
> };
>
> {
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: Pull request: SoCFPGA changes for commit 3c9bb8fbdc77f
Hi Tom, > -Original Message- > From: Tom Rini > Sent: Monday, January 22, 2024 10:47 PM > To: Chee, Tien Fong > Cc: u-boot@lists.denx.de; Vasut, Marek ; Maniyam, > Dinesh ; Hea, Kok Kiang > > Subject: Re: Pull request: SoCFPGA changes for commit 3c9bb8fbdc77f > > On Mon, Jan 22, 2024 at 09:30:40AM +, Chee, Tien Fong wrote: > > > Hi Tom, > > > > Please pull the SoCFPGA changes as shown in below. > > > > Best regards, > > Tien Fong > > > > The following changes since commit > 3c04fcf3137d5f694d52b8f355373e4baabe5f78: > > > > Merge patch series "k3-j721e: beagleboneai: Fix USB" (2024-01-20 > > 11:39:13 -0500) > > > > are available in the Git repository at: > > > > https://github.com/tienfong/uboot_mainline.git > > 3c9bb8fbdc77f6bd56e97597d875d8965db3b96c > > Lets talk off-list about getting things moved to https://source.denx.de/u- > boot/custodians/u-boot-socfpga/ please. Sure. > > > > > for you to fetch changes up to > 3c9bb8fbdc77f6bd56e97597d875d8965db3b96c: > > > > arm: dts: agilex: Increase reserved memory size to 32MB (2024-01-22 > > 16:51:29 +0800) > > There's a few more patches showing under: > https://patchwork.ozlabs.org/project/uboot/list/?q=socfpga are they ready > or need changes? Thanks for pointing. - Changes are needed for first item. - Second item is already part of this pull request - I will submit request for third item. Best regards, Tien Fong.
Pull request: SoCFPGA changes for commit 3c9bb8fbdc77f
Hi Tom, Please pull the SoCFPGA changes as shown in below. Best regards, Tien Fong The following changes since commit 3c04fcf3137d5f694d52b8f355373e4baabe5f78: Merge patch series "k3-j721e: beagleboneai: Fix USB" (2024-01-20 11:39:13 -0500) are available in the Git repository at: https://github.com/tienfong/uboot_mainline.git 3c9bb8fbdc77f6bd56e97597d875d8965db3b96c for you to fetch changes up to 3c9bb8fbdc77f6bd56e97597d875d8965db3b96c: arm: dts: agilex: Increase reserved memory size to 32MB (2024-01-22 16:51:29 +0800) Dinesh Maniyam (3): arm: socfpga: stratix10: SPI clock support clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0) arm: dts: agilex: Increase reserved memory size to 32MB arch/arm/dts/socfpga_agilex.dtsi | 4 ++-- arch/arm/mach-socfpga/clock_manager_s10.c | 17 - drivers/clk/altera/clk-mem-n5x.h | 4 ++-- 3 files changed, 20 insertions(+), 5 deletions(-)
RE: [PATCH] arm: socfpga: stratix10: SPI clock support
Hi,
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Thursday, December 7, 2023 3:46 PM
> To: u-boot@lists.denx.de
> Cc: Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Maniyam, Dinesh ;
> Ng, Boon Khai ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: [PATCH] arm: socfpga: stratix10: SPI clock support
>
> From: Dinesh Maniyam
>
> This patch is to add SPI clock support for stratix10. Get clock rate function
> always returning 0 because the DW-SPI driver get the rate from clock node in
> dts but Stratix10 does not support device tree clock node.To overcome this spi
> will get the clock_rate directly from spi clock controller override the weaker
> function.
>
> Signed-off-by: Dinesh Maniyam
> ---
> arch/arm/mach-socfpga/clock_manager_s10.c | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-
> socfpga/clock_manager_s10.c
> index 4b4f0749db..45300336d5 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2016-2018 Intel Corporation
> + * Copyright (C) 2016-2023 Intel Corporation
> *
> */
>
> @@ -399,6 +399,21 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
> return cm_get_l3_main_clk_hz() / 4;
> }
>
> +/*
> + * Override weak dw_spi_get_clk implementation in designware_spi.c
> +driver */
> +
> +int dw_spi_get_clk(struct udevice *bus, ulong *rate) {
> + *rate = cm_get_spi_controller_clk_hz();
> + if (!*rate) {
> + printf("SPI: clock rate is zero");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> void cm_print_clock_quick_summary(void)
> {
> printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
> --
> 2.26.2
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH] clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)
Hi, > -Original Message- > From: Maniyam, Dinesh > Sent: Friday, December 15, 2023 3:15 PM > To: u-boot@lists.denx.de > Cc: Marek ; Simon ; > Lukasz Majewski ; Sean Anderson ; > Chee, Tien Fong ; Hea, Kok Kiang > ; Maniyam, Dinesh > ; Ng, Boon Khai ; > Yuslaimi, Alif Zakuan ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun > Subject: [PATCH] clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to > bit(0) > > From: Dinesh Maniyam > > MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in > documentation but it is wrongly defined as BIT[7] in u-boot code. This > register is used to hold associated pingpong counter in reset while PLL and > 5:1 mux configuration is changed. > > Signed-off-by: Dinesh Maniyam > --- > drivers/clk/altera/clk-mem-n5x.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/altera/clk-mem-n5x.h b/drivers/clk/altera/clk-mem- > n5x.h > index 7b687012e8..c6bc44bb34 100644 > --- a/drivers/clk/altera/clk-mem-n5x.h > +++ b/drivers/clk/altera/clk-mem-n5x.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ > /* > - * Copyright (C) 2020-2022 Intel Corporation > + * Copyright (C) 2020-2023 Intel Corporation > */ > > #ifndef _CLK_MEM_N5X_ > @@ -77,7 +77,7 @@ > #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK > GENMASK(4, 0) > #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 > > -#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) > +#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(0) > #define MEMCLKMGR_EXTCNTRST_ALLCNTRST\ > (MEMCLKMGR_EXTCNTRST_C0CNTRST) > > -- > 2.26.2 Reviewed-by: Tien Fong Chee Regards Tien Fong
RE: [PATCH] arm: dts: agilex: Increase reserved memory size to 32MB
Hi,
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Friday, December 15, 2023 3:22 PM
> To: u-boot@lists.denx.de
> Cc: Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Maniyam, Dinesh
> ; Ng, Boon Khai ;
> Yuslaimi, Alif Zakuan ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: [PATCH] arm: dts: agilex: Increase reserved memory size to 32MB
>
> From: Dinesh Maniyam
>
> The reserved space is extended to 32MB in Linux kernel because additional
> space is needed for authorization execution of JIC/RBF file.
> U-Boot required to align with Linux.
>
> Signed-off-by: Dinesh Maniyam
> ---
> arch/arm/dts/socfpga_agilex.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_agilex.dtsi
> b/arch/arm/dts/socfpga_agilex.dtsi
> index c3ead2d72b..712304d07a 100644
> --- a/arch/arm/dts/socfpga_agilex.dtsi
> +++ b/arch/arm/dts/socfpga_agilex.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2019, Intel Corporation
> + * Copyright (C) 2019-2023 Intel Corporation
> */
>
> /dts-v1/;
> @@ -20,7 +20,7 @@
>
> service_reserved: svcbuffer@0 {
> compatible = "shared-dma-pool";
> - reg = <0x0 0x0 0x0 0x100>;
> + reg = <0x0 0x0 0x0 0x200>;
> alignment = <0x1000>;
> no-map;
> };
> --
> 2.26.2
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
Hi,
> -Original Message-
> From: Lau, Wan Yee
> Sent: Friday, December 8, 2023 4:37 PM
> To: u-boot@lists.denx.de
> Cc: Simon Glass ; Kever Yang chips.com>; Bin Meng ; Jonas Karlman
> ; Jean-Marie Lemetayer ; Peng
> Fan ; Vladimir Zapolskiy
> ; Konrad Dybcio ;
> Marek Vasut ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel
> SoCFPGA
>
> From: Wan Yee Lau
>
> This driver can be used to provide user a clean interface and all register
> settings are centralized in one place, device tree without need for
> hardcoding in the source code.
>
> Signed-off-by: Wan Yee Lau
> ---
> .../misc/socfpga_dtreg.txt| 66 ++
> drivers/misc/Kconfig | 7 ++
> drivers/misc/Makefile | 1 +
> drivers/misc/socfpga_dtreg.c | 117 ++
> 4 files changed, 191 insertions(+)
> create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
> create mode 100644 drivers/misc/socfpga_dtreg.c
>
> diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-
> tree-bindings/misc/socfpga_dtreg.txt
> new file mode 100644
> index 00..5458103f88
> --- /dev/null
> +++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
> @@ -0,0 +1,66 @@
> +* Firewall and privilege register settings in device tree
> +
> +Required properties:
> +
> +
> +- compatible: should contain "intel,socfpga-dtreg"
> +- reg: Physical base address and size of block register.
> +- intel,offset-settings: 32-bit offset address of block register,
> + followed by 32-bit value settings and
> + the masking bits, only masking bit
> + set to 1 allows modification.
> +
> +This driver can be used to provide user a clean interface and all
> +register settings are centralized in one place, device tree without
> +need for hardcoding in the source code.
> +
> +General setup would be to set the memory address used by the register,
> +followed by the offset-settings containing the 32-bit offset address of
> +the block register, then the 32-bit value settings and lastly the
> +masking bits.
> +
> +Example:
> +
> +
> +Configuration for multiple dtreg node support in device tree:
> +
> + socfpga_mainfirewall: socfpga-mainfirewall {
> + compatible = "intel,socfpga-dtreg";
> + #address-cells = <1>;
> +#size-cells = <1>;
> + bootph-all;
> +
> +coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
> + reg = <0xf7100200 0x0014>;
> +intel,offset-settings =
> + /* Disable ocram security at CCU for
> non secure
> access */
> +<0x004 0x8000 0xe007>,
> +<0x008 0x8000 0xe007>,
> +<0x00c 0x8000 0xe007>,
> +<0x010 0x8000 0xe007>;
> +bootph-all;
> +};
> +};
> +
> + socfpga_mpfefirewall: socfpga-mpfefirewall {
> + compatible = "intel,socfpga-dtreg";
> + #address-cells = <1>;
> +#size-cells = <1>;
> + bootph-all;
> +
> +soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f802 {
> +reg = <0xf802 0x001c>;
> +intel,offset-settings =
> +/* Disable MPFE firewall for SMMU */
> +<0x 0x00010101 0x00010101>,
> +/* Disable MPFE firewall for HMC
> adapter */
> +<0x0004 0x0001 0x00010101>;
> + bootph-all;
> +};
> +};
> +
> +To call the nodes use:
> +
> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
> mainfirewall", );
> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
> mpfefirewall",
>
RE: [PATCH v1 03/17] arch: arm: mach-socfpga: add new platform agilex5 mach-socfpga enablement
Hi Jit Loon, > -Original Message- > From: Lim, Jit Loon > Sent: Wednesday, 21 June, 2023 11:16 AM > To: u-boot@lists.denx.de > Cc: Jagan Teki ; Vignesh R > ; Vasut, Marek ; Simon > ; Chee, Tien Fong > ; Hea, Kok Kiang ; > Lokanathan, Raaj ; Maniyam, Dinesh > ; Ng, Boon Khai ; > Yuslaimi, Alif Zakuan ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun > Subject: [PATCH v1 03/17] arch: arm: mach-socfpga: add new platform > agilex5 mach-socfpga enablement > > This is for new platform enablement for agilex5. > Add platform related files to enable new product. You should not squash all IP drivers such as clock manager, reset manager into one patch, this is not the right way to generate the patch, very hard for me to review the codes. > > Signed-off-by: Jit Loon Lim > --- > arch/arm/mach-socfpga/Kconfig | 37 +++ > arch/arm/mach-socfpga/Makefile| 69 - > arch/arm/mach-socfpga/board.c | 65 - > arch/arm/mach-socfpga/clock_manager_agilex5.c | 82 ++ > arch/arm/mach-socfpga/firewall.c | 107 --- > arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 61 > arch/arm/mach-socfpga/lowlevel_init_soc64.S | 167 ++- > arch/arm/mach-socfpga/mailbox_s10.c | 21 ++ > arch/arm/mach-socfpga/misc.c | 19 +- > arch/arm/mach-socfpga/misc_soc64.c| 33 ++- > arch/arm/mach-socfpga/mmu-arm64_s10.c | 43 ++- > arch/arm/mach-socfpga/reset_manager_s10.c | 271 +++-- > - > arch/arm/mach-socfpga/secure_reg_helper.c | 4 +- > arch/arm/mach-socfpga/smmu_agilex5.c | 34 +++ > arch/arm/mach-socfpga/smmu_s10.c | 126 > arch/arm/mach-socfpga/spl_agilex5.c | 180 > arch/arm/mach-socfpga/spl_soc64.c | 188 +++- > arch/arm/mach-socfpga/u-boot-spl-soc64.lds| 93 ++ > arch/arm/mach-socfpga/wrap_handoff_soc64.c| 7 +- > 19 files changed, 1429 insertions(+), 178 deletions(-) > create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c > delete mode 100644 arch/arm/mach-socfpga/firewall.c > create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S > create mode 100644 arch/arm/mach-socfpga/smmu_agilex5.c > create mode 100644 arch/arm/mach-socfpga/smmu_s10.c > create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c > create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach- > socfpga/Kconfig > index 503c82d388..562c3796ec 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -44,6 +44,15 @@ config TEXT_BASE > default 0x0140 if TARGET_SOCFPGA_ARRIA10 > default 0x0140 if TARGET_SOCFPGA_GEN5 > > +config ARMV8_PSCI_NR_CPUS > + default 4 if TARGET_SOCFPGA_SOC64 > + > +config ARMV8_SECURE_BASE > + default 0x1000 if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI > + > +config SYS_HAS_ARMV8_SECURE_BASE > + default y if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI > + > config TARGET_SOCFPGA_AGILEX > bool > select ARMV8_MULTIENTRY > @@ -51,10 +60,31 @@ config TARGET_SOCFPGA_AGILEX > select BINMAN if SPL_ATF > select CLK > select FPGA_INTEL_SDM_MAILBOX > + select GICV2 > + select NCORE_CACHE > + select SPL_CLK if SPL > + select TARGET_SOCFPGA_SOC64 > + > +config TARGET_SOCFPGA_AGILEX5 > + bool > + select BINMAN if SPL_ATF > + select CLK > + select FPGA_INTEL_SDM_MAILBOX > + select GICV3 > select NCORE_CACHE > select SPL_CLK if SPL > select TARGET_SOCFPGA_SOC64 > > +config TARGET_SOCFPGA_AGILEX5_EMU > + bool "Enable build that bootable only on Agilex5 Emulator" > + help > + This is to use for Agilex5 Emulator. > + > +config TARGET_SOCFPGA_AGILEX5_SIMICS > + bool "Enable build that bootable only on Agilex5 Simics platform" > + help > + This is to use for Agilex5 Simics. > + > config TARGET_SOCFPGA_ARRIA5 > bool > select TARGET_SOCFPGA_GEN5 > @@ -126,6 +156,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK > bool "Intel SOCFPGA SoCDK (Agilex)" > select TARGET_SOCFPGA_AGILEX > > +config TARGET_SOCFPGA_AGILEX5_SOCDK > + bool "Intel SOCFPGA SoCDK (Agilex5)" > + select TARGET_SOCFPGA_AGILEX5 > + > config TARGET_SOCFPGA_ARIES_MCVEVK > bool "Aries MCVEVK (Cyclone V)" > select TARGET_SOCFPGA_CYCLONE5 > @@ -199,6 +233,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT > endchoice >
RE: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform agilex5
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 21 June, 2023 11:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lokanathan, Raaj ; Maniyam, Dinesh
> ; Ng, Boon Khai ;
> Yuslaimi, Alif Zakuan ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform
> agilex5
>
> This is for new platform enablement for agilex5.
> Add agilex5 dtsi and dts.
> Update checkpatch error for stratix10.
Why having checkpatch error for Stratix10?
This should be in a separate patch.
>
> Signed-off-by: Jit Loon Lim
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 +
> arch/arm/dts/socfpga_agilex5.dtsi | 634 ++
> .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131
> arch/arm/dts/socfpga_agilex5_socdk.dts| 165 +
> arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi| 38 +-
> arch/arm/dts/socfpga_soc64_u-boot.dtsi| 120
> arch/arm/dts/socfpga_stratix10.dtsi | 0
> .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0
> arch/arm/dts/socfpga_stratix10_socdk.dts | 0
> 10 files changed, 1534 insertions(+), 14 deletions(-) create mode 100644
> arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644
> arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts
> create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
> mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi
> mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-
> boot.dtsi
> mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 480269fa60..2e4bc556e1 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -456,6 +456,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) +=
> thunderx-88xx.dtb
>
> dtb-$(CONFIG_ARCH_SOCFPGA) +=\
> socfpga_agilex_socdk.dtb\
> + socfpga_agilex5_socdk.dtb \
> socfpga_arria5_secu1.dtb\
> socfpga_arria5_socdk.dtb\
> socfpga_arria10_chameleonv3_270_2.dtb \
> diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> new file mode 100644
> index 00..6a1299901a
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> @@ -0,0 +1,459 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2019-2022 Intel Corporation */
> +
> +#include "socfpga_soc64_u-boot.dtsi"
> +#include "socfpga_soc64_fit-u-boot.dtsi"
> +
> +/{
> + memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + bootph-all;
> + };
> +
> + soc {
> + bootph-all;
> +
> + socfpga_secreg: socfpga-secreg {
> + compatible = "intel,socfpga-secreg";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bootph-all;
> +
> + /* DSU */
> + i_ccu_caiu0@1c00 {
> + reg = <0x1c00 0x1000>;
> + intel,offset-settings =
> + /* CAIUAMIGR */
> + <0x03c0 0x0003 0x001f>,
> + /* CAIUMIFSR */
> + <0x03c4 0x
> 0x07070777>,
> + /* DII1_MPFEREGS */
> + <0x0414 0x00018000 0x>,
> + <0x0418 0x 0x00ff>,
> + <0x0410 0xc0e00200 0xc1f03e1f>,
> + /* DII2_GICREGS */
> + <0x0424 0x0001d000 0x>,
> + <0x0428 0x 0x00ff>,
> + <0x0420 0xc0800400 0xc1f03e1f>,
> + /* NCAIU0_LWSOC2FPGA */
>
RE: [PATCH v1 01/17] arch: arm: update kconfig for new platform agilex5
Hi Jit Loon, > -Original Message- > From: Lim, Jit Loon > Sent: Wednesday, 21 June, 2023 11:16 AM > To: u-boot@lists.denx.de > Cc: Jagan Teki ; Vignesh R > ; Vasut, Marek ; Simon > ; Chee, Tien Fong > ; Hea, Kok Kiang ; > Lokanathan, Raaj ; Maniyam, Dinesh > ; Ng, Boon Khai ; > Yuslaimi, Alif Zakuan ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun > Subject: [PATCH v1 01/17] arch: arm: update kconfig for new platform agilex5 > > This is for new platform enablement for agilex5 > > Signed-off-by: Jit Loon Lim > --- > arch/arm/Kconfig | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > 99264a6478..8e36456fa8 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1093,6 +1093,8 @@ config ARCH_SOCFPGA > select SPL_LIBGENERIC_SUPPORT > select SPL_OF_CONTROL > select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 > + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 > + select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 Please exclude these changes for now because this driver is not in mainline yet. You can submit another patch for these changes once the driver is accepted into mainline. > select SPL_SERIAL > select SPL_SYSRESET > select SPL_WATCHDOG > @@ -1101,7 +1103,8 @@ config ARCH_SOCFPGA > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select SYSRESET > select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 > + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 > && TARGET_SOCFPGA_SOC64 > + imply SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5 Please update your commit message, your message should be clear and accurate to reflect your changes here. > imply CMD_DM > imply CMD_MTDPARTS > imply CRC32_VERIFY > -- > 2.26.2 Thanks and regards, Tien Fong
RE: [PATCH] arch: arm: mach-socfpga: To notify SDM when U-Boot pass control to Linux
Hi,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 31 August, 2022 2:46 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lim, Elly Siew Chin ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Tang, Sieu Mun
> ; Lim, Jit Loon ; Chin
> Liang See
> Subject: [PATCH] arch: arm: mach-socfpga: To notify SDM when U-Boot pass
> control to Linux
>
> From: Chin Liang See
>
> Prior U-Boot pass control to Linux, U-Boot will send a mailbox command
> "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
> transition.
>
> Signed-off-by: Chin Liang See
> Signed-off-by: Jit Loon Lim
> ---
> arch/arm/mach-socfpga/misc_soc64.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-
> socfpga/misc_soc64.c
> index 2acdfad07b..00852d27d9 100644
> --- a/arch/arm/mach-socfpga/misc_soc64.c
> +++ b/arch/arm/mach-socfpga/misc_soc64.c
> @@ -89,3 +89,8 @@ void do_bridge_reset(int enable, unsigned int mask)
>
> socfpga_bridges_reset(enable);
> }
> +
> +void arch_preboot_os(void)
> +{
> + mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS);
I don't see this function in https://source.denx.de/u-boot/u-boot, you need to
submit the patch for this function first.
> +}
> --
> 2.26.2
Best regards,
TF.
RE: [PATCH] arch: arm: mach-socfpga: To notify SDM when SPL pass control to U-Boot
> -Original Message-
> From: Lim, Jit Loon
> Sent: Tuesday, 30 August, 2022 11:52 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R ;
> Vasut, Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Lim, Elly Siew Chin ;
> Kho, Sin Hui ; Lokanathan, Raaj
> ; Maniyam, Dinesh ;
> Ng, Boon Khai ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Tang, Sieu Mun
> ; Lim, Jit Loon ; Chin Liang
> See
> Subject: [PATCH] arch: arm: mach-socfpga: To notify SDM when SPL pass
> control to U-Boot
>
> From: Chin Liang See
>
> Prior SPL pass control to U-Boot, SPL will send a mailbox command
> "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
> transition.
>
> The purpose is for debug as user can query SDM on HPS error details when HPS
> enters a warm reset due to error such as watchdog.
>
> Signed-off-by: Jit Loon Lim
> ---
> arch/arm/mach-socfpga/spl_s10.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-
> socfpga/spl_s10.c index c20e87cdbe..9bfd1a0f6a 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -92,3 +92,9 @@ void board_init_f(ulong dummy)
> mbox_qspi_open();
> #endif
> }
> +
> +/* board specific function prior loading SSBL / U-Boot */ void
> +spl_board_prepare_for_boot(void) {
> + mbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
> +}
You should put this notify into spl_perform_fixups(), so this can used by both
boot flows:
SPL -> U-Boot and SPL -> ATF -> U-Boot.
Regards
Tien Fong
RE: [PATCH] arch: arm: mach-socfpga: Add mailbox command for HPS execution stage notification
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 31 August, 2022 1:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R ;
> Vasut, Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Lim, Elly Siew Chin ;
> Kho, Sin Hui ; Lokanathan, Raaj
> ; Maniyam, Dinesh ;
> Ng, Boon Khai ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Tang, Sieu Mun
> ; Lim, Jit Loon ; Chin Liang
> See
> Subject: [PATCH] arch: arm: mach-socfpga: Add mailbox command for HPS
> execution stage notification
>
> From: Chin Liang See
>
> Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
> Manager (SDM) on the stage of HPS code execution. In general, there are three
> main code execution stages: First Stage Boot Loader (FSBL) which is U-Boot
> SPL,
> Second Stage Boot Loader (SSBL) which is U-Boot, and the Operating System
> which is Linux
>
> Signed-off-by: Chin Liang See
> Signed-off-by: Jit Loon Lim
> ---
> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++
> arch/arm/mach-socfpga/mailbox_s10.c | 6 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> index fbaf11597e..87af6f1cfe 100644
> --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
> #define MBOX_QSPI_CLOSE 51
> #define MBOX_QSPI_DIRECT 59
> #define MBOX_REBOOT_HPS 71
> +#define MBOX_HPS_STAGE_NOTIFY93
>
> /* Mailbox registers */
> #define MBOX_CIN 0 /* command valid offset */
> @@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE {
> #define RCF_SOFTFUNC_STATUS_SEU_ERRORBIT(3)
> #define RCF_PIN_STATUS_NSTATUS BIT(31)
>
> +/* Defines for HPS_STAGE_NOTIFY */
> +#define HPS_EXECUTION_STATE_FSBL 0
> +#define HPS_EXECUTION_STATE_SSBL 1
> +#define HPS_EXECUTION_STATE_OS 2
> +
> int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8
> urgent,
> u32 *resp_buf_len, u32 *resp_buf);
> int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@
> -182,6 +188,7 @@ int mbox_qspi_open(void); #endif
>
> int mbox_reset_cold(void);
> +int mbox_hps_stage_notify(u32 execution_stage);
> int mbox_get_fpga_config_status(u32 cmd); int
> mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-
> socfpga/mailbox_s10.c
> index 101af23855..e86d9bf214 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8
> is_indirect, u32 len,
> urgent, resp_buf_len, resp_buf); }
>
> +int mbox_hps_stage_notify(u32 execution_stage) {
> + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY,
> + MBOX_CMD_DIRECT, 1, _stage, 0, 0,
> NULL); }
> +
> int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) {
> return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
> --
> 2.26.2
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH 016/347] FogBugz #516535: Fix QSPI write issues
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Tuesday, 2 August, 2022 9:55 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R ;
> Vasut, Marek ; Simon ;
> Chaplin, Kris ; Chee, Tien Fong
> ; Hea, Kok Kiang ; Lim,
> Elly Siew Chin ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Chee Hong Ang
> Subject: [PATCH 016/347] FogBugz #516535: Fix QSPI write issues
Please drop the "[PATCH 016/347]" and replace "FogBugz #516535" with
appropriate tag.
>
> From: Chee Hong Ang
>
> QSPI driver perform chip select on every flash read/write access. The driver
> need
> to disable/enable the QSPI controller while performing chip select. This may
> cause some data lost especially the QSPI controller is configured to run at
> slower speed as it may take longer time to access the flash device.
> This patch prevent the driver from disable/enable the QSPI controller too soon
> and inadvertently halting any ongoing flash read/write access by ensuring the
> QSPI controller is always in idle mode after each read/write access.
>
> Signed-off-by: Chee Hong Ang
> ---
> drivers/spi/cadence_qspi_apb.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index 2cdf4c9c9f..5e03495f45 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct
> cadence_spi_plat *plat,
> writel(CQSPI_REG_INDIRECTRD_DONE,
> plat->regbase + CQSPI_REG_INDIRECTRD);
>
> - /* Check indirect done status */
> - ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
> - CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
> - if (ret) {
> - printf("Indirect read clear completion error (%i)\n", ret);
> - goto failrd;
> - }
> + /* Wait til QSPI is idle */
> + if (!cadence_qspi_wait_idle(plat->regbase))
> + return -EIO;
>
> return 0;
>
> @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct
> cadence_spi_plat *plat,
>
> if (bounce_buf)
> free(bounce_buf);
> +
> + /* Wait til QSPI is idle */
> + if (!cadence_qspi_wait_idle(plat->regbase))
> + return -EIO;
> +
> return 0;
>
> failwr:
> --
> 2.25.1
Regards,
Tien Fong
Pull request: SoCFPGA changes for commit 05dcb5be507a
Hi Tom, Please pull the SoCFPGA changes as shown in below. Thanks. Best regards, Tien Fong The following changes since commit 05dcb5be507a0580a0fc57dd363c632ac4a6b3c4: mtd: mxs_nand_spl: fix nand_command protocol violation (2022-06-29 09:26:44 -0400) are available in the Git repository at: https://github.com/tienfong/uboot_mainline.git ef5ba2cef4a08b68caaa9215fcac142d3025bbf7 for you to fetch changes up to ef5ba2cef4a08b68caaa9215fcac142d3025bbf7: drivers: clk: Update license for Intel N5X device (2022-07-01 15:00:39 +0800) Paweł Anikiel (11): arm: dts: Add Mercury+ AA1 devicetrees arm: dts: Add Chameleonv3 handoff headers arm: dts: Add Chameleonv3 devicetrees board: Add Chameleonv3 board dir config: Add Chameleonv3 config misc: atsha204a: Increase wake delay by tWHI sysreset: socfpga: Use parent device for reading base address socfpga: arria10: Replace delays with busy waiting in cm_full_cfg socfpga: arria10: Improve bitstream loading speed socfpga: arria10: Wait for fifo empty after writing bitstream socfpga: arria10: Allow dcache_enable before relocation Teik Heng Chong (1): drivers: clk: Update license for Intel N5X device arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 ++ arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts | 5 + arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h | 305 +++ arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 ++ arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts | 5 + arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h | 305 +++ arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 ++ arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 + arch/arm/mach-socfpga/Kconfig | 7 ++ arch/arm/mach-socfpga/clock_manager_arria10.c | 31 -- arch/arm/mach-socfpga/misc_arria10.c | 26 + board/google/chameleonv3/Makefile | 5 + board/google/chameleonv3/board.c | 27 + board/google/chameleonv3/fpga.its | 28 + board/google/chameleonv3/fpga_early_io.its | 35 +++ board/google/chameleonv3/mercury_aa1.c | 43 board/google/chameleonv3/mercury_aa1.h | 12 +++ configs/socfpga_chameleonv3_defconfig | 29 ++ drivers/clk/altera/clk-mem-n5x.c | 4 +- drivers/clk/altera/clk-mem-n5x.h | 4 +- drivers/clk/altera/clk-n5x.c | 4 +- drivers/clk/altera/clk-n5x.h | 4 +- drivers/fpga/socfpga_arria10.c | 28 - drivers/misc/atsha204a-i2c.c | 5 +- drivers/sysreset/sysreset_socfpga.c| 2 +- include/configs/socfpga_chameleonv3.h | 44 28 files changed, 1170 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi create mode 100644 board/google/chameleonv3/Makefile create mode 100644 board/google/chameleonv3/board.c create mode 100644 board/google/chameleonv3/fpga.its create mode 100644 board/google/chameleonv3/fpga_early_io.its create mode 100644 board/google/chameleonv3/mercury_aa1.c create mode 100644 board/google/chameleonv3/mercury_aa1.h create mode 100644 configs/socfpga_chameleonv3_defconfig create mode 100644 include/configs/socfpga_chameleonv3.h
RE: [Update license 1/1] drivers: clk: Update license for Intel N5X device
> -Original Message- > From: Chong, Teik Heng > Sent: Wednesday, 29 June, 2022 1:52 PM > To: u-boot@lists.denx.de > Cc: Lukasz ; Sean ; Simon > ; Chaplin, Kris ; > Hea, Kok Kiang ; Chee, Tien Fong > ; Lim, Elly Siew Chin > ; Kho, Sin Hui ; > Lokanathan, Raaj ; Maniyam, Dinesh > ; Ng, Boon Khai ; > Yuslaimi, Alif Zakuan ; Chong, Teik Heng > > Subject: [Update license 1/1] drivers: clk: Update license for Intel N5X > device > > From: Teik Heng Chong > > All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel, update the > license to use both GPL2.0 and BSD-3 Clause because this copy of code may > used for open source and internal project. > > Signed-off-by: Teik Heng Chong > --- > drivers/clk/altera/clk-mem-n5x.c | 4 ++-- drivers/clk/altera/clk-mem-n5x.h > | 4 ++-- > drivers/clk/altera/clk-n5x.c | 4 ++-- > drivers/clk/altera/clk-n5x.h | 4 ++-- > 4 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem- > n5x.c > index ca44998641..9bbe2cd0ca 100644 > --- a/drivers/clk/altera/clk-mem-n5x.c > +++ b/drivers/clk/altera/clk-mem-n5x.c > @@ -1,6 +1,6 @@ > -// SPDX-License-Identifier: GPL-2.0 > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause > /* > - * Copyright (C) 2020-2021 Intel Corporation > + * Copyright (C) 2020-2022 Intel Corporation > */ > > #include > diff --git a/drivers/clk/altera/clk-mem-n5x.h b/drivers/clk/altera/clk-mem- > n5x.h > index d000ae260c..7b687012e8 100644 > --- a/drivers/clk/altera/clk-mem-n5x.h > +++ b/drivers/clk/altera/clk-mem-n5x.h > @@ -1,6 +1,6 @@ > -/* SPDX-License-Identifier: GPL-2.0 */ > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ > /* > - * Copyright (C) 2020-2021 Intel Corporation > + * Copyright (C) 2020-2022 Intel Corporation > */ > > #ifndef _CLK_MEM_N5X_ > diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index > bdcbbaae91..3fa19e05c4 100644 > --- a/drivers/clk/altera/clk-n5x.c > +++ b/drivers/clk/altera/clk-n5x.c > @@ -1,6 +1,6 @@ > -// SPDX-License-Identifier: GPL-2.0 > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause > /* > - * Copyright (C) 2020-2021 Intel Corporation > + * Copyright (C) 2020-2022 Intel Corporation > */ > > #include > diff --git a/drivers/clk/altera/clk-n5x.h b/drivers/clk/altera/clk-n5x.h index > 8c00e90f89..f6a9f0a794 100644 > --- a/drivers/clk/altera/clk-n5x.h > +++ b/drivers/clk/altera/clk-n5x.h > @@ -1,6 +1,6 @@ > -/* SPDX-License-Identifier: GPL-2.0 */ > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ > /* > - * Copyright (C) 2020-2021 Intel Corporation > + * Copyright (C) 2020-2022 Intel Corporation > */ > > #ifndef _CLK_N5X_ > -- > 2.26.2 Reviewed-by: Tien Fong Chee
RE: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
> -Original Message- > From: Paweł Anikiel > Sent: Tuesday, 21 June, 2022 12:00 AM > To: Chee, Tien Fong > Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com; > michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org; > feste...@denx.de; ja...@amarulasolutions.com; > andre.przyw...@arm.com; Armstrong, Neil ; > pbrobin...@gmail.com; thar...@gateworks.com; paul@linaro.org; > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com; > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew Chin > ; upstr...@semihalf.com; > ams...@chromium.org > Subject: Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy > waiting in cm_full_cfg > > On Mon, Jun 20, 2022 at 2:29 PM Chee, Tien Fong > wrote: > > > > > > > > > -Original Message- > > > From: Paweł Anikiel > > > Sent: Monday, 20 June, 2022 8:14 PM > > > To: Chee, Tien Fong > > > Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com; > > > michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org; > > > feste...@denx.de; ja...@amarulasolutions.com; > > > andre.przyw...@arm.com; Armstrong, Neil ; > > > pbrobin...@gmail.com; thar...@gateworks.com; paul@linaro.org; > > > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com; > > > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew > Chin > > > ; upstr...@semihalf.com; > > > ams...@chromium.org > > > Subject: Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with > > > busy waiting in cm_full_cfg > > > > > > On Mon, Jun 20, 2022 at 10:40 AM Chee, Tien Fong > > > wrote: > > > > > > > > Hi, > > > > > > > > > -Original Message- > > > > > From: Paweł Anikiel > > > > > Sent: Friday, 17 June, 2022 6:47 PM > > > > > To: Vasut, Marek ; > > > > > simon.k.r.goldschm...@gmail.com; Chee, Tien Fong > > > > > ; michal.si...@xilinx.com > > > > > Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de; > > > > > ja...@amarulasolutions.com; andre.przyw...@arm.com; Armstrong, > > > Neil > > > > > ; pbrobin...@gmail.com; > > > > > thar...@gateworks.com; paul@linaro.org; > > > > > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com; > > > > > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew > > > Chin > > > > > ; upstr...@semihalf.com; > > > > > ams...@chromium.org; Paweł Anikiel > > > > > Subject: [PATCH v3 08/11] socfpga: arria10: Replace delays with > > > > > busy waiting in cm_full_cfg > > > > > > > > > > Using udelay while the clocks aren't fully configured causes the > > > > > timer system to save the wrong clock rate. Use sdelay and > > > > > wait_on_value instead (the values used in these functions were > > > > > found > > > experimentally). > > > > > > > > > > Signed-off-by: Paweł Anikiel > > > > > --- > > > > > arch/arm/mach-socfpga/clock_manager_arria10.c | 31 > > > > > +- > > > > > - > > > > > 1 file changed, 22 insertions(+), 9 deletions(-) > > > > > > > > > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c > > > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c > > > > > index 58d5d3fd8a..b48a2b47bc 100644 > > > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c > > > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c > > > > > > > > Did you try to call timer_init() after cm_basic_init() in > > > > board_init_f? If that's > > > working, then no change is required to fix this clock issue. > > > > > > Seems like timer_init() isn't implemented on Arria 10 (it defaults > > > to the return 0 stub). I also tried dm_timer_init(), no luck. > > > > > > I did some code digging, the clock rate is read by clk_get_rate(), > > > and the timer rate is set by dw_apb_timer_probe() > > > (drivers/timer/dw-apb- timer.c:77), and there doesn't seem to be a > > > good way of updating that value later. > > > > > > The only other function I could find that sets the timer rate is > > > timer_pre_probe() from drivers/timer/timer-uclass.c, which very much > > > looks like what we need, but it's static and the name suggests it > > > shouldn't be
RE: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
> -Original Message- > From: Paweł Anikiel > Sent: Monday, 20 June, 2022 8:14 PM > To: Chee, Tien Fong > Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com; > michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org; > feste...@denx.de; ja...@amarulasolutions.com; > andre.przyw...@arm.com; Armstrong, Neil ; > pbrobin...@gmail.com; thar...@gateworks.com; paul@linaro.org; > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com; > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew Chin > ; upstr...@semihalf.com; > ams...@chromium.org > Subject: Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy > waiting in cm_full_cfg > > On Mon, Jun 20, 2022 at 10:40 AM Chee, Tien Fong > wrote: > > > > Hi, > > > > > -Original Message- > > > From: Paweł Anikiel > > > Sent: Friday, 17 June, 2022 6:47 PM > > > To: Vasut, Marek ; simon.k.r.goldschm...@gmail.com; > > > Chee, Tien Fong ; michal.si...@xilinx.com > > > Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de; > > > ja...@amarulasolutions.com; andre.przyw...@arm.com; Armstrong, > Neil > > > ; pbrobin...@gmail.com; > > > thar...@gateworks.com; paul@linaro.org; > > > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com; > > > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew > Chin > > > ; upstr...@semihalf.com; > > > ams...@chromium.org; Paweł Anikiel > > > Subject: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy > > > waiting in cm_full_cfg > > > > > > Using udelay while the clocks aren't fully configured causes the > > > timer system to save the wrong clock rate. Use sdelay and > > > wait_on_value instead (the values used in these functions were found > experimentally). > > > > > > Signed-off-by: Paweł Anikiel > > > --- > > > arch/arm/mach-socfpga/clock_manager_arria10.c | 31 > > > +- > > > - > > > 1 file changed, 22 insertions(+), 9 deletions(-) > > > > > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c > > > index 58d5d3fd8a..b48a2b47bc 100644 > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c > > > > Did you try to call timer_init() after cm_basic_init() in board_init_f? If > > that's > working, then no change is required to fix this clock issue. > > Seems like timer_init() isn't implemented on Arria 10 (it defaults to the > return 0 stub). I also tried dm_timer_init(), no luck. > > I did some code digging, the clock rate is read by clk_get_rate(), and the > timer rate is set by dw_apb_timer_probe() (drivers/timer/dw-apb- > timer.c:77), and there doesn't seem to be a good way of updating that value > later. > > The only other function I could find that sets the timer rate is > timer_pre_probe() from drivers/timer/timer-uclass.c, which very much looks > like what we need, but it's static and the name suggests it shouldn't be > called > manually anyway. > Thanks for the details finding. I found that both Cyclone 5 and S10 (including all AARCH64 devices) having own timer_init() as solution for this issue. Cyclone 5 : https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-socfpga/timer.c S10: https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-socfpga/timer_s10.c Do you think this is good idea having the same for A10 device? Best regards, Tien Fong.
RE: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Hi, > -Original Message- > From: Paweł Anikiel > Sent: Friday, 17 June, 2022 6:47 PM > To: Vasut, Marek ; simon.k.r.goldschm...@gmail.com; > Chee, Tien Fong ; michal.si...@xilinx.com > Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de; > ja...@amarulasolutions.com; andre.przyw...@arm.com; Armstrong, Neil > ; pbrobin...@gmail.com; > thar...@gateworks.com; paul@linaro.org; christianshew...@gmail.com; > adrian.fiergol...@fastree3d.com; marek.be...@nic.cz; Denk, Wolfgang > ; Lim, Elly Siew Chin ; > upstr...@semihalf.com; ams...@chromium.org; Paweł Anikiel > > Subject: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting > in cm_full_cfg > > Using udelay while the clocks aren't fully configured causes the timer system > to save the wrong clock rate. Use sdelay and wait_on_value instead (the > values used in these functions were found experimentally). > > Signed-off-by: Paweł Anikiel > --- > arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +- > - > 1 file changed, 22 insertions(+), 9 deletions(-) > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c > b/arch/arm/mach-socfpga/clock_manager_arria10.c > index 58d5d3fd8a..b48a2b47bc 100644 > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c Did you try to call timer_init() after cm_basic_init() in board_init_f? If that's working, then no change is required to fix this clock issue. Thanks. Best regards, Tien Fong.
Pull request: SoCFPGA changes for commit c18e5fb055ab
Hi Tom, Please pull the SoCFPGA changes as shown in below. Thanks. Best regards, Tien Fong The following changes since commit c18e5fb055ab789f58434e3cb432582adee0134c: dtoc: Update test_src_scan.py for new tegra compatibles (2022-06-14 13:59:23 -0400) are available in the Git repository at: https://github.com/tienfong/uboot_mainline.git 32e0379143b433e29d76404f5f4c279067e48853 for you to fetch changes up to 32e0379143b433e29d76404f5f4c279067e48853: ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched (2022-06-17 16:27:05 +0800) Dinesh Maniyam (5): arch: arm: socfpga: timer_s10: Override udelay for secure section arm: dts: socfpga: agilex: Add freeze controller node arm: dts: socfpga: stratix10: Add freeze controller node drivers: cache: ncore: Disable snoop filter ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched Marek Vasut (1): arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script Tien Fong Chee (3): intel: n5x: ddr: update license ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS ddr: altera: Stratix10: Use phys_size_t for memory size Yau Wai Gan (1): arm: dts: socfpga: stratix10: Update MMC smplsel value arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi| 11 ++- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +- arch/arm/mach-socfpga/timer_s10.c| 34 +- drivers/cache/cache-ncore.c | 6 +++--- drivers/ddr/altera/sdram_n5x.c | 4 ++-- drivers/ddr/altera/sdram_s10.c | 4 ++-- drivers/ddr/altera/sdram_soc64.c | 5 +++-- drivers/ddr/altera/sdram_soc64.h | 2 +- include/configs/socfpga_vining_fpga.h| 3 ++- 10 files changed, 67 insertions(+), 15 deletions(-)
RE: [PATCH v3] ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Wednesday, 1 June, 2022 6:49 PM
> To: u-boot@lists.denx.de
> Cc: Vasut, Marek ; Simon Goldschmidt
> ; Lim, Elly Siew Chin
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh
> Subject: [PATCH v3] ddr: altera: soc64: Integer fix overflow that caused DDR
> size mismatched
>
> From: Dinesh Maniyam
>
> Convert the constant integer to 'phys_size_t' to avoid overflow when
> calculating the SDRAM size.
>
> Signed-off-by: Dinesh Maniyam
>
> ---
>
> v3->v2
> - copyright year updated and alignment updated.
>
> v2->v1
> - add space in title
> ---
> drivers/ddr/altera/sdram_soc64.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ddr/altera/sdram_soc64.c
> b/drivers/ddr/altera/sdram_soc64.c
> index d6baac2410..9b1710c135 100644
> --- a/drivers/ddr/altera/sdram_soc64.c
> +++ b/drivers/ddr/altera/sdram_soc64.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2016-2021 Intel Corporation
> + * Copyright (C) 2016-2022 Intel Corporation
> *
> */
>
> @@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct
> altera_sdram_plat *plat) {
> u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
>
> - phys_size_t size = 1 <<
> (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
> + phys_size_t size = (phys_size_t)1 <<
> + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw)
> +
>
> DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
>
> DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
>
> DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
> --
> 2.25.1
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH] drivers: cache: ncore: Disable snoop filter
> -Original Message- > From: Maniyam, Dinesh > Sent: Wednesday, 1 June, 2022 3:57 PM > To: u-boot@lists.denx.de > Cc: Vasut, Marek ; Simon Goldschmidt > ; Chee, Tien Fong > ; Hea, Kok Kiang ; > Gan, Yau Wai ; Kho, Sin Hui > ; Lokanathan, Raaj ; > Maniyam, Dinesh > Subject: [PATCH] drivers: cache: ncore: Disable snoop filter > > From: Dinesh Maniyam > > There is hardware bug in NCORE CCU IP and it is causing an issue in the > coherent directory tracking of outstanding cache lines. > The workaround is disabling snoop filter. > > Signed-off-by: Dinesh Maniyam > --- > drivers/cache/cache-ncore.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c index > 3beff780de..117d2b91ab 100644 > --- a/drivers/cache/cache-ncore.c > +++ b/drivers/cache/cache-ncore.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Copyright (C) 2019 Intel Corporation > + * Copyright (C) 2019-2022 Intel Corporation > * > */ > #include > @@ -81,8 +81,8 @@ static void ncore_ccu_init_dirs(void __iomem *base) > hang(); > } > > - /* Enable snoop filter, a bit per snoop filter */ > - setbits_le32((ulong)CCU_DIR_REG_ADDR(base, > DIRUSFER, i), > + /* Disable snoop filter, a bit per snoop filter */ > + clrbits_le32((ulong)CCU_DIR_REG_ADDR(base, > DIRUSFER, i), >BIT(f)); > } > } > -- > 2.25.1 Reviewed-by: Tien Fong Chee Regards Tien Fong
RE: [PATCH] arch: arm: socfpga: timer_s10: Override udelay for secure section
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Wednesday, 1 June, 2022 3:55 PM
> To: u-boot@lists.denx.de
> Cc: Vasut, Marek ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Chee Hong Ang
>
> Subject: [PATCH] arch: arm: socfpga: timer_s10: Override udelay for secure
> section
>
> From: Dinesh Maniyam
>
> Override __udelay() as 'always inlined' function so that PSCI code run in
> '__secure' section can call this delay function as well.
>
> Signed-off-by: Chee Hong Ang
> Signed-off-by: Dinesh Maniyam
> ---
> arch/arm/mach-socfpga/timer_s10.c | 35
> ++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-
> socfpga/timer_s10.c
> index 7d5598e1a3..33afc87749 100644
> --- a/arch/arm/mach-socfpga/timer_s10.c
> +++ b/arch/arm/mach-socfpga/timer_s10.c
> @@ -1,11 +1,12 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2017-2018 Intel Corporation
> + * Copyright (C) 2017-2022 Intel Corporation
> *
> */
>
> #include
> #include
> +#include
> #include
> #include
>
> @@ -26,3 +27,35 @@ int timer_init(void)
> #endif
> return 0;
> }
> +
> +__always_inline u64 __get_time_stamp(void) {
> + u64 cntpct;
> +
> + isb();
> + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
> +
> + return cntpct;
> +}
> +
> +__always_inline uint64_t __usec_to_tick(unsigned long usec) {
> + u64 tick = usec;
> + u64 cntfrq;
> +
> + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
> + tick *= cntfrq;
> + do_div(tick, 100);
> +
> + return tick;
> +}
> +
> +__always_inline void __udelay(unsigned long usec) {
> + /* get current timestamp */
> + u64 tmp = __get_time_stamp() + __usec_to_tick(usec);
> +
> + while (__get_time_stamp() < tmp + 1)/* loop till event */
> + ;
> +}
> +
> --
> 2.25.1
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH] arm: dts: socfpga: stratix10: Add freeze controller node
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Tuesday, 31 May, 2022 4:15 PM
> To: u-boot@lists.denx.de
> Cc: Chee, Tien Fong ; Hea, Kok Kiang
> ; Gan, Yau Wai ; Kho,
> Sin Hui ; Lokanathan, Raaj
> ; Maniyam, Dinesh
>
> Subject: [PATCH] arm: dts: socfpga: stratix10: Add freeze controller node
>
> From: Dinesh Maniyam
>
> The freeze controller is required for FPGA partial reconfig.
> This node is disable on default.
> Enable this node via u-boot fdt command when needed.
>
> Signed-off-by: Yau Wai Gan
> Signed-off-by: Dinesh Maniyam
> ---
> arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> index 61df425f14..75a29045da 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> @@ -2,7 +2,7 @@
> /*
> * U-Boot additions
> *
> - * Copyright (C) 2019-2020 Intel Corporation
> + * Copyright (C) 2019-2022 Intel Corporation
> */
>
> #include "socfpga_stratix10-u-boot.dtsi"
> @@ -10,6 +10,15 @@
> /{
> aliases {
> spi0 =
> + freeze_br0 = _controller;
> + };
> +
> + soc {
> + freeze_controller: freeze_controller@f9000450 {
> + compatible = "altr,freeze-bridge-controller";
> + reg = <0xf9000450 0x0010>;
> + status = "disabled";
> + };
> };
> };
>
> --
> 2.25.1
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH] arm: dts: socfpga: agilex: Add freeze controller node
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Tuesday, 31 May, 2022 4:06 PM
> To: u-boot@lists.denx.de
> Cc: Chee, Tien Fong ; Hea, Kok Kiang
> ; Gan, Yau Wai ; Kho,
> Sin Hui ; Lokanathan, Raaj
> ; Maniyam, Dinesh
>
> Subject: [PATCH] arm: dts: socfpga: agilex: Add freeze controller node
>
> From: Dinesh Maniyam
>
> The freeze controller is required for FPGA partial reconfig.
> This node is disable on default.
> Enable this node via u-boot fdt command when needed.
>
> Signed-off-by: Yau Wai Gan
> Signed-off-by: Dinesh Maniyam
> ---
> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> index 6cac36a1fc..2400fad18a 100644
> --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> @@ -2,7 +2,7 @@
> /*
> * U-Boot additions
> *
> - * Copyright (C) 2019 Intel Corporation
> + * Copyright (C) 2019-2022 Intel Corporation
> */
>
> #include "socfpga_agilex-u-boot.dtsi"
> @@ -11,6 +11,15 @@
> aliases {
> spi0 =
> i2c0 =
> + freeze_br0 = _controller;
> + };
> +
> + soc {
> + freeze_controller: freeze_controller@f9000450 {
> + compatible = "altr,freeze-bridge-controller";
> + reg = <0xf9000450 0x0010>;
> + status = "disabled";
> + };
> };
>
> memory {
> --
> 2.26.2
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH v2 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Hi Pawel,
> -Original Message-
> From: Paweł Anikiel
> Sent: Thursday, 26 May, 2022 10:37 PM
> To: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> Chee, Tien Fong ; michal.si...@xilinx.com
> Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de;
> ja...@amarulasolutions.com; andre.przyw...@arm.com; Armstrong, Neil
> ; pbrobin...@gmail.com;
> thar...@gateworks.com; paul@linaro.org; christianshew...@gmail.com;
> adrian.fiergol...@fastree3d.com; marek.be...@nic.cz; Denk, Wolfgang
> ; Lim, Elly Siew Chin ;
> m...@semihalf.com; Paweł Anikiel
> Subject: [PATCH v2 08/11] socfpga: arria10: Replace delays with busy waiting
> in cm_full_cfg
>
> Using udelay while the clocks aren't fully configured causes the timer system
> to save the wrong clock rate. Use sdelay and wait_on_value instead (the
> values used in these functions were found experimentally).
>
> Signed-off-by: Paweł Anikiel
> ---
> arch/arm/mach-socfpga/clock_manager.c | 7 ---
> arch/arm/mach-socfpga/clock_manager_arria10.c | 12 ++--
> arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
> 3 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-
> socfpga/clock_manager.c
> index 9e645a4253..c9bd4859f7 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -39,9 +39,10 @@ void cm_wait_for_lock(u32 mask)
> /* function to poll in the fsm busy bit */ int cm_wait_for_fsm(void) {
> - return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr()
> +
> - CLKMGR_STAT), CLKMGR_STAT_BUSY, false,
> 2,
> - false);
> + void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
> +
> + /* 20s timeout */
> + return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 1);
This change breaking the socfpga_stratix10_atf_defconfig build(all aarch64
socfpga are impacted), can you fix it ?
aarch64-none-linux-gnu-ld.bfd: arch/arm/mach-socfpga/clock_manager.o: in
function `cm_wait_for_fsm':
/nfs/png/disks/swuser_work_tfchee/uboot_mainline/denx/u-boot/arch/arm/mach-socfpga/clock_manager.c:45:
undefined reference to `wait_on_value'
/nfs/png/disks/swuser_work_tfchee/uboot_mainline/denx/u-boot/arch/arm/mach-socfpga/clock_manager.c:45:(.text.cm_wait_for_fsm+0x24):
relocation truncated to fit: R_AARCH64_JUMP26 against undefined symbol
`wait_on_value'
make[1]: *** [scripts/Makefile.spl:525: spl/u-boot-spl] Error 1
make: *** [Makefile:2106: spl/u-boot-spl] Error 2
aarch64-none-linux-gnu-objcopy: 'spl/u-boot-spl-dtb.bin': No such file
Thanks.
Best regards,
Tien Fong.
RE: [PATCH v2 00/11] Add Chameleon v3 support
Hi, > -Original Message- > From: Paweł Anikiel > Sent: Wednesday, 15 June, 2022 7:08 PM > To: Simon Goldschmidt > Cc: U-Boot Mailing List ; Simon Glass > ; Fabio Estevam ; Jagan Teki > ; Andre Przywara ; > Armstrong, Neil ; Peter Robinson > ; Tim Harvey ; Ying-Chun > Liu ; Christian Hewitt ; > adrian.fiergol...@fastree3d.com; Marek Behún ; Denk, > Wolfgang ; Lim, Elly Siew Chin ; > Chee, Tien Fong ; Michal Simek > ; Vasut, Marek ; Marcin Wojtas > > Subject: Re: [PATCH v2 00/11] Add Chameleon v3 support > > On Thu, May 26, 2022 at 4:37 PM Paweł Anikiel wrote: > > > > The Google Chameleon v3 is a board made for testing both video and > > audio interfaces of external devices. It has a connector compatible > > with the > > Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The > > Mercury+ AA1 > > module comes in a few different configurations, the Chameleon V3 > > supports > > ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E. > > > > This patchset adds support for the Chameleon v3 (both versions), as > > well as some bugfixes and optimizations, mostly in Arria 10 code. > > > > V2: > > Adjust devicetrees so that they work both in u-boot and linux > > Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files > > Minor changes in Kconfig, defconfig, and config.h > > > > Paweł Anikiel (11): > > arm: dts: Add Mercury+ AA1 devicetrees > > arm: dts: Add Chameleonv3 handoff headers > > arm: dts: Add Chameleonv3 devicetrees > > board: Add Chameleonv3 board dir > > config: Add Chameleonv3 config > > misc: atsha204a: Increase wake delay by tWHI > > sysreset: socfpga: Use parent device for reading base address > > socfpga: arria10: Replace delays with busy waiting in cm_full_cfg > > socfpga: arria10: Improve bitstream loading speed > > socfpga: arria10: Wait for fifo empty after writing bitstream > > socfpga: arria10: Allow dcache_enable before relocation > > > > arch/arm/dts/Makefile | 2 + > > arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 ++ > > ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 + > > .../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 + > > ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 > ++ > > ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 + > > .../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 + > > ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 > ++ > > .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 > > arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 + > > arch/arm/mach-socfpga/Kconfig | 7 + > > arch/arm/mach-socfpga/clock_manager.c | 7 +- > > arch/arm/mach-socfpga/clock_manager_arria10.c | 12 +- > > .../mach-socfpga/include/mach/clock_manager.h | 4 + > > arch/arm/mach-socfpga/misc_arria10.c | 26 ++ > > board/google/chameleonv3/Makefile | 5 + > > board/google/chameleonv3/board.c | 27 ++ > > board/google/chameleonv3/fpga.its | 28 ++ > > board/google/chameleonv3/fpga_early_io.its| 35 ++ > > board/google/chameleonv3/mercury_aa1.c| 43 +++ > > board/google/chameleonv3/mercury_aa1.h| 12 + > > configs/socfpga_chameleonv3_defconfig | 29 ++ > > drivers/fpga/socfpga_arria10.c| 28 +- > > drivers/misc/atsha204a-i2c.c | 5 +- > > drivers/sysreset/sysreset_socfpga.c | 2 +- > > include/configs/socfpga_chameleonv3.h | 44 +++ > > 26 files changed, 1154 insertions(+), 14 deletions(-) create mode > > 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts > > create mode 100644 > > arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi > > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts > > create mode 100644 > > arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h > > create mode 100644 > > arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi > > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts > > create mode 100644 > > arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h > > create mode 100644 > > arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi > > create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi > > create mode 100644 board/google/chameleonv3/Makefile create mode > > 100644 board/google/chameleonv3/board.c create mode 100644 > > board/google/chameleonv3/fpga.its create mo
RE: [PATCH] intel: n5x: ddr: update license
> -Original Message- > From: Marek Vasut > Sent: Saturday, 11 June, 2022 6:08 PM > To: Chee, Tien Fong ; u-boot@lists.denx.de > Cc: Simon Goldschmidt ; Chaplin, Kris > ; Hea, Kok Kiang ; Kho, Sin > Hui ; Lokanathan, Raaj ; > Maniyam, Dinesh > Subject: Re: [PATCH] intel: n5x: ddr: update license > > On 6/10/22 13:23, tien.fong.c...@intel.com wrote: > > From: Tien Fong Chee > > > > All the source code of sdram_n5x.c are from Intel, update the license > > to use both GPL2.0 and BSD-3 Clause because this copy of code may used > > for open source and internal project. > > > > Signed-off-by: Tien Fong Chee > > That's still fine, since nobody did any other changes to this driver yet. > > Do you plan to collect those socfpga patches yourself and send a PR for next ? Yes, that's my next plan after submitting this patch for review.
RE: [PATCH] arm: socfpga: mailbox: Add mailbox command for HPS execution notifcation
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Friday, 13 May, 2022 10:15 AM
> To: u-boot@lists.denx.de
> Cc: Vasut, Marek ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh
> Subject: [PATCH] arm: socfpga: mailbox: Add mailbox command for HPS
> execution notifcation
>
> From: Dinesh Maniyam
>
> Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
> Manager (SDM) on the stage of HPS code execution. In general, there are
> three main code execution stages: First Stage Boot Loader (FSBL) which is U-
> Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot, and the
> Operating System which is Linux.
>
> Signed-off-by: Dinesh Maniyam
> ---
> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++
> arch/arm/mach-socfpga/mailbox_s10.c | 6 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> index fbaf11597e..50fe6393f9 100644
> --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
> #define MBOX_QSPI_CLOSE 51
> #define MBOX_QSPI_DIRECT 59
> #define MBOX_REBOOT_HPS 71
> +#define MBOX_HPS_STAGE_NOTIFY93
>
> /* Mailbox registers */
> #define MBOX_CIN 0 /* command valid offset */
> @@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE {
> #define RCF_SOFTFUNC_STATUS_SEU_ERRORBIT(3)
> #define RCF_PIN_STATUS_NSTATUS BIT(31)
>
> +/* Defines for HPS_STAGE_NOTIFY */
> +#define HPS_EXECUTION_STATE_FSBL 0
> +#define HPS_EXECUTION_STATE_SSBL 1
> +#define HPS_EXECUTION_STATE_OS 2
> +
> int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8
> urgent,
> u32 *resp_buf_len, u32 *resp_buf);
> int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
> @@ -182,6 +188,7 @@ int mbox_qspi_open(void); #endif
>
> int mbox_reset_cold(void);
> +int mbox_hps_stage_notify(u32 execution_stage);
> int mbox_get_fpga_config_status(u32 cmd); int
> mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_
> */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-
> socfpga/mailbox_s10.c
> index 101af23855..99f78c7c32 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd,
> u8 is_indirect, u32 len,
> urgent, resp_buf_len, resp_buf); }
>
> +int mbox_hps_stage_notify(u32 execution_stage) {
> + return mbox_send_cmd(MBOX_ID_UBOOT,
> MBOX_HPS_STAGE_NOTIFY,
> + MBOX_CMD_DIRECT, 1, _stage, 0,
> 0, NULL); }
> +
Please fix the alignment issue above.
Please extend the year of copyright.
> int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) {
> return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
> --
> 2.26.2
RE: [PATCH v3] fpga: intel_sdm_mb: Add checking for INTEL_SIP_SMC_STATUS_BUSY (1)
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Tuesday, 31 May, 2022 3:51 PM
> To: u-boot@lists.denx.de
> Cc: Michal Simek ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh
> Subject: [PATCH v3] fpga: intel_sdm_mb: Add checking for
> INTEL_SIP_SMC_STATUS_BUSY (1)
>
> From: Dinesh Maniyam
>
> Status busy means transfer is accepted but SDM does not have more freed
> buffer. It is not an error. Continue process the data if receive OK or BUSY
> status.
>
> Signed-off-by: Dinesh Maniyam
>
> ---
>
> v2->v3
> -Copyright year updated and alignment adjusted.
> ---
> drivers/fpga/intel_sdm_mb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
> index f5fd9a14c2..44ef7717d0 100644
> --- a/drivers/fpga/intel_sdm_mb.c
> +++ b/drivers/fpga/intel_sdm_mb.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright (C) 2018 Intel Corporation
> + * Copyright (C) 2018-2022 Intel Corporation
> */
>
> #include
> @@ -70,7 +70,8 @@ static int send_bitstream(const void *rbf_data, size_t
> rbf_size)
> debug("wr_ret = %d, rbf_data = %p, buf_size
> = %08lx\n",
> wr_ret, rbf_data, buf_size);
>
> - if (wr_ret)
> + if (wr_ret != INTEL_SIP_SMC_STATUS_OK &&
> + wr_ret != INTEL_SIP_SMC_STATUS_BUSY)
> continue;
>
> rbf_size -= buf_size;
> --
> 2.25.1
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH] fpga: intel_sdm_mb: Add checking for INTEL_SIP_SMC_STATUS_BUSY (1)
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Monday, 9 May, 2022 3:43 PM
> To: u-boot@lists.denx.de
> Cc: Michal Simek ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Ley Foon Tan
>
> Subject: [PATCH] fpga: intel_sdm_mb: Add checking for
> INTEL_SIP_SMC_STATUS_BUSY (1)
>
> From: Dinesh Maniyam
>
> Status busy means transfer is accepted but SDM does not have more freed
> buffer. It is not an error. Continue process the data if receive OK and BUSY
> status.
Can you help to improve the commit message? That is not possible wr_ret would
return with two results(OK and BUSY) in status at the same time. Please change
to "OK or Busy status".
Please extend the years of copyright to "2018-2022"
>
> Signed-off-by: Ley Foon Tan
> Signed-off-by: Dinesh Maniyam
> ---
> drivers/fpga/intel_sdm_mb.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
> index f5fd9a14c2..5e0b2777e0 100644
> --- a/drivers/fpga/intel_sdm_mb.c
> +++ b/drivers/fpga/intel_sdm_mb.c
> @@ -70,7 +70,8 @@ static int send_bitstream(const void *rbf_data, size_t
> rbf_size)
> debug("wr_ret = %d, rbf_data = %p, buf_size
> = %08lx\n",
> wr_ret, rbf_data, buf_size);
>
> - if (wr_ret)
> + if (wr_ret != INTEL_SIP_SMC_STATUS_OK &&
> + wr_ret != INTEL_SIP_SMC_STATUS_BUSY)
Alignment issue after "(" above, please run the checkpatch.pl
> continue;
>
> rbf_size -= buf_size;
> --
> 2.26.2
RE: [PATCH] arm: dts: socfpga: stratix10: Update MMC smplsel value
> -Original Message-
> From: Gan, Yau Wai
> Sent: Tuesday, 24 May, 2022 3:02 PM
> To: u-boot@lists.denx.de
> Cc: Gan, Yau Wai ; Chee, Tien Fong
>
> Subject: [PATCH] arm: dts: socfpga: stratix10: Update MMC smplsel value
>
> From: Yau Wai Gan
>
> This new MMC sample select value is obtained from running tests on
> multiple Stratix 10 boards and proven working.
>
> Signed-off-by: Yau Wai Gan
> ---
> arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> b/arch/arm/dts/socfpga_stratix10_socdk.dts
> index 6622720f77..8e6a405917 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk.dts
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -93,7 +93,7 @@
> broken-cd;
> bus-width = <4>;
> drvsel = <3>;
> - smplsel = <0>;
> + smplsel = <2>;
> };
>
> {
> --
> 2.13.0
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
RE: [PATCH] arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script
Hi,
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 21 December, 2021 5:58 AM
> To: u-boot@lists.denx.de
> Cc: tr...@konsulko.com; Vasut, Marek ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH] arm: socfpga: vining: Unmount UBIFS and detach UBI in
> ubi_load script
>
> Clean up in ubiload script. Unmount UBIFS from which kernel image was loaded
> and detach UBI on which the UBIFS is located, otherwise message similar to the
> following is printed just before booting kernel:
>
> Removing MTD device #7 (rootfs) with use count 1 Error when deleting partition
> "rootfs" (-16)
>
> Signed-off-by: Marek Vasut
> Cc: Siew Chin Lim
> Cc: Simon Goldschmidt
> Cc: Tien Fong Chee
> ---
> include/configs/socfpga_vining_fpga.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/configs/socfpga_vining_fpga.h
> b/include/configs/socfpga_vining_fpga.h
> index d9d0a4af5ac..5c0ed07c427 100644
> --- a/include/configs/socfpga_vining_fpga.h
> +++ b/include/configs/socfpga_vining_fpga.h
> @@ -118,7 +118,8 @@
> "addargs=run addcons addmtd addmisc\0"
> \
> "ubiload=" \
> "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \
> - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0"\
> + "ubifsload ${kernel_addr_r} /boot/${bootfile} ; " \
> + "ubifsumount ; ubi detach\0"\
> "netload=" \
> "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
> "miscargs=nohlt panic=1\0" \
> --
> 2.34.1
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
Pull request: SoCFPGA changes for clk-2022.01-rc3
Hi Tom, Please pull the SoCFPGA changes for clk-2022.01-rc3. Regards Tien Fong The following changes since commit 5b20efeafec0ebe0ee5742c611e4f2153346797a: Merge tag 'clk-2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-clk (2021-12-15 14:51:44 -0500) are available in the Git repository at: https://github.com/tienfong/uboot_mainline.git 4720b83d2c711062cfb55f03591b8f12c897d7cb for you to fetch changes up to 4720b83d2c711062cfb55f03591b8f12c897d7cb: arm: socfpga: arria10: Enable double peripheral RBF configuration (2021-12-17 12:58:01 +0800) Tien Fong Chee (3): arm: socfpga: arria10: Setting image magic value to romcode initswstate reg arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF arm: socfpga: arria10: Enable double peripheral RBF configuration arch/arm/mach-socfpga/include/mach/misc.h | 7 ++- arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 6 +- arch/arm/mach-socfpga/include/mach/system_manager_arria10.h | 7 ++- arch/arm/mach-socfpga/misc_arria10.c| 126 +- arch/arm/mach-socfpga/spl_a10.c | 120 drivers/fpga/socfpga_arria10.c | 3 ++- 6 files changed, 260 insertions(+), 9 deletions(-)
RE: [PATCH 3/3] arm: socfpga: arria10: Enable double peripheral RBF configuration
> -Original Message- > From: Kho, Sin Hui > Sent: Sunday, 7 November, 2021 11:09 PM > To: u-boot@lists.denx.de > Cc: Simon Goldschmidt ; Marek Vasut > ; Chee, Tien Fong ; Hea, Kok > Kiang ; Westergreen, Dalon > ; Cozart, Sue ; Kho, > Sin Hui > Subject: [PATCH 3/3] arm: socfpga: arria10: Enable double peripheral RBF > configuration > > From: Tien Fong Chee > > Double peripheral RBF configuration are needed on some devices or boards > to stabilize the IO configuration system. > > Signed-off-by: Tien Fong Chee > Signed-off-by: Sin Hui Kho > --- > arch/arm/mach-socfpga/include/mach/misc.h | 2 ++ > arch/arm/mach-socfpga/misc_arria10.c | 36 > +++ > arch/arm/mach-socfpga/spl_a10.c | 14 + > drivers/fpga/socfpga_arria10.c| 3 +- > 4 files changed, 54 insertions(+), 1 deletion(-) > Reviewed-by: Tien Fong Chee
RE: [PATCH 2/3] arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF
> -Original Message- > From: Kho, Sin Hui > Sent: Sunday, 7 November, 2021 11:09 PM > To: u-boot@lists.denx.de > Cc: Simon Goldschmidt ; Marek Vasut > ; Chee, Tien Fong ; Hea, Kok > Kiang ; Westergreen, Dalon > ; Cozart, Sue ; Kho, > Sin Hui > Subject: [PATCH 2/3] arm: socfpga: arria10: Reset MPFE NoC after program > periph / combined RBF > > From: Tien Fong Chee > > This patch triggers warm reset to recover the MPFE NoC from corruption due > to high frequency transient clock output from HPS EMIF IOPLL at VCO startup > after peripheral RBF is programmed. > > Signed-off-by: Tien Fong Chee > Signed-off-by: Sin Hui Kho > --- > arch/arm/mach-socfpga/include/mach/misc.h | 5 +- > .../include/mach/reset_manager_arria10.h | 6 +- > .../include/mach/system_manager_arria10.h | 4 + > arch/arm/mach-socfpga/misc_arria10.c | 90 - > arch/arm/mach-socfpga/spl_a10.c | 96 ++- > 5 files changed, 195 insertions(+), 6 deletions(-) Reviewed-by: Tien Fong Chee
RE: [PATCH 1/3] arm: socfpga: arria10: Setting image magic value to romcode initswstate reg
> -Original Message-
> From: Kho, Sin Hui
> Sent: Sunday, 7 November, 2021 11:09 PM
> To: u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Marek Vasut
> ; Chee, Tien Fong ; Hea, Kok
> Kiang ; Westergreen, Dalon
> ; Cozart, Sue ; Kho, Sin
> Hui
> Subject: [PATCH 1/3] arm: socfpga: arria10: Setting image magic value to
> romcode initswstate reg
>
> From: Tien Fong Chee
>
> The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID
> value if the current FSBL image is found valid, otherwise BootROM will look
> for
> next subsequent valid FSBL image when warm reset is triggered.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Sin Hui Kho
> ---
> .../mach-socfpga/include/mach/system_manager_arria10.h | 3 ++-
> arch/arm/mach-socfpga/spl_a10.c| 10 +-
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> index e4fc6d2e55..75e1fcd80f 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (C) 2016-2017 Intel Corporation
> + * Copyright (C) 2016-2021 Intel Corporation
> */
>
> #ifndef _SYSTEM_MANAGER_ARRIA10_H_
> @@ -31,6 +31,7 @@
> #define SYSMGR_A10_NOC_IDLEACK 0xd0
> #define SYSMGR_A10_NOC_IDLESTATUS0xd4
> #define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
> +#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
>
> #define SYSMGR_SDMMC SYSMGR_A10_SDMMC
>
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-
> socfpga/spl_a10.c index ecb656e4de..f6c4b5708d 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright (C) 2012-2019 Altera Corporation
> + * Copyright (C) 2012-2021 Altera Corporation
> */
>
> #include
> @@ -32,6 +32,7 @@
> #include
>
> #define FPGA_BUFSIZ 16 * 1024
> +#define FSBL_IMAGE_IS_VALID 0x49535756
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -169,3 +170,10 @@ void board_init_f(ulong dummy)
> config_dedicated_pins(gd->fdt_blob);
> WATCHDOG_RESET();
> }
> +
> +/* board specific function prior loading SSBL / U-Boot proper */ void
> +spl_board_prepare_for_boot(void) {
> + writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
> +SYSMGR_A10_ROMCODE_INITSWSTATE); }
> --
> 2.25.1
Reviewed-by: Tien Fong Chee
RE: [PATCH 8/8] arm: socfpga: vining: Let DWMAC configure PHY reset GPIO
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:26 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 8/8] arm: socfpga: vining: Let DWMAC configure PHY reset > GPIO > > The DM DWMAC driver is perfectly capable of configuring the ethernet PHY > reset GPIO, let the driver do it instead of doing it in the board file. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > board/softing/vining_fpga/socfpga.c | 7 --- > 1 file changed, 7 deletions(-) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH 7/8] arm: socfpga: vining: Enable DW I2C driver
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:26 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 7/8] arm: socfpga: vining: Enable DW I2C driver > > The Designware I2C IP is used to communicate with I2C peripherals on > SoCFPGA, and required to access I2C EEPROM on this board. Enable it. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > configs/socfpga_vining_fpga_defconfig | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH 6/8] arm: socfpga: vining: Fix UDC controller phandle in DT
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:26 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 6/8] arm: socfpga: vining: Fix UDC controller phandle in DT > > The USB peripheral controller is the DWC2 controller 1, not 0. > Update the phandle to fix UDC support on this board. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH 5/8] arm: socfpga: vining: Un-disable WDT in DT
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:26 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 5/8] arm: socfpga: vining: Un-disable WDT in DT > > The WDT on this system should be enabled, make it so. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 > 1 file changed, 4 deletions(-) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH 4/8] arm: socfpga: vining: Set default SPI NOR mode and frequency
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:26 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 4/8] arm: socfpga: vining: Set default SPI NOR mode and > frequency > > The SPI NOR bus mode is 0 on this system, update it accordingly. > Increase frequency to 40 MHz and enable SFDP parsing, since the flashes on > this system support that and it is a huge performance improvement. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > configs/socfpga_vining_fpga_defconfig | 3 +++ > 1 file changed, 3 insertions(+) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH 3/8] arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:26 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 3/8] arm: socfpga: vining: Set USB gadget manufacturer to > Softing with capital S > > This was configured in downstream, so it is likely that most of the custom > software used around the device depends on it. Make upstream compatible. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > configs/socfpga_vining_fpga_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH 2/8] arm: socfpga: vining: Increase environment size
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:26 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 2/8] arm: socfpga: vining: Increase environment size > > Increase the environment size from 4k to 16k to prevent environment from > becoming full. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > configs/socfpga_vining_fpga_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH 1/8] arm: socfpga: vining: Drop meaningless comment
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:25 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH 1/8] arm: socfpga: vining: Drop meaningless comment > > The comment is no longer meaningful due to DT conversion, drop it. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > include/configs/socfpga_vining_fpga.h | 2 -- > 1 file changed, 2 deletions(-) > Reviewed-by: Tien Fong Chee Regards, TF
RE: [PATCH] ddr: altera: use KBUILD_BASENAME instead of __FILE__
> -Original Message- > From: Marek Vasut > Sent: Tuesday, 14 September, 2021 11:20 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Lim, Elly Siew Chin > ; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: [PATCH] ddr: altera: use KBUILD_BASENAME instead of __FILE__ > > The KBUILD_BASENAME contains just the name of the compiled module, in this > case 'sequencer', rather than a full path to the compiled file. Use it to > prevent > pulling the full path into the U-Boot binary, which is useless and annoying. > > Signed-off-by: Marek Vasut > Cc: Siew Chin Lim > Cc: Simon Goldschmidt > Cc: Tien Fong Chee > --- > drivers/ddr/altera/sequencer.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > Reviewed-by: Tien Fong Chee Regards, TF
Pull request: SoCFPGA changes for efi-2021-10-rc3
Hi Tom
Please pull the SoCFPGA changes for efi-2021-10-rc3.
Regards
Tien Fong
The following changes since commit 4865db07169126ca0205f1a6265adf01bd69b3df:
Merge tag 'efi-2021-10-rc3' of
https://source.denx.de/u-boot/custodians/u-boot-efi (2021-08-23 12:44:12 -0400)
are available in the Git repository at:
https://github.com/tienfong/uboot_mainline.git next-socfpga
for you to fetch changes up to 31b51cb1d2b4114085cb5565502d39d6f6daa2a7:
arm: socfpga: Enable Intel N5X device build (2021-08-25 15:26:38 +0800)
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux
function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (3):
arm: socfpga: Add handoff data support for Intel N5X device
ddr: socfpga: Enable memory test on memory size less than 1GB
ddr: altera: Add SDRAM driver for Intel N5X device
arch/arm/dts/Makefile |
1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi |
191 +
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi|
63 ++
arch/arm/dts/socfpga_n5x_socdk.dts|
122 +++
arch/arm/mach-socfpga/Kconfig |
21 +-
arch/arm/mach-socfpga/Makefile|
32 ++-
arch/arm/mach-socfpga/board.c |
17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c |
80 +++
arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} |
11 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h|
3 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h |
2 -
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h|
1 -
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h |
1 -
arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h|
12 ++
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h|
1 -
arch/arm/mach-socfpga/include/mach/firewall.h |
6 +
arch/arm/mach-socfpga/include/mach/handoff_soc64.h|
38 +++-
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h |
10 +-
arch/arm/mach-socfpga/misc.c |
3 +
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c}|
12 +-
arch/arm/mach-socfpga/spl_n5x.c |
94 +
arch/arm/mach-socfpga/system_manager_soc64.c |
18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c|
132 +---
board/intel/n5x-socdk/MAINTAINERS |
7 +
board/intel/n5x-socdk/Makefile|
7 +
board/intel/n5x-socdk/socfpga.c |
7 +
configs/socfpga_agilex_atf_defconfig |
2 +-
configs/socfpga_n5x_atf_defconfig |
74 +++
configs/socfpga_n5x_defconfig |
65 ++
configs/socfpga_n5x_vab_defconfig |
75 +++
configs/socfpga_stratix10_atf_defconfig |
2 +-
drivers/clk/altera/Makefile |
4 +-
drivers/clk/altera/clk-mem-n5x.c |
136
drivers/clk/altera/clk-mem-n5x.h |
84
drivers/clk/altera/clk-n5x.c |
489 ++
drivers/clk/altera/clk-n5x.h |
217 +++
drivers/ddr/altera/Makefile |
3 +-
RE: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
Hi, > -Original Message- > From: Tom Rini > Sent: Wednesday, 11 August, 2021 4:57 AM > To: Marek Vasut > Cc: u-boot@lists.denx.de; Simon Goldschmidt > ; Chee, Tien Fong > > Subject: Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS > > On Tue, Aug 10, 2021 at 10:53:02PM +0200, Marek Vasut wrote: > > On 8/10/21 10:47 PM, Tom Rini wrote: > > > On Tue, Aug 10, 2021 at 10:11:08PM +0200, Marek Vasut wrote: > > > > On 8/10/21 10:05 PM, Tom Rini wrote: > > > > > None of the CONFIG_HPS namespace options are changed via the > > > > > board config.h file, nor does it make sense to move them to > > > > > Kconfig. Rename these options to the HPS namespace instead. > > > > > > > > > > Cc: Marek Vasut > > > > > Cc: Simon Goldschmidt > > > > > Cc: Tien Fong Chee > > > > > Signed-off-by: Tom Rini > > > > > --- > > > > > Note, this patch is complete as the changes to the regex > > > > > qts-filter.sh are such a long line that git send-email fails. > > > > > This patch was generated by: > > > > > $ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g' > > > > > and I will re-run that before applying. > > > > > > > > The problem is, it is the altera tools which generate all those > > > > CONFIG_* symbols which are processed by the qts-filter.sh and > > > > placed into those qts/ board directories, so this patch breaks all > > > > that. You'd have to fix the qts-filter to scrub the CONFIG_ prefixes > > > > first. > > > > > > Or rather, ugh, are there out of tree tools we need to deal with here? > > > Perhaps someone with the tools could pick up and v2 something tested > > > if so as it'll probably be a bit tricky getting it all right. > > > > See doc/README.socfpga . The out of tree tools generate > > board/bitstream specific input header files which you plug into the > > qts-filter.sh script , those files contain the CONFIG_* macros and > > those files get converted by the qts-filter.sh script into the output > > header files in board/*/qts/*.h . The output header files are what is used > > by U- > Boot then. > > So doc/README.socfpga needs to be updated to rST as well, when someone > that can run the tools and test the scripts work as expected and don't use the > CONFIG_HPS namespace. Thanks for explaining a bit more. Thanks for cleaning these up, the scripts are also required to get changed and testing. I will work with internal team to get these done, include converting doc/README.socfpga into rST as well. TF > > -- > Tom
RE: [v2 04/17] arm: socfpga: Add handoff data support for Intel N5X device
Hi Simon, > -Original Message- > From: Simon Glass > Sent: Tuesday, 22 June, 2021 9:32 PM > To: Chee, Tien Fong > Cc: Ley Foon Tan ; Lim, Elly Siew Chin > ; ZY - u-boot ; Marek > Vasut ; Tan, Ley Foon ; See, Chin > Liang ; Simon Goldschmidt > ; Westergreen, Dalon > ; Gan, Yau Wai > Subject: Re: [v2 04/17] arm: socfpga: Add handoff data support for Intel N5X > device > > Hi, > > On Mon, 31 May 2021 at 05:39, Chee, Tien Fong > wrote: > > > > Hi Ley Foon, > > > > > -Original Message- > > > From: Ley Foon Tan > > > Sent: Friday, 14 May, 2021 5:13 PM > > > To: Lim, Elly Siew Chin > > > Cc: ZY - u-boot ; Marek Vasut ; > > > Tan, Ley Foon ; See, Chin Liang > > > ; Simon Goldschmidt > > > ; Chee, Tien Fong > > > ; Westergreen, Dalon > > > ; Simon Glass ; Gan, > > > Yau Wai > > > Subject: Re: [v2 04/17] arm: socfpga: Add handoff data support for > > > Intel N5X device > > > > > > On Fri, Apr 30, 2021 at 3:39 PM Siew Chin Lim > > > > > > wrote: > > > > > > > > N5X support both HPS handoff data and DDR handoff data. > > > > Existing HPS handoff functions are restructured to support both > > > > existing devices and N5X device. > > > > > > > > Signed-off-by: Siew Chin Lim > > > > Signed-off-by: Tien Fong Chee > > > > > > > > --- > > > > v2: > > > > - Enabled auto detect the endianness from the magic word > > > > - Merged and simplifying the big and little endian flow > > > > --- > > > > .../mach-socfpga/include/mach/handoff_soc64.h | 38 +- > > > > arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-- > > > > arch/arm/mach-socfpga/wrap_handoff_soc64.c| 126 +-- > > > --- > > > > 3 files changed, 136 insertions(+), 46 deletions(-) > > I'm not too clear on what is happening here, but have you looked at > SPL_HANDOFF or BLOBLIST? Yeah, but these are not for our use case here. Our handoff are generated from the tool, which having user settings. Our secure device manager will pass these handoff to SPL, this driver is mainly for parsing our handoff format to consistent format in the table, which will be consumed and checking other drivers. > > Regards, > Simon Regards, Tien Fong
RE: [v2 04/17] arm: socfpga: Add handoff data support for Intel N5X device
Hi Ley Foon,
> -Original Message-
> From: Ley Foon Tan
> Sent: Friday, 14 May, 2021 5:13 PM
> To: Lim, Elly Siew Chin
> Cc: ZY - u-boot ; Marek Vasut ;
> Tan, Ley Foon ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: Re: [v2 04/17] arm: socfpga: Add handoff data support for Intel N5X
> device
>
> On Fri, Apr 30, 2021 at 3:39 PM Siew Chin Lim
> wrote:
> >
> > N5X support both HPS handoff data and DDR handoff data.
> > Existing HPS handoff functions are restructured to support both
> > existing devices and N5X device.
> >
> > Signed-off-by: Siew Chin Lim
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> > v2:
> > - Enabled auto detect the endianness from the magic word
> > - Merged and simplifying the big and little endian flow
> > ---
> > .../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
> > arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
> > arch/arm/mach-socfpga/wrap_handoff_soc64.c| 126 +--
> ---
> > 3 files changed, 136 insertions(+), 46 deletions(-)
>
> [...]
>
> >
> > @@ -10,12 +10,54 @@
> > #include
> > #include "log.h"
> >
> > -int socfpga_get_handoff_size(void *handoff_address, enum endianness
> > endian)
> > +static enum endianness check_endianness(u32 handoff) {
> > + switch (handoff) {
> > + case SOC64_HANDOFF_MAGIC_BOOT:
> > + case SOC64_HANDOFF_MAGIC_MUX:
> > + case SOC64_HANDOFF_MAGIC_IOCTL:
> > + case SOC64_HANDOFF_MAGIC_FPGA:
> > + case SOC64_HANDOFF_MAGIC_DELAY:
> > + case SOC64_HANDOFF_MAGIC_CLOCK:
> > + case SOC64_HANDOFF_MAGIC_MISC:
> > + return BIG_ENDIAN;
> > +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> > + case SOC64_HANDOFF_DDR_UMCTL2_MAGIC:
> > + debug("%s: umctl2 handoff data\n", __func__);
> > + return LITTLE_ENDIAN;
> > + case SOC64_HANDOFF_DDR_PHY_MAGIC:
> > + debug("%s: PHY handoff data\n", __func__);
> > + return LITTLE_ENDIAN;
> > + case SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC:
> > + debug("%s: PHY engine handoff data\n", __func__);
> > + return LITTLE_ENDIAN;
> Can merge to one 'return' and print the 'handoff' if needed.
I can merge to one 'return' but has to compromise accuracy of DDR handoff type
debug print out. So, I don’t see any benefit of doing these.
Do you have any suggestion?
>
> > +#endif
> > + default:
> > + debug("%s: Unknown endianness!!\n", __func__);
> > + return UNKNOWN_ENDIANNESS;
> > + }
> > +}
> > +
> > +int socfpga_get_handoff_size(void *handoff_address)
> > {
> > u32 size;
> > + enum endianness endian_t;
> > +
> > + /* Checking handoff data is little endian ? */
> > + endian_t = check_endianness(readl(handoff_address));
> > +
> > + if (endian_t == UNKNOWN_ENDIANNESS) {
> > + /* Trying to check handoff data is big endian? */
> > + endian_t = check_endianness(swab32(readl(handoff_address)));
> > + if (endian_t == UNKNOWN_ENDIANNESS) {
> > + debug("%s: Cannot find HANDOFF MAGIC ", __func__);
> > + debug("at addr 0x%p\n", (u32 *)handoff_address);
> > + return -EPERM;
> > + }
> > + }
> >
> > size = readl(handoff_address + SOC64_HANDOFF_OFFSET_LENGTH);
> > - if (endian == BIG_ENDIAN)
> > + if (endian_t == BIG_ENDIAN)
> > size = swab32(size);
> >
> > size = (size - SOC64_HANDOFF_OFFSET_DATA) / sizeof(u32); @@
> > -26,41 +68,61 @@ int socfpga_get_handoff_size(void *handoff_address,
> enum endianness endian)
> > return size;
> > }
> >
> > -int socfpga_handoff_read(void *handoff_address, void *table, u32
> table_len,
> > -enum endianness big_endian)
> > +int socfpga_handoff_read(void *handoff_address, void *table, u32
> > +table_len)
> > {
> > - u32 temp, i;
> > + u32 temp;
> > u32 *table_x32 = table;
> > + u32 i = 0;
> > + enum endianness endian_t;
> > +
> > + /* Checking handoff data is little endian ? */
> > + endian_t = check_endianness(readl(han
RE: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
> -Original Message- > From: Tan, Ley Foon > Sent: Wednesday, 14 April, 2021 6:30 PM > To: Lim, Elly Siew Chin ; u-boot@lists.denx.de > Cc: Marek Vasut ; See, Chin Liang > ; Simon Goldschmidt > ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai > Subject: RE: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device > > > > > -Original Message- > > From: Lim, Elly Siew Chin > > Sent: Wednesday, March 31, 2021 10:39 PM > > To: u-boot@lists.denx.de > > Cc: Marek Vasut ; Tan, Ley Foon > > ; See, Chin Liang ; > > Simon Goldschmidt ; Chee, Tien Fong > > ; Westergreen, Dalon > > ; Simon Glass ; Gan, > > Yau Wai ; Lim, Elly Siew Chin > > > > Subject: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device > > > > The DDR subsystem in Diamond Mesa is consisted of controller, PHY, > > memory reset manager and memory clock manager. > > > > Configuration settings of controller, PHY and memory reset manager > > is come from DDR handoff data in bitstream, which contain the register > > base addresses and user settings from Quartus. > > > > Configuration settings of memory clock manager is come from the HPS > > handoff data in bitstream, however the register base address is defined > > in device tree. > > > > The calibration is fully done in HPS, which requires IMEM and DMEM > > binaries loading to PHY SRAM for running this calibration, both > > IMEM and DMEM binaries are also part of bitstream, this bitstream > > would be loaded to OCRAM by SDM, and configured by DDR driver. > > > > Signed-off-by: Siew Chin Lim > > Signed-off-by: Tien Fong Chee > > --- > > arch/arm/mach-socfpga/include/mach/firewall.h |6 + > > .../include/mach/system_manager_soc64.h| 10 +- > > drivers/ddr/altera/Makefile|3 +- > > drivers/ddr/altera/sdram_n5x.c | 2316 > > > drivers/ddr/altera/sdram_soc64.c | 10 +- > > 5 files changed, 2342 insertions(+), 3 deletions(-) > > create mode 100644 drivers/ddr/altera/sdram_n5x.c > > [...] > > > --- /dev/null > > +++ b/drivers/ddr/altera/sdram_n5x.c > > @@ -0,0 +1,2316 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2020-2021 Intel Corporation > > + * > > + */ > > + > > +#include > Sorting this. > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include "sdram_soc64.h" > > +#include > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +/* MPFE NOC registers */ > > +#define FPGA2SDRAM_MGR_MAIN_SIDEBANDMGR_FLAGOUTSET0 > > 0xF8024050 > > + > > +/* Memory reset manager */ > > +#define MEM_RST_MGR_STATUS 0x8 > > + > > +/* Register and bit in memory reset manager */ > > +#define MEM_RST_MGR_STATUS_RESET_COMPLETE BIT(0) > > +#define MEM_RST_MGR_STATUS_PWROKIN_STATUS BIT(1) > > +#define MEM_RST_MGR_STATUS_CONTROLLER_RST BIT(2) > > +#define MEM_RST_MGR_STATUS_AXI_RST BIT(3) > > + > > +#define TIMEOUT_200MS 200 > > +#define TIMEOUT_5000MS5000 > > + > > +/* DDR4 umctl2 */ > > +#define DDR4_MSTR_OFFSET 0x0 > > +#define DDR4_FREQ_RATIOBIT(22) > > + > > +#define DDR4_STAT_OFFSET 0x4 > > +#define DDR4_STAT_SELFREF_TYPE (BIT(5) | BIT(4)) > > +#define DDR4_STAT_SELFREF_TYPE_SHIFT 4 > > +#define DDR4_STAT_OPERATING_MODE (BIT(2) | BIT(1) | BIT(0)) > > + > > +#define DDR4_MRCTRL0_OFFSET0x10 > > +#define DDR4_MRCTRL0_MR_TYPE BIT(0) > > +#define DDR4_MRCTRL0_MPR_ENBIT(1) > > +#define DDR4_MRCTRL0_MR_RANK (BIT(5) | BIT(4)) > > +#define DDR4_MRCTRL0_MR_RANK_SHIFT 4 > > +#define DDR4_MRCTRL0_MR_ADDR (BIT(15) | BIT(14) | > BIT(13) | > > BIT(12)) > This is mask value? If yes, can use GENMASK() macro. > Same for the defines below. Okay. > > > +#define DDR4_MRCTRL0_MR_ADDR_SHIFT 12 > > +#define DDR4_MRCTRL0_MR_WR BIT(31) > > + > > +#define DDR4_MRCTRL1_OFFSET0x14 > > +#define DDR4_MRCTRL1_MR_DATA 0x3 > > + >
RE: [v1 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Friday, 9 April, 2021 1:54 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v1 11/17] ddr: socfpga: Enable memory test on memory size less
> than 1GB
>
>
>
> > -Original Message-
> > From: Lim, Elly Siew Chin
> > Sent: Wednesday, March 31, 2021 10:39 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Tan, Ley Foon
> > ; See, Chin Liang ;
> > Simon Goldschmidt ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai
> > Subject: [v1 11/17] ddr: socfpga: Enable memory test on memory size
> > less than 1GB
> >
> > From: Tien Fong Chee
> >
> > Minimum 1GB memory size is required in current memory test, so this
> > patch improves the memory test for processing memory size less than
> > 1GB, and the size in power of two.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> > drivers/ddr/altera/sdram_soc64.c | 18 --
> > 1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/ddr/altera/sdram_soc64.c
> > b/drivers/ddr/altera/sdram_soc64.c
> > index a08f0953e5..171cde0e6b 100644
> > --- a/drivers/ddr/altera/sdram_soc64.c
> > +++ b/drivers/ddr/altera/sdram_soc64.c
> > @@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
> > phys_size_t total_ram_check = 0;
> > phys_size_t ram_check = 0;
> > phys_addr_t start = 0;
> > + phys_size_t size, total_size;
>
> Use "remaining_size" is more suitable.
Okay
>
> > int bank;
> >
> > /* Sanity check ensure correct SDRAM size specified */ @@ -189,10
> > +190,23 @@ void sdram_size_check(struct bd_info *bd)
> >
> > for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> > start = bd->bi_dram[bank].start;
> > + total_size = bd->bi_dram[bank].size;
> > while (ram_check < bd->bi_dram[bank].size) {
> > - ram_check += get_ram_size((void *)(start +
> > ram_check),
> > -(phys_size_t)SZ_1G);
> > + size = min((phys_addr_t)SZ_1G,
> > (phys_addr_t)total_size);
> > +
> > + /*
> > +* Ensure the size is power of two, this is requirement
> > to run
> > +* get_ram_size() / memory test
> > +*/
> > + if (size != 0 && ((size & (size - 1)) == 0)) {
> > + ram_check += get_ram_size((void *)(start +
> > ram_check), size);
> > + total_size = bd->bi_dram[bank].size -
> > ram_check;
> > + } else {
> > + puts("DDR: Memory test requires SDRAM
> > size in power of two!\n");
> > + hang();
> > + }
> > }
> > +
> > total_ram_check += ram_check;
> > ram_check = 0;
> > }
> > --
> > 2.13.0
RE: [v1 10/17] arm: socfpga: Add SDRAM driver helper function for Intel N5X device
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Friday, 9 April, 2021 2:08 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v1 10/17] arm: socfpga: Add SDRAM driver helper function for
> Intel N5X device
>
>
>
> > -Original Message-
> > From: Lim, Elly Siew Chin
> > Sent: Wednesday, March 31, 2021 10:39 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Tan, Ley Foon
> > ; See, Chin Liang ;
> > Simon Goldschmidt ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai ; Lim, Elly Siew Chin
> >
> > Subject: [v1 10/17] arm: socfpga: Add SDRAM driver helper function for
> > Intel N5X device
> >
> > Add is_ddr_init_skipped function to check if need to skip DDR
> > initialization for N5X. This patch is preparation for N5X DDR driver
> > support.
> >
> > Signed-off-by: Siew Chin Lim
> > Signed-off-by: Tien Fong Chee
> > ---
> > arch/arm/mach-socfpga/include/mach/misc.h | 4 ++
> > arch/arm/mach-socfpga/misc_soc64.c| 67
> > ++-
> > 2 files changed, 70 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
> > b/arch/arm/mach- socfpga/include/mach/misc.h index
> > 649d2f6ce2..c41b7c14cd 100644
> > --- a/arch/arm/mach-socfpga/include/mach/misc.h
> > +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> > @@ -44,6 +44,10 @@ void socfpga_sdram_remap_zero(void); int
> > is_fpga_config_ready(void); #endif
> >
> > +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> > +bool is_ddr_init_skipped(void);
> > +#endif
> > +
> > void do_bridge_reset(int enable, unsigned int mask); void
> > socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); diff
> > --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-
> > socfpga/misc_soc64.c index 7b973a79e8..d3945e55aa 100644
> > --- a/arch/arm/mach-socfpga/misc_soc64.c
> > +++ b/arch/arm/mach-socfpga/misc_soc64.c
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /*
> > - * Copyright (C) 2016-2018 Intel Corporation
> > + * Copyright (C) 2016-2021 Intel Corporation
> > *
> > */
> >
> > @@ -19,6 +19,13 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +/* Reset type */
> > +enum reset_type {
> > + POR_RESET,
> > + WARM_RESET,
> > + COLD_RESET
> > +};
> > +
> > /*
> > * FPGA programming support for SoC FPGA Stratix 10
> > */
> > @@ -88,3 +95,61 @@ void do_bridge_reset(int enable, unsigned int mask)
> >
> > socfpga_bridges_reset(enable);
> > }
> > +
> > +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> > +static bool is_ddr_retention_enabled(u32 boot_scratch_cold0_reg) {
> > + return boot_scratch_cold0_reg &
> > + ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK;
> > +}
> > +
> > +static bool is_ddr_bitstream_sha_matching(u32 boot_scratch_cold0_reg)
> {
> > + return boot_scratch_cold0_reg &
> > ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK;
> > +}
> > +
> > +static enum reset_type get_reset_type(u32 boot_scratch_cold0_reg) {
> > + return (boot_scratch_cold0_reg &
> > + ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK) >>
> > + ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT;
> > +}
> > +
> > +bool is_ddr_init_skipped(void)
>
> 1. This function can move to DDR driver.
> 2. Change this function return true if need the DDR init, so that doesn't need
> to invert checking when call to this function, more readable.
Okay.
>
> > +{
> > + u32 reg = readl(socfpga_get_sysmgr_addr() +
> > + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > +
> > + if (get_reset_type(reg) == POR_RESET) {
> Store reset type in a variable, don't call get_reset_type() multiple times.
>
> > + debug("%s: POR reset is triggered\n", __func__);
> > + debug("%s: DDR init is required\n", __func__);
> > + return false;
> > + }
> > +
> > + if (get_reset_type(reg) == WARM_RESET) {
> > + debug("%s: Warm reset is triggered\n", __func__);
> > + debug("%s: DDR init is skipped\n", __func__);
> > + return true;
> > + }
> > +
> > + if (get_reset_type(reg) == CO
RE: [v1 03/17] arm: socfpga: Add handoff data support for Intel N5X device
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Monday, 5 April, 2021 3:17 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v1 03/17] arm: socfpga: Add handoff data support for Intel N5X
> device
>
>
>
> > -Original Message-
> > From: Lim, Elly Siew Chin
> > Sent: Wednesday, March 31, 2021 10:39 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Tan, Ley Foon
> > ; See, Chin Liang ;
> > Simon Goldschmidt ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai ; Lim, Elly Siew Chin
> >
> > Subject: [v1 03/17] arm: socfpga: Add handoff data support for Intel
> > N5X device
> >
> > N5X support both HPS handoff data and DDR handoff data.
> > HPS handoff data support re-use Straix10 and Agilex code. DDR handoff
> > data is newly introduced for N5X.
> >
> > Signed-off-by: Siew Chin Lim
> > ---
> > arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 28
> > +++
> > arch/arm/mach-socfpga/wrap_handoff_soc64.c | 40
> > ++
> > 2 files changed, 68 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
>
>
> [...]
>
>
> > diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > index a7ad7a18ed..37b4c360fb 100644
> > --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > @@ -60,6 +60,46 @@ int socfpga_handoff_read(void *handoff_address,
> > void *table, u32 table_len,
> > debug("at addr 0x%p\n", (u32 *)handoff_address);
> > return -EPERM;
> > }
> > + } else {
> > +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> > + temp = readl(handoff_address);
> > + if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC) {
> > + debug("%s: umctl2 handoff data =\n{\n",
> > + __func__);
> > + } else if (temp == SOC64_HANDOFF_DDR_PHY_MAGIC) {
> > + debug("%s: PHY handoff data =\n{\n",
> > + __func__);
> > + } else if (temp ==
> > SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> > + debug("%s: PHY engine handoff data =\n{\n",
> > + __func__);
> > + }
> > +
> > + debug("handoff table address = 0x%p table length = 0x%x\n",
> > + table_x32, table_len);
> > +
> > + if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC ||
> > + temp == SOC64_HANDOFF_DDR_PHY_MAGIC ||
> > + temp ==
> > SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> > + for (i = 0; i < table_len; i++) {
> > + *table_x32 = readl(handoff_address +
> > +
> > SOC64_HANDOFF_OFFSET_DATA +
> > + (i * 4));
> > +
> > + if (!(i % 2))
> > + debug(" No.%d Addr 0x%08x: ", i,
> > + *table_x32);
> > + else
> > + debug(" 0x%08x\n", *table_x32);
> > +
> > + table_x32++;
> > + }
> > + debug("\n}\n");
> > + } else {
> > + debug("%s: Cannot find HANDOFF MAGIC ",
> > __func__);
> > + debug("at addr 0x%p\n", (u32 *)handoff_address);
> > + return -EPERM;
> > + }
> > +#endif
> > }
> >
> > return 0;
>
> 1. Can we auto detect the endianness from the magic word?
> 2. Can merge or simplify the big and little endian flow? Do swap when it is
> big
> endian.
Yes, we can do.
Regards,
Tien Fong
>
>
> Regards
> Ley Foon
>
>
> Regards
> Ley Foon
Re: [U-Boot] [PATCH 1/8] ARM: socfpga: arria10: Add qts-filter for arria10 socfpga
On Fri, 2019-10-04 at 15:30 -0700, Dalon Westergreen wrote:
> From: Dalon Westergreen
>
> Add a script to process hps handoff data and generate a header
> for inclusion in u-boot specific devicetree addons. The header
> should be included in the top level u-boot.dtsi.
>
> Signed-off-by: Dalon Westergreen
> ---
> arch/arm/mach-socfpga/qts-filter-a10.sh | 141
>
> 1 file changed, 141 insertions(+)
> create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh
>
> diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-
> socfpga/qts-filter-a10.sh
> new file mode 100755
> index 00..ddb0d0a6f3
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
> @@ -0,0 +1,141 @@
> +#!/bin/bash
> +
> +#
> +# helper function to convert from DOS to Unix, if necessary, and
> handle
> +# lines ending in '\'.
> +#
> +fix_newlines_in_macros() {
> + sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
> +}
> +
> +#filter out only what we need from a10 hps.xml
> +grep_a10_hps_config() {
> + egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
> +}
Above function seems unused.
> +
> +#
> +# Process hps.xml
> +# $1:hps.xml
> +# $2:Output File
> +#
> +process_a10_hps_config() {
> + hps_xml="$1"
> + outfile="$2"
> +
> + (cat << EOF
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Altera Arria10 SoCFPGA configuration
> + */
> +
> +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
> +#define __SOCFPGA_ARRIA10_CONFIG_H__
> +
> +EOF
> +
> + echo "/* Clocks */"
> + fix_newlines_in_macros \
> + ${hps_xml} | egrep "clk_hz" |
> + awk -F"'" '{ gsub("\\.","_",$2) ; \
> + print "#define" " " toupper($2) " "
> $4}' |
> + sed 's/\.[0-9]//' |
> + sed 's/I_CLK_MGR_//' |
> + sort
> + fix_newlines_in_macros \
> + ${hps_xml} | egrep "i_clk_mgr_mainpll" |
> + awk -F"'" '{ gsub("\\.","_",$2) ; \
> + print "#define" " " toupper($2) " "
> $4}' |
> + sed 's/\.[0-9]//' |
> + sed 's/I_CLK_MGR_//' |
> + sort
> + fix_newlines_in_macros \
> + ${hps_xml} | egrep "i_clk_mgr_perpll" |
> + awk -F"'" '{ gsub("\\.","_",$2) ; \
> + print "#define" " " toupper($2) " "
> $4}' |
> + sed 's/\.[0-9]//' |
> + sed 's/I_CLK_MGR_//' |
> + sort
> + fix_newlines_in_macros \
> + ${hps_xml} | egrep "i_clk_mgr_clkmgr" |
> + awk -F"'" '{ gsub("\\.","_",$2) ; \
> + print "#define" " " toupper($2) " "
> $4}' |
> + sed 's/\.[0-9]//' |
> + sed 's/I_CLK_MGR_//' |
> + sort
> + fix_newlines_in_macros \
> + ${hps_xml} | egrep "i_clk_mgr_alteragrp" |
> + awk -F"'" '{ gsub("\\.","_",$2) ; \
> + print "#define" " " toupper($2) " "
> $4}' |
> + sed 's/\.[0-9]//' |
> + sed 's/I_CLK_MGR_//' |
> + sort
> + echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT <<
> 16) | \\"
> + echo " (ALTERAGRP_MPUCLK_MAINCNT))"
> + echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT <<
> 16) | \\"
> + echo " (ALTERAGRP_NOCCLK_MAINCNT))"
> +
> + echo
> + echo "/* Pin Mux Configuration */"
> + fix_newlines_in_macros \
> + ${hps_xml} | egrep "i_io48_pin_mux" |
> + awk -F"'" '{ gsub("\\.","_",$2) ; \
> + print "#define" " " toupper($2) " "
> $4}' |
> + sed 's/I_IO48_PIN_MUX_//' |
> + sed 's/SHARED_3V_IO_GRP_//' |
> + sed 's/FPGA_INTERFACE_GRP_//' |
> + sed 's/DEDICATED_IO_GRP_//' |
> + sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
> + sort
> +
> + echo
> + echo "/* Bridge Configuration */"
> + fix_newlines_in_macros \
> + ${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
> + awk -F"'" '{ gsub("\\.","_",$2) ; \
> + print "#define" " " toupper($2) " "
> $4}' |
> + sed 's/true/1/' |
> + sed 's/false/0/' |
> + sort
> +
> + echo
> + echo "/* Voltage Select for Config IO */"
> + echo "#define CONFIG_IO_BANK_VSEL \\"
> + echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3)
> << 8) | \\"
> + echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
> +
> + echo
> + echo "/* Macro for Config IO bit mapping */"
> + echo -n "#define CONFIG_IO_MACRO(NAME) "
> + echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
> + echo " ((NAME ##
Re: [U-Boot] [PATCH 1/2] mtd: spi: Add SYS_SPI_BLOCK_SIZE to Kconfig
On Thu, 2019-08-22 at 09:54 +0200, Marek Vasut wrote: > On 8/22/19 9:40 AM, Chee, Tien Fong wrote: > > > > On Mon, 2019-07-29 at 15:48 +0800, tien.fong.c...@intel.com wrote: > > > > > > From: Tien Fong Chee > > > > > > Different SPI flash has different block erase size configuration, > > > it > > > can > > > be configured as block erase size or sub-block erase size, so > > > SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block > > > reading. > > > UBI block reading would be eventually translated to offset > > > access into SPI regardless how the block erase size is configured > > > on > > > SPI. > > > This would made the UBI transparent from SPI layer. > > > > > > Signed-off-by: Tien Fong Chee > > > --- > > > drivers/mtd/spi/Kconfig | 7 +++ > > > 1 file changed, 7 insertions(+) > > > > > > diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig > > > index d3b007a731..ea3779c521 100644 > > > --- a/drivers/mtd/spi/Kconfig > > > +++ b/drivers/mtd/spi/Kconfig > > > @@ -196,4 +196,11 @@ config SPI_FLASH_MTD > > > > > > If unsure, say N > > > > > > +config SYS_SPI_BLOCK_SIZE > > > + hex "SPI chip eraseblock size for UBI reading" > > > + depends on SPL_SPI_FLASH_SUPPORT > > > + default 65536 > > > + help > > > + Number of data bytes in a physical eraseblock for UBI > > > reading. > > > + > > > endmenu # menu "SPI Flash Support" > > Any comment? > UBI is able to obtain underlying media erase block size from the MTD > subsystem, just let it do that. Besides, any such compile-time config > would fail the next time you change the SPI NOR (e.g. because it's > EOL), > as that would force you to rebuild U-Boot, which might ultimately not > be > possible. Okay, let me check how to get this info from MTD. If you have some ideas, you can let me know too :) . ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] drivers: ubi: Adding UBI loader for SPI flash
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > Adding UBI support for SPI flash. > > Signed-off-by: Tien Fong Chee > --- > common/spl/spl_ubi.c| 11 ++- > drivers/mtd/spi/sf-uclass.c | 30 ++ > include/spi_flash.h | 10 ++ > 3 files changed, 50 insertions(+), 1 deletion(-) > > diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c > index 0cb5080882..40a449b42b 100644 > --- a/common/spl/spl_ubi.c > +++ b/common/spl/spl_ubi.c [...] Any comment? THanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mtd: spi: Add SYS_SPI_BLOCK_SIZE to Kconfig
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > Different SPI flash has different block erase size configuration, it > can > be configured as block erase size or sub-block erase size, so > SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block > reading. > UBI block reading would be eventually translated to offset > access into SPI regardless how the block erase size is configured on > SPI. > This would made the UBI transparent from SPI layer. > > Signed-off-by: Tien Fong Chee > --- > drivers/mtd/spi/Kconfig | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig > index d3b007a731..ea3779c521 100644 > --- a/drivers/mtd/spi/Kconfig > +++ b/drivers/mtd/spi/Kconfig > @@ -196,4 +196,11 @@ config SPI_FLASH_MTD > > If unsure, say N > > +config SYS_SPI_BLOCK_SIZE > + hex "SPI chip eraseblock size for UBI reading" > + depends on SPL_SPI_FLASH_SUPPORT > + default 65536 > + help > + Number of data bytes in a physical eraseblock for UBI > reading. > + > endmenu # menu "SPI Flash Support" Any comment? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] reset: socfpga: release more A10 peripherals out of reset
On Fri, 2019-05-24 at 14:00 +0200, Simon Goldschmidt wrote:
> On Fri, May 24, 2019 at 1:57 PM Chee, Tien Fong
> wrote:
> >
> >
> > On Fri, 2019-05-24 at 13:53 +0200, Simon Goldschmidt wrote:
> > >
> > > On Fri, May 24, 2019 at 1:44 PM Marek Vasut
> > > wrote:
> > > >
> > > >
> > > >
> > > > On 5/24/19 1:40 PM, tien.fong.c...@intel.com wrote:
> > > > >
> > > > >
> > > > > From: Tien Fong Chee
> > > > >
> > > > > Current implementation almost release all peripherals out of
> > > > > reset for
> > > > > gen5, but A10 has more peripherals than gen5, hence this
> > > > > patch is
> > > > > required
> > > > > to release the rest of peripherals to support old kernels.
> > > > >
> > > > > Signed-off-by: Tien Fong Chee
> > > > > ---
> > > > > drivers/reset/reset-socfpga.c | 3 +++
> > > > > 1 file changed, 3 insertions(+)
> > > > >
> > > > > diff --git a/drivers/reset/reset-socfpga.c
> > > > > b/drivers/reset/reset-
> > > > > socfpga.c
> > > > > index cb8312619f..d8b8b25fc3 100644
> > > > > --- a/drivers/reset/reset-socfpga.c
> > > > > +++ b/drivers/reset/reset-socfpga.c
> > > > > @@ -127,6 +127,9 @@ static int socfpga_reset_remove(struct
> > > > > udevice *dev)
> > > > > if (socfpga_reset_keep_enabled()) {
> > > > > puts("Deasserting all peripheral resets\n");
> > > > > writel(0, data->modrst_base + 4);
> > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > + writel(0, data->modrst_base + 8);
> > > > This should be using match on compatible string.
> > > > Which register is this modrst_base + 8 ?
> > > Well, even modrst_base + 4 is not really ideal. After all,
> > > modrst_base is a
> > > dts-given offset into the rstmgr's registers, so there is not
> > > really
> > > a
> > > comptile time known constant to do this.
> > >
> > > Maybe it would be better to use an offset to the device's
> > > membase.
> > > However, as this is a backwards-compatibility workaround, there's
> > > no
> > > use to
> > > add this into the devicetree.
> > >
> > > And unfortunately, both gen5 and a10 use the same compatible
> > > string,
> > > which
> > > probably would have to be changed.
> > >
> > > Regards,
> > > Simon
> > This register is per1modrst, here is the link https://www.intel.com
> > /con
> > tent/www/us/en/programmable/hps/arria-
> > 10/hps.html#reg_soc_top/sfo1429890576520.html
> > This whole mechanism should be removed once Dinh has fixed this
> > issue
> > at Linux v4.14-lts or moving to Linux v5.0 onwards.
> I agree it can be removed in the future, but is it really enough to
> have this
> in 4.14-lts? I'm not so sure that we should prevent people from using
> mainline U-Boot with older kernels...
I have no strong opinion on this, but how old the kernel U-Boot want to
support, subject to the maintainer :) .
>
> Regards,
> Simon
>
> >
> >
> > >
> > >
> > > >
> > > >
> > > >
> > > > >
> > > > >
> > > > > +#endif
> > > > > }
> > > > >
> > > > > return 0;
> > > > >
> > > > --
> > > > Best regards,
> > > > Marek Vasut
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Re: [U-Boot] [PATCH] reset: socfpga: release more A10 peripherals out of reset
On Fri, 2019-05-24 at 13:53 +0200, Simon Goldschmidt wrote:
> On Fri, May 24, 2019 at 1:44 PM Marek Vasut wrote:
> >
> >
> > On 5/24/19 1:40 PM, tien.fong.c...@intel.com wrote:
> > >
> > > From: Tien Fong Chee
> > >
> > > Current implementation almost release all peripherals out of
> > > reset for
> > > gen5, but A10 has more peripherals than gen5, hence this patch is
> > > required
> > > to release the rest of peripherals to support old kernels.
> > >
> > > Signed-off-by: Tien Fong Chee
> > > ---
> > > drivers/reset/reset-socfpga.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-
> > > socfpga.c
> > > index cb8312619f..d8b8b25fc3 100644
> > > --- a/drivers/reset/reset-socfpga.c
> > > +++ b/drivers/reset/reset-socfpga.c
> > > @@ -127,6 +127,9 @@ static int socfpga_reset_remove(struct
> > > udevice *dev)
> > > if (socfpga_reset_keep_enabled()) {
> > > puts("Deasserting all peripheral resets\n");
> > > writel(0, data->modrst_base + 4);
> > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > + writel(0, data->modrst_base + 8);
> > This should be using match on compatible string.
> > Which register is this modrst_base + 8 ?
> Well, even modrst_base + 4 is not really ideal. After all,
> modrst_base is a
> dts-given offset into the rstmgr's registers, so there is not really
> a
> comptile time known constant to do this.
>
> Maybe it would be better to use an offset to the device's membase.
> However, as this is a backwards-compatibility workaround, there's no
> use to
> add this into the devicetree.
>
> And unfortunately, both gen5 and a10 use the same compatible string,
> which
> probably would have to be changed.
>
> Regards,
> Simon
This register is per1modrst, here is the link https://www.intel.com/con
tent/www/us/en/programmable/hps/arria-
10/hps.html#reg_soc_top/sfo1429890576520.html
This whole mechanism should be removed once Dinh has fixed this issue
at Linux v4.14-lts or moving to Linux v5.0 onwards.
>
> >
> >
> > >
> > > +#endif
> > > }
> > >
> > > return 0;
> > >
> >
> > --
> > Best regards,
> > Marek Vasut
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Re: [U-Boot] [RFC 05/11] arm: K3: Introduce System Firmware loader framework
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> Introduce a framework that allows loading the System Firmware (SYSFW)
> binary as well as the associated configuration data from an image
> tree
> blob named "sysfw.itb" from an FS-based boot media using the FS
> loader
> framework.
>
> Signed-off-by: Andreas Dannenberg
> ---
> arch/arm/mach-k3/Kconfig | 22 ++
> arch/arm/mach-k3/Makefile| 3 +
> arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 +
> arch/arm/mach-k3/sysfw-loader.c | 296
> +++
> 4 files changed, 333 insertions(+)
> create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h
> create mode 100644 arch/arm/mach-k3/sysfw-loader.c
>
> diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
> index e677a2e01b..fd28593cec 100644
> --- a/arch/arm/mach-k3/Kconfig
> +++ b/arch/arm/mach-k3/Kconfig
> @@ -58,6 +58,28 @@ config SYS_K3_BOOT_CORE_ID
> int
> default 16
>
> +config K3_LOAD_SYSFW
> + bool
> + depends on SPL
> +
> +config K3_SYSFW_IMAGE_NAME
> + string "File name of SYSFW firmware and configuration blob"
> + depends on K3_LOAD_SYSFW
> + default "sysfw.itb"
> + help
> + Filename of the combined System Firmware and configuration
> image tree
> + blob to be loaded when booting from a filesystem.
> +
> +config K3_SYSFW_IMAGE_SIZE_MAX
> + int "Amount of memory dynamically allocated for loading
> SYSFW blob"
> + depends on K3_LOAD_SYSFW
> + default 269000
> + help
> + Amount of memory (in bytes) reserved through dynamic
> allocation at
> + runtime for loading the combined System Firmware and
> configuration image
> + tree blob. Keep it as tight as possible, as this directly
> affects the
> + overall SPL memory footprint.
> +
> config SYS_K3_SPL_ATF
> bool "Start Cortex-A from SPL"
> depends on SPL && CPU_V7R
> diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
> index 0c3a4f7db1..3af7f2ec96 100644
> --- a/arch/arm/mach-k3/Makefile
> +++ b/arch/arm/mach-k3/Makefile
> @@ -7,4 +7,7 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
> obj-$(CONFIG_ARM64) += arm64-mmu.o
> obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
> obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
> +ifeq ($(CONFIG_SPL_BUILD),y)
> +obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
> +endif
> obj-y += common.o
> diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h
> b/arch/arm/mach-k3/include/mach/sysfw-loader.h
> new file mode 100644
> index 00..c335c7ed92
> --- /dev/null
> +++ b/arch/arm/mach-k3/include/mach/sysfw-loader.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti
> .com/
> + * Andreas Dannenberg
> + */
> +
> +#ifndef _SYSFW_LOADER_H_
> +#define _SYSFW_LOADER_H_
> +
> +void k3_sysfw_loader(void (*config_pm_done_callback)(void));
> +
> +#endif
> diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-
> k3/sysfw-loader.c
> new file mode 100644
> index 00..1191640acd
> --- /dev/null
> +++ b/arch/arm/mach-k3/sysfw-loader.c
> @@ -0,0 +1,296 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * K3: System Firmware Loader
> + *
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti
> .com/
> + * Andreas Dannenberg
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* Name of the FIT image nodes for SYSFW and its config data */
> +#define SYSFW_FIRMWARE "sysfw.bin"
> +#define SYSFW_CFG_BOARD "board-cfg.bin"
> +#define SYSFW_CFG_PM "pm-cfg.bin"
> +#define SYSFW_CFG_RM "rm-cfg.bin"
> +#define SYSFW_CFG_SEC"sec-cfg.bin"
> +
> +static int fit_get_data_by_name(const void *fit, int images, const
> char *name,
> + const void **addr, size_t *size)
> +{
> + int node_offset;
> +
> + node_offset = fdt_subnode_offset(fit, images, name);
> + if (node_offset < 0)
> + return -ENOENT;
> +
> + return fit_image_get_data(fit, node_offset, addr, size);
> +}
> +
> +static void k3_sysfw_load_using_fit(void *fit, struct ti_sci_handle
> **ti_sci)
> +{
> + int images;
> + const void *sysfw_addr;
> + size_t sysfw_size;
> + struct udevice *dev;
> + int ret;
> +
> + /* Find the node holding the images information */
> + images = fdt_path_offset(fit, FIT_IMAGES_PATH);
> + if (images < 0)
> + panic("Cannot find /images node (%d)\n", images);
> +
> + /* Extract System Firmware (SYSFW) image from FIT */
> + ret = fit_get_data_by_name(fit, images, SYSFW_FIRMWARE,
> + _addr, _size);
> + if
Re: [U-Boot] [RFC 09/11] armv7R: dts: k3: am654: Update for loading SYSFW from MMC
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> From: Lokesh Vutla
>
> In order to load the sysfw.itb from an MMC device, clocks should be
> hard
> coded to the same value as ROM configured frequency. Clock updates
> cannot
> happen at this point as SYSFW is not yet available. So updating the
> clock
> properties for MMC nodes.
>
> Furthermore, create a new node for the FS loader framework which we
> want
> to use to load the actual firmware file from the boot media.
>
> Signed-off-by: Andreas Dannenberg
> ---
> arch/arm/dts/k3-am654-r5-base-board.dts | 24
>
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts
> b/arch/arm/dts/k3-am654-r5-base-board.dts
> index a07038be70..75880158a2 100644
> --- a/arch/arm/dts/k3-am654-r5-base-board.dts
> +++ b/arch/arm/dts/k3-am654-r5-base-board.dts
> @@ -22,6 +22,12 @@
> chosen {
> stdout-path = "serial2:115200n8";
> tick-timer =
> + firmware-loader = _loader0;
> + };
> +
> + fs_loader0: fs_loader@0 {
> + u-boot,dm-pre-reloc;
> + compatible = "u-boot,fs-loader";
Why not using phandlepart = < 1>, this would help to avoid mmc init
duplication in a few places such as patch [05/11].
> };
>
> aliases {
> @@ -96,6 +102,12 @@
> u-boot,dm-spl;
> };
>
> + clk_200mhz: dummy_clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <2>;
> + u-boot,dm-spl;
> + };
> };
>
> {
> @@ -137,3 +149,15 @@
> pinctrl-names = "default";
> pinctrl-0 = <_vtt_pins_default>;
> };
> +
> + {
> + clock-names = "clk_xin";
> + clocks = <_200mhz>;
> + /delete-property/ power-domains;
> +};
> +
> + {
> + clock-names = "clk_xin";
> + clocks = <_200mhz>;
> + /delete-property/ power-domains;
> +};
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Re: [U-Boot] [RFC 04/11] misc: fs_loader: Allow initializing blkdev using platform data
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> To give us more flexibility using the FS loader eliminate the need of
> always having to use the ENV to configure the block device but rather
> allow the respective block device and partition to be setup through
> platform data.
>
> Signed-off-by: Andreas Dannenberg
Why not using DT method?
> ---
> drivers/misc/fs_loader.c | 17 -
> include/fs_loader.h | 4
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c
> index f42eeff8f6..69f474da99 100644
> --- a/drivers/misc/fs_loader.c
> +++ b/drivers/misc/fs_loader.c
> @@ -81,6 +81,15 @@ static int select_fs_dev(struct device_platdata
> *plat)
> return -ENODEV;
> }
> }
> + } else if (plat->blkdev) {
> + struct blk_desc *desc = blk_get_by_device(plat-
> >blkdev);
> +
> + if (desc) {
> + ret = fs_set_blk_dev_with_part(desc, plat-
> >blkpart);
> + } else {
> + debug("%s: No device found\n", __func__);
> + return -ENODEV;
> + }
> } else if (plat->mtdpart && plat->ubivol) {
> ret = mount_ubifs(plat->mtdpart, plat->ubivol);
> if (ret)
> @@ -138,13 +147,18 @@ static int _request_firmware_prepare(struct
> udevice *dev,
> static int fw_get_filesystem_firmware(struct udevice *dev)
> {
> loff_t actread;
> - char *storage_interface, *dev_part, *ubi_mtdpart,
> *ubi_volume;
> + char *storage_interface = NULL;
> + char *dev_part = NULL;
> + char *ubi_mtdpart = NULL;
> + char *ubi_volume = NULL;
> int ret;
>
> +#if CONFIG_IS_ENABLED(ENV_SUPPORT)
> storage_interface = env_get("storage_interface");
> dev_part = env_get("fw_dev_part");
> ubi_mtdpart = env_get("fw_ubi_mtdpart");
> ubi_volume = env_get("fw_ubi_volume");
> +#endif
>
> if (storage_interface && dev_part) {
> ret = fs_set_blk_dev(storage_interface, dev_part,
> FS_TYPE_ANY);
> @@ -159,6 +173,7 @@ static int fw_get_filesystem_firmware(struct
> udevice *dev)
> else
> ret = -ENODEV;
> } else {
> + debug("%s: init via platdata\n", __func__);
> ret = select_fs_dev(dev->platdata);
> }
>
> diff --git a/include/fs_loader.h b/include/fs_loader.h
> index b728c06fcf..adaa2b5db8 100644
> --- a/include/fs_loader.h
> +++ b/include/fs_loader.h
> @@ -28,11 +28,15 @@ struct phandle_part {
> * This holds information about all supported storage devices for
> driver use.
> *
> * @phandlepart: Attribute data for block device.
> + * @blkdev: Block device (alternative to using phandlepart)
> + * @blkpart: Partition number of block device (alternative to using
> phandlepart)
> * @mtdpart: MTD partition for ubi partition.
> * @ubivol: UBI volume-name for ubifsmount.
> */
> struct device_platdata {
> struct phandle_part phandlepart;
> + struct udevice *blkdev;
> + u32 blkpart;
> char *mtdpart;
> char *ubivol;
> };
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Re: [U-Boot] [RFC 05/11] arm: K3: Introduce System Firmware loader framework
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> Introduce a framework that allows loading the System Firmware (SYSFW)
> binary as well as the associated configuration data from an image
> tree
> blob named "sysfw.itb" from an FS-based boot media using the FS
> loader
> framework.
>
> Signed-off-by: Andreas Dannenberg
> ---
> arch/arm/mach-k3/Kconfig | 22 ++
> arch/arm/mach-k3/Makefile| 3 +
> arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 +
> arch/arm/mach-k3/sysfw-loader.c | 296
> +++
> 4 files changed, 333 insertions(+)
> create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h
> create mode 100644 arch/arm/mach-k3/sysfw-loader.c
>
> diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
> index e677a2e01b..fd28593cec 100644
> --- a/arch/arm/mach-k3/Kconfig
> +++ b/arch/arm/mach-k3/Kconfig
> @@ -58,6 +58,28 @@ config SYS_K3_BOOT_CORE_ID
> int
> default 16
>
> +config K3_LOAD_SYSFW
> + bool
> + depends on SPL
> +
> +config K3_SYSFW_IMAGE_NAME
> + string "File name of SYSFW firmware and configuration blob"
> + depends on K3_LOAD_SYSFW
> + default "sysfw.itb"
> + help
> + Filename of the combined System Firmware and configuration
> image tree
> + blob to be loaded when booting from a filesystem.
> +
> +config K3_SYSFW_IMAGE_SIZE_MAX
> + int "Amount of memory dynamically allocated for loading
> SYSFW blob"
> + depends on K3_LOAD_SYSFW
> + default 269000
> + help
> + Amount of memory (in bytes) reserved through dynamic
> allocation at
> + runtime for loading the combined System Firmware and
> configuration image
> + tree blob. Keep it as tight as possible, as this directly
> affects the
> + overall SPL memory footprint.
> +
> config SYS_K3_SPL_ATF
> bool "Start Cortex-A from SPL"
> depends on SPL && CPU_V7R
> diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
> index 0c3a4f7db1..3af7f2ec96 100644
> --- a/arch/arm/mach-k3/Makefile
> +++ b/arch/arm/mach-k3/Makefile
> @@ -7,4 +7,7 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
> obj-$(CONFIG_ARM64) += arm64-mmu.o
> obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
> obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
> +ifeq ($(CONFIG_SPL_BUILD),y)
> +obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
> +endif
> obj-y += common.o
> diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h
> b/arch/arm/mach-k3/include/mach/sysfw-loader.h
> new file mode 100644
> index 00..c335c7ed92
> --- /dev/null
> +++ b/arch/arm/mach-k3/include/mach/sysfw-loader.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti
> .com/
> + * Andreas Dannenberg
> + */
> +
> +#ifndef _SYSFW_LOADER_H_
> +#define _SYSFW_LOADER_H_
> +
> +void k3_sysfw_loader(void (*config_pm_done_callback)(void));
> +
> +#endif
> diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-
> k3/sysfw-loader.c
> new file mode 100644
> index 00..1191640acd
> --- /dev/null
> +++ b/arch/arm/mach-k3/sysfw-loader.c
> @@ -0,0 +1,296 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * K3: System Firmware Loader
> + *
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti
> .com/
> + * Andreas Dannenberg
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* Name of the FIT image nodes for SYSFW and its config data */
> +#define SYSFW_FIRMWARE "sysfw.bin"
> +#define SYSFW_CFG_BOARD "board-cfg.bin"
> +#define SYSFW_CFG_PM "pm-cfg.bin"
> +#define SYSFW_CFG_RM "rm-cfg.bin"
> +#define SYSFW_CFG_SEC"sec-cfg.bin"
> +
> +static int fit_get_data_by_name(const void *fit, int images, const
> char *name,
> + const void **addr, size_t *size)
> +{
> + int node_offset;
> +
> + node_offset = fdt_subnode_offset(fit, images, name);
> + if (node_offset < 0)
> + return -ENOENT;
> +
> + return fit_image_get_data(fit, node_offset, addr, size);
> +}
> +
> +static void k3_sysfw_load_using_fit(void *fit, struct ti_sci_handle
> **ti_sci)
> +{
> + int images;
> + const void *sysfw_addr;
> + size_t sysfw_size;
> + struct udevice *dev;
> + int ret;
> +
> + /* Find the node holding the images information */
> + images = fdt_path_offset(fit, FIT_IMAGES_PATH);
> + if (images < 0)
> + panic("Cannot find /images node (%d)\n", images);
> +
> + /* Extract System Firmware (SYSFW) image from FIT */
> + ret = fit_get_data_by_name(fit, images, SYSFW_FIRMWARE,
> + _addr, _size);
> + if
Re: [U-Boot] fit: Add support for printing more than one FPGA node name
On Sat, 2019-04-27 at 10:43 -0400, Tom Rini wrote:
> On Fri, Apr 26, 2019 at 06:12:40AM +0000, Chee, Tien Fong wrote:
> >
> > On Mon, 2019-04-22 at 13:29 -0400, Tom Rini wrote:
> > >
> > > On Wed, Feb 13, 2019 at 08:32:24PM +0800, tien.fong.c...@intel.co
> > > m
> > > wrote:
> > >
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > This would print out all the FPGA node names setting to fpga
> > > > property.
> > > >
> > > > Signed-off-by: Tien Fong Chee
> > > > ---
> > > > common/image-fit.c | 14 +++---
> > > > 1 files changed, 11 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/common/image-fit.c b/common/image-fit.c
> > > > index ac901e1..816e17d 100644
> > > > --- a/common/image-fit.c
> > > > +++ b/common/image-fit.c
> > > > @@ -263,6 +263,7 @@ static void fit_conf_print(const void *fit,
> > > > int
> > > > noffset, const char *p)
> > > > int ret;
> > > > int fdt_index, loadables_index;
> > > > int ndepth;
> > > > + ulong count;
> > > >
> > > > /* Mandatory properties */
> > > > ret = fit_get_desc(fit, noffset, );
> > > > @@ -299,9 +300,16 @@ static void fit_conf_print(const void
> > > > *fit,
> > > > int noffset, const char *p)
> > > > printf("%s\n", uname);
> > > > }
> > > >
> > > > - uname = fdt_getprop(fit, noffset, FIT_FPGA_PROP,
> > > > NULL);
> > > > - if (uname)
> > > > - printf("%s FPGA: %s\n", p, uname);
> > > > + count = fit_conf_get_prop_node_count(fit, noffset,
> > > > FIT_FPGA_PROP);
> > > > +
> > > > + for (ndepth = 0; ndepth < count; ndepth++) {
> > > > + int images_noffset =
> > > > fit_conf_get_prop_node_index(fit, noffset,
> > > > + FIT_FPGA_PROP,
> > > > ndepth);
> > > > + uname = fit_get_name(fit, images_noffset,
> > > > NULL);
> > > > +
> > > > + if (uname)
> > > > + printf("%s FPGA: %s\n", p,
> > > > uname);
> > > > + }
> > > >
> > > > /* Print out all of the specified loadables */
> > > > for (loadables_index = 0;
> > > While I'm fine with the conceptual change here, both
> > > fit_conf_get_prop_node_count / fit_conf_get_prop_node_index are
> > > defined
> > > later in the file and while public functions not documented in a
> > > header.
> > > Can you please do a patch that does so first, as we otherwise get
> > > a
> > > warning? Thanks!
> > The header file in this patch https://patchwork.ozlabs.org/patch/10
> > 58289/,
> > unfortunately the review taking a bit longer than what i expected.
> >
> > I would update you once the whole series patches are accepted.
> Ah, OK, I'll hold off until the other series is complete.
The series is already in mainline master branch.
Thanks.
>
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Re: [U-Boot] [PATCH 00/13] System Firmware Loader for TI K3 family SoCs
On Wed, 2019-05-08 at 13:43 -0500, dannenb...@ti.com wrote:
> Hi TF,
> thanks for chiming in. Comments inlined...
>
> On Wed, May 08, 2019 at 04:31:35AM +, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 07.05.19 19:25, Andreas Dannenberg wrote:
> > > >
> > > >
> > [...]
> > >
> > > >
> > > >
> > > > While I also have a working solution based on the existing FS
> > > > loader
> > > > framework this has its own challenges, namely by its very
> > > > nature
> > > > only
> > > > addressing a subset of our use cases (no eMMC/SD RAW boot
> > > > support
> > > > for
> > > > example),
> > IMO, it's actually not that hard to enhance RAW support, i think
> > minimal changes are required. I have attached the patches about an
> > example of loading RAW from QSPI that i have done locally last few
> > week
> > ago.
> As your patches show, no it's not hard, it's more or less taking
> pieces
> from the SPL loader framework and refactoring them into the FS
> loader,
> creating a good and universal solution usable across SPL and U-Boot
> in
> environments that are not tightly constrained in terms of memory.
>
> What I was going after is finding a way to load from different media
> "pre-relocation" SPL (board_init_f), with almost no memory available,
> where I have to agonize over every single KB available.
This is just a simple "loader", provide user flexibility of loading
stuff in anywhere, from SPL to U-Boot. As long as DM is supported by
the time running at "pre-relocation" SPL, then FS loader should be able
to work.
> >
> > >
> > > >
> > > > being heavier on resource usage (needing to use ENV to pass
> > > > parameters),
> > ENV is optional, you can use DTS.
> Is it? I had to update the FS loader framework when I experimented
> with
> it, please see attached patch. I had refactored it such that I can
> pass
> in all relevant data via platform data for the intial boot mode I was
> going after, so that I can dynamically configure it on the fly from
> early SPL board_init_f() based on boot media / boot mode, etc.
Yes, you can tie up loader with target HW node for destination loading.
For example, tie up with FPGA manager node, loading bistream file from
MMC to FPGA manager.
Here is an example, but i put the fs loader phandle under chosen node
because most files and images are stored in the same storage.
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=commit;h=0a42a132a4b8
46031df2c4a7d04692240ed34843
>
> >
> > For example loading FPGA bitstream from QSPI RAW:
> >
> > /* DTS */
> > / {
> > + aliases {
> > + spi0 =
> > + };
> > +
> > + fs_loader0: fs-loader {
> > + u-boot,dm-pre-reloc;
> > + compatible = "u-boot,fs-loader";
> > + sfconfig = <0 0 1 3>;
> > + };
> > +};
> > +
> > +_mgr {
> > + u-boot,dm-pre-reloc;
> > + firmware-loader = <_loader0>;
> > + altr,bitstream = "30";
> > +};
> The above hard-codes and duplicates information that is already known
> to
> U-Boot (CONFIG_SF_DEFAULT_*), and will do more of the same as this is
> being extended. How does one keep this consistent?
Current fs loader not support RAW loading yet, i'm not sure whether it
should support it by adding more specific storage API(much more messy),
or just fully support filesystem only with one generic filesystem
abstract interface.
This example codes provide user opportunity to override the spi setting
when running fs loader. CONFIG_SF_DEFAULT_* would be used by the
drivers which are not running the fs loader.
>
> And how does this scale to support like 5 different boot modes using
> a
> single DTB? I guess one could populate 5 nodes, and then pick one
> based
> on boot mode during SPL execution, by extending the probe function
> accordingly.
This is just a very simple fs loader. This is totally up to user how
they want to scale it up, may be adding the function to populate the fs
loader nodes, or loading the images based on boot storages ordering in
DTS?
>
> >
> >
> > >
> > > >
> > > > and not addressing the need to probe the boot peripheral.
> > You can add more different probing method in function called
> > "fs_loader_probe". Current fs_loader supports block(sdmmc, emmc,
> > etc...) probing, and with
> > the patc
Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
> On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
> > >
> > > On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > On 07.05.19 21:41, Marek Vasut wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > According to SoCFPGA Cyclone V datasheet
> > > > > > > > > rev.2018.01.26
> > > > > > > > > page
> > > > > > > > > 175
> > > > > > > > > (Chapter 5, FPGA Manager, data register) and Arria10
> > > > > > > > > datasheet
> > > > > > > > > rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA
> > > > > > > > > Manager,
> > > > > > > > > img_data_w
> > > > > > > > > register), the FPGA data register must be written
> > > > > > > > > with
> > > > > > > > > writes
> > > > > > > > > with
> > > > > > > > > non-incrementing address.
> > > > > > > > >
> > > > > > > > > The current code increments the address in 32-byte
> > > > > > > > > bursts.
> > > > > > > > > Fix the
> > > > > > > > > code so it does not increment the address and writes
> > > > > > > > > the
> > > > > > > > > register
> > > > > > > > > repeatedly instead. >
> > > > > > > > > Signed-off-by: Marek Vasut
> > > > > > > > > Cc: Chin Liang See
> > > > > > > > > Cc: Dinh Nguyen
> > > > > > > > > Cc: Simon Goldschmidt > > > > > > > > m>
> > > > > > > > > Cc: Tien Fong Chee
> > > > > > > > > ---
> > > > > > > > > drivers/fpga/socfpga.c | 3 +--
> > > > > > > > > 1 file changed, 1 insertion(+), 2 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/fpga/socfpga.c
> > > > > > > > > b/drivers/fpga/socfpga.c
> > > > > > > > > index 685957626b..6ecea771ce 100644
> > > > > > > > > --- a/drivers/fpga/socfpga.c
> > > > > > > > > +++ b/drivers/fpga/socfpga.c
> > > > > > > > > @@ -55,8 +55,7 @@ void fpgamgr_program_write(const
> > > > > > > > > void
> > > > > > > > > *rbf_data,
> > > > > > > > > size_t rbf_size)
> > > > > > > > > " cmp %2, #0\n"
> > > > > > > > > " beq 2f\n"
> > > > > > > > > "1: ldmia %0!, {r0-r7}\n"
> > > > > > > > > - " stmia %1!, {r0-r7}\n"
> > > > > > > > > - " sub %1, #32\n"
> > > > > > > > > + " stmia %1, {r0-r7}\n"
> > > > > > > > Iirc, stmia without the "!" still stores the registers
> > > > > > > > to
> > > > > > > > different
> > > > > > > > addresses, it just does not change %1 any more if you
> > > > > > > > leave
> > > > > > > > away the
Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
> On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:41, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > > > >
> > > > > > >
> > > > > > > According to SoCFPGA Cyclone V datasheet rev.2018.01.26
> > > > > > > page
> > > > > > > 175
> > > > > > > (Chapter 5, FPGA Manager, data register) and Arria10
> > > > > > > datasheet
> > > > > > > rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager,
> > > > > > > img_data_w
> > > > > > > register), the FPGA data register must be written with
> > > > > > > writes
> > > > > > > with
> > > > > > > non-incrementing address.
> > > > > > >
> > > > > > > The current code increments the address in 32-byte
> > > > > > > bursts.
> > > > > > > Fix the
> > > > > > > code so it does not increment the address and writes the
> > > > > > > register
> > > > > > > repeatedly instead. >
> > > > > > > Signed-off-by: Marek Vasut
> > > > > > > Cc: Chin Liang See
> > > > > > > Cc: Dinh Nguyen
> > > > > > > Cc: Simon Goldschmidt
> > > > > > > Cc: Tien Fong Chee
> > > > > > > ---
> > > > > > > drivers/fpga/socfpga.c | 3 +--
> > > > > > > 1 file changed, 1 insertion(+), 2 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/fpga/socfpga.c
> > > > > > > b/drivers/fpga/socfpga.c
> > > > > > > index 685957626b..6ecea771ce 100644
> > > > > > > --- a/drivers/fpga/socfpga.c
> > > > > > > +++ b/drivers/fpga/socfpga.c
> > > > > > > @@ -55,8 +55,7 @@ void fpgamgr_program_write(const void
> > > > > > > *rbf_data,
> > > > > > > size_t rbf_size)
> > > > > > > " cmp %2, #0\n"
> > > > > > > " beq 2f\n"
> > > > > > > "1: ldmia %0!, {r0-r7}\n"
> > > > > > > - " stmia %1!, {r0-r7}\n"
> > > > > > > - " sub %1, #32\n"
> > > > > > > + " stmia %1, {r0-r7}\n"
> > > > > > Iirc, stmia without the "!" still stores the registers to
> > > > > > different
> > > > > > addresses, it just does not change %1 any more if you leave
> > > > > > away the
> > > > > > "!"? So this would save on opcode, but not change anything?
> > > > > Uh oh, you're right. Do we have a bigger problem here then ?
> > > > > Or
> > > > > is the
> > > > > socfpga ignoring the bottom 5 bits of this register address ?
> > > > Well, bitsream programming works for me very well (we're
> > > > loading
> > > > all our
> > > > FGPAs in U-Boot from a FIT image), so maybe it's the
> > > > documentation
> > > > that
> > > > has a problem?
> > > That could indeed be, maybe someone on the CC list can take a
> > > look
> > > into
> > > it and crosscheck it with internal docs ?
> > I can't find any doc mention about "FPGA data must be written in
> > non-
> > incremting address", but i saw there is a description about
> > configuration data is buffered in a 64 deep x 32 bits wide FIFO in
> > the
> > FPGA Manager https://www.intel.com/content/dam/www/programmable/us/
> > en/p
> > dfs/literature/hb/arria-10/a10_5v4.pdf (pg. 204)
> Well yes, it's a FIFO, but is the FIFO populated by writing to a
> single
> non-incrementing address or are we supposed to write to subsequent
> incrementing addresses ?
>
> >
> > Based on my understand through this register fpga_mgr_fpgamgrdata
> > address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes of
> > FIFO
> > buffer is mapping to above range addresses.
> 0xFFCFE7FF-0xFFCFE400 = 0x400 = 1024 Bytes , not 256 . Why ?
Finally, i have connected all scattered dot information from few
internal docs. The register fpga_mgr_fpgamgrdata is actually a space in
memory, acting like a buffer for the FPGA data. Regardless of the
programming mode, data input from this buffer is translated into a 32-
bit wide data path used by the configuration logic.
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Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
> > > > > According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page
> > > > > 175
> > > > > (Chapter 5, FPGA Manager, data register) and Arria10
> > > > > datasheet
> > > > > rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager,
> > > > > img_data_w
> > > > > register), the FPGA data register must be written with writes
> > > > > with
> > > > > non-incrementing address.
> > > > >
> > > > > The current code increments the address in 32-byte bursts.
> > > > > Fix the
> > > > > code so it does not increment the address and writes the
> > > > > register
> > > > > repeatedly instead. >
> > > > > Signed-off-by: Marek Vasut
> > > > > Cc: Chin Liang See
> > > > > Cc: Dinh Nguyen
> > > > > Cc: Simon Goldschmidt
> > > > > Cc: Tien Fong Chee
> > > > > ---
> > > > > drivers/fpga/socfpga.c | 3 +--
> > > > > 1 file changed, 1 insertion(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > > > > index 685957626b..6ecea771ce 100644
> > > > > --- a/drivers/fpga/socfpga.c
> > > > > +++ b/drivers/fpga/socfpga.c
> > > > > @@ -55,8 +55,7 @@ void fpgamgr_program_write(const void
> > > > > *rbf_data,
> > > > > size_t rbf_size)
> > > > > " cmp %2, #0\n"
> > > > > " beq 2f\n"
> > > > > "1: ldmia %0!, {r0-r7}\n"
> > > > > - " stmia %1!, {r0-r7}\n"
> > > > > - " sub %1, #32\n"
> > > > > + " stmia %1, {r0-r7}\n"
> > > > Iirc, stmia without the "!" still stores the registers to
> > > > different
> > > > addresses, it just does not change %1 any more if you leave
> > > > away the
> > > > "!"? So this would save on opcode, but not change anything?
> > > Uh oh, you're right. Do we have a bigger problem here then ? Or
> > > is the
> > > socfpga ignoring the bottom 5 bits of this register address ?
> > Well, bitsream programming works for me very well (we're loading
> > all our
> > FGPAs in U-Boot from a FIT image), so maybe it's the documentation
> > that
> > has a problem?
> That could indeed be, maybe someone on the CC list can take a look
> into
> it and crosscheck it with internal docs ?
I can't find any doc mention about "FPGA data must be written in non-
incremting address", but i saw there is a description about
configuration data is buffered in a 64 deep x 32 bits wide FIFO in the
FPGA Manager https://www.intel.com/content/dam/www/programmable/us/en/p
dfs/literature/hb/arria-10/a10_5v4.pdf (pg. 204)
Based on my understand through this register fpga_mgr_fpgamgrdata
address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes of FIFO
buffer is mapping to above range addresses.
Thanks.
Regards,
TF.
>
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Re: [U-Boot] [PATCH 00/13] System Firmware Loader for TI K3 family SoCs
On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
>
> On 07.05.19 19:25, Andreas Dannenberg wrote:
> >
[...]
> >
> > While I also have a working solution based on the existing FS
> > loader
> > framework this has its own challenges, namely by its very nature
> > only
> > addressing a subset of our use cases (no eMMC/SD RAW boot support
> > for
> > example),
IMO, it's actually not that hard to enhance RAW support, i think
minimal changes are required. I have attached the patches about an
example of loading RAW from QSPI that i have done locally last few week
ago.
> > being heavier on resource usage (needing to use ENV to pass
> > parameters),
ENV is optional, you can use DTS. For example loading FPGA bitstream
from QSPI RAW:
/* DTS */
/ {
+ aliases {
+ spi0 =
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ sfconfig = <0 0 1 3>;
+ };
+};
+
+_mgr {
+ u-boot,dm-pre-reloc;
+ firmware-loader = <_loader0>;
+ altr,bitstream = "30";
+};
> > and not addressing the need to probe the boot peripheral.
You can add more different probing method in function called
"fs_loader_probe". Current fs_loader supports block(sdmmc, emmc, etc...)
probing, and with
the patches attached support QSPI probing.
Another idea come to mind, we can use fs_loader for loading FIT boot
image into RAM, and boot from RAM with existing SPL loader framework,
but i'm not sure this implementation fit to your use case?
> > This particular framework works well for use cases requiring to
> > load
> > firmware from FS-based media once DDR is up and U-Boot is in a more
> > "initialized" state but it is not a one-fits all solution for very
> > early use in SPL board_init_f() accross different boot modes.
> And would it be an option to improve the loader (maybe dropping the
> "fs"
> from its name)? I think it's an "fs" loader because its idea has
> been
> copied from Linux. I think in U-Boot, it's more common to have things
> at
> a raw offset instead of a file system. Just thinking...
Current fs_loader only support filesystem, and i agree that it made
sense to remove the "fs" once it supports the RAW offset as well.
Thanks.
Regards,
TF
>
> And the current state of that fs_loader is like it is because it
> fits
> its single user (socfpga stratix 10), I think.
>
> Anyway, even if you do need yet another loader, would it make sense
> to
> create a common file instead of adding this in your arch/mach?
>
> Regards,
> Simon
>
> >
> >
> > Andreas Dannenberg (10):
> > mmc: k3_arasan: Allow driver to probe without PDs specified
> > spl: Allow skipping clearing BSS during relocation
> > spl: Make image loader infrastructure more universal
> > arm: K3: Introduce System Firmware loader framework
> > armV7R: K3: am654: Allow using SPL BSS pre-relocation
> > armv7R: K3: am654: Use full malloc implementation in SPL
> > armV7R: K3: am654: Load SYSFW binary and config from boot media
> > configs: am65x_evm_r5: All sysfw to be loaded via MMC
> > configs: am65x_hs_evm_r5: All sysfw to be loaded via MMC
> > configs: am65x_hs_evm: Add Support for eMMC boot
> >
> > Faiz Abbas (2):
> > configs: am65x_evm: Add Support for eMMC boot
> > am65x: README: Add eMMC layout and flash instructions
> >
> > Lokesh Vutla (1):
> > armv7R: dts: k3: am654: Update mmc nodes for loading sysfw
> >
> > arch/arm/dts/k3-am654-r5-base-board.dts | 18 ++
> > arch/arm/lib/crt0.S | 3 +
> > arch/arm/mach-k3/Kconfig | 40 +++
> > arch/arm/mach-k3/Makefile| 1 +
> > arch/arm/mach-k3/am6_init.c | 34 ++-
> > arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 +
> > arch/arm/mach-k3/sysfw-loader.c | 263
> > +++
> > board/ti/am65x/Kconfig | 1 +
> > board/ti/am65x/README| 52
> > common/spl/Kconfig | 13 +
> > common/spl/spl_fit.c | 14 +
> > common/spl/spl_mmc.c | 76 --
> > configs/am65x_evm_a53_defconfig | 2 +
> > configs/am65x_evm_r5_defconfig | 7 +-
> > configs/am65x_hs_evm_a53_defconfig | 2 +
> > configs/am65x_hs_evm_r5_defconfig| 7 +-
> > drivers/mmc/k3_arsan_sdhci.c | 16 +-
> > include/configs/am65x_evm.h | 30 ++-
> > include/spl.h| 26 ++
> > 19 files changed, 577 insertions(+), 40 deletions(-)
> > create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h
> > create mode 100644 arch/arm/mach-k3/sysfw-loader.c
> > From ff0fa68b8141fa7c83b3b42e7d6cf5a6bc27c980 Mon Sep 17 00:00:00 2001
From: Tien Fong Chee
Date: Mon, 15 Apr 2019 14:02:44 +0800
Subject:
Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
> > > > > According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page
> > > > > 175
> > > > > (Chapter 5, FPGA Manager, data register) and Arria10
> > > > > datasheet
> > > > > rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager,
> > > > > img_data_w
> > > > > register), the FPGA data register must be written with writes
> > > > > with
> > > > > non-incrementing address.
> > > > >
> > > > > The current code increments the address in 32-byte bursts.
> > > > > Fix the
> > > > > code so it does not increment the address and writes the
> > > > > register
> > > > > repeatedly instead. >
> > > > > Signed-off-by: Marek Vasut
> > > > > Cc: Chin Liang See
> > > > > Cc: Dinh Nguyen
> > > > > Cc: Simon Goldschmidt
> > > > > Cc: Tien Fong Chee
> > > > > ---
> > > > > drivers/fpga/socfpga.c | 3 +--
> > > > > 1 file changed, 1 insertion(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > > > > index 685957626b..6ecea771ce 100644
> > > > > --- a/drivers/fpga/socfpga.c
> > > > > +++ b/drivers/fpga/socfpga.c
> > > > > @@ -55,8 +55,7 @@ void fpgamgr_program_write(const void
> > > > > *rbf_data,
> > > > > size_t rbf_size)
> > > > > " cmp %2, #0\n"
> > > > > " beq 2f\n"
> > > > > "1: ldmia %0!, {r0-r7}\n"
> > > > > - " stmia %1!, {r0-r7}\n"
> > > > > - " sub %1, #32\n"
> > > > > + " stmia %1, {r0-r7}\n"
> > > > Iirc, stmia without the "!" still stores the registers to
> > > > different
> > > > addresses, it just does not change %1 any more if you leave
> > > > away the
> > > > "!"? So this would save on opcode, but not change anything?
> > > Uh oh, you're right. Do we have a bigger problem here then ? Or
> > > is the
> > > socfpga ignoring the bottom 5 bits of this register address ?
> > Well, bitsream programming works for me very well (we're loading
> > all our
> > FGPAs in U-Boot from a FIT image), so maybe it's the documentation
> > that
> > has a problem?
> That could indeed be, maybe someone on the CC list can take a look
> into
> it and crosscheck it with internal docs ?
sure. let me check.
Thanks for finding.
>
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Re: [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
On Sat, 2019-04-27 at 21:34 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Ensure the watchdog is reset timely on each status polling.
> I would have expected a longer commit message here explaining why
> this
> is done, and from where, where to, and why the watchdog reset has
> been
> moved.
>
> Anyway, I don't want to hold back this series again for this, but
> please
> next time: write longer commit messages. Better write too much than
> risk
> someone in the future doesn't get what or why you did things.
>
> Thanks,
> Simon
>
I will improve the commit messages in next version patch set.
Thanks.
> >
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v12
> > - Improved the commit messages.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > - This patch was split out from [PATCH v10 5/9]
> > ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
> > ---
> > drivers/fpga/socfpga_arria10.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index b0abe1955c..9499d1a014 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
> > printf("nstatus == 0 while waiting for
> > condone\n");
> > return -EPERM;
> > }
> > + WATCHDOG_RESET();
> > }
> >
> > if (i == FPGA_TIMEOUT_CNT)
> > @@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
> > printf("FPGA: Poll CD failed with error code
> > %d\n", status);
> > return -EPERM;
> > }
> > - WATCHDOG_RESET();
> >
> > /* Ensure the FPGA entering user mode */
> > status = fpgamgr_program_poll_usermode();
> >
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Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Fri, 2019-05-03 at 13:26 +0200, Simon Goldschmidt wrote:
> On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong com> wrote:
> >
> >
> > On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > >
> > > On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> > > wrote:
> > > >
> > > >
> > > >
> > > > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > > > >
> > > > >
> > > > >
> > > > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee
> > > > > >
> > > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > > loading
> > > > > > from
> > > > > > filesystem. The driver are designed based on generic
> > > > > > firmware
> > > > > > loader
> > > > > > framework. The driver can handle FPGA program operation
> > > > > > from
> > > > > > loading FPGA
> > > > > > bitstream in flash to memory and then to program FPGA.
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee
> > > > > >
> > > > > > ---
> > > > > >
> > > > > > changes for v12
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v11
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v10
> > > > > > -Cleaned up the codes.
> > > > > > -Return -EPERM when programing core on non early IO release
> > > > > > mode. >
> > > > > > -Using live function to get rid of gd->
> > > > > You got rid of gd-> in v10? How come I see numerous
> > > > > references to
> > > > > it
> > > > > below?
> > > > get rid of using gd->fdt_blob for finding the node_offset.
> > > > Details in https://patchwork.ozlabs.org/patch/1044415/
> > > Ah, ok. But still, here you're introducing yet more references to
> > > gd-
> > > >
> > > > fdt_blob.
> > > That wouldn't work with a live tree, either, or would it?
> > Yeah, few direct call to config_pin function are still using gd-
> > fdt_blob as argument. But, i'm not sure i should fix this function
> > in
> > this series patch set, or separately patch after this series patch
> > set?
> >
> > What do you think?
> While I do have a strong opinion that this should be cleaned up,
> it would be kind of off-topic in this patch. I was just confused by
> the
> version log.
>
> Regards,
> Simon
Okay, how about we keep these changes. I will send out the fix
separately after this patch set.
Thanks.
>
> >
> >
> > Thanks,
> > TF
> > >
> > >
> > > >
> > > >
> > > >
> > > > -/*
> > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > used by
> > > > FPGA driver.
> > > > - * Return 0 for sucess, non-zero for error.
> > > > - */
> > > > +ofnode get_fpga_mgr_ofnode(void)
> > > > +{
> > > > + int node_offset;
> > > > +
> > > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > > >
> > > > nit: using of live functions would be better to get rid of gd-
> > > > >.
> > > >
> > > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > > + _offset, 1);
> > > >
> > > > Thanks.
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > -Removed @0 for fs-loader node
> > > > > >
> > > > > > changes for v9
> > > > > > - Support data offset
> > > > > > - Added default DDR load address
> > > > > > - Squashed the image.h
> > > > > > - Changed to phandle
> > > > > > - Ensure the DDR is fully up running by checking the gd-
> > > > > > >ram
> > > > > >
> > > > > > chan
Re: [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
On Fri, 2019-05-03 at 13:54 +0200, Simon Goldschmidt wrote: > On Thu, May 2, 2019 at 9:56 AM Chee, Tien Fong com> wrote: > > > > > > On Tue, 2019-04-30 at 14:26 +0200, Simon Goldschmidt wrote: > > > > > > On Tue, Apr 30, 2019 at 2:19 PM Chee, Tien Fong > > > wrote: > > > > > > > > > > > > > > > > On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote: > > > > > > > > > > > > > > > > > > > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > > > Increasing Malloc pool size up to 0x15000 is required to > > > > > > support > > > > > > FAT in SPL > > > > > > . The result of calculation is come from after applying > > > > > > some > > > > > > few > > > > > > patches > > > > > "Some few patches"? What should that mean? Either you refer > > > > > to > > > > > the > > > > > current state or you can refer to the patchwork items. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > which are required for optimizing vfat and maximizing > > > > > > resusable > > > > > > of > > > > > > the > > > > > > memory pool, and then followed by the size required come > > > > > > from > > > > > > default max > > > > > > cluster(0x1) + others(0x2000) + additional memory for > > > > > > headroom(0x3000). > > > > > > Previous records of describing these few patches can be > > > > > > checked > > > > > > from here > > > > > > [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg > > > > > > 3145 > > > > > > 11.h > > > > > > tml . > > > > > Why do you refer to mail-archive.com instead of patchwork? > > > > Contains the cover letter in case reviewer need to know more > > > > information. > > > I think you understood that wrong. Why do you reference a 3rd > > > party > > > host (mail-archive.com) instead of the official list archive or > > > patchwork? > > > > > > And please note patchwork keeps the cover letter as well. > > Okay, i can't find any cover letter from this link https://patchwor > > k.oz > > labs.org/project/uboot/list/?series==70549=*= > > hive > > =both= . Do you know how to find it? > - Go to one of the patches of v7, e.g.: > https://patchwork.ozlabs.org/patch/1034279/ > - click "Related" > - click the 0/7 link and you'll get the cover letter: > https://patchwork.ozlabs.org/cover/1034282/ > > > > > > > > > > > > > > Also note, this is the commit message which will got into the git > > > lot. > > > Referencing v7 and older history seems misplaced here. Better > > > move > > > it below the '---'. > > Okay, noted. So, what should i do with this patch now? Should i > > send > > next version with new commit message? > Well, I don't really care about which host you reference, but yes, > please send a version that doesn't contain such a reference in > the commit log. > > Other than that, the series is, well, good enough for me to be > accepted, I guess. > > Regards, > Simon > Okay, i will send a next version. > > > > > > Thanks. > > TF > > > > > > > > > > > > > > > > > > > > > > > > Thanks. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee > > > > > > > > > > > > --- > > > > > > > > > > > > changes for v12 > > > > > > - Improved the commit messages. > > > > > > > > > > > > changes for v11 > > > > > > - No changes. > > > > > > > > > > > > changes for v10 > > > > > > - No changes. > > > >
Re: [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
On Tue, 2019-04-30 at 14:26 +0200, Simon Goldschmidt wrote: > On Tue, Apr 30, 2019 at 2:19 PM Chee, Tien Fong > wrote: > > > > > > On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote: > > > > > > > > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote: > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > Increasing Malloc pool size up to 0x15000 is required to > > > > support > > > > FAT in SPL > > > > . The result of calculation is come from after applying some > > > > few > > > > patches > > > "Some few patches"? What should that mean? Either you refer to > > > the > > > current state or you can refer to the patchwork items. > > > > > > > > > > > > > > > which are required for optimizing vfat and maximizing resusable > > > > of > > > > the > > > > memory pool, and then followed by the size required come from > > > > default max > > > > cluster(0x1) + others(0x2000) + additional memory for > > > > headroom(0x3000). > > > > Previous records of describing these few patches can be checked > > > > from here > > > > [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg3145 > > > > 11.h > > > > tml . > > > Why do you refer to mail-archive.com instead of patchwork? > > Contains the cover letter in case reviewer need to know more > > information. > I think you understood that wrong. Why do you reference a 3rd party > host (mail-archive.com) instead of the official list archive or > patchwork? > > And please note patchwork keeps the cover letter as well. Okay, i can't find any cover letter from this link https://patchwork.oz labs.org/project/uboot/list/?series==70549=*= =both= . Do you know how to find it? > > Also note, this is the commit message which will got into the git > lot. > Referencing v7 and older history seems misplaced here. Better move > it below the '---'. Okay, noted. So, what should i do with this patch now? Should i send next version with new commit message? Thanks. TF > > > > > > > Thanks. > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee > > > > > > > > --- > > > > > > > > changes for v12 > > > > - Improved the commit messages. > > > > > > > > changes for v11 > > > > - No changes. > > > > > > > > changes for v10 > > > > - No changes. > > > > > > > > changes for v9 > > > > - No changes. > > > > > > > > changes for v8 > > > > - Moved the FIT related configs to the patch of configuration > > > > for > > > > FPGA > > > > SoCFPGA A10 SoCDK. > > > > > > > > changes for v7 > > > > - Keep minimal configs. > > > > --- > > > > include/configs/socfpga_common.h | 4 ++-- > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/include/configs/socfpga_common.h > > > > b/include/configs/socfpga_common.h > > > > index 181af9b646..22533036ed 100644 > > > > --- a/include/configs/socfpga_common.h > > > > +++ b/include/configs/socfpga_common.h > > > > @@ -1,6 +1,6 @@ > > > > /* SPDX-License-Identifier: GPL-2.0+ */ > > > > /* > > > > - * Copyright (C) 2012 Altera Corporation > > > > + * Copyright (C) 2012-2019 Altera Corporation > > > > */ > > > > #ifndef __CONFIG_SOCFPGA_COMMON_H__ > > > > #define __CONFIG_SOCFPGA_COMMON_H__ > > > > @@ -254,7 +254,7 @@ unsigned int > > > > cm_get_qspi_controller_clk_hz(void); > > > > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > > > /* SPL memory allocation configuration, this is for FAT > > > > implementation */ > > > > #ifndef CONFIG_SYS_SPL_MALLOC_START > > > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001 > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 > > > > #define > > > > CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_S > > > > IZE - \ > > > > CONFIG_SYS_SPL_MALLOC_SI > > > > ZE + \ > > > > CONFIG_SYS_INIT_RAM_ADDR > > > > ) > > > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> wrote:
> >
> >
> > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > loading
> > > > from
> > > > filesystem. The driver are designed based on generic firmware
> > > > loader
> > > > framework. The driver can handle FPGA program operation from
> > > > loading FPGA
> > > > bitstream in flash to memory and then to program FPGA.
> > > >
> > > > Signed-off-by: Tien Fong Chee
> > > >
> > > > ---
> > > >
> > > > changes for v12
> > > > - No changes.
> > > >
> > > > changes for v11
> > > > - No changes.
> > > >
> > > > changes for v10
> > > > -Cleaned up the codes.
> > > > -Return -EPERM when programing core on non early IO release
> > > > mode. >
> > > > -Using live function to get rid of gd->
> > > You got rid of gd-> in v10? How come I see numerous references to
> > > it
> > > below?
> > get rid of using gd->fdt_blob for finding the node_offset.
> > Details in https://patchwork.ozlabs.org/patch/1044415/
> Ah, ok. But still, here you're introducing yet more references to gd-
> >fdt_blob.
> That wouldn't work with a live tree, either, or would it?
Yeah, few direct call to config_pin function are still using gd-
fdt_blob as argument. But, i'm not sure i should fix this function in
this series patch set, or separately patch after this series patch set?
What do you think?
Thanks,
TF
>
> >
> >
> > -/*
> > - * FPGA Manager to program the FPGA. This is the interface used by
> > FPGA driver.
> > - * Return 0 for sucess, non-zero for error.
> > - */
> > +ofnode get_fpga_mgr_ofnode(void)
> > +{
> > + int node_offset;
> > +
> > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> >
> > nit: using of live functions would be better to get rid of gd->.
> >
> > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > + _offset, 1);
> >
> > Thanks.
> > >
> > >
> > > >
> > > >
> > > > -Removed @0 for fs-loader node
> > > >
> > > > changes for v9
> > > > - Support data offset
> > > > - Added default DDR load address
> > > > - Squashed the image.h
> > > > - Changed to phandle
> > > > - Ensure the DDR is fully up running by checking the gd->ram
> > > >
> > > > changes for v8
> > > > - Added codes to discern bitstream type based on fpga node
> > > > name.
> > > >
> > > > changes for v7
> > > > - Restructure the FPGA driver to support both peripheral
> > > > bitstream
> > > > and core
> > > > bitstream bundled into FIT image.
> > > > - Support loadable property for core bitstream. User can set
> > > > loadable
> > > > in DDR for better performance. This loading would be done in
> > > > one
> > > > large
> > > > chunk instead of chunk by chunk loading with small memory
> > > > buffer.
> > > > ---
> > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > .../include/mach/fpga_manager_arria10.h| 39 +-
> > > > drivers/fpga/socfpga_arria10.c | 497
> > > > -
> > > > include/image.h| 4 +
> > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > index 998d811210..cc761967c7 100644
> > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > @@ -18,6 +18,23 @@
> > > > /dts-v1/;
> > > > #include "socfpga_arria10_socdk.dtsi"
> > > >
> > > > +/ {
> > > > +
Re: [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote: > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote: > > > > From: Tien Fong Chee > > > > Increasing Malloc pool size up to 0x15000 is required to support > > FAT in SPL > > . The result of calculation is come from after applying some few > > patches > "Some few patches"? What should that mean? Either you refer to the > current state or you can refer to the patchwork items. > > > > > which are required for optimizing vfat and maximizing resusable of > > the > > memory pool, and then followed by the size required come from > > default max > > cluster(0x1) + others(0x2000) + additional memory for > > headroom(0x3000). > > Previous records of describing these few patches can be checked > > from here > > [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg314511.h > > tml . > Why do you refer to mail-archive.com instead of patchwork? Contains the cover letter in case reviewer need to know more information. Thanks. > > > > > > > Signed-off-by: Tien Fong Chee > > > > --- > > > > changes for v12 > > - Improved the commit messages. > > > > changes for v11 > > - No changes. > > > > changes for v10 > > - No changes. > > > > changes for v9 > > - No changes. > > > > changes for v8 > > - Moved the FIT related configs to the patch of configuration for > > FPGA > > SoCFPGA A10 SoCDK. > > > > changes for v7 > > - Keep minimal configs. > > --- > > include/configs/socfpga_common.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/include/configs/socfpga_common.h > > b/include/configs/socfpga_common.h > > index 181af9b646..22533036ed 100644 > > --- a/include/configs/socfpga_common.h > > +++ b/include/configs/socfpga_common.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: GPL-2.0+ */ > > /* > > - * Copyright (C) 2012 Altera Corporation > > + * Copyright (C) 2012-2019 Altera Corporation > > */ > > #ifndef __CONFIG_SOCFPGA_COMMON_H__ > > #define __CONFIG_SOCFPGA_COMMON_H__ > > @@ -254,7 +254,7 @@ unsigned int > > cm_get_qspi_controller_clk_hz(void); > > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > /* SPL memory allocation configuration, this is for FAT > > implementation */ > > #ifndef CONFIG_SYS_SPL_MALLOC_START > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001 > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 > > #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_S > > IZE - \ > > CONFIG_SYS_SPL_MALLOC_SI > > ZE + \ > > CONFIG_SYS_INIT_RAM_ADDR > > ) > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> > loader
> > framework. The driver can handle FPGA program operation from
> > loading FPGA
> > bitstream in flash to memory and then to program FPGA.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v12
> > - No changes.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > -Cleaned up the codes.
> > -Return -EPERM when programing core on non early IO release mode. >
> > -Using live function to get rid of gd->
> You got rid of gd-> in v10? How come I see numerous references to it
> below?
get rid of using gd->fdt_blob for finding the node_offset.
Details in https://patchwork.ozlabs.org/patch/1044415/
-/*
- * FPGA Manager to program the FPGA. This is the interface used by
FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
+ofnode get_fpga_mgr_ofnode(void)
+{
+ int node_offset;
+
+ fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
nit: using of live functions would be better to get rid of gd->.
+ COMPAT_ALTERA_SOCFPGA_FPGA0,
+ _offset, 1);
Thanks.
>
> >
> > -Removed @0 for fs-loader node
> >
> > changes for v9
> > - Support data offset
> > - Added default DDR load address
> > - Squashed the image.h
> > - Changed to phandle
> > - Ensure the DDR is fully up running by checking the gd->ram
> >
> > changes for v8
> > - Added codes to discern bitstream type based on fpga node name.
> >
> > changes for v7
> > - Restructure the FPGA driver to support both peripheral bitstream
> > and core
> > bitstream bundled into FIT image.
> > - Support loadable property for core bitstream. User can set
> > loadable
> > in DDR for better performance. This loading would be done in one
> > large
> > chunk instead of chunk by chunk loading with small memory
> > buffer.
> > ---
> > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > .../include/mach/fpga_manager_arria10.h| 39 +-
> > drivers/fpga/socfpga_arria10.c | 497
> > -
> > include/image.h| 4 +
> > 4 files changed, 542 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > index 998d811210..cc761967c7 100644
> > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > @@ -18,6 +18,23 @@
> > /dts-v1/;
> > #include "socfpga_arria10_socdk.dtsi"
> >
> > +/ {
> > + chosen {
> > + firmware-loader = <_loader0>;
> > + };
> > +
> > + fs_loader0: fs-loader {
> > + u-boot,dm-pre-reloc;
> > + compatible = "u-boot,fs-loader";
> > + phandlepart = < 1>;
> > + };
> > +};
> > +
> > +_mgr {
> > + u-boot,dm-pre-reloc;
> > + altr,bitstream = "fit_spl_fpga.itb";
> > +};
> > +
> > {
> > u-boot,dm-pre-reloc;
> > status = "okay";
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h
> > index 09d13f6fd3..c5f67714aa 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > @@ -1,9 +1,13 @@
> > /* SPDX-License-Identifier: GPL-2.0 */
> > /*
> > - * Copyright (C) 2017 Intel Corporation
> > + * Copyright (C) 2017-2019 Intel Corporation
> > * All rights reserved.
> > */
> >
> > +#include
> > +#include
> > +#include
> > +
> > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > #define _FPGA_MANAGER_ARRIA10_H_
> >
> > @@ -51,6 +55,10 @@
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > BIT(24)
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > 16
> >
> > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > +#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
> > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > #ifndef __ASSEMBLY__
> >
> > struct socfpga_fpga_manager {
> > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > u32 imgcfg_fifo_status;
> > };
> >
> > +enum rbf_type {
> > + unknown,
> > + periph_section,
> > + core_section
> > +};
> > +
> > +enum rbf_security {
> > + invalid,
> > + unencrypted,
> > + encrypted
> > +};
> > +
> > +struct rbf_info {
> > + enum rbf_type section;
> > + enum rbf_security security;
> > +};
> > +
> > +struct fpga_loadfs_info {
> > + fpga_fs_info *fpga_fsinfo;
> > + u32 remaining;
> > + u32 offset;
> > + struct rbf_info rbfinfo;
> > +};
> > +
> >
Re: [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
On Sat, 2019-04-27 at 21:34 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Ensure the watchdog is reset timely on each status polling.
> I would have expected a longer commit message here explaining why
> this
> is done, and from where, where to, and why the watchdog reset has
> been
> moved.
>
> Anyway, I don't want to hold back this series again for this, but
> please
> next time: write longer commit messages. Better write too much than
> risk
> someone in the future doesn't get what or why you did things.
>
Noted.
Thanks.
>
> >
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v12
> > - Improved the commit messages.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > - This patch was split out from [PATCH v10 5/9]
> > ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
> > ---
> > drivers/fpga/socfpga_arria10.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index b0abe1955c..9499d1a014 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
> > printf("nstatus == 0 while waiting for
> > condone\n");
> > return -EPERM;
> > }
> > + WATCHDOG_RESET();
> > }
> >
> > if (i == FPGA_TIMEOUT_CNT)
> > @@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
> > printf("FPGA: Poll CD failed with error code
> > %d\n", status);
> > return -EPERM;
> > }
> > - WATCHDOG_RESET();
> >
> > /* Ensure the FPGA entering user mode */
> > status = fpgamgr_program_poll_usermode();
> >
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] fit: Add support for printing more than one FPGA node name
On Mon, 2019-04-22 at 13:29 -0400, Tom Rini wrote:
> On Wed, Feb 13, 2019 at 08:32:24PM +0800, tien.fong.c...@intel.com
> wrote:
>
> >
> > From: Tien Fong Chee
> >
> > This would print out all the FPGA node names setting to fpga
> > property.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> > common/image-fit.c | 14 +++---
> > 1 files changed, 11 insertions(+), 3 deletions(-)
> >
> > diff --git a/common/image-fit.c b/common/image-fit.c
> > index ac901e1..816e17d 100644
> > --- a/common/image-fit.c
> > +++ b/common/image-fit.c
> > @@ -263,6 +263,7 @@ static void fit_conf_print(const void *fit, int
> > noffset, const char *p)
> > int ret;
> > int fdt_index, loadables_index;
> > int ndepth;
> > + ulong count;
> >
> > /* Mandatory properties */
> > ret = fit_get_desc(fit, noffset, );
> > @@ -299,9 +300,16 @@ static void fit_conf_print(const void *fit,
> > int noffset, const char *p)
> > printf("%s\n", uname);
> > }
> >
> > - uname = fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
> > - if (uname)
> > - printf("%s FPGA: %s\n", p, uname);
> > + count = fit_conf_get_prop_node_count(fit, noffset,
> > FIT_FPGA_PROP);
> > +
> > + for (ndepth = 0; ndepth < count; ndepth++) {
> > + int images_noffset =
> > fit_conf_get_prop_node_index(fit, noffset,
> > + FIT_FPGA_PROP,
> > ndepth);
> > + uname = fit_get_name(fit, images_noffset, NULL);
> > +
> > + if (uname)
> > + printf("%s FPGA: %s\n", p,
> > uname);
> > + }
> >
> > /* Print out all of the specified loadables */
> > for (loadables_index = 0;
> While I'm fine with the conceptual change here, both
> fit_conf_get_prop_node_count / fit_conf_get_prop_node_index are
> defined
> later in the file and while public functions not documented in a
> header.
> Can you please do a patch that does so first, as we otherwise get a
> warning? Thanks!
The header file in this patch https://patchwork.ozlabs.org/patch/105828
9/ , unfortunately the review taking a bit longer than what i expected.
I would update you once the whole series patches are accepted.
Thanks a lot.
>
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Re: [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream
On Tue, 2019-03-19 at 16:50 +0800, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > This version mainly resolved comments from Dinh in [v11]. > > This series is working on top of u-boot.git http://git.denx.de/u-boot > .git > > These patches are required before applying this series of patches > 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block > device > https://patchwork.ozlabs.org/project/uboot/list/?series=89282 (done > review) > > 2. [U-Boot] fpga: Replace char * with const char * for filename > https://patchwork.ozlabs.org/patch/1042665/ (done review) > > 3. [U-Boot] misc: fs_loader: Replace label with DT phandle > https://patchwork.ozlabs.org/patch/1051782/ (under review) > > [v11]: https://www.mail-archive.com/u-boot@lists.denx.de/msg318174.ht > ml > [v10]: https://www.mail-archive.com/u-boot@lists.denx.de/msg318167.ht > ml > [v9]: https://www.mail-archive.com/u-boot@lists.denx.de/msg316086.htm > l > [v8]: https://www.mail-archive.com/u-boot@lists.denx.de/msg316086.htm > l > [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg314511.htm > l > > Tien Fong Chee (9): > ARM: socfpga: Description on FPGA bitstream type and file name for > Arria 10 > ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK > ARM: socfpga: Cleaning up and ensuring consistent format messages > in > driver > ARM: socfpga: Moving the watchdog reset to the for-loop status > polling > ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading > ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK > spl : socfpga: Implement fpga bitstream loading with socfpga loadfs > ARM: socfpga: Synchronize the configuration for A10 SoCDK > ARM: socfpga: Increase Malloc pool size to support FAT filesystem > in > SPL > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 + > .../include/mach/fpga_manager_arria10.h| 40 +- > arch/arm/mach-socfpga/spl_a10.c| 31 +- > board/altera/arria10-socdk/fit_spl_fpga.its| 38 ++ > configs/socfpga_arria10_defconfig | 22 +- > .../fpga/altera-socfpga-a10-fpga-mgr.txt | 26 +- > drivers/fpga/socfpga_arria10.c | 514 > - > include/configs/socfpga_common.h | 4 +- > include/image.h| 4 + > 9 files changed, 664 insertions(+), 32 deletions(-) > create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its > Any comment about this series of patches? Thanks. Regards, TF. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [SoCFPGA] co-custodianship
On Wed, 2019-03-27 at 09:40 -0400, Tom Rini wrote: > On Wed, Mar 27, 2019 at 07:00:19AM +0100, Stefan Roese wrote: > > > > Hi Marek, > > > > On 26.03.19 17:43, Marek Vasut wrote: > > > > > > I would like to nominate Simon Goldschmidt as a co-custodian for > > > the > > > SoCFPGA platform to help me review patches and collect them into > > > PRs. > > > Any objections ? > > Not at all. Simon is doing a magnificent job with his U-Boot > > contributions since quite a long time. So I would very much > > welcome him "on-board" here too. > Indeed! Please send a patch updating MAINTAINERS / git-mailrc, Yeah, i agree with you all, Simon is very helpful, and he has made a lot improvements in U-Boot. > thanks! > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/6] arm: socfpga: a10: move SPL stack size to Kconfig
On Tue, 2019-03-19 at 17:29 +0100, Simon Goldschmidt wrote: > Am 19.03.2019 um 17:19 schrieb Chee, Tien Fong: > > > > On Fri, 2019-03-15 at 21:13 +0100, Simon Goldschmidt wrote: > > > > > > Instead of fixing the SPL stack to 64 KiB in the board config > > > header > > > via > > > CONFIG_SYS_SPL_MALLOC_SIZE, let's just use > > > CONFIG_SPL_SYS_MALLOC_F_LEN > > > in the defconfig. > > > > > > This also has the advandage that it removes sub-mach specific > > > ifdefs > > > in > > > socfpga_common.h. > > > > > > Signed-off-by: Simon Goldschmidt > > > > > > --- > > Hi Simon, > > > > I found the culprit in patch[5], you cannot put mem_malloc_init in > > spl_common_init function because spl_common_init would be called in > > board_init_f, then board_init_f would call mem_malloc_init, > > mem_malloc_init would store start and end addresses to few global > > variables such as mem_malloc_start, mem_malloc_end and > > mem_malloc_brk. > > By that time, global variables are unavailable yet. > Thanks for testing. Patch 2/6 should make sure global variables are > available in board_init_f by clearing bss *before* calling that > function, not *after* calling it. Because technicaly, global > variables > are always available for a10-SPL as they are located in SRAM. They > only > got cleared after board_init_f... Yes, you are right, memset would clear .BSS after mem_malloc_init. > > Which gets me to my error: I forgot to enable the newly added > CONFIG_SPL_CLEAR_BSS_F in this patch. Could you probably try again > with > CONFIG_SPL_CLEAR_BSS_F enabled? That would be great! Tested, passing. May be force enabling it or compile error if full malloc is used? Thanks. TF. > > Regards, > Simon > > > > > > > Thanks. > > TF > > > > > > > > > > > Changes in v2: None > > > > > > configs/socfpga_arria10_defconfig | 1 + > > > include/configs/socfpga_common.h | 14 -- > > > 2 files changed, 1 insertion(+), 14 deletions(-) > > > > > > diff --git a/configs/socfpga_arria10_defconfig > > > b/configs/socfpga_arria10_defconfig > > > index f321a0ac3b..8d0479cc05 100644 > > > --- a/configs/socfpga_arria10_defconfig > > > +++ b/configs/socfpga_arria10_defconfig > > > @@ -2,6 +2,7 @@ CONFIG_ARM=y > > > CONFIG_ARCH_SOCFPGA=y > > > CONFIG_SYS_TEXT_BASE=0x0140 > > > CONFIG_SYS_MALLOC_F_LEN=0x2000 > > > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1 > > > CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y > > > CONFIG_SPL=y > > > CONFIG_IDENT_STRING="socfpga_arria10" > > > diff --git a/include/configs/socfpga_common.h > > > b/include/configs/socfpga_common.h > > > index 181af9b646..16c83900c3 100644 > > > --- a/include/configs/socfpga_common.h > > > +++ b/include/configs/socfpga_common.h > > > @@ -251,16 +251,6 @@ unsigned int > > > cm_get_qspi_controller_clk_hz(void); > > > #define CONFIG_SPL_TEXT_BASECONFIG_SYS_INIT_RAM > > > _ADDR > > > #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_ > > > SIZE > > > > > > -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > > -/* SPL memory allocation configuration, this is for FAT > > > implementation */ > > > -#ifndef CONFIG_SYS_SPL_MALLOC_START > > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001 > > > -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ > > > SIZE > > > - \ > > > - CONFIG_SYS_SPL_MALLOC_S > > > IZE > > > + \ > > > - CONFIG_SYS_INIT_RAM_ADD > > > R) > > > -#endif > > > -#endif > > > - > > > /* SPL SDMMC boot support */ > > > #ifdef CONFIG_SPL_MMC_SUPPORT > > > #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) > > > @@ -294,11 +284,7 @@ unsigned int > > > cm_get_qspi_controller_clk_hz(void); > > > /* > > > * Stack setup > > > */ > > > -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > > #define CONFIG_SPL_STACKCONFIG_SYS_INIT_SP_ADDR > > > -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > > -#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_ST > > > ART > > > -#endif > > > > > > /* Extra Environment */ > > > #ifndef CONFIG_SPL_BUILD ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/6] arm: socfpga: a10: move SPL stack size to Kconfig
On Fri, 2019-03-15 at 21:13 +0100, Simon Goldschmidt wrote: > Instead of fixing the SPL stack to 64 KiB in the board config header > via > CONFIG_SYS_SPL_MALLOC_SIZE, let's just use > CONFIG_SPL_SYS_MALLOC_F_LEN > in the defconfig. > > This also has the advandage that it removes sub-mach specific ifdefs > in > socfpga_common.h. > > Signed-off-by: Simon Goldschmidt > --- Hi Simon, I found the culprit in patch[5], you cannot put mem_malloc_init in spl_common_init function because spl_common_init would be called in board_init_f, then board_init_f would call mem_malloc_init, mem_malloc_init would store start and end addresses to few global variables such as mem_malloc_start, mem_malloc_end and mem_malloc_brk. By that time, global variables are unavailable yet. Thanks. TF > > Changes in v2: None > > configs/socfpga_arria10_defconfig | 1 + > include/configs/socfpga_common.h | 14 -- > 2 files changed, 1 insertion(+), 14 deletions(-) > > diff --git a/configs/socfpga_arria10_defconfig > b/configs/socfpga_arria10_defconfig > index f321a0ac3b..8d0479cc05 100644 > --- a/configs/socfpga_arria10_defconfig > +++ b/configs/socfpga_arria10_defconfig > @@ -2,6 +2,7 @@ CONFIG_ARM=y > CONFIG_ARCH_SOCFPGA=y > CONFIG_SYS_TEXT_BASE=0x0140 > CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1 > CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y > CONFIG_SPL=y > CONFIG_IDENT_STRING="socfpga_arria10" > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > index 181af9b646..16c83900c3 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -251,16 +251,6 @@ unsigned int > cm_get_qspi_controller_clk_hz(void); > #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR > #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE > > -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > -/* SPL memory allocation configuration, this is for FAT > implementation */ > -#ifndef CONFIG_SYS_SPL_MALLOC_START > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001 > -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE > - \ > - CONFIG_SYS_SPL_MALLOC_SIZE > + \ > - CONFIG_SYS_INIT_RAM_ADDR) > -#endif > -#endif > - > /* SPL SDMMC boot support */ > #ifdef CONFIG_SPL_MMC_SUPPORT > #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) > @@ -294,11 +284,7 @@ unsigned int > cm_get_qspi_controller_clk_hz(void); > /* > * Stack setup > */ > -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR > -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > -#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START > -#endif > > /* Extra Environment */ > #ifndef CONFIG_SPL_BUILD ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] misc: fs_loader: Replace label with DT phandle
On Tue, 2019-03-19 at 09:22 +0800, Simon Glass wrote: > Hi Tien Fong, > > On Mon, 11 Mar 2019 at 12:28, Chee, Tien Fong om> wrote: > > > > > > On Sun, 2019-03-10 at 15:51 -0600, Simon Glass wrote: > > > > > > Hi Tien Fong, > > > > > > On Tue, 26 Feb 2019 at 05:37, Chee, Tien Fong > > el.c > > > om> wrote: > > > > > > > > > > > > > > > > On Fri, 2019-02-15 at 14:35 +0800, tien.fong.c...@intel.com > > > > wrote: > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > In previously label which will be expanded to the node's full > > > > > path > > > > > was > > > > > used, and now replacing label with most commonly used DT > > > > > phandle. > > > > > The > > > > > codes were changed accordingly to the use of DT phandle and > > > > > supporting > > > > > multiple instances. > > > > > > > > > > Signed-off-by: Tien Fong Chee > > > > > --- > > > > > doc/driver-model/fs_firmware_loader.txt | 58 > > > > > +-- > > > > > drivers/misc/fs_loader.c| 36 - > > > > > > > > > > -- > > > > > 2 files changed, 62 insertions(+), 32 deletions(-) > > > This seems OK to me, but I think this feature needs a test. > > Yes, i have ran the test passed with FPGA driver. > No I mean that you should add a test in test/py/tests Okay, noted. > > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
