[U-Boot] [PATCH] T4240RDB: Enable CONFIG_SYS_CORTINA_FW_IN_NOR config
Now cortina driver uses macro CONFIG_SYS_CORTINA_FW_IN_NOR to define that firmware of cortina driver is stored in the nor flash. Signed-off-by: Chunhe Lan chunhe@freescale.com --- include/configs/T4240RDB.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b644a6c..36fbaff 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -639,6 +639,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHYLIB_10G #define CONFIG_PHY_VITESSE #define CONFIG_PHY_CORTINA +#define CONFIG_SYS_CORTINA_FW_IN_NOR #define CONFIG_CORTINA_FW_ADDR 0xefe0 #define CONFIG_CORTINA_FW_LENGTH 0x4 #define CONFIG_PHY_TERANETICS -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/t4rdb: Add SD boot support for T4240RDB board
This patch adds SD boot support for T4240RDB board. SPL
framework is used. PBL initializes the internal RAM and
copies SPL to it. Then SPL initializes DDR using SPD and
copies u-boot from SD card to DDR, finally SPL transfers
control to u-boot.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
arch/powerpc/cpu/mpc85xx/Kconfig |1 +
board/freescale/t4rdb/MAINTAINERS |1 +
board/freescale/t4rdb/Makefile|6 ++-
board/freescale/t4rdb/ddr.c |6 ++-
board/freescale/t4rdb/spl.c | 95 +
board/freescale/t4rdb/t4_pbi.cfg |3 -
board/freescale/t4rdb/t4_rcw.cfg |6 +-
board/freescale/t4rdb/tlb.c |8 +++
configs/T4240RDB_SDCARD_defconfig |5 ++
include/configs/T4240RDB.h| 71 ---
10 files changed, 186 insertions(+), 16 deletions(-)
create mode 100644 board/freescale/t4rdb/spl.c
create mode 100644 configs/T4240RDB_SDCARD_defconfig
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index adb5bd3..27eea29 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -131,6 +131,7 @@ config TARGET_T4240QDS
config TARGET_T4240RDB
bool Support T4240RDB
+ select SUPPORT_SPL
config TARGET_CONTROLCENTERD
bool Support controlcenterd
diff --git a/board/freescale/t4rdb/MAINTAINERS
b/board/freescale/t4rdb/MAINTAINERS
index 845c1b6..53ccabc 100644
--- a/board/freescale/t4rdb/MAINTAINERS
+++ b/board/freescale/t4rdb/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/freescale/t4rdb/
F: include/configs/T4240RDB.h
F: configs/T4160RDB_defconfig
F: configs/T4240RDB_defconfig
+F: configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 3886e3d..83b55ee 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -4,10 +4,14 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-$(CONFIG_T4240RDB) += t4240rdb.o
obj-y += cpld.o
-obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 5a43c1b..27b37b5 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -108,11 +108,15 @@ phys_size_t initdram(int board_type)
puts(Initializingusing SPD\n);
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x10);
dram_size *= 0x10;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
- puts(DDR: );
return dram_size;
}
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
new file mode 100644
index 000..68ecde7
--- /dev/null
+++ b/board/freescale/t4rdb/spl.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Chunhe Lan chunhe@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/spl.h
+#include malloc.h
+#include ns16550.h
+#include nand.h
+#include mmc.h
+#include fsl_esdhc.h
+#include i2c.h
+
+#include t4rdb.h
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC = 3.4 */
+ __asm__ __volatile__( : : : memory);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(gur-rcwsr[0]) 25) 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ccb_clk / 16 / CONFIG_BAUDRATE);
+
+ puts(\nSD boot...\n);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd-bd = bd;
+ bd-bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd-bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR
[U-Boot] [PATCH] driver/ddr/fsl: Remove duplicate inclusion of header file
The fsl_immap.h header file had been included in common.h header file. So remove duplicated header. Signed-off-by: Chunhe Lan chunhe@freescale.com --- drivers/ddr/fsl/ctrl_regs.c|1 - drivers/ddr/fsl/fsl_ddr_gen4.c |1 - drivers/ddr/fsl/util.c |1 - 3 files changed, 0 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 03d7ff1..325bf06 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -14,7 +14,6 @@ #include fsl_ddr_sdram.h #include fsl_ddr.h -#include fsl_immap.h #include asm/io.h unsigned int picos_to_mclk(unsigned int picos); diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index a3c01e7..8b78652 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -8,7 +8,6 @@ #include asm/io.h #include fsl_ddr_sdram.h #include asm/processor.h -#include fsl_immap.h #include fsl_ddr.h #if (CONFIG_CHIP_SELECTS_PER_CTRL 4) diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 58b519b..a66f1ea 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -13,7 +13,6 @@ #include div64.h #include fsl_ddr.h -#include fsl_immap.h #include asm/io.h /* To avoid 64-bit full-divides, we factor this here */ -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/t4240rdb: Add alternate SerDes 2 protocol to align with RCW
SerDes 2 protocol 56 is not valid any longer due to
the new RCW; protocol 55 is used instead, so add
SerDes 2 protocol 55 to align with RCW.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/t4rdb/eth.c |2 +-
board/freescale/t4rdb/t4_rcw.cfg |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 142c6a8..879bd1a 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -101,7 +101,7 @@ int board_eth_init(bd_t *bis)
}
#if (CONFIG_SYS_NUM_FMAN == 2)
- if (srds_prtcl_s2 == 56) {
+ if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII XFI */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index fdbbe5e..32959e3 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 27_56_1_9
+#serdes protocol 27_55_1_9
16070019 18101916
-6c700848 00448c00 6c02 f500
+6c6e0848 00448c00 0c02 f500
eeee 000287fc
5000 0028
--
1.7.6.5
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[U-Boot] [PATCH v2] powerpc/t4240rdb: Add alternate SerDes 2 protocol to align with RCW
SerDes 2 protocol 56 is not valid any longer due to
the new RCW; protocol 55 is used instead, so add
SerDes 2 protocol 55 to align with RCW.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/t4rdb/eth.c |2 +-
board/freescale/t4rdb/t4_rcw.cfg |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 142c6a8..879bd1a 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -101,7 +101,7 @@ int board_eth_init(bd_t *bis)
}
#if (CONFIG_SYS_NUM_FMAN == 2)
- if (srds_prtcl_s2 == 56) {
+ if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII XFI */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index fdbbe5e..e46c7b2 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 27_56_1_9
+#serdes protocol 27_55_1_9
16070019 18101916
-6c700848 00448c00 6c02 f500
+6c6e0848 00448c00 6c02 f500
eeee 000287fc
5000 0028
--
1.7.6.5
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[U-Boot] [PATCH] powerpc/t4240rdb: Convert to use generic board code
Signed-off-by: Chunhe Lan chunhe@freescale.com --- include/configs/T4240RDB.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 5ab1b47..eff1db9 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,6 +12,8 @@ #define CONFIG_T4240RDB #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/hydra: Update MDIO mux fixups
The new device trees use a more generic interface for supporting muxing mdio buses. The mux property is thus specified in reg, rather than fsl,hydra-mdio-muxval. In order to support using old device trees, we keep the old fixup in there. Linux will therefore see the both properties, but will ignore fsl,hydra-mdio-muxval. Signed-off-by: Chunhe Lan chunhe@freescale.com --- board/freescale/corenet_ds/eth_hydra.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 35825c4..a934c8c 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -62,7 +62,7 @@ #ifdef CONFIG_FMAN_ENET -#define BRDCFG1_EMI1_SEL_MASK 0x70 +#define BRDCFG1_EMI1_SEL_MASK 0x78 #define BRDCFG1_EMI1_SEL_SLOT1 0x10 #define BRDCFG1_EMI1_SEL_SLOT2 0x20 #define BRDCFG1_EMI1_SEL_SLOT5 0x30 @@ -202,6 +202,8 @@ static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) if (!path) path = alias; + do_fixup_by_path(fdt, path, reg, +mux, sizeof(mux), 1); do_fixup_by_path(fdt, path, fsl,hydra-mdio-muxval, mux, sizeof(mux), 1); } -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/p1023rdb: Enable configs to use generic board code
Add configs: o CONFIG_SYS_GENERIC_BOARD o CONFIG_DISPLAY_BOARDINFO in P1023RDB config header file to use U-boot generic board code. Signed-off-by: Chunhe Lan chunhe@freescale.com --- include/configs/P1023RDB.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index ba3da06..2631636 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff4 #endif -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/c29xpcie: Enable configs to use generic board code
Add configs: o CONFIG_SYS_GENERIC_BOARD o CONFIG_DISPLAY_BOARDINFO in C29XPCIE config header file to use U-boot generic board code. Signed-off-by: Chunhe Lan chunhe@freescale.com --- include/configs/C29XPCIE.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 9e12fac..be91704 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -12,6 +12,8 @@ #define __CONFIG_H #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_C29XPCIE #define CONFIG_PPC_C29X -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] powerpc/t4rdb: Add support of CPLD
This support of CPLD includes
- Files and register definitions
- Command to switch alternate bank
- Command to switch default bank
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/t4rdb/Makefile |1 +
board/freescale/t4rdb/cpld.c | 136 ++
board/freescale/t4rdb/cpld.h | 49 ++
board/freescale/t4rdb/law.c |3 +
board/freescale/t4rdb/t4240rdb.c | 12
board/freescale/t4rdb/tlb.c |5 ++
include/configs/T4240RDB.h | 23 +++
7 files changed, 229 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/t4rdb/cpld.c
create mode 100644 board/freescale/t4rdb/cpld.h
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index f7f7fc0..3886e3d 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -5,6 +5,7 @@
#
obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += cpld.o
obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
new file mode 100644
index 000..d5f3812
--- /dev/null
+++ b/board/freescale/t4rdb/cpld.c
@@ -0,0 +1,136 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Author: Chunhe Lan chunhe@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some
Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include common.h
+#include command.h
+#include asm/io.h
+
+#include cpld.h
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+ u8 val, curbank, altbank, override;
+
+ val = CPLD_READ(vbank);
+ curbank = val CPLD_BANK_SEL_MASK;
+
+ switch (curbank) {
+ case CPLD_SELECT_BANK0:
+ altbank = CPLD_SELECT_BANK4;
+ CPLD_WRITE(vbank, altbank);
+ override = CPLD_READ(software_on);
+ CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
+ CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
+ break;
+ case CPLD_SELECT_BANK4:
+ altbank = CPLD_SELECT_BANK0;
+ CPLD_WRITE(vbank, altbank);
+ override = CPLD_READ(software_on);
+ CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
+ CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
+ break;
+ default:
+ printf(CPLD Altbank Fail: Invalid value!\n);
+ return;
+ }
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ u8 val;
+
+ val = CPLD_DEFAULT_BANK;
+
+ CPLD_WRITE(global_reset, val);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf(chip_id1= 0x%02x\n, CPLD_READ(chip_id1));
+ printf(chip_id2= 0x%02x\n, CPLD_READ(chip_id2));
+ printf(sw_maj_ver = 0x%02x\n, CPLD_READ(sw_maj_ver));
+ printf(sw_min_ver = 0x%02x\n, CPLD_READ(sw_min_ver));
+ printf(hw_ver = 0x%02x\n, CPLD_READ(hw_ver));
+ printf(software_on = 0x%02x\n, CPLD_READ(software_on));
+ printf(cfg_rcw_src = 0x%02x\n, CPLD_READ(cfg_rcw_src));
+ printf(res0= 0x%02x\n, CPLD_READ(res0));
+ printf(vbank = 0x%02x\n, CPLD_READ(vbank));
+ printf(sw1_sysclk = 0x%02x\n, CPLD_READ(sw1_sysclk));
+ printf(sw2_status = 0x%02x\n, CPLD_READ(sw2_status));
+ printf(sw3_status = 0x%02x\n, CPLD_READ(sw3_status));
+ printf(sw4_status = 0x%02x\n, CPLD_READ(sw4_status));
+ printf(sys_reset = 0x%02x\n, CPLD_READ(sys_reset));
+ printf(global_reset= 0x%02x\n, CPLD_READ(global_reset));
+ printf(res1= 0x%02x\n, CPLD_READ(res1));
+ putc('\n');
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc = 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], reset) == 0) {
+ if (strcmp(argv[2], altbank) == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], dump) == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ Reset the board or alternate bank,
+ reset - reset to default bank\n
[U-Boot] [PATCH] P1023RDB: Update default environment
Signed-off-by: Chunhe Lan chunhe@freescale.com --- include/configs/P1023RDB.h | 43 +++ 1 files changed, 43 insertions(+), 0 deletions(-) diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index ba3da06..6b29add 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -374,6 +374,49 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + netdev=eth0\0 \ + uboot= __stringify(CONFIG_UBOOTPATH) \0 \ + loadaddr=100\0\ + ubootaddr= __stringify(CONFIG_SYS_TEXT_BASE) \0 \ + tftpflash=tftpboot $loadaddr $uboot; \ + protect off $ubootaddr +$filesize;\ + erase $ubootaddr +$filesize; \ + cp.b $loadaddr $ubootaddr $filesize; \ + protect on $ubootaddr +$filesize; \ + cmp.b $loadaddr $ubootaddr $filesize\0\ + consoledev=ttyS0\0\ + ramdiskaddr=200\0 \ + ramdiskfile=rootfs.ext2.gz.uboot\0\ + fdtaddr=c0\0 \ + fdtfile=p1023rdb.dtb\0\ + othbootargs=ramdisk_size=60\0 \ + bdev=sda1\0 \ hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 +#define CONFIG_HDBOOT \ + setenv bootargs root=/dev/$bdev rw\ + console=$consoledev,$baudrate $othbootargs; \ + tftp $loadaddr $bootfile; \ + tftp $fdtaddr $fdtfile; \ + bootm $loadaddr - $fdtaddr + +#define CONFIG_NFSBOOTCOMMAND \ + setenv bootargs root=/dev/nfs rw \ + nfsroot=$serverip:$rootpath \ + ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off \ + console=$consoledev,$baudrate $othbootargs; \ + tftp $loadaddr $bootfile; \ + tftp $fdtaddr $fdtfile; \ + bootm $loadaddr - $fdtaddr + +#define CONFIG_RAMBOOTCOMMAND \ + setenv bootargs root=/dev/ram rw \ + console=$consoledev,$baudrate $othbootargs; \ + tftp $ramdiskaddr $ramdiskfile; \ + tftp $loadaddr $bootfile; \ + tftp $fdtaddr $fdtfile; \ + bootm $loadaddr $ramdiskaddr $fdtaddr + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + #endif /* __CONFIG_H */ -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/t4rdb: Add support of CPLD
This support of CPLD includes
- Files and register definitions
- Command to switch alternate bank
- Command to switch default bank
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/t4rdb/Makefile |1 +
board/freescale/t4rdb/cpld.c | 136 ++
board/freescale/t4rdb/cpld.h | 49 ++
board/freescale/t4rdb/law.c |3 +
board/freescale/t4rdb/t4240rdb.c | 12
board/freescale/t4rdb/tlb.c |5 ++
include/configs/T4240RDB.h | 23 +++
7 files changed, 229 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/t4rdb/cpld.c
create mode 100644 board/freescale/t4rdb/cpld.h
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index f7f7fc0..3886e3d 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -5,6 +5,7 @@
#
obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += cpld.o
obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
new file mode 100644
index 000..d5f3812
--- /dev/null
+++ b/board/freescale/t4rdb/cpld.c
@@ -0,0 +1,136 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Author: Chunhe Lan chunhe@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some
Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include common.h
+#include command.h
+#include asm/io.h
+
+#include cpld.h
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+ u8 val, curbank, altbank, override;
+
+ val = CPLD_READ(vbank);
+ curbank = val CPLD_BANK_SEL_MASK;
+
+ switch (curbank) {
+ case CPLD_SELECT_BANK0:
+ altbank = CPLD_SELECT_BANK4;
+ CPLD_WRITE(vbank, altbank);
+ override = CPLD_READ(software_on);
+ CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
+ CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
+ break;
+ case CPLD_SELECT_BANK4:
+ altbank = CPLD_SELECT_BANK0;
+ CPLD_WRITE(vbank, altbank);
+ override = CPLD_READ(software_on);
+ CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
+ CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
+ break;
+ default:
+ printf(CPLD Altbank Fail: Invalid value!\n);
+ return;
+ }
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ u8 val;
+
+ val = CPLD_DEFAULT_BANK;
+
+ CPLD_WRITE(global_reset, val);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf(chip_id1= 0x%02x\n, CPLD_READ(chip_id1));
+ printf(chip_id2= 0x%02x\n, CPLD_READ(chip_id2));
+ printf(sw_maj_ver = 0x%02x\n, CPLD_READ(sw_maj_ver));
+ printf(sw_min_ver = 0x%02x\n, CPLD_READ(sw_min_ver));
+ printf(hw_ver = 0x%02x\n, CPLD_READ(hw_ver));
+ printf(software_on = 0x%02x\n, CPLD_READ(software_on));
+ printf(cfg_rcw_src = 0x%02x\n, CPLD_READ(cfg_rcw_src));
+ printf(res0= 0x%02x\n, CPLD_READ(res0));
+ printf(vbank = 0x%02x\n, CPLD_READ(vbank));
+ printf(sw1_sysclk = 0x%02x\n, CPLD_READ(sw1_sysclk));
+ printf(sw2_status = 0x%02x\n, CPLD_READ(sw2_status));
+ printf(sw3_status = 0x%02x\n, CPLD_READ(sw3_status));
+ printf(sw4_status = 0x%02x\n, CPLD_READ(sw4_status));
+ printf(sys_reset = 0x%02x\n, CPLD_READ(sys_reset));
+ printf(global_reset= 0x%02x\n, CPLD_READ(global_reset));
+ printf(res1= 0x%02x\n, CPLD_READ(res1));
+ putc('\n');
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc = 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], reset) == 0) {
+ if (strcmp(argv[2], altbank) == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], dump) == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ Reset the board or alternate bank,
+ reset - reset to default bank\n
[U-Boot] [PATCH v2] powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.
Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/t4rdb/eth.c |2 +-
board/freescale/t4rdb/t4_rcw.cfg |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index d220475..142c6a8 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, tgec_mdio_info);
- if (srds_prtcl_s1 == 28) {
+ if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index 13408bd..51e9539 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 28_56_2_10
+#serdes protocol 27_56_1_9
16070019 18101916
-70701050 00448c00 6c02 f500
+6c700848 00448c00 0c02 f500
eeee 000287fc
5000 0028
--
1.7.6.5
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[U-Boot] [PATCH v3] powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.
Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/t4rdb/eth.c |2 +-
board/freescale/t4rdb/t4_rcw.cfg |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index d220475..142c6a8 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, tgec_mdio_info);
- if (srds_prtcl_s1 == 28) {
+ if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index 13408bd..fdbbe5e 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 28_56_2_10
+#serdes protocol 27_56_1_9
16070019 18101916
-70701050 00448c00 6c02 f500
+6c700848 00448c00 6c02 f500
eeee 000287fc
5000 0028
--
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[U-Boot] [PATCH] powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes Ring VCO does not maintain lock
throughout specified temperature range.
Option 1 of the workaround states:
-
For all 1.25/2.5/5 GHz protocols, use LC VCO instead
of Ring VCO. Rather than selecting the SRDS_PRTCL_Sx
in the RCW, use the Alternate SRDS_PRTCL_Sx option.
The alternate option has the same functionality as
the original option; the only difference being LC VCO
rather than Ring VCO.
The alternate Protocols are:
Serdes1: 27 instead of 28
Serdes2: Not impacted
Serdes3: 1 instead of 2
Serdes4: 9 instead of 10
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/t4rdb/eth.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index d220475..142c6a8 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, tgec_mdio_info);
- if (srds_prtcl_s1 == 28) {
+ if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
--
1.7.6.5
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[U-Boot] [PATCH v3] fsl/pci: Add workaround for erratum A-005434
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/include/asm/config_mpc85xx.h |1 +
drivers/pci/fsl_pci_init.c|9 +++--
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 8b79c05..4bf5bc7 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -277,6 +277,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (has_erratum_a006261())
puts(Work-around for Erratum A006261 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ puts(Work-around for Erratum A-005434 enabled\n);
+#endif
return 0;
}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index df44451..94c769d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -583,6 +583,7 @@
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A005434
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 6317fb1..3a41b0e 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -49,8 +49,13 @@ static void set_inbound_window(volatile pit_t *pi,
u64 size)
{
u32 sz = (__ilog2_u64(size) - 1);
- u32 flag = PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ u32 flag = 0;
+#else
+ u32 flag = PIWAR_LOCAL;
+#endif
+
+ flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
out_be32(pi-pitar, r-phys_start 12);
out_be32(pi-piwbar, r-bus_start 12);
--
1.7.6.5
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[U-Boot] [PATCH] powerpc/85xx: Add T4160RDB board support
T4160RDB shares the same platform as T4240RDB. T4160 is a low power version of T4240, with the eight e6500 cores, two DDR3 controllers, and same peripheral bus interfaces. Signed-off-by: Chunhe Lan chunhe@freescale.com --- boards.cfg |1 + include/configs/T4240RDB.h |4 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/boards.cfg b/boards.cfg index 3ac45b2..a8ea91e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -963,6 +963,7 @@ Active powerpc mpc85xx- freescale t4qds Active powerpc mpc85xx- freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF4 - Active powerpc mpc85xx- freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF4 - Active powerpc mpc85xx- freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4 - +Active powerpc mpc85xx- freescale t4rdb T4160RDB T4240RDB:PPC_T4160 Chunhe Lan chunhe@freescale.com Active powerpc mpc85xx- freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan chunhe@freescale.com Active powerpc mpc85xx- gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach eib...@gdsys.de Active powerpc mpc85xx- gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach eib...@gdsys.de diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 1bb083a..f14e710 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -678,7 +678,11 @@ unsigned long get_board_ddr_clk(void); * interleaving. It can be cacheline, page, bank, superbank. * See doc/README.fsl-ddr for details. */ +#ifdef CONFIG_PPC_T4240 #define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif #defineCONFIG_EXTRA_ENV_SETTINGS \ hwconfig=fsl_ddr: \ -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] fsl/pci: Add workaround for erratum A-005434
For BSC9132 platform, all PEX inbound windows PEX_PEXIWARn[TRGT]
defaults to 0xF, which is mapped to CCSRBAR. However, for other
products, 0xF is mapped to the local memory. Therefore, for the
BSC9132, any default PCI Express access to the local memory (DDR)
will now access the CCSRBAR.
This patch can change the mapping of targets of inbound windows
PEX_PEXIWARn[TRGT] to the following value:
Local address space – 0x0 (from 0xF)
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/include/asm/config_mpc85xx.h |1 +
drivers/pci/fsl_pci_init.c|9 +++--
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 8b79c05..4bf5bc7 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -277,6 +277,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (has_erratum_a006261())
puts(Work-around for Erratum A006261 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ puts(Work-around for Erratum A-005434 enabled\n);
+#endif
return 0;
}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index df44451..94c769d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -583,6 +583,7 @@
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A005434
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 6317fb1..3a41b0e 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -49,8 +49,13 @@ static void set_inbound_window(volatile pit_t *pi,
u64 size)
{
u32 sz = (__ilog2_u64(size) - 1);
- u32 flag = PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ u32 flag = 0;
+#else
+ u32 flag = PIWAR_LOCAL;
+#endif
+
+ flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
out_be32(pi-pitar, r-phys_start 12);
out_be32(pi-piwbar, r-bus_start 12);
--
1.7.6.5
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[U-Boot] [PATCH] net: phy/cortina: Add four phy addresses support
Before CORTINA driver only supports two phy addresses.
This patch adds the four phy addresses support for
CORTINA PHY module.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
drivers/net/phy/cortina.c | 28 ++--
1 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 7e46679..1b9434f 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -289,25 +289,41 @@ int phy_cortina_init(void)
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
+ bool cortina_phy = false;
+
+ switch (addr) {
+#ifdef CORTINA_PHY_ADDR1
+ case CORTINA_PHY_ADDR1:
+#endif
+#ifdef CORTINA_PHY_ADDR2
+ case CORTINA_PHY_ADDR2:
+#endif
+#ifdef CORTINA_PHY_ADDR3
+ case CORTINA_PHY_ADDR3:
+#endif
+#ifdef CORTINA_PHY_ADDR4
+ case CORTINA_PHY_ADDR4:
+#endif
+ cortina_phy = true;
+ break;
+ default:
+ break;
+ }
-#if defined(CORTINA_PHY_ADDR1) || defined(CORTINA_PHY_ADDR2)
/* Cortina PHY has non-standard offset of PHY ID registers */
- if (addr == CORTINA_PHY_ADDR1 || addr == CORTINA_PHY_ADDR2)
+ if (cortina_phy)
phy_reg = bus-read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
else
-#endif
phy_reg = bus-read(bus, addr, devad, MII_PHYSID1);
if (phy_reg 0)
return -EIO;
*phy_id = (phy_reg 0x) 16;
-#if defined(CORTINA_PHY_ADDR1) || defined(CORTINA_PHY_ADDR2)
/* Cortina PHY has non-standard offset of PHY ID registers */
- if (addr == CORTINA_PHY_ADDR1 || addr == CORTINA_PHY_ADDR2)
+ if (cortina_phy)
phy_reg = bus-read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
else
-#endif
phy_reg = bus-read(bus, addr, devad, MII_PHYSID2);
if (phy_reg 0)
--
1.7.6.5
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[U-Boot] [PATCH] fsl/pci: Add workaround for erratum A-005434
For BSC9132 platform, all PEX inbound windows PEX_PEXIWARn[TRGT] defaults to 0xF, which is mapped to CCSRBAR. However, for other products, 0xF is mapped to the local memory. Therefore, for the BSC9132, any default PCI Express access to the local memory (DDR) will now access the CCSRBAR. This patch can change the mapping of targets of inbound windows PEX_PEXIWARn[TRGT] to the following value: Local address space – 0x0 (from 0xF) Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Chunhe Lan chunhe@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++ arch/powerpc/include/asm/config_mpc85xx.h |1 + drivers/pci/fsl_pci_init.c|4 3 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 8b79c05..4bf5bc7 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -277,6 +277,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a006261()) puts(Work-around for Erratum A006261 enabled\n); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + puts(Work-around for Erratum A-005434 enabled\n); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index df44451..94c769d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -583,6 +583,7 @@ #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A005434 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 6317fb1..f82ded4 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -52,6 +52,10 @@ static void set_inbound_window(volatile pit_t *pi, u32 flag = PIWAR_EN | PIWAR_LOCAL | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + flag = PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; +#endif + out_be32(pi-pitar, r-phys_start 12); out_be32(pi-piwbar, r-bus_start 12); #ifdef CONFIG_SYS_PCI_64BIT -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: phy/vitesse: Add support for VSC8664 phy module
This patch adds support for VSC8664 PHY module which can
be found on Freescale's T4240RDB boards.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
drivers/net/phy/vitesse.c | 46 +
1 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index c555979..b04d1e0 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -58,6 +58,14 @@
#define MIIM_VSC8514_18G_QSGMII0x80e0
#define MIIM_VSC8514_18G_CMDSTAT 0x8000
+/* Vitesse VSC8664 Control/Status Register */
+#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
+#define MIIM_VSC8664_ADDITIONAL_DEV0x16
+#define MIIM_VSC8664_EPHY_CON 0x17
+#define MIIM_VSC8664_LED_CON 0x1E
+
+#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
+
/* CIS8201 */
static int vitesse_config(struct phy_device *phydev)
{
@@ -244,6 +252,33 @@ static int vsc8514_config(struct phy_device *phydev)
return 0;
}
+static int vsc8664_config(struct phy_device *phydev)
+{
+ u32 val;
+
+ /* Enable MAC interface auto-negotiation */
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
+ val |= (1 13);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+ PHY_EXT_PAGE_ACCESS_EXTENDED);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
+ val |= (1 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+ /* Enable LED blink */
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
+ val = ~(1 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static struct phy_driver VSC8211_driver = {
.name = Vitesse VSC8211,
.uid= 0xfc4b0,
@@ -334,6 +369,16 @@ static struct phy_driver VSC8662_driver = {
.shutdown = genphy_shutdown,
};
+static struct phy_driver VSC8664_driver = {
+ .name = Vitesse VSC8664,
+ .uid = 0x70660,
+ .mask = 0x0,
+ .features = PHY_GBIT_FEATURES,
+ .config = vsc8664_config,
+ .startup = vitesse_startup,
+ .shutdown = genphy_shutdown,
+};
+
/* Vitesse bought Cicada, so we'll put these here */
static struct phy_driver cis8201_driver = {
.name = CIS8201,
@@ -366,6 +411,7 @@ int phy_vitesse_init(void)
phy_register(VSC8574_driver);
phy_register(VSC8514_driver);
phy_register(VSC8662_driver);
+ phy_register(VSC8664_driver);
phy_register(cis8201_driver);
phy_register(cis8204_driver);
--
1.7.6.5
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[U-Boot] [PATCH] NAND: Add Micron MT29F16G identifier
The Micron MT29F16G parts are 2048Mbytes x 8 bits 3.3V
parts with the 0x48 identifier. Add these to the list
of known devices IDs.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
drivers/mtd/nand/nand_ids.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index f3f0cb6..c11d227 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -113,6 +113,7 @@ const struct nand_flash_dev nand_flash_ids[] = {
/* 16 Gigabit */
{NAND 2GiB 1,8V 8-bit,0xA5, 0, 2048, 0, LP_OPTIONS},
+ {NAND 2GiB 3,3V 8-bit,0x48, 0, 2048, 0, LP_OPTIONS},
{NAND 2GiB 3,3V 8-bit,0xD5, 0, 2048, 0, LP_OPTIONS},
{NAND 2GiB 1,8V 16-bit, 0xB5, 0, 2048, 0, LP_OPTIONS16},
{NAND 2GiB 3,3V 16-bit, 0xC5, 0, 2048, 0, LP_OPTIONS16},
--
1.7.6.5
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[U-Boot] [PATCH] powerpc/85xx: Add T4240RDB board support
T4240RDB board Specification
Memory subsystem:
6GB DDR3
128MB NOR flash
2GB NAND flash
Ethernet:
Eight 1G SGMII ports
Four 10Gbps SFP+ ports
PCIe:
Two PCIe slots
USB:
Two USB2.0 Type A ports
SDHC:
One SD-card port
SATA:
One SATA port
UART:
Dual RJ45 ports
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
arch/powerpc/cpu/mpc85xx/t4240_ids.c |2 +
board/freescale/t4rdb/Makefile | 12 +
board/freescale/t4rdb/ddr.c | 118 ++
board/freescale/t4rdb/ddr.h | 78
board/freescale/t4rdb/eth.c | 146 +++
board/freescale/t4rdb/law.c | 28 ++
board/freescale/t4rdb/pci.c | 23 +
board/freescale/t4rdb/t4240rdb.c | 125 ++
board/freescale/t4rdb/t4_pbi.cfg | 31 ++
board/freescale/t4rdb/t4_rcw.cfg |7 +
board/freescale/t4rdb/t4rdb.h| 18 +
board/freescale/t4rdb/tlb.c | 111 +
boards.cfg |1 +
drivers/mmc/fsl_esdhc.c |2 +-
include/configs/T4240RDB.h | 752 ++
15 files changed, 1453 insertions(+), 1 deletions(-)
create mode 100644 board/freescale/t4rdb/Makefile
create mode 100644 board/freescale/t4rdb/ddr.c
create mode 100644 board/freescale/t4rdb/ddr.h
create mode 100644 board/freescale/t4rdb/eth.c
create mode 100644 board/freescale/t4rdb/law.c
create mode 100644 board/freescale/t4rdb/pci.c
create mode 100644 board/freescale/t4rdb/t4240rdb.c
create mode 100644 board/freescale/t4rdb/t4_pbi.cfg
create mode 100644 board/freescale/t4rdb/t4_rcw.cfg
create mode 100644 board/freescale/t4rdb/t4rdb.h
create mode 100644 board/freescale/t4rdb/tlb.c
create mode 100644 include/configs/T4240RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index f181315..1a3cb33 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
};
#endif
+#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_BASE(1, 307),
SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
new file mode 100644
index 000..f7f7fc0
--- /dev/null
+++ b/board/freescale/t4rdb/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += ddr.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
new file mode 100644
index 000..5a43c1b
--- /dev/null
+++ b/board/freescale/t4rdb/ddr.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include hwconfig.h
+#include asm/mmu.h
+#include fsl_ddr_sdram.h
+#include fsl_ddr_dimm_params.h
+#include asm/fsl_law.h
+#include ddr.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num 2) {
+ printf(Not supported controller number %d\n, ctrl_num);
+ return;
+ }
+ if (!pdimm-n_ranks)
+ return;
+
+ /*
+* we use identical timing for all slots. If needed, change the code
+* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+*/
+ if (popts-registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+* freqency and n_banks specified in board_specific_parameters table.
+*/
+ ddr_freq = get_ddr_freq(0) / 100;
+ while (pbsp-datarate_mhz_high) {
+ if (pbsp-n_ranks == pdimm-n_ranks
+ (pdimm-rank_density 30) = pbsp-rank_gb) {
+ if (ddr_freq = pbsp-datarate_mhz_high) {
+ popts-clk_adjust = pbsp-clk_adjust;
+ popts-wrlvl_start = pbsp-wrlvl_start;
+ popts-wrlvl_ctl_2 = pbsp-wrlvl_ctl_2;
+ popts-wrlvl_ctl_3 = pbsp-wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf(Error: board specific timing
[U-Boot] [PATCH] net/phy: Fix the phy id mask of AR8031
The both AR8031 and AR8035 belong to Atheros 803x serial PHY.
So the phy id mask of AR8031 is the same to the phy id mask
of AR8035. The right mask value is 0x4f.
This patch has been tested on the P1010 and P1023.
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/phy/atheros.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 0f2dfd6..466988e 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -50,7 +50,7 @@ static struct phy_driver AR8021_driver = {
static struct phy_driver AR8031_driver = {
.name = AR8031,
.uid = 0x4dd074,
- .mask = 0xf0,
+ .mask = 0x4f,
.features = PHY_GBIT_FEATURES,
.config = genphy_config,
.startup = genphy_startup,
--
1.7.6.5
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[U-Boot] [PATCH v3 2/2] fsl_i2c: add workaround for the erratum I2C A004447
This workaround is for the erratum I2C A004447. Device reference manual provides a scheme that allows the I2C master controller to generate nine SCL pulses, which enable an I2C slave device that held SDA low to release SDA. However, due to this erratum, this scheme no longer works. In addition, when I2C is used as a source of the PBL, the state machine is not able to recover. At the same time, delete the reduplicative definition of SVR_VER and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16 bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro instead of hard-code value 0x10, 0x11 and 0x20. The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one version of platform has this I2C errata. So enable this errata by IS_SVR_REV(svr, maj, min) function. Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Chunhe Lan chunhe@freescale.com Cc: Scott Wood scottw...@freescale.com Cc: Heiko Schocher h...@denx.de --- Changes for v2: - Caller directly uses CONFIG_SYS_FSL_A004447_SVR_REV to judge whether SVR_REV is less than or equal CONFIG_SYS_FSL_A004447_SVR_REV - SVR_REV is the low 8 bits rather than the low 16 bits of svr Changes for v3: - Rework codes for the newest mainline arch/powerpc/cpu/mpc85xx/cmd_errata.c |5 + arch/powerpc/include/asm/config_mpc85xx.h | 16 arch/powerpc/include/asm/fsl_i2c.h|1 + arch/powerpc/include/asm/processor.h |5 + drivers/i2c/fsl_i2c.c | 14 +++--- 5 files changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index cbb443f..05436f9 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -248,6 +248,11 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 puts(Work-around for Erratum A-005812 enabled\n); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 + if ((SVR_SOC_VER(svr) == SVR_8548 IS_SVR_REV(svr, 3, 1)) || + (SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV)) + puts(Work-around for Erratum I2C-A004447 enabled\n); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ce1bf05..3d1de4a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -67,6 +67,8 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS1 @@ -132,6 +134,8 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -249,6 +253,8 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x1 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff60 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -334,6 +340,8 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -369,6 +377,8 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_A005812 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -415,6 +425,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A004580 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 #define CONFIG_SYS_FSL_ERRATUM_A005812 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -446,6 +458,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 @@ -510,6 +524,8 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define
[U-Boot] [PATCH v3 1/2] fsl_i2c: generate nine pulses on SCL if the I2C bus is hung
When the code detected that the bus is hung (e.g. SDA stuck low),
send 9 pulses on SCL to try to fixup the bus.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Scott Wood scottw...@freescale.com
Cc: Heiko Schocher h...@denx.de
---
Changes for v2:
- No change
Changes for v3:
- Rework codes for the newest mainline
drivers/i2c/fsl_i2c.c | 59 +++-
1 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 38455e1..44b08f7 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -206,9 +206,50 @@ static unsigned int get_i2c_clock(int bus)
return gd-arch.i2c1_clk; /* I2C1 clock */
}
+static int fsl_i2c_fixup(const struct fsl_i2c *dev)
+{
+ const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ unsigned long long timeval = 0;
+ int ret = -1;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, dev-cr);
+
+ timeval = get_ticks();
+ while (!(readb(dev-sr) I2C_SR_MBB)) {
+ if ((get_ticks() - timeval) timeout)
+ goto err;
+ }
+
+ if (readb(dev-sr) I2C_SR_MAL) {
+ /* SDA is stuck low */
+ writeb(0, dev-cr);
+ udelay(100);
+ writeb(I2C_CR_MSTA, dev-cr);
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, dev-cr);
+ }
+
+ readb(dev-dr);
+
+ timeval = get_ticks();
+ while (!(readb(dev-sr) I2C_SR_MIF)) {
+ if ((get_ticks() - timeval) timeout)
+ goto err;
+ }
+ ret = 0;
+
+err:
+ writeb(I2C_CR_MEN, dev-cr);
+ writeb(0, dev-sr);
+ udelay(100);
+
+ return ret;
+}
+
static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
const struct fsl_i2c *dev;
+ const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ unsigned long long timeval;
#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* Call board specific i2c bus reset routine before accessing the
@@ -226,6 +267,18 @@ static void fsl_i2c_init(struct i2c_adapter *adap, int
speed, int slaveadd)
writeb(0x0, dev-sr); /* clear status register */
writeb(I2C_CR_MEN, dev-cr); /* start I2C controller */
+ timeval = get_ticks();
+ while (readb(dev-sr) I2C_SR_MBB) {
+ if ((get_ticks() - timeval) timeout)
+ continue;
+
+ if (fsl_i2c_fixup(dev))
+ debug(i2c_init: BUS#%d failed to init\n,
+ adap-hwadapnr);
+
+ break;
+ }
+
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
/* Call board specific i2c bus reset routine AFTER the bus has been
* initialized. Use either this callpoint or i2c_init_board;
@@ -394,8 +447,10 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
int alen,
int i = -1; /* signal error */
u8 *a = (u8*)addr;
- if (i2c_wait4bus(adap) = 0
- i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
+ if (i2c_wait4bus(adap) 0)
+ return -1;
+
+ if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
__i2c_write(adap, a[4 - alen], alen) == alen) {
i = __i2c_write(adap, data, length);
}
--
1.7.6.5
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[U-Boot] [PATCH v2 2/2] fsl_i2c: add workaround for the erratum I2C A004447
This workaround is for the erratum I2C A004447. Device reference manual provides a scheme that allows the I2C master controller to generate nine SCL pulses, which enable an I2C slave device that held SDA low to release SDA. However, due to this erratum, this scheme no longer works. In addition, when I2C is used as a source of the PBL, the state machine is not able to recover. At the same time, delete the reduplicative definition of SVR_VER and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16 bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro instead of hard-code value 0x10, 0x11 and 0x20. The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one version of platform has this I2C errata. So enable this errata by IS_SVR_REV(svr, maj, min) function. Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Chunhe Lan chunhe@freescale.com Cc: Scott Wood scottw...@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c |5 + arch/powerpc/include/asm/config_mpc85xx.h | 16 arch/powerpc/include/asm/fsl_i2c.h|1 + arch/powerpc/include/asm/processor.h |5 + drivers/i2c/fsl_i2c.c | 14 +++--- 5 files changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a7ed877..18ecb04 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -261,6 +261,11 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts(Work-around for Erratum A006593 enabled\n); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 + if ((SVR_SOC_VER(svr) == SVR_8548 IS_SVR_REV(svr, 3, 1)) || + (SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV)) + puts(Work-around for Erratum I2C-A004447 enabled\n); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1d46b14..e965a79 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -81,6 +81,8 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS1 @@ -146,6 +148,8 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -263,6 +267,8 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x1 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff60 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -347,6 +353,8 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -380,6 +388,8 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -424,6 +434,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_A004580 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -454,6 +466,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 @@ -512,6 +526,8 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define CONFIG_E6500 diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h index 4f71341..d6537fd 100644
[U-Boot] [PATCH v2 1/2] fsl_i2c: generate nine pulses on SCL if the I2C bus is hung
When the code detected that the bus is hung (e.g. SDA stuck low),
send 9 pulses on SCL to try to fixup the bus.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
drivers/i2c/fsl_i2c.c | 58 +++-
1 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 5d7e010..ef0004d 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -222,9 +222,50 @@ static unsigned int get_i2c_clock(int bus)
return gd-arch.i2c1_clk; /* I2C1 clock */
}
+static int i2c_fixup(const struct fsl_i2c *dev)
+{
+ const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ unsigned long long timeval = 0;
+ int ret = -1;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, dev-cr);
+
+ timeval = get_ticks();
+ while (!(readb(dev-sr) I2C_SR_MBB)) {
+ if ((get_ticks() - timeval) timeout)
+ goto err;
+ }
+
+ if (readb(dev-sr) I2C_SR_MAL) {
+ /* SDA is stuck low */
+ writeb(0, dev-cr);
+ udelay(100);
+ writeb(I2C_CR_MSTA, dev-cr);
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, dev-cr);
+ }
+
+ readb(dev-dr);
+
+ timeval = get_ticks();
+ while (!(readb(dev-sr) I2C_SR_MIF)) {
+ if ((get_ticks() - timeval) timeout)
+ goto err;
+ }
+ ret = 0;
+
+err:
+ writeb(I2C_CR_MEN, dev-cr);
+ writeb(0, dev-sr);
+ udelay(100);
+
+ return ret;
+}
+
void
i2c_init(int speed, int slaveadd)
{
+ const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ unsigned long long timeval;
const struct fsl_i2c *dev;
unsigned int temp;
int bus_num, i;
@@ -252,6 +293,17 @@ i2c_init(int speed, int slaveadd)
writeb(slaveadd 1, dev-adr);/* write slave address */
writeb(0x0, dev-sr); /* clear status register */
writeb(I2C_CR_MEN, dev-cr); /* start I2C controller */
+
+ timeval = get_ticks();
+ while (readb(dev-sr) I2C_SR_MBB) {
+ if ((get_ticks() - timeval) timeout)
+ continue;
+
+ if (i2c_fixup(dev))
+ debug(i2c_init: BUS#%d failed to init\n, i);
+
+ break;
+ }
}
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
@@ -412,8 +464,10 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int
length)
int i = -1; /* signal error */
u8 *a = (u8*)addr;
- if (i2c_wait4bus() = 0
-i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
+ if (i2c_wait4bus() 0)
+ return -1;
+
+ if (i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
__i2c_write(a[4 - alen], alen) == alen) {
i = __i2c_write(data, length);
}
--
1.7.6.5
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[U-Boot] [PATCH 2/2] fsl_i2c: add workaround for the erratum I2C A004447
This workaround is for the erratum I2C A004447. Device reference manual provides a scheme that allows the I2C master controller to generate nine SCL pulses, which enable an I2C slave device that held SDA low to release SDA. However, due to this erratum, this scheme no longer works. In addition, when I2C is used as a source of the PBL, the state machine is not able to recover. At the same time, use the CONFIG_SYS_FSL_A004447_VERSION macro instead of hard-code value 0x11 and 0x20. The CONFIG_SYS_FSL_A004447_VERSION = 0x00 represents that one version of platform has this I2C errata. So enable this errata by IS_SVR_REV(svr, maj, min) function. Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Chunhe Lan chunhe@freescale.com Cc: Scott Wood scottw...@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c |6 ++ arch/powerpc/include/asm/config_mpc85xx.h | 16 arch/powerpc/include/asm/fsl_i2c.h|1 + arch/powerpc/include/asm/processor.h |2 ++ drivers/i2c/fsl_i2c.c | 15 --- 5 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a7ed877..b5c451a 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -261,6 +261,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts(Work-around for Erratum A006593 enabled\n); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 + if ((SVR_SOC_VER(svr) == SVR_8548 IS_SVR_REV(svr, 3, 1)) || + (SVR_SOC_VER(svr) == SVR_P1010 IS_SVR_REV(svr, 1, 0)) || +FIT_SVR_REV(svr, CONFIG_SYS_FSL_A004447_VERSION)) + puts(Work-around for Erratum I2C-A004447 enabled\n); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1d46b14..f1d513e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -81,6 +81,8 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x00 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS1 @@ -146,6 +148,8 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x00 /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -263,6 +267,8 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x1 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff60 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x11 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -347,6 +353,8 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x11 #elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -380,6 +388,8 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x20 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -424,6 +434,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_A004580 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x20 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -454,6 +466,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x20 #elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 @@ -512,6 +526,8 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_VERSION 0x11 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define CONFIG_E6500 diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h index 4f71341..d6537fd 100644 --- a/arch/powerpc/include/asm/fsl_i2c.h +++ b/arch/powerpc/include
[U-Boot] [PATCH 1/2] fsl_i2c: generate nine pulses on SCL if the I2C bus is hung
When the code detected that the bus is hung (e.g. SDA stuck low),
send 9 pulses on SCL to try to fixup the bus.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
drivers/i2c/fsl_i2c.c | 58 +++-
1 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 5d7e010..ef0004d 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -222,9 +222,50 @@ static unsigned int get_i2c_clock(int bus)
return gd-arch.i2c1_clk; /* I2C1 clock */
}
+static int i2c_fixup(const struct fsl_i2c *dev)
+{
+ const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ unsigned long long timeval = 0;
+ int ret = -1;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, dev-cr);
+
+ timeval = get_ticks();
+ while (!(readb(dev-sr) I2C_SR_MBB)) {
+ if ((get_ticks() - timeval) timeout)
+ goto err;
+ }
+
+ if (readb(dev-sr) I2C_SR_MAL) {
+ /* SDA is stuck low */
+ writeb(0, dev-cr);
+ udelay(100);
+ writeb(I2C_CR_MSTA, dev-cr);
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, dev-cr);
+ }
+
+ readb(dev-dr);
+
+ timeval = get_ticks();
+ while (!(readb(dev-sr) I2C_SR_MIF)) {
+ if ((get_ticks() - timeval) timeout)
+ goto err;
+ }
+ ret = 0;
+
+err:
+ writeb(I2C_CR_MEN, dev-cr);
+ writeb(0, dev-sr);
+ udelay(100);
+
+ return ret;
+}
+
void
i2c_init(int speed, int slaveadd)
{
+ const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ unsigned long long timeval;
const struct fsl_i2c *dev;
unsigned int temp;
int bus_num, i;
@@ -252,6 +293,17 @@ i2c_init(int speed, int slaveadd)
writeb(slaveadd 1, dev-adr);/* write slave address */
writeb(0x0, dev-sr); /* clear status register */
writeb(I2C_CR_MEN, dev-cr); /* start I2C controller */
+
+ timeval = get_ticks();
+ while (readb(dev-sr) I2C_SR_MBB) {
+ if ((get_ticks() - timeval) timeout)
+ continue;
+
+ if (i2c_fixup(dev))
+ debug(i2c_init: BUS#%d failed to init\n, i);
+
+ break;
+ }
}
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
@@ -412,8 +464,10 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int
length)
int i = -1; /* signal error */
u8 *a = (u8*)addr;
- if (i2c_wait4bus() = 0
-i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
+ if (i2c_wait4bus() 0)
+ return -1;
+
+ if (i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
__i2c_write(a[4 - alen], alen) == alen) {
i = __i2c_write(data, length);
}
--
1.7.6.5
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[U-Boot] [PATCH v4] powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
---
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB:
Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |1 +
board/freescale/p1023rdb/Makefile | 33 +++
board/freescale/p1023rdb/ddr.c | 105 +
board/freescale/p1023rdb/law.c | 34 +++
board/freescale/p1023rdb/p1023rdb.c | 161 ++
board/freescale/p1023rdb/tlb.c | 115 ++
boards.cfg |1 +
include/configs/P1023RDB.h | 401 +++
8 files changed, 851 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/p1023rdb/Makefile
create mode 100644 board/freescale/p1023rdb/ddr.c
create mode 100644 board/freescale/p1023rdb/law.c
create mode 100644 board/freescale/p1023rdb/p1023rdb.c
create mode 100644 board/freescale/p1023rdb/tlb.c
create mode 100644 include/configs/P1023RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 2318064..4669883 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_P1014) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
+COBJS-$(CONFIG_P1023) += ddr-gen3.o
COBJS-$(CONFIG_P1024) += ddr-gen3.o
COBJS-$(CONFIG_P1025) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
diff --git a/board/freescale/p1023rdb/Makefile
b/board/freescale/p1023rdb/Makefile
new file mode 100644
index 000..45c4f8b
--- /dev/null
+++ b/board/freescale/p1023rdb/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y+= $(BOARD).o
+COBJS-y+= ddr.o
+COBJS-y+= law.o
+COBJS-y+= tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644
index 000..7ed275a
--- /dev/null
+++ b/board/freescale/p1023rdb/ddr.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mmu.h
+#include asm/immap_85xx.h
+#include asm/processor.h
+#include asm/fsl_ddr_sdram.h
+#include asm/fsl_ddr_dimm_params.h
+#include asm/io.h
+#include asm/fsl_law.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1875,
+ .caslat_X = 0x1e 4, /* 5,6,7,8 */
+ .tAA_ps = 13125,
+ .tWR_ps = 18000,
+ .tRCD_ps = 13125,
+ .tRRD_ps = 7500,
+ .tRP_ps = 13125,
+ .tRAS_ps = 37500,
+ .tRC_ps = 50625,
+ .tRFC_ps = 16,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500
Re: [U-Boot] [PATCH v2] powerpc/85xx: Add P1023RDB board support
On 06/12/2013 02:00 AM, Scott Wood wrote: On 06/09/2013 05:24:05 AM, Chunhe Lan wrote: +/* W**G* - Flash, localbus */ +/* This will be changed to *I*G* after relocation to RAM. */ +SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), Do not set MAS3_SX on I/O regions. Here is need to use MAS3_SX, or u-boot does NOT work. +/* + * Memory map + * + * 0x_0x1fff_DDR500M Cacheable 500M? Are you sure? Yes, system has the 500MB size of ddr. Thanks, -Chunhe +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE230400/* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX2/* which serial port to use */ +#endif Get rid of this. +#define CONFIG_BOOTDELAY 10/* -1 disables auto-boot */ The out-of-the-box environment is not going to work unmodified (I don't even see a CONFIG_BOOTCOMMAND), so let's just default this to -1 now that it no longer has the affect of disabling the code at compile-time. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
---
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB: Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |1 +
board/freescale/p1023rdb/Makefile | 33 +++
board/freescale/p1023rdb/ddr.c | 105 +
board/freescale/p1023rdb/law.c | 34 +++
board/freescale/p1023rdb/p1023rdb.c | 161 ++
board/freescale/p1023rdb/tlb.c | 115 ++
boards.cfg |1 +
include/configs/P1023RDB.h | 401 +++
8 files changed, 851 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/p1023rdb/Makefile
create mode 100644 board/freescale/p1023rdb/ddr.c
create mode 100644 board/freescale/p1023rdb/law.c
create mode 100644 board/freescale/p1023rdb/p1023rdb.c
create mode 100644 board/freescale/p1023rdb/tlb.c
create mode 100644 include/configs/P1023RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 2318064..4669883 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_P1014) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
+COBJS-$(CONFIG_P1023) += ddr-gen3.o
COBJS-$(CONFIG_P1024) += ddr-gen3.o
COBJS-$(CONFIG_P1025) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
diff --git a/board/freescale/p1023rdb/Makefile
b/board/freescale/p1023rdb/Makefile
new file mode 100644
index 000..45c4f8b
--- /dev/null
+++ b/board/freescale/p1023rdb/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y+= $(BOARD).o
+COBJS-y+= ddr.o
+COBJS-y+= law.o
+COBJS-y+= tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644
index 000..7ed275a
--- /dev/null
+++ b/board/freescale/p1023rdb/ddr.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mmu.h
+#include asm/immap_85xx.h
+#include asm/processor.h
+#include asm/fsl_ddr_sdram.h
+#include asm/fsl_ddr_dimm_params.h
+#include asm/io.h
+#include asm/fsl_law.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1875,
+ .caslat_X = 0x1e 4, /* 5,6,7,8 */
+ .tAA_ps = 13125,
+ .tWR_ps = 18000,
+ .tRCD_ps = 13125,
+ .tRRD_ps = 7500,
+ .tRP_ps = 13125,
+ .tRAS_ps = 37500,
+ .tRC_ps = 50625,
+ .tRFC_ps = 16,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500
[U-Boot] [PATCH v2] powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
---
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB: Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |1 +
board/freescale/p1023rdb/Makefile | 33 +++
board/freescale/p1023rdb/ddr.c | 105 +
board/freescale/p1023rdb/law.c | 34 +++
board/freescale/p1023rdb/p1023rdb.c | 161 ++
board/freescale/p1023rdb/tlb.c | 115 ++
boards.cfg |1 +
include/configs/P1023RDB.h | 406 +++
8 files changed, 856 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/p1023rdb/Makefile
create mode 100644 board/freescale/p1023rdb/ddr.c
create mode 100644 board/freescale/p1023rdb/law.c
create mode 100644 board/freescale/p1023rdb/p1023rdb.c
create mode 100644 board/freescale/p1023rdb/tlb.c
create mode 100644 include/configs/P1023RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 2318064..4669883 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_P1014) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
+COBJS-$(CONFIG_P1023) += ddr-gen3.o
COBJS-$(CONFIG_P1024) += ddr-gen3.o
COBJS-$(CONFIG_P1025) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
diff --git a/board/freescale/p1023rdb/Makefile
b/board/freescale/p1023rdb/Makefile
new file mode 100644
index 000..45c4f8b
--- /dev/null
+++ b/board/freescale/p1023rdb/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y+= $(BOARD).o
+COBJS-y+= ddr.o
+COBJS-y+= law.o
+COBJS-y+= tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644
index 000..7ed275a
--- /dev/null
+++ b/board/freescale/p1023rdb/ddr.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mmu.h
+#include asm/immap_85xx.h
+#include asm/processor.h
+#include asm/fsl_ddr_sdram.h
+#include asm/fsl_ddr_dimm_params.h
+#include asm/io.h
+#include asm/fsl_law.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1875,
+ .caslat_X = 0x1e 4, /* 5,6,7,8 */
+ .tAA_ps = 13125,
+ .tWR_ps = 18000,
+ .tRCD_ps = 13125,
+ .tRRD_ps = 7500,
+ .tRP_ps = 13125,
+ .tRAS_ps = 37500,
+ .tRC_ps = 50625,
+ .tRFC_ps = 16,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500
[U-Boot] [PATCH] powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
---
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB: Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/p1023rdb/Makefile | 32 +++
board/freescale/p1023rdb/law.c | 34 +++
board/freescale/p1023rdb/p1023rdb.c | 194
board/freescale/p1023rdb/tlb.c | 116 ++
boards.cfg |1 +
include/configs/P1023RDB.h | 433 +++
6 files changed, 810 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/p1023rdb/Makefile
create mode 100644 board/freescale/p1023rdb/law.c
create mode 100644 board/freescale/p1023rdb/p1023rdb.c
create mode 100644 board/freescale/p1023rdb/tlb.c
create mode 100644 include/configs/P1023RDB.h
diff --git a/board/freescale/p1023rdb/Makefile
b/board/freescale/p1023rdb/Makefile
new file mode 100644
index 000..c8e0866
--- /dev/null
+++ b/board/freescale/p1023rdb/Makefile
@@ -0,0 +1,32 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y+= $(BOARD).o
+COBJS-y+= law.o
+COBJS-y+= tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
new file mode 100644
index 000..b041d1f
--- /dev/null
+++ b/board/freescale/p1023rdb/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/fsl_law.h
+#include asm/mmu.h
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
+ LAW_TRGT_IF_DPAA_SWP_SRAM),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c
b/board/freescale/p1023rdb/p1023rdb.c
new file mode 100644
index 000..16659e9
--- /dev/null
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors: Roy Zang tie-fei.z...@freescale.com
+ * Chunhe Lan chunhe@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include command.h
+#include pci.h
+#include asm/io.h
+#include asm/cache.h
+#include asm/processor.h
+#include asm/mmu.h
+#include
Re: [U-Boot] [PATCH] powerpc/85xx: Add P1023RDB board support
On 04/16/2013 09:57 PM, Sinan Akman wrote: Chunhe Lan wrote: P1023RDB Specification: --- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Chunhe, what is the orderable part number of this board, I don't see anything on the FSL web page with the description above. Now, Freescale is developing it, and does not normally release it. Thanks, -Chunhe Regards Sinan Akman ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/t4240: work around errata A-005977
The PCI Express internal transmit and receive buffers are ECC protected.
When these buffers are being read before they are written, a false
multi-bit ECC error is likely to occur. So disable the PCI Express ECC
error reporting.
The Workaround is for the T4 silicon rev 1.0.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |4
arch/powerpc/cpu/mpc85xx/cpu_init.c |8
arch/powerpc/include/asm/config_mpc85xx.h |2 ++
3 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 0711064..7489174 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -270,6 +270,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A005553
puts(Work-around for Erratum A005553 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005977
+ if (IS_SVR_REV(svr, 1, 0))
+ puts(Work-around for Erratum A005977 enabled\n);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6f7a10f..0b6668b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -675,6 +675,14 @@ skip_l2:
setbits_be32((void *)DCFG_ECC, 1 (31 - 15));
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005977
+ if (IS_SVR_REV(svr, 1, 0)) {
+ void *p;
+ p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ setbits_be32(p, 0xf (31 - 15));
+ }
+#endif
+
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 650df14..bc619e9 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -540,6 +540,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004809
#define CONFIG_SYS_FSL_ERRATUM_A004857
#define CONFIG_SYS_FSL_ERRATUM_A005553
+#define CONFIG_SYS_FSL_ERRATUM_A005977
#define CONFIG_SYS_FSL_ERRATUM_A004390
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -583,6 +584,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004809
#define CONFIG_SYS_FSL_ERRATUM_A004857
#define CONFIG_SYS_FSL_ERRATUM_A005553
+#define CONFIG_SYS_FSL_ERRATUM_A005977
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#define CONFIG_SYS_FSL_PCI_VER_3_X
--
1.7.6.5
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Re: [U-Boot] [PATCH] powerpc/85xx: fix NAND boot linker scripts for -fpic
Scott Wood wrote: GOT is now handled the way the main u-boot.lds does it. Without this, the boot hangs when built with newer GCC (since 4.6). Older toolchains hid the issue by converting -fpic to -fPIC. Signed-off-by: Scott Wood scottw...@freescale.com Tested-by: Chunhe Lan chunhe@freescale.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] PowerPC: Change -fpic flag to -fPIC flag in the config.mk
Wolfgang Denk wrote: Dear Chunhe Lan, In message 1334719161-3500-1-git-send-email-chunhe@freescale.com you wrote: The -fPIC/-fpic flag belongs with -mrelocatable. The -fpic flag can limit the size of the GOT and produce smaller binaries, so it causes some GOT entries to be lost in the gcc 4.6 version. But -fPIC flag allows the maximum possible size of the GOT entries. However, currently -mrelocatable promotes -fpic flag to -fPIC flag. This reverts that portion of the commit 33ee4c92339ee386662c0ee2d221098c5cc8b07e. As you state yourself, your modification has the negative impact of increasing the image size. What would be the benefits of it? Are you trying to fix any specific problem? Which one? I am not aware of any related isses for any of the mainline PowerPC systems... Yes, I have fixed the booting issue of nand u-boot of P1010/P1022/P1023/P2020 with this patch. When use gcc 4.5 version, produce the size of u-boot-nand.bin to be same with -fpic or -fPIC. The u-boot-nand.bin is OK. But when use gcc 4.6 version, produce the size of u-boot-nand.bin to be different with -fpic or -fPIC. The some GOT entries of u-boot-nand.bin are lost with -fpic(because limit the size), so u-boot-nand.bin hangs when booting. But use -fPIC, the u-boot-nand.bin is OK. And this patch reverts that portion of the commit 33ee4c92339ee386662c0ee2d221098c5cc8b07e. Thanks, Chunhe Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] PowerPC: Change -fpic flag to -fPIC flag in the config.mk
The -fPIC/-fpic flag belongs with -mrelocatable. The -fpic flag can limit the size of the GOT and produce smaller binaries, so it causes some GOT entries to be lost in the gcc 4.6 version. But -fPIC flag allows the maximum possible size of the GOT entries. However, currently -mrelocatable promotes -fpic flag to -fPIC flag. This reverts that portion of the commit 33ee4c92339ee386662c0ee2d221098c5cc8b07e. Signed-off-by: Chunhe Lan chunhe@freescale.com --- arch/powerpc/config.mk |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index a307154..7c14ff6 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -25,7 +25,7 @@ CROSS_COMPILE ?= ppc_8xx- CONFIG_STANDALONE_LOAD_ADDR ?= 0x4 LDFLAGS_FINAL += --gc-sections -PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -fPIC -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n -- 1.5.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 v5] fdt: Add a do_fixup_by_path_string() function
On Tue, 30 Aug 2011 13:20:48 +0800, Wolfgang Denk w...@denx.de wrote: Dear Chunhe Lan, In message 1314675674-9825-1-git-send-email-chunhe@freescale.com you wrote: The do_fixup_by_path_string() will set the specified node's property to the value contained in status. It would just be an inline wrapper for do_fixup_by_path() that calls strlen on the argument. Signed-off-by: Chunhe Lan chunhe@freescale.com --- include/fdt_support.h |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) This is v5, but there is no log of changes. This change log is MANDATORY!! OK. Thanks. -Jack Lan Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 v5] powerpc/p1023rds: Disable nor flash node and enable nand flash node
On Tue, 30 Aug 2011 13:24:34 +0800, Wolfgang Denk w...@denx.de wrote: Dear Chunhe Lan, In message 1314675698-9847-1-git-send-email-chunhe@freescale.com you wrote: ... status = okay; ... When booting from nor flash, the status of nor node is null that means it Description does not match code. I rewrite it. is enabled and the status of nand node is disabled in the default dts file, ... But, when booting from nand flash, need to do some operations: o the status of nor node should be disabled. o the status of nand node should be enabled. Make this: o Disable the NOR node by setting status = disabled; o Enable the NAND node by setting status = okay; I rewrite it. Signed-off-by: Chunhe Lan chunhe@freescale.com --- board/freescale/p1023rds/p1023rds.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) This is patch v5, but there is no change log. This is MANDATORY! OK. Thanks. -Jack Lan Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2 v6] fdt: Add a do_fixup_by_path_string() function
The do_fixup_by_path_string() will set the specified node's property to the
value contained in status. It would just be an inline wrapper for
do_fixup_by_path() that calls strlen on the argument.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
Changes for v2:
- renamed from fdt_set_node_status() to do_fixup_by_path_string()
- removed fdt_get_alias()
- removed copyright line
Changes for v3:
- moved function into a header file as an inline function
Changes for v4:
- none
Changes for v5:
- none
Changes for v6:
- added change log
include/fdt_support.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 863024f..1de4a1d 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -36,6 +36,13 @@ void do_fixup_by_path(void *fdt, const char *path, const
char *prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create);
+
+static inline void do_fixup_by_path_string(void *fdt, const char *path,
+ const char *prop, const char *status)
+{
+ do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
--
1.5.6.5
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[U-Boot] [PATCH 2/2 v6] powerpc/p1023rds: Disable nor flash node and enable nand flash node
In the p1023rds, when system boots from nor flash, kernel only accesses nor
flash and can not access nand flash with BR0/OR0; when system boots from
nand flash, kernel only accesses nand flash and can not access nor flash
with BR0/OR0.
Default device tree nor and nand node should have the following structure:
Example:
nor_flash: nor@0,0 {
#address-cells = 1;
#size-cells = 1;
compatible = cfi-flash;
reg = 0x0 0x0 0x0200;
bank-width = 2;
device-width = 1;
status = okay;
partition@0 {
label = ramdisk;
reg = 0x 0x01c0;
};
}
nand_flash: nand@1,0 {
#address-cells = 1;
#size-cells = 1;
compatible = fsl,p1023-fcm-nand,
fsl,elbc-fcm-nand;
reg = 0x2 0x0 0x0004;
status = disabled;
u-boot-nand@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = 0x0 0x0010;
read-only;
};
}
When booting from nor flash, the status of nor node is enabled and the
status of nand node is disabled in the default dts file, so do not do
anything.
But, when booting from nand flash, need to do some operations:
o Disable the NOR node by setting status = disabled;
o Enable the NAND node by setting status = okay;
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
Changes for v2:
- used do_fixup_by_path_string() instead of fdt_set_node_status()
Changes for v3:
- none
Changes for v4:
- modified comments from Kumar Gala
- no need for a separate function, and put the two lines in
ft_board_setup()
Changes for v5:
- modified comments from Wolfgang Denk and Tabi Timur
Changes for v6:
- modified comments from Wolfgang Denk
- added change log
board/freescale/p1023rds/p1023rds.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1023rds/p1023rds.c
b/board/freescale/p1023rds/p1023rds.c
index 8cfd199..c99ccee 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -158,5 +158,10 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_NAND_U_BOOT
+ do_fixup_by_path_string(fdt, nor_flash, status, disabled);
+ do_fixup_by_path_string(fdt, nand_flash, status, okay);
+#endif
}
#endif
--
1.5.6.5
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[U-Boot] [PATCH 1/2 v4] fdt: Add a do_fixup_by_path_string() function
The do_fixup_by_path_string() will set the specified node's property to the
value contained in status. It would just be an inline wrapper for
do_fixup_by_path() that calls strlen on the argument.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
include/fdt_support.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 863024f..1de4a1d 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -36,6 +36,13 @@ void do_fixup_by_path(void *fdt, const char *path, const
char *prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create);
+
+static inline void do_fixup_by_path_string(void *fdt, const char *path,
+ const char *prop, const char *status)
+{
+ do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
--
1.5.6.5
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[U-Boot] [PATCH 2/2 v4] powerpc/p1023rds: Disable nor flash node and enable nand flash node
In the p1023rds, accessing exclusively nor flash or nand flash device by
BR0/OR0.
Default device tree nor and nand node should have the following structure:
Example:
nor_flash: nor@0,0 {
#address-cells = 1;
#size-cells = 1;
compatible = cfi-flash;
reg = 0x0 0x0 0x0200;
bank-width = 2;
device-width = 1;
partition@0 {
label = ramdisk;
reg = 0x 0x01c0;
};
}
nand_flash: nand@1,0 {
#address-cells = 1;
#size-cells = 1;
compatible = fsl,p1023-fcm-nand,
fsl,elbc-fcm-nand;
reg = 0x2 0x0 0x0004;
status = disabled;
u-boot-nand@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = 0x0 0x0010;
read-only;
};
}
When booting from nor flash, the status of nor node is null that means it
is enabled and the status of nand node is disabled in the default dts file,
so do not do anything.
But, when booting from nand flash, need to do some operations:
o the status of nor node should be disabled.
o the status of nand node should be enabled.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/p1023rds/p1023rds.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1023rds/p1023rds.c
b/board/freescale/p1023rds/p1023rds.c
index 8cfd199..c99ccee 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -158,5 +158,10 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_NAND_U_BOOT
+ do_fixup_by_path_string(fdt, nor_flash, status, disabled);
+ do_fixup_by_path_string(fdt, nand_flash, status, okay);
+#endif
}
#endif
--
1.5.6.5
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Re: [U-Boot] [PATCH 2/2 v4] powerpc/p1023rds: Disable nor flash node and enable nand flash node
On Mon, 29 Aug 2011 15:42:09 +0800, Wolfgang Denk w...@denx.de wrote:
Dear Chunhe Lan,
In message 1314602152-9114-1-git-send-email-chunhe@freescale.com
you wrote:
In the p1023rds, accessing exclusively nor flash or nand flash device by
BR0/OR0.
...
When booting from nor flash, the status of nor node is null that means
it
is enabled and the status of nand node is disabled in the default dts
file,
so do not do anything.
It would be more intuitive to the reader, when the enabled node would
use an explicit
status = enabled;
+#ifdef CONFIG_NAND_U_BOOT
+do_fixup_by_path_string(fdt, nor_flash, status, disabled);
+do_fixup_by_path_string(fdt, nand_flash, status, okay);
+#endif
What does okay mean? This is not documented anywhere. Is this
supposed to mean enabled? Then please write enabled - for certain
configurations it is definitely OK to disable the device.
In the kernel, whether the status of node is enabled or not, it is
determined by
of_device_is_available( ).
The following content of of_device_is_available( ):
245 /**
246 * of_device_is_available - check if a device is available for use
247 *
248 * @device: Node to check for availability
249 *
250 * Returns 1 if the status property is absent or set to okay or
ok,
251 * 0 otherwise
252 */
253 int of_device_is_available(const struct device_node *device)
254 {
255 const char *status;
256 int statlen;
257
258 status = of_get_property(device, status, statlen);
259 if (status == NULL)
260 return 1;
261
262 if (statlen 0) {
263 if (!strcmp(status, okay) || !strcmp(status, ok))
264 return 1;
265 }
266
267 return 0;
268 }
return 1 is enabled.
return 0 is disabled.
So, we do NOT use enabled to set status.
Thanks.
-Jack Lan
Best regards,
Wolfgang Denk
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Re: [U-Boot] [PATCH 2/2 v4] powerpc/p1023rds: Disable nor flash node and enable nand flash node
On Tue, 30 Aug 2011 04:23:11 +0800, Tabi Timur-B04825 b04...@freescale.com wrote: On Mon, Aug 29, 2011 at 2:15 AM, Chunhe Lan chunhe@freescale.com wrote: In the p1023rds, accessing exclusively nor flash or nand flash device by BR0/OR0. This is not an English sentence. I do not understand what you're saying. OK. I will rewrite it. Thanks. -Jack Lan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2 v5] fdt: Add a do_fixup_by_path_string() function
The do_fixup_by_path_string() will set the specified node's property to the
value contained in status. It would just be an inline wrapper for
do_fixup_by_path() that calls strlen on the argument.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
include/fdt_support.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 863024f..1de4a1d 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -36,6 +36,13 @@ void do_fixup_by_path(void *fdt, const char *path, const
char *prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create);
+
+static inline void do_fixup_by_path_string(void *fdt, const char *path,
+ const char *prop, const char *status)
+{
+ do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
--
1.5.6.5
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[U-Boot] [PATCH 2/2 v5] powerpc/p1023rds: Disable nor flash node and enable nand flash node
In the p1023rds, when system boots from nor flash, kernel only accesses nor
flash and can not access nand flash with BR0/OR0; when system boots from
nand flash, kernel only accesses nand flash and can not access nor flash
with BR0/OR0.
Default device tree nor and nand node should have the following structure:
Example:
nor_flash: nor@0,0 {
#address-cells = 1;
#size-cells = 1;
compatible = cfi-flash;
reg = 0x0 0x0 0x0200;
bank-width = 2;
device-width = 1;
status = okay;
partition@0 {
label = ramdisk;
reg = 0x 0x01c0;
};
}
nand_flash: nand@1,0 {
#address-cells = 1;
#size-cells = 1;
compatible = fsl,p1023-fcm-nand,
fsl,elbc-fcm-nand;
reg = 0x2 0x0 0x0004;
status = disabled;
u-boot-nand@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = 0x0 0x0010;
read-only;
};
}
When booting from nor flash, the status of nor node is null that means it
is enabled and the status of nand node is disabled in the default dts file,
so do not do anything.
But, when booting from nand flash, need to do some operations:
o the status of nor node should be disabled.
o the status of nand node should be enabled.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/p1023rds/p1023rds.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1023rds/p1023rds.c
b/board/freescale/p1023rds/p1023rds.c
index 8cfd199..c99ccee 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -158,5 +158,10 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_NAND_U_BOOT
+ do_fixup_by_path_string(fdt, nor_flash, status, disabled);
+ do_fixup_by_path_string(fdt, nand_flash, status, okay);
+#endif
}
#endif
--
1.5.6.5
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Re: [U-Boot] [PATCH 2/2 v3] powerpc/p1023rds: Enable nand node and disable nor node
On Mon, 29 Aug 2011 02:14:20 +0800, Kumar Gala kumar.g...@freescale.com
wrote:
On Aug 17, 2011, at 1:24 AM, Chunhe Lan wrote:
In the p1023rds, accessing exclusively nor flash or nand flash
device by BR0/OR0. When booting from nor flash, nand node is
disabled and nor node is enabled in the default dtb. So, when
booting from nand flash, nand node should be enabled and nor
node should be disabled.
Fix where you break the line, should like more like (use upto 75 chars
per line):
OK.
In the p1023rds, accessing exclusively nor flash or nand flash
device by
BR0/OR0. When booting from nor flash, nand node is disabled and nor
node
is enabled in the default dtb. So, when booting from nand flash, nand
node should be enabled and nor node should be disabled.
Signed-off-by: Chunhe Lan chunhe@freescale.com
Can you provide example of what the device tree looks like for the two
cases.
OK.
---
board/freescale/p1023rds/p1023rds.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1023rds/p1023rds.c
b/board/freescale/p1023rds/p1023rds.c
index 8cfd199..2fec3ee 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -146,6 +146,14 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+void fdt_fixup_flash(void *fdt)
+{
+#ifdef CONFIG_NAND_U_BOOT
+do_fixup_by_path_string(fdt, nor_flash, status, disabled);
+do_fixup_by_path_string(fdt, nand_flash, status, okay);
+#endif
+}
+
No need for a separate function, just put the two line in
ft_board_setup()
OK.
Thanks.
-Jack Lan
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
@@ -158,5 +166,7 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+fdt_fixup_flash(blob);
}
#endif
--
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Re: [U-Boot] [PATCH 1/2 v3] fdt: Add a do_fixup_by_path_string() function
On Mon, 29 Aug 2011 02:15:15 +0800, Kumar Gala kumar.g...@freescale.com
wrote:
On Aug 17, 2011, at 1:24 AM, Chunhe Lan wrote:
The do_fixup_by_path_string() will set the specified
node's property to the value contained in status.
It would just be a wrapper for do_fixup_by_path()
that calls strlen on the argument.
Fix where you break the line, should like more like (use upto 75 chars
per line):
OK.
Thanks.
-Jack Lan
The do_fixup_by_path_string() will set the specified node's property
to the
value contained in status. It would just be a wrapper for
do_fixup_by_path() that calls strlen on the argument.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
include/fdt_support.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 863024f..1de4a1d 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -36,6 +36,13 @@ void do_fixup_by_path(void *fdt, const char *path,
const char *prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create);
+
+static inline void do_fixup_by_path_string(void *fdt, const char *path,
+ const char *prop, const char *status)
+{
+do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
--
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[U-Boot] [PATCH 2/2 v3] powerpc/p1023rds: Enable nand node and disable nor node
In the p1023rds, accessing exclusively nor flash or nand flash
device by BR0/OR0. When booting from nor flash, nand node is
disabled and nor node is enabled in the default dtb. So, when
booting from nand flash, nand node should be enabled and nor
node should be disabled.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/p1023rds/p1023rds.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1023rds/p1023rds.c
b/board/freescale/p1023rds/p1023rds.c
index 8cfd199..2fec3ee 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -146,6 +146,14 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+void fdt_fixup_flash(void *fdt)
+{
+#ifdef CONFIG_NAND_U_BOOT
+ do_fixup_by_path_string(fdt, nor_flash, status, disabled);
+ do_fixup_by_path_string(fdt, nand_flash, status, okay);
+#endif
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
@@ -158,5 +166,7 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_flash(blob);
}
#endif
--
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[U-Boot] [PATCH 1/2 v3] fdt: Add a do_fixup_by_path_string() function
The do_fixup_by_path_string() will set the specified
node's property to the value contained in status.
It would just be a wrapper for do_fixup_by_path()
that calls strlen on the argument.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
include/fdt_support.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 863024f..1de4a1d 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -36,6 +36,13 @@ void do_fixup_by_path(void *fdt, const char *path, const
char *prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create);
+
+static inline void do_fixup_by_path_string(void *fdt, const char *path,
+ const char *prop, const char *status)
+{
+ do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
--
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[U-Boot] [PATCH 1/2 v2] fdt: Add a do_fixup_by_path_string() function
The do_fixup_by_path_string() will set the specified
node's property to the value contained in status.
It would just be a wrapper for do_fixup_by_path()
that calls strlen on the argument.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
common/fdt_support.c |8 +++-
include/fdt_support.h |2 ++
2 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 19b2ef6..99ff84f 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -2,7 +2,7 @@
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanba...@cideas.com
*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -307,6 +307,12 @@ void do_fixup_by_path_u32(void *fdt, const char *path,
const char *prop,
do_fixup_by_path(fdt, path, prop, val, sizeof(val), create);
}
+void do_fixup_by_path_string(void *fdt, const char *path, const char *prop,
+const char *status)
+{
+ do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 863024f..06d6a51 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -36,6 +36,8 @@ void do_fixup_by_path(void *fdt, const char *path, const char
*prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create);
+void do_fixup_by_path_string(void *fdt, const char *path, const char *prop,
+const char *status);
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
--
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[U-Boot] [PATCH 2/2 v2] powerpc/p1023rds: Enable nand node and disable nor node
In the p1023rds, accessing exclusively nor flash or nand flash
device by BR0/OR0. When booting from nor flash, nand node is
disabled and nor node is enabled in the default dtb. So, when
booting from nand flash, nand node should be enabled and nor
node should be disabled.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/p1023rds/p1023rds.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1023rds/p1023rds.c
b/board/freescale/p1023rds/p1023rds.c
index 8cfd199..2fec3ee 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -146,6 +146,14 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+void fdt_fixup_flash(void *fdt)
+{
+#ifdef CONFIG_NAND_U_BOOT
+ do_fixup_by_path_string(fdt, nor_flash, status, disabled);
+ do_fixup_by_path_string(fdt, nand_flash, status, okay);
+#endif
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
@@ -158,5 +166,7 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_flash(blob);
}
#endif
--
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[U-Boot] [PATCH 1/2] fdt: Add a fdt_set_node_status function
Add a fdt_set_node_status function that will set the specified
node's status to the value contained in status. If the node
doesn't have status property that will be created.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
common/fdt_support.c | 17 -
include/fdt_support.h |3 +++
2 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 19b2ef6..384523b 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -2,7 +2,7 @@
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanba...@cideas.com
*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -904,6 +904,21 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
fdt_delprop(blob, off, alias);
}
+/*
+ * Sets the specified node's status to the value contained in status.
+ * If the first character of the specified path is / then we use
+ * alias as a path. Otherwise, we look for an alias of that name.
+ */
+void fdt_set_node_status(void *fdt, const char *alias, const char *status)
+{
+ const char *path = fdt_get_alias(fdt, alias);
+
+ if (!path)
+ path = alias;
+
+ do_fixup_by_path(fdt, path, status, status, strlen(status) + 1, 1);
+}
+
/* Helper to read a big number; size is in cells (not bytes) */
static inline u64 of_read_number(const __be32 *cell, int size)
{
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 863024f..74d7c83 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -2,6 +2,8 @@
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanba...@cideas.com
*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -85,6 +87,7 @@ int fdt_fixup_nor_flash_size(void *blob);
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
void fdt_del_node_and_alias(void *blob, const char *alias);
+void fdt_set_node_status(void *fdt, const char *alias, const char *status);
u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
phys_addr_t compat_off);
--
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[U-Boot] [PATCH 2/2] powerpc/p1023rds: Enable nand node and disable nor node
In the p1023rds, accessing exclusively nor flash or nand flash
device by BR0/OR0. When booting from nor flash, nand node is
disabled and nor node is enabled in the default dtb. So, when
booting from nand flash, nand node should be enabled and nor
node should be disabled.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
board/freescale/p1023rds/p1023rds.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1023rds/p1023rds.c
b/board/freescale/p1023rds/p1023rds.c
index 8cfd199..b3511a4 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -146,6 +146,14 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+void fdt_fixup_flash(void *fdt)
+{
+#ifdef CONFIG_NAND_U_BOOT
+ fdt_set_node_status(fdt, nor_flash, disabled);
+ fdt_set_node_status(fdt, nand_flash, okay);
+#endif
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
@@ -158,5 +166,7 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_flash(blob);
}
#endif
--
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