Re: [PATCH v4] common: avb_verify: prevent opening incorrect session
Any comments to this patch? -- Regards, Ivan Khoronzhuk
[PATCH v4] common: avb_verify: prevent opening incorrect session
The arg->session is not valid if arg->ret != NULL, so can't be
assigned, correct this.
Signed-off-by: Ivan Khoronzhuk
---
common/avb_verify.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 0520a71455..48ba8db51e 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -619,10 +619,11 @@ static int get_open_session(struct AvbOpsData *ops_data)
memset(, 0, sizeof(arg));
tee_optee_ta_uuid_to_octets(arg.uuid, );
rc = tee_open_session(tee, , 0, NULL);
- if (!rc) {
- ops_data->tee = tee;
- ops_data->session = arg.session;
- }
+ if (rc || arg.ret)
+ continue;
+
+ ops_data->tee = tee;
+ ops_data->session = arg.session;
}
return 0;
--
2.34.1
Re: [PATCH v3] common: avb_verify: prevent opening incorrect session
Ignore this version please, will send v4. Skipped previous comment unintentionally. -- Regards, Ivan Khoronzhuk
[PATCH v3] common: avb_verify: prevent opening incorrect session
The arg->session is not valid if arg->ret != NULL, so can't be
assigned, correct this. Also remove "while" loop as there is no
reason for looping till correct session is opened.
Signed-off-by: Ivan Khoronzhuk
---
common/avb_verify.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 0520a71455..c3cccd986d 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -605,26 +605,26 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
#ifdef CONFIG_OPTEE_TA_AVB
static int get_open_session(struct AvbOpsData *ops_data)
{
- struct udevice *tee = NULL;
-
- while (!ops_data->tee) {
- const struct tee_optee_ta_uuid uuid = TA_AVB_UUID;
- struct tee_open_session_arg arg;
- int rc;
-
- tee = tee_find_device(tee, NULL, NULL, NULL);
- if (!tee)
- return -ENODEV;
-
- memset(, 0, sizeof(arg));
- tee_optee_ta_uuid_to_octets(arg.uuid, );
- rc = tee_open_session(tee, , 0, NULL);
- if (!rc) {
- ops_data->tee = tee;
- ops_data->session = arg.session;
- }
- }
+ const struct tee_optee_ta_uuid uuid = TA_AVB_UUID;
+ struct tee_open_session_arg arg;
+ struct udevice *tee;
+ int rc;
+
+ if (ops_data->tee)
+ return 0;
+
+ tee = tee_find_device(NULL, NULL, NULL, NULL);
+ if (!tee)
+ return -ENODEV;
+
+ memset(, 0, sizeof(arg));
+ tee_optee_ta_uuid_to_octets(arg.uuid, );
+ rc = tee_open_session(tee, , 0, NULL);
+ if (rc || arg.ret)
+ return -EIO;
+ ops_data->tee = tee;
+ ops_data->session = arg.session;
return 0;
}
--
2.34.1
Re: [PATCH v2] common: avb_verify: prevent opening incorrect session
On Mon, Jan 23, 2023 at 04:34:33PM +0100, Jens Wiklander wrote:
On Mon, Jan 23, 2023 at 04:51:29PM +0200, Ivan Khoronzhuk wrote:
The arg->session is not valid if arg->ret != NULL, so can't be
assigned. Leave retry for just "ret" error to save same behaviour.
Signed-off-by: Ivan Khoronzhuk
---
common/avb_verify.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 0520a71455..97451592f5 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -619,10 +619,14 @@ static int get_open_session(struct AvbOpsData *ops_data)
memset(, 0, sizeof(arg));
tee_optee_ta_uuid_to_octets(arg.uuid, );
rc = tee_open_session(tee, , 0, NULL);
- if (!rc) {
- ops_data->tee = tee;
- ops_data->session = arg.session;
- }
+ if (rc)
+ continue;
+
+ if (arg.ret)
+ return -EIO;
+
+ ops_data->tee = tee;
+ ops_data->session = arg.session;
}
return 0;
It looks like this function is still slightly broken. The function
should, if I understand it correctly, return usable tee and session
pointers on success, else return an error code. The unconditional return
0 at the end doesn't seem right.
Thanks,
Jens
It doesn't return, it loops infinitely...
Yes, it looks so, but it's how it works. I don't see a reason why the
function must loop trying to open the session that potentially never will be
opened. But this is how it's implemented and I didn't wont to change this
behaviour that can have some "sacral" roots, only add a fix I bother, I've
mentioned it in the comment. Better would be drop this loop ofc and add the
following:
+ if (ret || arg.ret)
+ return -EIO;
I can do this in v3 if you don't mind.
--
Regards,
Ivan Khoronzhuk
[PATCH v2] common: avb_verify: prevent opening incorrect session
The arg->session is not valid if arg->ret != NULL, so can't be
assigned. Leave retry for just "ret" error to save same behaviour.
Signed-off-by: Ivan Khoronzhuk
---
common/avb_verify.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 0520a71455..97451592f5 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -619,10 +619,14 @@ static int get_open_session(struct AvbOpsData *ops_data)
memset(, 0, sizeof(arg));
tee_optee_ta_uuid_to_octets(arg.uuid, );
rc = tee_open_session(tee, , 0, NULL);
- if (!rc) {
- ops_data->tee = tee;
- ops_data->session = arg.session;
- }
+ if (rc)
+ continue;
+
+ if (arg.ret)
+ return -EIO;
+
+ ops_data->tee = tee;
+ ops_data->session = arg.session;
}
return 0;
--
2.34.1
[PATCH] common: avb_verify: prevent opening incorrect session
The arg->session is not valid if arg->ret != NULL, so can't be
assigned. Leave retry for just "ret" error to save same behaviour.
Signed-off-by: Ivan Khoronzhuk
---
common/avb_verify.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 0520a71455..05d5a97896 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -619,10 +619,14 @@ static int get_open_session(struct AvbOpsData *ops_data)
memset(, 0, sizeof(arg));
tee_optee_ta_uuid_to_octets(arg.uuid, );
rc = tee_open_session(tee, , 0, NULL);
- if (!rc) {
- ops_data->tee = tee;
- ops_data->session = arg.session;
- }
+ if (rc)
+ continue;
+
+ if (arg.ret)
+ return AVB_IO_RESULT_ERROR_IO;
+
+ ops_data->tee = tee;
+ ops_data->session = arg.session;
}
return 0;
--
2.34.1
Re: [U-Boot] [PATCH v5] bitops: introduce BIT() definition
On 09.09.15 19:22, Scott Wood wrote: On Tue, 2015-09-08 at 21:01 +0300, ivan.khoronzhuk wrote: Hi, Andreas On 07.09.15 14:43, Andreas Bießmann wrote: From: Heiko Schocher <h...@denx.de> introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <h...@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.de...@googlemail.com> --- Full buildman is running +#define BIT(nr)(1UL << (nr)) Why UL? Why not simply 1 << (nr)? That would give the wrong result for nr == 31 if used as a 64-bit number, and Did you mean with 64-bit signed number? After fast glance seems there is no places, but if they are, this can add interesting fixes. would produce undefined behavior for nr >= 32 (though even with 1UL that would be undefined on 32-bit builds). What if I need set ULL bit on 32-bit system? Thanks for explanation. Yes, ULL would be better. -Scott -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] bitops: introduce BIT() definition
On 09.09.15 20:10, Scott Wood wrote: On Wed, 2015-09-09 at 12:37 -0400, Tom Rini wrote: On Wed, Sep 09, 2015 at 11:22:25AM -0500, Scott Wood wrote: On Tue, 2015-09-08 at 21:01 +0300, ivan.khoronzhuk wrote: Hi, Andreas On 07.09.15 14:43, Andreas Bießmann wrote: From: Heiko Schocher <h...@denx.de> introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <h...@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.de...@googlemail.com> --- Full buildman is running +#define BIT(nr)(1UL << (nr)) Why UL? Why not simply 1 << (nr)? That would give the wrong result for nr == 31 if used as a 64-bit number, and would produce undefined behavior for nr >= 32 (though even with 1UL that would be undefined on 32-bit builds). What if I need set ULL bit on 32-bit system? Thanks for explanation. Yes, ULL would be better. That would be BIT_ULL(nr) ? I want to assume that there was some care given upstream here. It was about 2 years ago now the kernel added a specific BIT_ULL and family in addition to BIT(nr) from back in 2007. A quick search didn't turn up much justification for keeping them separate (and it seems like using BIT where BIT_ULL is needed could be a source of difficult bugs), but sure, we don't want to encourage writing driver code that will break on Linux. Better to keep same approach. -Scott -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] driver: net: keystone_net: fix phy mode configuration
On 23.07.15 15:43, Mugunthan V N wrote: On Thursday 23 July 2015 04:46 PM, Ivan Khoronzhuk wrote: Hi, Mugunthan You are right, phy mode is a board property. But just for clarifying, does Ethernet SS, which contains SGMII on board, support another i/f mode except SGMII? Can it work w/o SerDes? There is a upcoming SoC (K2E) using the same IP with RGMII phy connected. So the IP is capable of supporting multiple phy modes. Regards Mugunthan V N Then I would ask you to add it in commit message. Also, if it can work in RGMII mode, could you please check if a following errata doesn't affect you configuration. This is only for Marvell phys, and if it's your case, it be good, probably, to extend it`s impact on RGMII mode also. net: phy: marvell: add errata w/a for 88E151* chips 35fa0dda0ccee8075b1ef8922e930d5dcdea9f5e ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] driver: net: keystone_net: fix phy mode configuration
Hi, Mugunthan
You are right, phy mode is a board property.
But just for clarifying, does Ethernet SS, which contains SGMII
on board, support another i/f mode except SGMII? Can it work
w/o SerDes?
On 23.07.15 12:01, Mugunthan V N wrote:
Phy mode is a board property and it can be different between
multiple board and ports, so it should not be hardcoded in
driver to one specific mode. So adding a field in eth_priv_t
structure to pass phy mode to driver.
Cc: Murali Karicheri m-kariche...@ti.com
Cc: Lokesh Vutla lokeshvu...@ti.com
Cc: Vitaly Andrianov vita...@ti.com
Cc: Joe Hershberger joe.hershber...@ni.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/include/asm/ti-common/keystone_net.h | 2 ++
board/ti/ks2_evm/board_k2e.c | 8
board/ti/ks2_evm/board_k2hk.c | 4
board/ti/ks2_evm/board_k2l.c | 4
drivers/net/keystone_net.c| 4 ++--
5 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_net.h
b/arch/arm/include/asm/ti-common/keystone_net.h
index 011c03c..235a9fa 100644
--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -11,6 +11,7 @@
#define _KEYSTONE_NET_H_
#include asm/io.h
+#include phy.h
/* EMAC */
#ifdef CONFIG_KSNET_NETCP_V1_0
@@ -239,6 +240,7 @@ struct eth_priv_t {
int phy_addr;
int slave_port;
int sgmii_link_type;
+ phy_interface_t phy_if;
struct phy_device *phy_dev;
};
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 43dfc48..59c6516 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -47,6 +47,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name= K2E_EMAC1,
@@ -54,6 +55,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name= K2E_EMAC2,
@@ -61,6 +63,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name= K2E_EMAC3,
@@ -68,6 +71,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name= K2E_EMAC4,
@@ -75,6 +79,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 4,
.slave_port = 5,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name= K2E_EMAC5,
@@ -82,6 +87,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 5,
.slave_port = 6,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name= K2E_EMAC6,
@@ -89,6 +95,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 6,
.slave_port = 7,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name= K2E_EMAC7,
@@ -96,6 +103,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr= 7,
.slave_port = 8,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
};
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index ed181f4..acd4205 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -54,6 +54,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = K2HK_EMAC1,
@@ -61,6 +62,7 @@ struct eth_priv_t eth_priv_cfg[] = {
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
Re: [U-Boot] [PATCH] keystone2: use appropriate HD field for destination port
Hi, Vitaly
I suppose it's better to decide in upper driver how to use swinfo field.
Like in drivers/net/keystone_net.c
The keystone navigator supposed to be used as a tool for communicating
between different IPs, and each of them decide how to use swinfo fields.
It's protocol specific information and should be known only in sending
parts. What if tomorrow you will decide to send some packet to PA?, you
will rewrite this function again?
It's not the place for such kind information.
Even more, this is the h/w specific decision and no need to check this
for each sent packet. You better statically assign how to use this field
depending on h/w revision, using #if.
On 08.07.15 18:45, Vitaly Andrianov wrote:
K2L and L2E have different from K2HK EthSS version, which uses tag_info
field for destination slave port. This commit adds the dest_port_info field
to the struct pktdma_cfg, to configure which HD filed tag_info or pkt_info
shall be used to configure descriptor.
Before that commit the swinfo[2] was used for that purpose. Even if that
worked on K2HK devices, the correct field for K2HK is the pkt_info.
The netcp_send() configure appropriate HD info field depending on the
direct_info of the currently using netcp.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
---
arch/arm/include/asm/ti-common/keystone_nav.h | 9 -
drivers/dma/keystone_nav.c| 12 ++--
drivers/net/keystone_net.c| 3 +--
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h
b/arch/arm/include/asm/ti-common/keystone_nav.h
index 696d8c6..5a0e391 100644
--- a/arch/arm/include/asm/ti-common/keystone_nav.h
+++ b/arch/arm/include/asm/ti-common/keystone_nav.h
@@ -152,6 +152,11 @@ struct rx_flow_regs {
u32 thresh[3];
};
+enum dest_port_info {
+ PKT_INFO,
+ TAG_INFO
+};
+
struct pktdma_cfg {
struct global_ctl_regs *global;
struct tx_chan_regs *tx_ch;
@@ -167,6 +172,7 @@ struct pktdma_cfg {
u32 tx_snd_q;
u32 rx_flow; /* flow that is used for RX */
+ enum dest_port_info dest_port_info;/* HD fiels for dest port bits */
};
extern struct pktdma_cfg netcp_pktdma;
@@ -184,7 +190,8 @@ struct rx_buff_desc {
int ksnav_close(struct pktdma_cfg *pktdma);
int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32
swinfo2);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port);
void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c
index dfca75a..64b1cee 100644
--- a/drivers/dma/keystone_nav.c
+++ b/drivers/dma/keystone_nav.c
@@ -278,7 +278,8 @@ int ksnav_close(struct pktdma_cfg *pktdma)
return QM_OK;
}
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2)
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port)
{
struct qm_host_desc *hd;
@@ -286,8 +287,15 @@ int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int
num_bytes, u32 swinfo2)
if (hd == NULL)
return QM_ERR;
+ dest_port = 0xf;
hd-desc_info= num_bytes;
- hd-swinfo[2]= swinfo2;
+ if (pktdma-dest_port_info == PKT_INFO) {
+ hd-packet_info = qm_cfg-qpool_num | (dest_port 16);
+ } else {
+ hd-packet_info = qm_cfg-qpool_num;
+ hd-tag_info = dest_port;
+ }
+
hd-packet_info = qm_cfg-qpool_num;
qm_buff_push(hd, pktdma-tx_snd_q, pkt, num_bytes);
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 0c5fdee..e2adb67 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -381,8 +381,7 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int
slave_port_num)
if (num_bytes EMAC_MIN_ETHERNET_PKT_SIZE)
num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
- return ksnav_send(netcp_pktdma, buffer,
- num_bytes, (slave_port_num) 16);
+ return ksnav_send(netcp_pktdma, buffer, num_bytes, slave_port_num);
}
/* Eth device open */
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] keystone2: use appropriate HD field for destination port
On 08.07.15 22:22, ivan.khoronzhuk wrote:
Vitaly,
On 08.07.15 21:28, Vitaly Andrianov wrote:
On 07/08/2015 01:50 PM, ivan.khoronzhuk wrote:
Vitaly,
On 08.07.15 20:26, Vitaly Andrianov wrote:
On 07/08/2015 01:05 PM, Ivan Khoronzhuk wrote:
Vitaly,
On 08.07.15 20:05, Vitaly Andrianov wrote:
On 07/08/2015 12:38 PM, Ivan Khoronzhuk wrote:
Hi, Vitaly
I suppose it's better to decide in upper driver how to use swinfo
field.
Like in drivers/net/keystone_net.c
The keystone navigator supposed to be used as a tool for
communicating
between different IPs, and each of them decide how to use swinfo
fields.
It's protocol specific information and should be known only in
sending
parts. What if tomorrow you will decide to send some packet to PA?,
you
will rewrite this function again?
It's not the place for such kind information.
Even more, this is the h/w specific decision and no need to check
this
for each sent packet. You better statically assign how to use this
field
depending on h/w revision, using #if.
On 08.07.15 18:45, Vitaly Andrianov wrote:
K2L and L2E have different from K2HK EthSS version, which uses
tag_info
field for destination slave port. This commit adds the
dest_port_info
field
to the struct pktdma_cfg, to configure which HD filed tag_info or
pkt_info
shall be used to configure descriptor.
Before that commit the swinfo[2] was used for that purpose. Even if
that
worked on K2HK devices, the correct field for K2HK is the pkt_info.
The netcp_send() configure appropriate HD info field depending on
the
direct_info of the currently using netcp.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
---
arch/arm/include/asm/ti-common/keystone_nav.h | 9 -
drivers/dma/keystone_nav.c| 12 ++--
drivers/net/keystone_net.c| 3 +--
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h
b/arch/arm/include/asm/ti-common/keystone_nav.h
index 696d8c6..5a0e391 100644
--- a/arch/arm/include/asm/ti-common/keystone_nav.h
+++ b/arch/arm/include/asm/ti-common/keystone_nav.h
@@ -152,6 +152,11 @@ struct rx_flow_regs {
u32thresh[3];
};
+enum dest_port_info {
+PKT_INFO,
+TAG_INFO
+};
+
struct pktdma_cfg {
struct global_ctl_regs*global;
struct tx_chan_regs*tx_ch;
@@ -167,6 +172,7 @@ struct pktdma_cfg {
u32tx_snd_q;
u32rx_flow; /* flow that is used for RX */
+enum dest_port_info dest_port_info;/* HD fiels for dest
port
bits */
};
extern struct pktdma_cfg netcp_pktdma;
@@ -184,7 +190,8 @@ struct rx_buff_desc {
int ksnav_close(struct pktdma_cfg *pktdma);
int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc
*rx_buffers);
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
u32 swinfo2);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port);
void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int
*num_bytes);
void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
diff --git a/drivers/dma/keystone_nav.c
b/drivers/dma/keystone_nav.c
index dfca75a..64b1cee 100644
--- a/drivers/dma/keystone_nav.c
+++ b/drivers/dma/keystone_nav.c
@@ -278,7 +278,8 @@ int ksnav_close(struct pktdma_cfg *pktdma)
return QM_OK;
}
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
u32 swinfo2)
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port)
{
struct qm_host_desc *hd;
@@ -286,8 +287,15 @@ int ksnav_send(struct pktdma_cfg *pktdma, u32
*pkt, int num_bytes, u32 swinfo2)
if (hd == NULL)
return QM_ERR;
+dest_port = 0xf;
hd-desc_info= num_bytes;
-hd-swinfo[2]= swinfo2;
+if (pktdma-dest_port_info == PKT_INFO) {
+hd-packet_info= qm_cfg-qpool_num | (dest_port
16);
+} else {
+hd-packet_info = qm_cfg-qpool_num;
+hd-tag_info = dest_port;
+}
+
hd-packet_info = qm_cfg-qpool_num;
qm_buff_push(hd, pktdma-tx_snd_q, pkt, num_bytes);
diff --git a/drivers/net/keystone_net.c
b/drivers/net/keystone_net.c
index 0c5fdee..e2adb67 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -381,8 +381,7 @@ int32_t cpmac_drv_send(u32 *buffer, int
num_bytes,
int slave_port_num)
if (num_bytes EMAC_MIN_ETHERNET_PKT_SIZE)
num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
-return ksnav_send(netcp_pktdma, buffer,
- num_bytes, (slave_port_num) 16);
+return ksnav_send(netcp_pktdma, buffer, num_bytes,
slave_port_num);
}
/* Eth device open */
Hi Ivan,
I agree with you. And probably we will need to implement your
proposal
in future commits. This commit is to fix the bug, which is in
existing
driver.
Thanks,
Vitaly
Sorry, I supposed that first msg was not sent.
It's better to fix it in drivers/net/keystone_net.c
Ivan
Re: [U-Boot] [PATCH] keystone2: use appropriate HD field for destination port
Hi, Vitaly
I suppose it's better to decide in upper driver how to use swinfo field.
Like in drivers/net/keystone_net.c
The keystone navigator supposed to be used as a tool for communicating
between different IPs, and each of them decide how to use swinfo fields.
It's protocol specific information and should be known only for sending
parts. What if tomorrow will be decided to send some packet to PA?,
rewrite this function again?
It's not the place for such kind information.
This is the h/w specific static decision and no need to check this
for each sent packet. It be better to statically assign how to use this
field depending on h/w revision, using macro configs, for instance:
CONFIG_SOC_K2HK
CONFIG_KSNET_NETCP_V1_0
CONFIG_KSNET_NETCP_V1_5
On 08.07.15 18:45, Vitaly Andrianov wrote:
K2L and L2E have different from K2HK EthSS version, which uses tag_info
field for destination slave port. This commit adds the dest_port_info field
to the struct pktdma_cfg, to configure which HD filed tag_info or pkt_info
shall be used to configure descriptor.
Before that commit the swinfo[2] was used for that purpose. Even if that
worked on K2HK devices, the correct field for K2HK is the pkt_info.
The netcp_send() configure appropriate HD info field depending on the
direct_info of the currently using netcp.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
---
arch/arm/include/asm/ti-common/keystone_nav.h | 9 -
drivers/dma/keystone_nav.c| 12 ++--
drivers/net/keystone_net.c| 3 +--
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h
b/arch/arm/include/asm/ti-common/keystone_nav.h
index 696d8c6..5a0e391 100644
--- a/arch/arm/include/asm/ti-common/keystone_nav.h
+++ b/arch/arm/include/asm/ti-common/keystone_nav.h
@@ -152,6 +152,11 @@ struct rx_flow_regs {
u32 thresh[3];
};
+enum dest_port_info {
+ PKT_INFO,
+ TAG_INFO
+};
+
struct pktdma_cfg {
struct global_ctl_regs *global;
struct tx_chan_regs *tx_ch;
@@ -167,6 +172,7 @@ struct pktdma_cfg {
u32 tx_snd_q;
u32 rx_flow; /* flow that is used for RX */
+ enum dest_port_info dest_port_info;/* HD fiels for dest port bits */
};
extern struct pktdma_cfg netcp_pktdma;
@@ -184,7 +190,8 @@ struct rx_buff_desc {
int ksnav_close(struct pktdma_cfg *pktdma);
int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32
swinfo2);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port);
void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c
index dfca75a..64b1cee 100644
--- a/drivers/dma/keystone_nav.c
+++ b/drivers/dma/keystone_nav.c
@@ -278,7 +278,8 @@ int ksnav_close(struct pktdma_cfg *pktdma)
return QM_OK;
}
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2)
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port)
{
struct qm_host_desc *hd;
@@ -286,8 +287,15 @@ int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int
num_bytes, u32 swinfo2)
if (hd == NULL)
return QM_ERR;
+ dest_port = 0xf;
hd-desc_info= num_bytes;
- hd-swinfo[2]= swinfo2;
+ if (pktdma-dest_port_info == PKT_INFO) {
+ hd-packet_info = qm_cfg-qpool_num | (dest_port 16);
+ } else {
+ hd-packet_info = qm_cfg-qpool_num;
+ hd-tag_info = dest_port;
+ }
+
hd-packet_info = qm_cfg-qpool_num;
qm_buff_push(hd, pktdma-tx_snd_q, pkt, num_bytes);
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 0c5fdee..e2adb67 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -381,8 +381,7 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int
slave_port_num)
if (num_bytes EMAC_MIN_ETHERNET_PKT_SIZE)
num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
- return ksnav_send(netcp_pktdma, buffer,
- num_bytes, (slave_port_num) 16);
+ return ksnav_send(netcp_pktdma, buffer, num_bytes, slave_port_num);
}
/* Eth device open */
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Re: [U-Boot] [PATCH] keystone2: use appropriate HD field for destination port
Vitaly,
On 08.07.15 20:05, Vitaly Andrianov wrote:
On 07/08/2015 12:38 PM, Ivan Khoronzhuk wrote:
Hi, Vitaly
I suppose it's better to decide in upper driver how to use swinfo field.
Like in drivers/net/keystone_net.c
The keystone navigator supposed to be used as a tool for communicating
between different IPs, and each of them decide how to use swinfo fields.
It's protocol specific information and should be known only in sending
parts. What if tomorrow you will decide to send some packet to PA?, you
will rewrite this function again?
It's not the place for such kind information.
Even more, this is the h/w specific decision and no need to check this
for each sent packet. You better statically assign how to use this field
depending on h/w revision, using #if.
On 08.07.15 18:45, Vitaly Andrianov wrote:
K2L and L2E have different from K2HK EthSS version, which uses tag_info
field for destination slave port. This commit adds the dest_port_info
field
to the struct pktdma_cfg, to configure which HD filed tag_info or
pkt_info
shall be used to configure descriptor.
Before that commit the swinfo[2] was used for that purpose. Even if that
worked on K2HK devices, the correct field for K2HK is the pkt_info.
The netcp_send() configure appropriate HD info field depending on the
direct_info of the currently using netcp.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
---
arch/arm/include/asm/ti-common/keystone_nav.h | 9 -
drivers/dma/keystone_nav.c| 12 ++--
drivers/net/keystone_net.c| 3 +--
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h
b/arch/arm/include/asm/ti-common/keystone_nav.h
index 696d8c6..5a0e391 100644
--- a/arch/arm/include/asm/ti-common/keystone_nav.h
+++ b/arch/arm/include/asm/ti-common/keystone_nav.h
@@ -152,6 +152,11 @@ struct rx_flow_regs {
u32thresh[3];
};
+enum dest_port_info {
+PKT_INFO,
+TAG_INFO
+};
+
struct pktdma_cfg {
struct global_ctl_regs*global;
struct tx_chan_regs*tx_ch;
@@ -167,6 +172,7 @@ struct pktdma_cfg {
u32tx_snd_q;
u32rx_flow; /* flow that is used for RX */
+enum dest_port_info dest_port_info;/* HD fiels for dest port
bits */
};
extern struct pktdma_cfg netcp_pktdma;
@@ -184,7 +190,8 @@ struct rx_buff_desc {
int ksnav_close(struct pktdma_cfg *pktdma);
int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc
*rx_buffers);
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
u32 swinfo2);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port);
void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int
*num_bytes);
void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c
index dfca75a..64b1cee 100644
--- a/drivers/dma/keystone_nav.c
+++ b/drivers/dma/keystone_nav.c
@@ -278,7 +278,8 @@ int ksnav_close(struct pktdma_cfg *pktdma)
return QM_OK;
}
-int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
u32 swinfo2)
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes,
+ u32 dest_port)
{
struct qm_host_desc *hd;
@@ -286,8 +287,15 @@ int ksnav_send(struct pktdma_cfg *pktdma, u32
*pkt, int num_bytes, u32 swinfo2)
if (hd == NULL)
return QM_ERR;
+dest_port = 0xf;
hd-desc_info= num_bytes;
-hd-swinfo[2]= swinfo2;
+if (pktdma-dest_port_info == PKT_INFO) {
+hd-packet_info= qm_cfg-qpool_num | (dest_port 16);
+} else {
+hd-packet_info = qm_cfg-qpool_num;
+hd-tag_info = dest_port;
+}
+
hd-packet_info = qm_cfg-qpool_num;
qm_buff_push(hd, pktdma-tx_snd_q, pkt, num_bytes);
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 0c5fdee..e2adb67 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -381,8 +381,7 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes,
int slave_port_num)
if (num_bytes EMAC_MIN_ETHERNET_PKT_SIZE)
num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
-return ksnav_send(netcp_pktdma, buffer,
- num_bytes, (slave_port_num) 16);
+return ksnav_send(netcp_pktdma, buffer, num_bytes,
slave_port_num);
}
/* Eth device open */
Hi Ivan,
I agree with you. And probably we will need to implement your proposal
in future commits. This commit is to fix the bug, which is in existing
driver.
Thanks,
Vitaly
Sorry, I supposed that first msg was not sent.
It's better to fix it in drivers/net/keystone_net.c
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[U-Boot] [U-boot] [Patch 0/2] keystone2: config: customize uboot environment
Customize default uboot environment in order to simplify it's support and to align with current MCSDK. Based on [U-boot] [Patch 0/2] keystone2: change default boot mode to ubi https://www.mail-archive.com/u-boot@lists.denx.de/msg152442.html Ivan Khoronzhuk (1): keystone2: config: align names of images with MCSDK Murali Karicheri (1): keystone2: config: restructure handling of default env settings include/configs/k2e_evm.h | 17 + include/configs/k2hk_evm.h | 17 + include/configs/k2l_evm.h | 17 + include/configs/ks2_evm.h | 10 ++ 4 files changed, 29 insertions(+), 32 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch 2/2] keystone2: config: align names of images with MCSDK
The Multicore Software Development Kit (MCSDK) provides foundational
software for TI KeyStone II device platforms. It's supposed to be used
with uboot, and it's convenient to have the same names for images, so
correct environment image names according to the last MCSDK3.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
include/configs/k2e_evm.h | 5 +++--
include/configs/k2hk_evm.h | 5 +++--
include/configs/k2l_evm.h | 5 +++--
include/configs/ks2_evm.h | 3 +--
4 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 6b87f6c..d83e07e 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -21,10 +21,11 @@
addr_mon=0x0c14\0 \
args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs \
root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0 \
- name_fdt=k2e-evm.dtb\0\
+ name_fdt=uImage-k2e-evm.dtb\0 \
name_mon=skern-k2e-evm.bin\0 \
name_ubi=k2e-evm-ubifs.ubi\0 \
- name_uboot=u-boot-spi-k2e-evm.gph\0
+ name_uboot=u-boot-spi-k2e-evm.gph\0 \
+ name_fs=arago-console-image-k2e-evm.cpio.gz\0
#include configs/ks2_evm.h
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 33e43eb..ffddf13 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -21,10 +21,11 @@
addr_mon=0x0c5f\0 \
args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs \
root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0 \
- name_fdt=k2hk-evm.dtb\0 \
+ name_fdt=uImage-k2hk-evm.dtb\0\
name_mon=skern-k2hk-evm.bin\0 \
name_ubi=k2hk-evm-ubifs.ubi\0 \
- name_uboot=u-boot-spi-k2hk-evm.gph\0
+ name_uboot=u-boot-spi-k2hk-evm.gph\0 \
+ name_fs=arago-console-image-k2hk-evm.cpio.gz\0
#include configs/ks2_evm.h
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 07326fc..805164a 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -21,10 +21,11 @@
addr_mon=0x0c14\0 \
args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs \
root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0 \
- name_fdt=k2l-evm.dtb\0\
+ name_fdt=uImage-k2l-evm.dtb\0 \
name_mon=skern-k2l-evm.bin\0 \
name_ubi=k2l-evm-ubifs.ubi\0 \
- name_uboot=u-boot-spi-k2l-evm.gph\0
+ name_uboot=u-boot-spi-k2l-evm.gph\0 \
+ name_fs=arago-console-image-k2l-evm.cpio.gz\0
#include configs/ks2_evm.h
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 19273d9..e4890ba 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -260,8 +260,7 @@
addr_ubi=0x8200\0 \
addr_secdb_key=0xc00\0\
fdt_high=0x\0 \
- name_fs=arago-console-image.cpio.gz\0 \
- name_kern=uImage\0\
+ name_kern=uImage-keystone-evm.bin\0 \
run_mon=mon_install ${addr_mon}\0 \
run_kern=bootm ${addr_kern} - ${addr_fdt}\0 \
init_net=run args_all args_net\0 \
--
1.9.1
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Re: [U-Boot] [U-boot] [Patch] ks2_evm: config: enable fatload command
On 11/04/2014 04:54 PM, Tom Rini wrote: On Wed, Oct 29, 2014 at 04:28:56PM +0200, Ivan Khoronzhuk wrote: The keystone2 evm can boot from USB partition with FAT32 FS, so enable fatload command usage. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- include/configs/ks2_evm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index b30e72f..e5e628f 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -225,6 +225,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_USB +#define CONFIG_CMD_FAT Please also add CONFIG_CMD_FS_GENERIC so that you can just use 'load', etc and it just works with various fs types. Ok Thanks. -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch 1/2] keystone2: config: restructure handling of default env settings
From: Murali Karicheri m-kariche...@ti.com
Currently to customize env for various ks2 boards, individual
variables such as NAME_FS etc are defined and included in the
common config.h to define CONFIG_EXTRA_ENV_SETTINGS. This
doesn't scale well if a variable is not applicable on a
specific board. Using this scheme, we have to define variables
with empty value and it's ugly. Instead, to allow board specific
customization of default env variable, define a common
CONFIG_EXTRA_ENV_KS2_SETTINGS for all common variables and define
board specific variables in individual board specific config.h
using CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS. Use the common and board
specific variables to define CONFIG_EXTRA_ENV_SETTINGS. This way
more variables can be added in future for individual boards
without affecting the other config.h files.
Signed-off-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
include/configs/k2e_evm.h | 16
include/configs/k2hk_evm.h | 16
include/configs/k2l_evm.h | 16
include/configs/ks2_evm.h | 7 +--
4 files changed, 25 insertions(+), 30 deletions(-)
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 8c3a0c0..6b87f6c 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -17,14 +17,14 @@
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT K2E EVM #
-#define KS2_ARGS_UBI args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs
\
- root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0
-
-#define KS2_FDT_NAME name_fdt=k2e-evm.dtb\0
-#define KS2_ADDR_MON addr_mon=0x0c14\0
-#define KS2_NAME_MON name_mon=skern-k2e-evm.bin\0
-#define NAME_UBOOT name_uboot=u-boot-spi-k2e-evm.gph\0
-#define NAME_UBI name_ubi=k2e-evm-ubifs.ubi\0
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
+ addr_mon=0x0c14\0 \
+ args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs \
+ root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0 \
+ name_fdt=k2e-evm.dtb\0\
+ name_mon=skern-k2e-evm.bin\0 \
+ name_ubi=k2e-evm-ubifs.ubi\0 \
+ name_uboot=u-boot-spi-k2e-evm.gph\0
#include configs/ks2_evm.h
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index ebf4630..33e43eb 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -17,14 +17,14 @@
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT K2HK EVM #
-#define KS2_ARGS_UBI args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs
\
- root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0
-
-#define KS2_FDT_NAME name_fdt=k2hk-evm.dtb\0
-#define KS2_ADDR_MON addr_mon=0x0c5f\0
-#define KS2_NAME_MON name_mon=skern-k2hk-evm.bin\0
-#define NAME_UBOOT name_uboot=u-boot-spi-k2hk-evm.gph\0
-#define NAME_UBI name_ubi=k2hk-evm-ubifs.ubi\0
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
+ addr_mon=0x0c5f\0 \
+ args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs \
+ root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0 \
+ name_fdt=k2hk-evm.dtb\0 \
+ name_mon=skern-k2hk-evm.bin\0 \
+ name_ubi=k2hk-evm-ubifs.ubi\0 \
+ name_uboot=u-boot-spi-k2hk-evm.gph\0
#include configs/ks2_evm.h
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index ec0d543..07326fc 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -17,14 +17,14 @@
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT K2L EVM #
-#define KS2_ARGS_UBI args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs
\
- root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0
-
-#define KS2_FDT_NAME name_fdt=k2l-evm.dtb\0
-#define KS2_ADDR_MON addr_mon=0x0c14\0
-#define KS2_NAME_MON name_mon=skern-k2l-evm.bin\0
-#define NAME_UBOOT name_uboot=u-boot-spi-k2l-evm.gph\0
-#define NAME_UBI name_ubi=k2l-evm-ubifs.ubi\0
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
+ addr_mon=0x0c14\0 \
+ args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs \
+ root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0 \
+ name_fdt=k2l-evm.dtb\0\
+ name_mon=skern-k2l-evm.bin\0 \
+ name_ubi=k2l-evm-ubifs.ubi\0 \
+ name_uboot=u-boot-spi-k2l-evm.gph\0
#include configs
[U-Boot] [U-boot] [Patch v2] ks2_evm: config: enable fatload command
The keystone2 evm can boot from USB partition with FAT32 FS, so enable generic load command and fatload command usage. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- v2..v1: - enabled generic load command include/configs/ks2_evm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index b30e72f..bddbb1c 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -225,6 +225,8 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC /* U-Boot general configuration */ #define CONFIG_SYS_GENERIC_BOARD -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch] keystone2: replace printf on puts where it's possible
On 11/04/2014 06:46 PM, Tom Rini wrote:
On Tue, Nov 04, 2014 at 01:44:53AM +0200, Ivan Khoronzhuk wrote:
It is better to use simple puts() function instead of printf()
when it's possible. Also remove redundant sprintf().
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
One of the outcomes of the mini-summit and I think was summarized on the
list as well was that we're going to stop with the use puts instead of
printf! thing as it ends up being more annoying to contributors than
useful in terms of functionality and code size.
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 4029493..ff7bc4b 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -122,7 +122,6 @@ void ft_board_setup(void *blob, bd_t *bd)
int nbanks;
u64 size[2];
u64 start[2];
- char name[32];
int nodeoffset;
u32 ddr3a_size;
int unitrd_fixup = 0;
@@ -158,15 +157,13 @@ void ft_board_setup(void *blob, bd_t *bd)
}
/* reserve memory at start of bank */
- sprintf(name, mem_reserve_head);
- env = getenv(name);
+ env = getenv(mem_reserve_head);
if (env) {
start[0] += ustrtoul(env, endp, 0);
size[0] -= ustrtoul(env, endp, 0);
}
- sprintf(name, mem_reserve);
- env = getenv(name);
+ env = getenv(mem_reserve);
if (env)
size[0] -= ustrtoul(env, endp, 0);
This is good to fix however.
Ok,
Reject this patch.
I will send new patch that delete only sprintf.
Thanks!
--
Regards,
Ivan Khoronzhuk
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[U-Boot] [U-boot] [Patch] ks2_evm: board: remove sprintf for simple string
There is no reason to sprintf simple string.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
board/ti/ks2_evm/board.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 4029493..ff7bc4b 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -122,7 +122,6 @@ void ft_board_setup(void *blob, bd_t *bd)
int nbanks;
u64 size[2];
u64 start[2];
- char name[32];
int nodeoffset;
u32 ddr3a_size;
int unitrd_fixup = 0;
@@ -158,15 +157,13 @@ void ft_board_setup(void *blob, bd_t *bd)
}
/* reserve memory at start of bank */
- sprintf(name, mem_reserve_head);
- env = getenv(name);
+ env = getenv(mem_reserve_head);
if (env) {
start[0] += ustrtoul(env, endp, 0);
size[0] -= ustrtoul(env, endp, 0);
}
- sprintf(name, mem_reserve);
- env = getenv(name);
+ env = getenv(mem_reserve);
if (env)
size[0] -= ustrtoul(env, endp, 0);
--
1.9.1
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[U-Boot] [U-boot] [Patch 0/2] keystone2: change default boot mode to ubi
These patches fix ubi boot and enable it by default. Ivan Khoronzhuk (1): ks2_evm: configs: fix UBI volume name Murali Karicheri (1): keystone2: change default boot mode to ubi include/configs/ks2_evm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch 1/2] ks2_evm: configs: fix UBI volume name
The UBI volume name has to be prefixed with ubi:.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
include/configs/ks2_evm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index e5e628f..3c72517 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -270,7 +270,7 @@
run_kern=bootm ${addr_kern} - ${addr_fdt}\0 \
init_net=run args_all args_net\0 \
init_ubi=run args_all args_ubi; \
- ubi part ubifs; ubifsmount boot; \
+ ubi part ubifs; ubifsmount ubi:boot; \
ubifsload ${addr_secdb_key} securedb.key.bin;\0 \
get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0 \
get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0 \
--
1.9.1
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[U-Boot] [U-boot] [Patch 2/2] keystone2: change default boot mode to ubi
From: Murali Karicheri m-kariche...@ti.com To allow out of box demo, change default boot mode to ubi boot now that NAND is functional in latest EVMs. Signed-off-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- include/configs/ks2_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 3c72517..f7585ba 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -247,7 +247,7 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILEuImage #define CONFIG_EXTRA_ENV_SETTINGS \ - boot=ramfs\0 \ + boot=ubi\0\ tftp_root=/\0 \ nfs_root=/export\0\ mem_lpae=1\0 \ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch] dma: keystone_nav: remove spurious qm_cfg verification
The verification qm_cfg existence is done at ksnav_init().
So, there is no need to verify it after initialization.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/dma/keystone_nav.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c
index 77707c2..dfca75a 100644
--- a/drivers/dma/keystone_nav.c
+++ b/drivers/dma/keystone_nav.c
@@ -81,9 +81,6 @@ void qm_close(void)
{
u32 j;
- if (qm_cfg == NULL)
- return;
-
queue_close(qm_cfg-qpool_num);
qm_cfg-mngr_cfg-link_ram_base0= 0;
@@ -105,9 +102,6 @@ void qm_push(struct qm_host_desc *hd, u32 qnum)
{
u32 regd;
- if (!qm_cfg)
- return;
-
cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
regd = (u32)hd | ((sizeof(struct qm_host_desc) 4) - 1);
writel(regd, qm_cfg-queue[qnum].ptr_size_thresh);
@@ -127,9 +121,6 @@ struct qm_host_desc *qm_pop(u32 qnum)
{
u32 uhd;
- if (!qm_cfg)
- return NULL;
-
uhd = readl(qm_cfg-queue[qnum].ptr_size_thresh) ~0xf;
if (uhd)
cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
@@ -139,9 +130,6 @@ struct qm_host_desc *qm_pop(u32 qnum)
struct qm_host_desc *qm_pop_from_free_pool(void)
{
- if (!qm_cfg)
- return NULL;
-
return qm_pop(qm_cfg-qpool_num);
}
--
1.9.1
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[U-Boot] [U-boot] [Patch] keystone2: replace printf on puts where it's possible
It is better to use simple puts() function instead of printf()
when it's possible. Also remove redundant sprintf().
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/ddr3.c | 2 +-
arch/arm/cpu/armv7/keystone/keystone.c | 4 ++--
board/ti/ks2_evm/board.c | 7 ++-
board/ti/ks2_evm/ddr3_k2e.c| 4 ++--
board/ti/ks2_evm/ddr3_k2hk.c | 10 +-
board/ti/ks2_evm/ddr3_k2l.c| 2 +-
6 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 923906a..3e65c2e 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -352,7 +352,7 @@ void ddr3_err_reset_workaround(void)
tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
if (((tmp_a 0x0FE0) != 0) || ((tmp_b 0x0FE0) != 0)) {
- printf(DDR Leveling Error Detected!\n);
+ puts(DDR Leveling Error Detected!\n);
printf(DDR3A PGSR0 = 0x%x\n, tmp_a);
printf(DDR3B PGSR0 = 0x%x\n, tmp_b);
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c
b/arch/arm/cpu/armv7/keystone/keystone.c
index 11a9357..52cb6fc 100644
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -32,7 +32,7 @@ int cpu_to_bus(u32 *ptr, u32 length)
static int turn_off_myself(void)
{
- printf(Turning off ourselves\r\n);
+ puts(Turning off ourselves\r\n);
mon_power_off(0);
psc_disable_module(KS2_LPSC_TETRIS);
@@ -42,7 +42,7 @@ static int turn_off_myself(void)
dsb\n
wfi\n);
- printf(What! Should not see that\n);
+ puts(What! Should not see that\n);
return 0;
}
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 4029493..ff7bc4b 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -122,7 +122,6 @@ void ft_board_setup(void *blob, bd_t *bd)
int nbanks;
u64 size[2];
u64 start[2];
- char name[32];
int nodeoffset;
u32 ddr3a_size;
int unitrd_fixup = 0;
@@ -158,15 +157,13 @@ void ft_board_setup(void *blob, bd_t *bd)
}
/* reserve memory at start of bank */
- sprintf(name, mem_reserve_head);
- env = getenv(name);
+ env = getenv(mem_reserve_head);
if (env) {
start[0] += ustrtoul(env, endp, 0);
size[0] -= ustrtoul(env, endp, 0);
}
- sprintf(name, mem_reserve);
- env = getenv(name);
+ env = getenv(mem_reserve);
if (env)
size[0] -= ustrtoul(env, endp, 0);
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
index 40fd966..3f100ed 100644
--- a/board/ti/ks2_evm/ddr3_k2e.c
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -31,7 +31,7 @@ void ddr3_init(void)
if (!strcmp(dimm_name, 18KSF1G72HZ-1G6E2 )) {
/* 8G SO-DIMM */
ddr3_size = 8;
- printf(DRAM: 8 GiB\n);
+ puts(DRAM: 8 GiB\n);
ddr3phy_1600_8g.zq0cr1 |= 0x1;
ddr3phy_1600_8g.zq1cr1 |= 0x1;
ddr3phy_1600_8g.zq2cr1 |= 0x1;
@@ -40,7 +40,7 @@ void ddr3_init(void)
} else if (!strcmp(dimm_name, 18KSF51272HZ-1G6K2)) {
/* 4G SO-DIMM */
ddr3_size = 4;
- printf(DRAM: 4 GiB\n);
+ puts(DRAM: 4 GiB\n);
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, ddr3phy_1600_4g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_1600_4g);
}
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index a1c3d05..115aed7 100644
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -45,14 +45,14 @@ void ddr3_init(void)
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
ddr3_1600_8g);
- printf(DRAM: Capacity 8 GiB (includes reported
below)\n);
+ puts(DRAM: Capacity 8 GiB (includes reported
below)\n);
ddr3_size = 8;
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, ddr3phy_1600_8g);
ddr3_1600_8g.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
ddr3_1600_8g);
- printf(DRAM: Capacity 4 GiB (includes reported
below)\n);
+ puts(DRAM: Capacity 4 GiB (includes reported
below)\n);
ddr3_size = 4;
}
} else if (!strcmp(dimm_name, SQR-SD3T-2G1333SED)) {
@@ -75,17 +75,17 @@ void ddr3_init(void)
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
ddr3_1333_2g
Re: [U-Boot] [U-boot] [Patch] net: phy: marvell: add errata w/a for 88E151* chips
On 10/30/2014 08:53 AM, Stefan Roese wrote:
On 29.10.2014 19:38, Ivan Khoronzhuk wrote:
From: Hao Zhang hzh...@ti.com
As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514
Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires
that certain registers get written in order to restart
autonegotiation.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/phy/marvell.c | 51
++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index d2ecadc..425db94 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -276,6 +276,55 @@ static int m88es_config(struct phy_device
*phydev)
return 0;
}
+/**
+ * m88e1518_phy_writebits - write bits to a register
+ */
+void m88e1518_phy_writebits(struct phy_device *phydev,
+ u8 reg_num, u16 offset, u16 len, u16 data)
+{
+u16 reg, mask;
+
+if ((len + offset) = 16)
+mask = 0 - (1 offset);
+else
+mask = (1 (len + offset)) - (1 offset);
+
+reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
+
+reg = ~mask;
+reg |= data offset;
+
+phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
+}
+
+static int m88e1518_config(struct phy_device *phydev)
+{
+/*
+ * As per Marvell Release Notes - Alaska
88E1510/88E1518/88E1512/88E1514
+ * Rev A0, Errata Section 3.1
+ */
+phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);/* reg page
0xff */
+phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x);/* reg page 0 */
+phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);/* reg page 18 */
+/* Write HWCFG_MODE = SGMII to Copper */
+m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
Won't this set the mode to SGMII for all users of this code? I know of
at least one board that uses this driver and uses RGMII. So you
shouldn't set this mode here to SGMII unconditionally.
Thanks,
Stefan
Yes.
I will put whole errata w/o under:
if (phydev-interface == PHY_INTERFACE_MODE_SGMII) {
}
as I can face it only for SGMII
Thanks!
--
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[U-Boot] [U-boot] [Patch v2] net: phy: marvell: add errata w/a for 88E151* chips
From: Hao Zhang hzh...@ti.com
As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514
Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires
that certain registers get written in order to restart
autonegotiation.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
v2..v1
use only for SGMII interface.
drivers/net/phy/marvell.c | 53 ++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index d2ecadc..9437c3b 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -276,6 +276,57 @@ static int m88es_config(struct phy_device *phydev)
return 0;
}
+/**
+ * m88e1518_phy_writebits - write bits to a register
+ */
+void m88e1518_phy_writebits(struct phy_device *phydev,
+ u8 reg_num, u16 offset, u16 len, u16 data)
+{
+ u16 reg, mask;
+
+ if ((len + offset) = 16)
+ mask = 0 - (1 offset);
+ else
+ mask = (1 (len + offset)) - (1 offset);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
+
+ reg = ~mask;
+ reg |= data offset;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
+}
+
+static int m88e1518_config(struct phy_device *phydev)
+{
+ /*
+* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
+* /88E1514 Rev A0, Errata Section 3.1
+*/
+ if (phydev-interface == PHY_INTERFACE_MODE_SGMII) {
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* page 0xff */
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x); /* reg page 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);/* reg page 18 */
+ /* Write HWCFG_MODE = SGMII to Copper */
+ m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
+
+ /* Phy reset */
+ m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */
+ udelay(100);
+ }
+
+ return m88es_config(phydev);
+}
+
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
@@ -493,7 +544,7 @@ static struct phy_driver M88E1518_driver = {
.uid = 0x1410dd1,
.mask = 0xff0,
.features = PHY_GBIT_FEATURES,
- .config = m88es_config,
+ .config = m88e1518_config,
.startup = m88e1011s_startup,
.shutdown = genphy_shutdown,
};
--
1.8.3.2
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[U-Boot] [U-boot] [Patch 0/4] keystone2: add network support for K2L SoC and EVM
These patches add network support for Keystone2 Lamar SoC boards. Based on u-boot-ti/master Hao Zhang (1): board: k2l_evm: add network support Ivan Khoronzhuk (3): ARM: keystone2: keysonte_nav: add support for K2L SoC net: keystone_serdes: add keystone K2L SoC support net: keystone_net: add Keystone2 K2L SoC support arch/arm/include/asm/arch-keystone/hardware-k2e.h | 2 -- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 -- arch/arm/include/asm/arch-keystone/hardware-k2l.h | 7 arch/arm/include/asm/arch-keystone/hardware.h | 4 +++ board/ti/ks2_evm/board_k2l.c | 40 +- drivers/net/keystone_net.c | 7 ++-- include/configs/k2e_evm.h | 6 include/configs/k2hk_evm.h | 6 include/configs/k2l_evm.h | 5 +++ include/configs/ks2_evm.h | 6 10 files changed, 66 insertions(+), 19 deletions(-) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch 1/4] ARM: keystone2: keysonte_nav: add support for K2L SoC
The Keystone2 Lamar SoC uses the same keystone navigator. Move queue numbers to common hardware file, as all Keystone2 SoCs have the same ones. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 2 -- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 -- arch/arm/include/asm/arch-keystone/hardware.h | 4 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index 9512756..df49995 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -57,8 +57,6 @@ #define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 #define KS2_NETCP_PDMA_RX_FLOW_BASE0x24189000 #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 -#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 -#define KS2_NETCP_PDMA_RX_RCV_QUEUE4002 #define KS2_NETCP_PDMA_TX_SND_QUEUE896 /* NETCP */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 5a9ea4f..195c0d3 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -98,8 +98,6 @@ #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 #define KS2_NETCP_PDMA_RX_FLOW_BASE0x02005000 #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 -#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 -#define KS2_NETCP_PDMA_RX_RCV_QUEUE4002 #define KS2_NETCP_PDMA_TX_SND_QUEUE648 /* NETCP */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index c6a54d8..be22bdb 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -122,6 +122,10 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_EDMA_QEESR 0x108c #define KS2_EDMA_PARAM_1(x)(0x4020 + (4 * x)) +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE4002 + /* Chip Interrupt Controller */ #define KS2_CIC2_BASE 0x02608000 -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch 4/4] board: k2l_evm: add network support
From: Hao Zhang hzh...@ti.com
This patch adds network support code and enables keystone_net
driver usage for k2l_evm evaluation board.
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
board/ti/ks2_evm/board_k2l.c | 40 +++-
include/configs/k2e_evm.h| 3 ---
include/configs/k2hk_evm.h | 3 ---
include/configs/k2l_evm.h| 5 +
include/configs/ks2_evm.h| 3 +++
5 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 559d20c..729a193 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -10,7 +10,7 @@
#include common.h
#include asm/arch/ddr3.h
#include asm/arch/hardware.h
-#include asm/ti-common/ti-aemif.h
+#include asm/ti-common/keystone_net.h
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +42,44 @@ static struct pll_init_data tetris_pll_config[] = {
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name= K2L_EMAC,
+ .rx_flow = 0,
+ .phy_addr= 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name= K2L_EMAC1,
+ .rx_flow = 8,
+ .phy_addr= 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name= K2L_EMAC2,
+ .rx_flow = 16,
+ .phy_addr= 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name= K2L_EMAC3,
+ .rx_flow = 32,
+ .phy_addr= 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index c79d50c..8c3a0c0 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -35,9 +35,6 @@
#define CONFIG_SYS_NAND_PAGE_2K
/* Network */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_TI_KSNAV
-#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS9
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 45bd72d..ebf4630 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -35,9 +35,6 @@
#define CONFIG_SYS_NAND_PAGE_2K
/* Network */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_TI_KSNAV
-#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNET_NETCP_V1_0
#define CONFIG_KSNET_CPSW_NUM_PORTS5
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 0e1f725..ec0d543 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -34,4 +34,9 @@
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_4K
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS5
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
#endif /* __CONFIG_K2L_EVM_H */
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 74202f3..b30e72f 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -106,6 +106,7 @@
#define CONFIG_SYS_SGMII_RATESCALE 2
/* Keyston Navigator Configuration */
+#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
#define CONFIG_KSNAV_QM_DESC_SETUP_BASEKS2_QM_DESC_SETUP_BASE
@@ -122,6 +123,7 @@
#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
/* NETCP pktdma */
+#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_BASEKS2_NETCP_PDMA_TX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
@@ -135,6 +137,7 @@
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
/* Keystone net */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASEKS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
--
1.8.3.2
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[U-Boot] [U-boot] [Patch 2/4] net: keystone_serdes: add keystone K2L SoC support
Keystone2 Lamar SoC uses the same keystone SerDes driver. All Keystone2 EVM boards currently use SerDes driver, so move CONFIG_TI_KEYSTONE_SERDES to common configuration file. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/include/asm/arch-keystone/hardware-k2l.h | 4 drivers/net/keystone_net.c| 2 +- include/configs/k2e_evm.h | 3 --- include/configs/k2hk_evm.h| 3 --- include/configs/ks2_evm.h | 3 +++ 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h index 05532ad..da448fd 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -84,6 +84,10 @@ /* OSR memory size */ #define KS2_OSR_SIZE 0x10 +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x0232 +#define KS2_LANES_PER_SGMII_SERDES 2 + /* Number of DSP cores */ #define KS2_NUM_DSPS 4 diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index c8681d0..83eeeda 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -582,7 +582,7 @@ static void keystone2_net_serdes_setup(void) ks2_serdes_sgmii_156p25mhz, CONFIG_KSNET_SERDES_LANES_PER_SGMII); -#ifdef CONFIG_SOC_K2E +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, ks2_serdes_sgmii_156p25mhz, CONFIG_KSNET_SERDES_LANES_PER_SGMII); diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 7c8065a..c79d50c 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -42,7 +42,4 @@ #define CONFIG_KSNET_CPSW_NUM_PORTS9 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -/* SerDes */ -#define CONFIG_TI_KEYSTONE_SERDES - #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 034cbfd..45bd72d 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -41,7 +41,4 @@ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS5 -/* SerDes */ -#define CONFIG_TI_KEYSTONE_SERDES - #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 5dae409..74202f3 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -141,6 +141,9 @@ #define CONFIG_KSNET_SERDES_SGMII2_BASEKS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMIIKS2_LANES_PER_SGMII_SERDES +/* SerDes */ +#define CONFIG_TI_KEYSTONE_SERDES + /* AEMIF */ #define CONFIG_TI_AEMIF #define CONFIG_AEMIF_CNTRL_BASEKS2_AEMIF_CNTRL_BASE -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch 3/4] net: keystone_net: add Keystone2 K2L SoC support
The Keystone2 Lamar SoC uses the same keystone net driver. This patch adds opportunity to use it by K2L SoCs. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/include/asm/arch-keystone/hardware-k2l.h | 3 +++ drivers/net/keystone_net.c| 5 - 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h index da448fd..4f1197e 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -102,4 +102,7 @@ #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 #define KS2_NETCP_PDMA_TX_SND_QUEUE896 +/* NETCP */ +#define KS2_NETCP_BASE 0x2600 + #endif /* __ASM_ARCH_HARDWARE_K2L_H */ diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 83eeeda..bedab1d 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -315,7 +315,7 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) writel(cfg-max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); writel(cfg-ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); -#ifdef CONFIG_K2E_EVM +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) /* Map RX packet flow priority to 0 */ writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); #endif @@ -400,6 +400,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) keystone2_net_serdes_setup(); + if (sys_has_mdio) + keystone2_mdio_reset(mdio_bus); + keystone_sgmii_config(phy_dev, eth_priv-slave_port - 1, eth_priv-sgmii_link_type); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch] ks2_evm: readme: add k2l evm board information
From: Khoronzhuk, Ivan ivan.khoronz...@ti.com Currently Keystone2 Lamar evm (K2L) board is added, so update Keystone2 readme file to have such one. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- Based on [U-boot] [Patch 0/4] keystone2: add network support for K2L SoC and EVM https://www.mail-archive.com/u-boot@lists.denx.de/msg151871.html board/ti/ks2_evm/README | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index a551e28..9ee90a4 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -3,10 +3,11 @@ U-Boot port for Texas Instruments Keystone II EVM boards Author: Murali Karicheri m-kariche...@ti.com -This README has information on the u-boot port for K2HK, K2E boards. +This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards. Documentation for this board can be found at http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K. More details on these SoCs are available at company websites @@ -14,7 +15,10 @@ More details on these SoCs are available at company websites K2H: http://www.ti.com/product/tci6638k2h The K2E SoC details are available at - K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + +The K2L SoC details are available at + http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf Board configuration: @@ -25,6 +29,7 @@ Some of the peripherals that are configured by u-boot +--+---+---+---+---+---+---++ |K2HK |2 |512MB |6MB |4(2) |2 |3 |3 | |K2E |4 |512MB |2MB |8(2) |2 |3 |3 | +|K2L |2 |512MB |2MB |4(2) |4 |3 |3 | +--+---+---+---+---+---+---++ There are only 2 eth port installed on the boards. @@ -41,10 +46,13 @@ The port related files can be found at following folders Board configuration files: include/configs/k2hk_evm.h include/configs/k2e_evm.h +include/configs/k2l_evm.h +include/configs/k2l_evm.h As u-boot is migrating to Kconfig there is also board defconfig files configs/k2e_evm_defconfig configs/k2hk_evm_defconfig +configs/k2l_evm_defconfig Supported boot modes: - SPI NOR boot @@ -58,7 +66,7 @@ Supported image formats: Build instructions: === -Examples for k2hk, for k2e just replace k2hk prefix accordingly. +Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly. Don't forget to add ARCH=arm and CROSS_COMPILE. To build u-boot.bin @@ -84,6 +92,8 @@ Use u-boot.bin from the build folder for loading and running u-boot binary on EVM. Follow instructions at K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup +K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup + to configure SW1 dip switch to use No Boot/JTAG DSP Little Endian Boot Mode and Power ON the EVM. Follow instructions to connect serial port of EVM to PC and start TeraTerm or Hyper Terminal. @@ -128,8 +138,8 @@ instructions: 2. Suspend Target. Select Run - Suspend from top level menu CortexA15_1 (Free Running) 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x8700 - through CCS as described in step 2 of Load and Run U-Boot on K2HK/K2E EVM - using CCS, but using address 0x8700. + through CCS as described in step 2 of Load and Run U-Boot on K2HK/K2E/K2L + EVM using CCS, but using address 0x8700. 4. Free Run the target as described earlier (step 4) to get u-boot prompt 5. At the U-Boot console type following to setup u-boot environment variables. setenv addr_uboot 0x8700 -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch] ks2_evm: config: enable fatload command
The keystone2 evm can boot from USB partition with FAT32 FS, so enable fatload command usage. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- include/configs/ks2_evm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index b30e72f..e5e628f 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -225,6 +225,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_USB +#define CONFIG_CMD_FAT /* U-Boot general configuration */ #define CONFIG_SYS_GENERIC_BOARD -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch] net: phy: marvell: add errata w/a for 88E151* chips
From: Hao Zhang hzh...@ti.com
As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514
Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires
that certain registers get written in order to restart
autonegotiation.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/phy/marvell.c | 51 ++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index d2ecadc..425db94 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -276,6 +276,55 @@ static int m88es_config(struct phy_device *phydev)
return 0;
}
+/**
+ * m88e1518_phy_writebits - write bits to a register
+ */
+void m88e1518_phy_writebits(struct phy_device *phydev,
+ u8 reg_num, u16 offset, u16 len, u16 data)
+{
+ u16 reg, mask;
+
+ if ((len + offset) = 16)
+ mask = 0 - (1 offset);
+ else
+ mask = (1 (len + offset)) - (1 offset);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
+
+ reg = ~mask;
+ reg |= data offset;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
+}
+
+static int m88e1518_config(struct phy_device *phydev)
+{
+ /*
+* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514
+* Rev A0, Errata Section 3.1
+*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* reg page 0xff */
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x); /* reg page 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); /* reg page 18 */
+ /* Write HWCFG_MODE = SGMII to Copper */
+ m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
+
+ /* Phy reset */
+ m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */
+ udelay(100);
+
+ return m88es_config(phydev);
+}
+
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
@@ -493,7 +542,7 @@ static struct phy_driver M88E1518_driver = {
.uid = 0x1410dd1,
.mask = 0xff0,
.features = PHY_GBIT_FEATURES,
- .config = m88es_config,
+ .config = m88e1518_config,
.startup = m88e1011s_startup,
.shutdown = genphy_shutdown,
};
--
1.8.3.2
___
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[U-Boot] [U-boot] [Patch] ARM: cmd_clock: generalize command usage description
The usage description of commands refers to headers of sources,
that is not correct. This patch is intended to fix it.
Also generalize code in order to reduce SoC dependent #ifdefs.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
Based on
[U-boot] [Patch v2] keystone: usb: add support of usb xhci
https://patchwork.ozlabs.org/patch/386506
arch/arm/cpu/armv7/keystone/cmd_clock.c | 24 -
arch/arm/include/asm/arch-keystone/clock-k2e.h | 43 +++---
arch/arm/include/asm/arch-keystone/clock-k2hk.h | 47 +
arch/arm/include/asm/arch-keystone/clock.h | 8 +
4 files changed, 61 insertions(+), 61 deletions(-)
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c
b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95b..af1b701 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -58,20 +58,11 @@ pll_cmd_usage:
return cmd_usage(cmdtp);
}
-#ifdef CONFIG_SOC_K2HK
-U_BOOT_CMD(
- pllset, 5, 0, do_pll_cmd,
- set pll multiplier and pre divider,
- pa|arm|ddr3a|ddr3b mult div OD\n
-);
-#endif
-#ifdef CONFIG_SOC_K2E
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
set pll multiplier and pre divider,
- pa|ddr3 mult div OD\n
+ PLLSET_CMD_LIST mult div OD\n
);
-#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -95,12 +86,8 @@ U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
get clock rate,
clk index\n
-#ifdef CONFIG_SOC_K2HK
- See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n
-#endif
-#ifdef CONFIG_SOC_K2E
- See the 'enum clk_e' in the clock-k2e.h for clk indexes\n
-#endif
+ The indexes for clocks:\n
+ CLOCK_INDEXES_LIST
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -141,5 +128,8 @@ U_BOOT_CMD(
psc,3, 0, do_psc_cmd,
enable/disable psc module os disable domain,
mod/domain index en|di|domain\n
- See the hardware.h for Power and Sleep Controller (PSC) Domains\n
+ Intended to control Power and Sleep Controller (PSC) domains and\n
+ modules. The module or domain index exectly corresponds to ones\n
+ listed in official TRM. For instance, to enable MSMC RAM clock\n
+ domain use command: psc 14 en.\n
);
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h
b/arch/arm/include/asm/arch-keystone/clock-k2e.h
index df33a78..d013b83 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -25,27 +25,28 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- ddr3_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, ddr3_pll_clk)\
+ CLK(3, sys_clk0_clk)\
+ CLK(4, sys_clk0_1_clk)\
+ CLK(5, sys_clk0_2_clk)\
+ CLK(6, sys_clk0_3_clk)\
+ CLK(7, sys_clk0_4_clk)\
+ CLK(8, sys_clk0_6_clk)\
+ CLK(9, sys_clk0_8_clk)\
+ CLK(10, sys_clk0_12_clk)\
+ CLK(11, sys_clk0_24_clk)\
+ CLK(12, sys_clk1_clk)\
+ CLK(13, sys_clk1_3_clk)\
+ CLK(14, sys_clk1_4_clk)\
+ CLK(15, sys_clk1_6_clk)\
+ CLK(16, sys_clk1_12_clk)\
+ CLK(17, sys_clk2_clk)\
+ CLK(18, sys_clk3_clk)
+
+#define PLLSET_CMD_LISTpa|ddr3
#define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index bdb869b..f28d5f0 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -28,29 +28,30 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- tetris_pll_clk,
- ddr3a_pll_clk,
- ddr3b_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, tetris_pll_clk)\
+ CLK(3, ddr3a_pll_clk)\
+ CLK(4, ddr3b_pll_clk)\
+ CLK(5, sys_clk0_clk
[U-Boot] [U-boot] [Patch v6 5/6] keystone2: enable OSR clock domain for K2L SoC
From: Hao Zhang hzh...@ti.com
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/init.c| 51 +++
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 24 +++
arch/arm/include/asm/arch-keystone/hardware.h | 1 +
3 files changed, 76 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/init.c
b/arch/arm/cpu/armv7/keystone/init.c
index 62081b7..c2b9478 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
#include asm/arch/msmc.h
#include asm/arch/clock.h
#include asm/arch/hardware.h
+#include asm/arch/psc_defs.h
void chip_configuration_unlock(void)
{
@@ -20,6 +21,53 @@ void chip_configuration_unlock(void)
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+ u32 i;
+ u32 j;
+ u32 val;
+ u32 base = KS2_OSR_CFG_BASE;
+ u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+ /* Enable the OSR clock domain */
+ psc_enable_module(KS2_LPSC_OSR);
+
+ /* Disable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++) {
+ val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+ (KS2_OSR_ECC_CTRL KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+ writel(val , base + KS2_OSR_ECC_VEC);
+
+ /**
+* wait till read is done.
+* Print should be added after earlyprintk support is added.
+*/
+ for (j = 0; j 1; j++) {
+ val = readl(base + KS2_OSR_ECC_VEC);
+ if (val KS2_OSR_ECC_VEC_RD_DONE)
+ break;
+ }
+
+ ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+ KS2_OSR_ECC_CTRL_CHK;
+
+ writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+ writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+ }
+
+ /* Reset OSR memory to all zeros */
+ for (i = 0; i KS2_OSR_SIZE; i += 4)
+ writel(0, KS2_OSR_DATA_BASE + i);
+
+ /* Enable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++)
+ writel(ecc_ctrl[i] |
+ KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
@@ -32,6 +80,9 @@ int arch_cpu_init(void)
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
#endif
+#ifdef CONFIG_SOC_K2L
+ osr_init();
+#endif
/*
* just initialise the COM2 port so that TI specific
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index c1fa3af..05532ad 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -60,6 +60,30 @@
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+/* OSR */
+#define KS2_OSR_DATA_BASE 0x7000 /* OSR data base */
+#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
+#define KS2_OSR_ECC_VEC0x08/* ECC Vector
reg */
+#define KS2_OSR_ECC_CTRL 0x14/* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RDBIT(15) /* trigger a
read op */
+#define KS2_OSR_ECC_VEC_RD_DONEBIT(24) /* read
complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_ENBIT(0) /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS 4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE 0x10
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 4
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 295c6b0..08a7c70 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -142,6 +142,7 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc0
+#define KS2_MSMC_DATA_BASE 0x0c00
#define KS2_MSMC_SEGMENT_TETRIS8
#define KS2_MSMC_SEGMENT_NETCP 9
#define KS2_MSMC_SEGMENT_QM_PDSP 10
--
1.8.3.2
[U-Boot] [U-boot] [Patch v6 4/6] ARM: keystone2: spl: move board specific code
From: Hao Zhang hzh...@ti.com
The initialization of PLLs is a part of board specific code, so
move it appropriate places.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 1 -
arch/arm/cpu/armv7/keystone/spl.c| 53
arch/arm/include/asm/arch-keystone/spl.h | 12
board/ti/ks2_evm/board.c | 19
board/ti/ks2_evm/board.h | 1 +
board/ti/ks2_evm/board_k2e.c | 11 +++
board/ti/ks2_evm/board_k2hk.c| 12
7 files changed, 43 insertions(+), 66 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/keystone/spl.c
delete mode 100644 arch/arm/include/asm/arch-keystone/spl.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 4750371..57f6ea6 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -14,6 +14,5 @@ obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
-obj-$(CONFIG_SPL_BUILD)+= spl.o
obj-y += ddr3.o
obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/spl.c
b/arch/arm/cpu/armv7/keystone/spl.c
deleted file mode 100644
index d4b0e9b..000
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * common spl init code
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, www.ti.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include common.h
-#include config.h
-#include ns16550.h
-#include malloc.h
-#include spl.h
-#include spi_flash.h
-
-#include asm/u-boot.h
-#include asm/utils.h
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_K2HK_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_799,
- TETRIS_PLL_500,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_800,
-};
-#endif
-
-void spl_init_keystone_plls(void)
-{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
-}
-
-void spl_board_init(void)
-{
- spl_init_keystone_plls();
- preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-#if defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#else
- puts(Unknown boot device\n);
- hang();
-#endif
-}
diff --git a/arch/arm/include/asm/arch-keystone/spl.h
b/arch/arm/include/asm/arch-keystone/spl.h
deleted file mode 100644
index a7102d5..000
--- a/arch/arm/include/asm/arch-keystone/spl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012-2014
- * Texas Instruments, www.ti.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_SPI2
-
-#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index dfe7be6..c07d284 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -9,6 +9,7 @@
#include board.h
#include common.h
+#include spl.h
#include exports.h
#include fdt_support.h
#include asm/arch/ddr3.h
@@ -83,6 +84,24 @@ int board_eth_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts(Unknown boot device\n);
+ hang();
+#endif
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT) defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index d91ef73..7a613ac 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -15,5 +15,6 @@
extern struct eth_priv_t eth_priv_cfg[];
int get_num_eth_ports(void);
+void spl_init_keystone_plls(void);
#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 5472a43..810a8e2 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -52,3 +52,14 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_800,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index 6fb3d21..d7dd292 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -100,3 +100,15 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
--
1.8.3.2
___
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[U-Boot] [U-boot] [Patch v6 2/6] keystone2: clock: add K2L clock definitions and commands
From: Hao Zhang hzh...@ti.com
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 1 +
arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 +
arch/arm/include/asm/arch-keystone/clock-k2l.h | 89
arch/arm/include/asm/arch-keystone/clock.h | 4 +
4 files changed, 232 insertions(+)
create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c
create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 3d8fb70..4750371 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,6 +10,7 @@ obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c
b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644
index 000..1c5e4d5
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/clock.h
+#include asm/arch/clock_defs.h
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = (((tmp PLLM_MULT_HI_SMASK) 6) |
+ (pllctl_reg_read(pll, mult)
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl)
+ PLL_CLKOD_SHIFT) PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+ if (!(tmp PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = ((tmp PLL_MULT_SHIFT) PLL_MULT_MASK) + 1;
+ output_div = ((tmp PLL_CLKOD_SHIFT)
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk:return pll_freq_get(TETRIS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2
[U-Boot] [U-boot] [Patch v6 0/6] keystone2: add k2l SoC and k2l_evm board support
This patch series adds Keystone II Lamar (K2L) SoC and k2l_evm board support. Based on [U-Boot,U-boot] ARM: cmd_clock: generalize command usage description http://patchwork.ozlabs.org/patch/402102/ v6..v5 - keystone2: clock: add K2L clock definitions and commands update according to changes made by [U-Boot,U-boot] ARM: cmd_clock: generalize command usage description http://patchwork.ozlabs.org/patch/402102/ - keystone2: msmc: add MSMC cache coherency support for K2L SOC added definitions for msmc segment numbers v5..v4 - ARM: keystone2: spl: move board specific code this patch replace ARM: keystone2: spl: add K2L SoC support as result of moving board specific code to board directory. v4..v3 - keystone2: k2l-evm: add board support remove dimm name reading v3..v2 - keystone2: k2l-evm: add board support Add maintainers information Enable SPL by default v2..v1 Rebased according to changes of c338f09e965a300ddd78af73e86c4af4c9464ce4 keystone: kconfig: move board select menu and common settings Hao Zhang (6): ARM: keystone2: add K2L device hardware definitions keystone2: clock: add K2L clock definitions and commands keystone2: msmc: add MSMC cache coherency support for K2L SOC ARM: keystone2: spl: move board specific code keystone2: enable OSR clock domain for K2L SoC keystone2: k2l-evm: add board support arch/arm/cpu/armv7/keystone/Kconfig| 3 + arch/arm/cpu/armv7/keystone/Makefile | 2 +- arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 + arch/arm/cpu/armv7/keystone/init.c | 63 +- arch/arm/cpu/armv7/keystone/spl.c | 53 arch/arm/include/asm/arch-keystone/clock-k2l.h | 95 ++ arch/arm/include/asm/arch-keystone/clock.h | 4 + arch/arm/include/asm/arch-keystone/hardware-k2e.h | 3 + arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 - arch/arm/include/asm/arch-keystone/hardware-k2l.h | 101 +++ arch/arm/include/asm/arch-keystone/hardware.h | 24 +++- arch/arm/include/asm/arch-keystone/spl.h | 12 -- board/ti/ks2_evm/Kconfig | 16 +++ board/ti/ks2_evm/MAINTAINERS | 2 + board/ti/ks2_evm/Makefile | 2 + board/ti/ks2_evm/board.c | 19 +++ board/ti/ks2_evm/board.h | 1 + board/ti/ks2_evm/board_k2e.c | 11 ++ board/ti/ks2_evm/board_k2hk.c | 12 ++ board/ti/ks2_evm/board_k2l.c | 72 +++ board/ti/ks2_evm/ddr3_cfg.c| 36 ++ board/ti/ks2_evm/ddr3_cfg.h| 3 + board/ti/ks2_evm/ddr3_k2l.c| 38 ++ configs/k2l_evm_defconfig | 4 + include/configs/k2l_evm.h | 37 ++ 25 files changed, 676 insertions(+), 77 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c delete mode 100644 arch/arm/cpu/armv7/keystone/spl.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h delete mode 100644 arch/arm/include/asm/arch-keystone/spl.h create mode 100644 board/ti/ks2_evm/board_k2l.c create mode 100644 board/ti/ks2_evm/ddr3_k2l.c create mode 100644 configs/k2l_evm_defconfig create mode 100644 include/configs/k2l_evm.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v6 1/6] ARM: keystone2: add K2L device hardware definitions
From: Hao Zhang hzh...@ti.com
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 -
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 74 ++
arch/arm/include/asm/arch-keystone/hardware.h | 13
3 files changed, 87 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 43c2c42..2db806c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644
index 000..3402d0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,74 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x2600
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DFE_IQN_SYS 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PAKS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMACKS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO9
+#define KS2_LPSC_PCIE0 10
+#define KS2_LPSC_PCIE1 11
+#define KS2_LPSC_JESD_MISC 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_DDUC4X_CFR2X_BB 27
+#define KS2_LPSC_FFTC_A28
+#define KS2_LPSC_OSR 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 37
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_VCP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DPD4X 48
+#define KS2_LPSC_FFTC_B49
+#define KS2_LPSC_IQN_AIL 50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
+#define KS2_NETCP_PDMA_TX_BASE 0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE896
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index c1642a5..adae69e 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -143,6 +143,7 @@ typedef volatile unsigned int *dv_reg_p;
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
#define KS2_QM_BASE_ADDRESS0x23a8
@@ -177,6 +178,10 @@ typedef volatile unsigned int *dv_reg_p;
#include asm/arch/hardware-k2e.h
#endif
+#ifdef CONFIG_SOC_K2L
+#include asm/arch/hardware-k2l.h
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
@@ -194,6 +199,14 @@ static inline int cpu_is_k2e(void)
return (part_no == 0xb9a6) ? 1 : 0
[U-Boot] [U-boot] [Patch v6 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
From: Hao Zhang hzh...@ti.com This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Hao Zhang hzh...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/cpu/armv7/keystone/init.c| 12 ++-- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 3 +++ arch/arm/include/asm/arch-keystone/hardware-k2l.h | 3 +++ arch/arm/include/asm/arch-keystone/hardware.h | 10 +++--- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index a8f8aee..62081b7 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -25,12 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); - msmc_share_all_segments(8); /* TETRIS */ - msmc_share_all_segments(9); /* NETCP */ - msmc_share_all_segments(10); /* QM PDSP */ - msmc_share_all_segments(11); /* PCIE 0 */ -#ifdef CONFIG_SOC_K2E - msmc_share_all_segments(13); /* PCIE 1 */ + msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); + msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); #endif /* diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index 62172a4..a70c184 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -34,6 +34,9 @@ #define KS2_LPSC_PCIE_127 #define KS2_LPSC_XGE 50 +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 13 + /* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h index 3402d0c..c1fa3af 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -53,6 +53,9 @@ #define KS2_LPSC_FFTC_B49 #define KS2_LPSC_IQN_AIL 50 +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 14 + /* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index adae69e..295c6b0 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -140,6 +140,13 @@ typedef volatile unsigned int *dv_reg_p; /* Flag from ks2_debug options to check if DSPs need to stay ON */ #define DBG_LEAVE_DSPS_ON 0x1 +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc0 +#define KS2_MSMC_SEGMENT_TETRIS8 +#define KS2_MSMC_SEGMENT_NETCP 9 +#define KS2_MSMC_SEGMENT_QM_PDSP 10 +#define KS2_MSMC_SEGMENT_PCIE0 11 + /* Device speed */ #define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98) #define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90) @@ -161,9 +168,6 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_QM_REGION_NUM 64 #define KS2_QM_QPOOL_NUM 4000 -/* MSMC control */ -#define KS2_MSMC_CTRL_BASE 0x0bc0 - /* USB */ #define KS2_USB_SS_BASE0x0268 #define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x1) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v6 6/6] keystone2: k2l-evm: add board support
From: Hao Zhang hzh...@ti.com
This patch adds Keystone II Lammar (K2L) EVM board support.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Kconfig| 3 ++
arch/arm/include/asm/arch-keystone/clock-k2l.h | 6 +++
board/ti/ks2_evm/Kconfig | 16 ++
board/ti/ks2_evm/MAINTAINERS | 2 +
board/ti/ks2_evm/Makefile | 2 +
board/ti/ks2_evm/board_k2l.c | 72 ++
board/ti/ks2_evm/ddr3_cfg.c| 36 +
board/ti/ks2_evm/ddr3_cfg.h| 3 ++
board/ti/ks2_evm/ddr3_k2l.c| 38 ++
configs/k2l_evm_defconfig | 4 ++
include/configs/k2l_evm.h | 37 +
11 files changed, 219 insertions(+)
create mode 100644 board/ti/ks2_evm/board_k2l.c
create mode 100644 board/ti/ks2_evm/ddr3_k2l.c
create mode 100644 configs/k2l_evm_defconfig
create mode 100644 include/configs/k2l_evm.h
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig
b/arch/arm/cpu/armv7/keystone/Kconfig
index 24d0cbe..91211fd 100644
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ b/arch/arm/cpu/armv7/keystone/Kconfig
@@ -9,6 +9,9 @@ config TARGET_K2HK_EVM
config TARGET_K2E_EVM
bool TI Keystone 2 Edison EVM
+config TARGET_K2L_EVM
+ bool TI Keystone 2 Lamar EVM
+
endchoice
config SYS_CPU
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h
b/arch/arm/include/asm/arch-keystone/clock-k2l.h
index ad2e407..bb9a5c4 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h
@@ -70,7 +70,9 @@ enum {
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
@@ -79,8 +81,12 @@ enum {
#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1000{TETRIS_PLL, 114, 7, 2}
#define TETRIS_PLL_1167{TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1198{TETRIS_PLL, 39, 2, 2}
#define TETRIS_PLL_1228{TETRIS_PLL, 20, 1, 2}
+#define TETRIS_PLL_1352{TETRIS_PLL, 22, 1, 2}
+#define TETRIS_PLL_1401{TETRIS_PLL, 114, 5, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index 3108782..36c31ff 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -29,3 +29,19 @@ config SYS_CONFIG_NAME
default k2hk_evm
endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+ string
+ default ks2_evm
+
+config SYS_VENDOR
+ string
+ default ti
+
+config SYS_CONFIG_NAME
+ string
+ default k2l_evm
+
+endif
diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS
index 595a80a..87c36c9 100644
--- a/board/ti/ks2_evm/MAINTAINERS
+++ b/board/ti/ks2_evm/MAINTAINERS
@@ -6,3 +6,5 @@ F: include/configs/k2hk_evm.h
F: configs/k2hk_evm_defconfig
F: include/configs/k2e_evm.h
F: configs/k2e_evm_defconfig
+F: include/configs/k2l_evm.h
+F: configs/k2l_evm_defconfig
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 00f1164..071dbee 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
new file mode 100644
index 000..559d20c
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -0,0 +1,72 @@
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/ddr3.h
+#include asm/arch/hardware.h
+#include asm/ti-common/ti-aemif.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 12288,
+ [alt_core_clk] = 1,
+ [pa_clk]= 12288,
+ [tetris_clk]= 12288,
+ [ddr3_clk] = 1,
+ [pcie_clk] = 1,
+ [sgmii_clk] = 15625,
+ [usb_clk] = 1,
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_1000
Re: [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
On 10/20/2014 06:55 PM, Tom Rini wrote:
On Mon, Oct 20, 2014 at 06:41:29PM +0300, Ivan Khoronzhuk wrote:
On 10/20/2014 06:13 PM, Tom Rini wrote:
On Wed, Oct 15, 2014 at 02:55:28AM +0300, Ivan Khoronzhuk wrote:
From: Hao Zhang hzh...@ti.com
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
[snip]
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c
b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95b..9204887 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -72,6 +72,13 @@ U_BOOT_CMD(
pa|ddr3 mult div OD\n
);
#endif
+#ifdef CONFIG_SOC_K2L
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ set pll multiplier and pre divider,
+ pa|arm|ddr3 mult div OD\n
+);
+#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -101,6 +108,9 @@ U_BOOT_CMD(
#ifdef CONFIG_SOC_K2E
See the 'enum clk_e' in the clock-k2e.h for clk indexes\n
#endif
+#ifdef CONFIG_SOC_K2L
+ See the 'enum clk_e' in the clock-k2l.h for clk indexes\n
+#endif
);
I'm not going to block on all of this duplication, but we need to think
how to do this cleaner so that the next K2 variant doesn't expand this
mess further. Thanks!
I'll correct it to one line:
See the 'enum clk_e' in the clock-k2*.h for clk indexes\n
That helps the second hunk, but still leaves the first. At some point,
even, we shouldn't say go modify file foo in the binary, that belongs
in board documentation. Like I said, this needs a little bit of
thinking.
Tom,
the series is updated according to your propositions:
[U-boot] [Patch v6 0/6] keystone2: add k2l SoC and k2l_evm board support
https://www.mail-archive.com/u-boot@lists.denx.de/msg150727.html
It's based on patch that corrects command usage descriptions:
[U-Boot,U-boot] ARM: cmd_clock: generalize command usage description
http://patchwork.ozlabs.org/patch/402102/
I've sent it separately to not mix it with K2L support series.
Thanks!
--
Regards,
Ivan Khoronzhuk
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v4 2/4] soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations
From: Hao Zhang hzh...@ti.com
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 +
arch/arm/include/asm/arch-keystone/hardware.h | 3 +
drivers/soc/keystone/keystone_serdes.c | 166 +++--
include/configs/ks2_evm.h | 4 +
4 files changed, 94 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 706b21d..28de3f5 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -79,6 +79,9 @@
#define KS2_DDR3B_EMIF_DATA_BASE 0x6000
#define KS2_DDR3B_DDRPHYC 0x02328000
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 0441b29..6e2e939 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -177,6 +177,9 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES_BASE 0x0232a000
+
#ifdef CONFIG_SOC_K2HK
#include asm/arch/hardware-k2hk.h
#endif
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index dc4e78d..3632c22 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -9,92 +9,94 @@
#include common.h
+#define SERDES_LANE_REGS(x)(0x0200 + (0x200 * (x)))
+
+struct serdes_cfg {
+ u32 ofs;
+ u32 val;
+ u32 mask;
+};
+
+static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
+ {0x, 0x0080, 0x},
+ {0x0014, 0x8282, 0x},
+ {0x0060, 0x00142438, 0x00ff},
+ {0x0064, 0x00c3c700, 0x0000},
+ {0x0078, 0xc000, 0xff00}
+};
+
+static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
+ {0x0a00, 0x0800, 0xff00},
+ {0x0a08, 0x38a2, 0x},
+ {0x0a30, 0x008a8a00, 0x0000},
+ {0x0a84, 0x0600, 0xff00},
+ {0x0a94, 0x1000, 0xff00},
+ {0x0aa0, 0x8100, 0xff00},
+ {0x0abc, 0xff00, 0xff00},
+ {0x0ac0, 0x008b, 0x00ff},
+ {0x0b08, 0x583f, 0x},
+ {0x0b0c, 0x004e, 0x00ff}
+};
+
+static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
+ {0x0004, 0x3880, 0xffff},
+ {0x0008, 0x, 0x00ff},
+ {0x000c, 0x0200, 0xff00},
+ {0x0010, 0x1b00, 0xff00},
+ {0x0014, 0x6fb8, 0x},
+ {0x0018, 0x758000e4, 0x00ff},
+ {0x00ac, 0x4400, 0xff00},
+ {0x002c, 0x00100800, 0x0000},
+ {0x0080, 0x00820082, 0x00ff00ff},
+ {0x0084, 0x1d0f0385, 0x}
+
+};
+
+static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
+{
+ writel(((readl(addr) (~mask)) | (value mask)), addr);
+}
+
+static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
+{
+ u32 i;
+
+ for (i = 0; i size; i++)
+ ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
+}
+
+static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
+ u32 size, u32 lane)
+{
+ u32 i;
+
+ for (i = 0; i size; i++)
+ ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
+ cfg_lane[i].val, cfg_lane[i].mask);
+}
+
+static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
+{
+ u32 i;
+
+ ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g,
+ARRAY_SIZE(cfg_cmu_156p25m_5g));
+ ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g,
+ARRAY_SIZE(cfg_comlane_156p25m_5g));
+
+ for (i = 0; i num_lanes; i++)
+ ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g,
+ ARRAY_SIZE(cfg_lane_156p25mhz_5g), i);
+
+ return 0;
+}
+
void ks2_serdes_sgmii_156p25mhz_setup(void)
{
unsigned int cnt;
- /*
-* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-* hardware vendor published only register addresses and their values
-* to be used for configuring SerDes. So had to use hardcoded values
-* below.
-*/
- clrsetbits_le32(0x0232a000, 0x, 0x0080);
- clrsetbits_le32(0x0232a014, 0x, 0x8282);
- clrsetbits_le32(0x0232a060, 0x00ff, 0x00142438
[U-Boot] [U-boot] [Patch v4 0/4] keystone2: serdes: add seredes driver
This patch series adds serdes driver, moving it from keystone_net driver. Based on [U-boot] [Patch v2 0/5] keystone2: generalize keystone_net driver usage http://u-boot.10912.n7.nabble.com/U-boot-Patch-v2-0-5-keystone2-generalize- keystone-net-driver-usage-td190624.html v4..v3: - soc: keystone_serdes: create a separate SGMII SerDes driver squashed with soc: add soc specific drivers directory v3..v1: just rebase. Hao Zhang (2): soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations soc: keystone_serdes: generalize to be used by other sub systems Ivan Khoronzhuk (2): soc: keystone_serdes: create a separate SGMII SerDes driver soc: keystone_serdes: generalize configuration mechanism arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 + arch/arm/include/asm/arch-keystone/hardware.h | 3 + arch/arm/include/asm/ti-common/keystone_serdes.h | 55 ++ drivers/Makefile | 2 + drivers/net/keystone_net.c | 154 ++- drivers/soc/Makefile | 5 + drivers/soc/keystone/Makefile | 1 + drivers/soc/keystone/keystone_serdes.c | 210 + include/configs/k2hk_evm.h | 3 + include/configs/ks2_evm.h | 6 +- 10 files changed, 303 insertions(+), 139 deletions(-) create mode 100644 arch/arm/include/asm/ti-common/keystone_serdes.h create mode 100644 drivers/soc/Makefile create mode 100644 drivers/soc/keystone/Makefile create mode 100644 drivers/soc/keystone/keystone_serdes.c -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v4 4/4] soc: keystone_serdes: generalize configuration mechanism
The cmu, comlane, lane configuration mechanism are similar for sub
systems as well such as PCI or sRIO, but they have different values
based on input clock and output bus rate. According to this compact
driver to simplify adding different configuration settings based
on clock and rate.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/soc/keystone/keystone_serdes.c | 112 +++--
1 file changed, 65 insertions(+), 47 deletions(-)
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index 84ed9ba..dd5eac9 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -29,12 +29,24 @@
#define SERDES_LANE_LOOPBACK BIT(30)
#define SERDES_LANE_EN_VAL(x, y, z)(x[y] | (z 26) | (z 10))
+#define SERDES_CMU_CFG_NUM 5
+#define SERDES_COMLANE_CFG_NUM 10
+#define SERDES_LANE_CFG_NUM10
+
struct serdes_cfg {
u32 ofs;
u32 val;
u32 mask;
};
+struct cfg_entry {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
+ struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
+ struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
+};
+
/* SERDES PHY lane enable configuration value, indexed by PHY interface */
static u32 serdes_cfg_lane_enable[] = {
0xf000f0c0, /* SGMII */
@@ -47,39 +59,46 @@ static u32 serdes_cfg_pll_enable[] = {
0xee00, /* PCSR */
};
-static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
- {0x, 0x0080, 0x},
- {0x0014, 0x8282, 0x},
- {0x0060, 0x00142438, 0x00ff},
- {0x0064, 0x00c3c700, 0x0000},
- {0x0078, 0xc000, 0xff00}
-};
-
-static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
- {0x0a00, 0x0800, 0xff00},
- {0x0a08, 0x38a2, 0x},
- {0x0a30, 0x008a8a00, 0x0000},
- {0x0a84, 0x0600, 0xff00},
- {0x0a94, 0x1000, 0xff00},
- {0x0aa0, 0x8100, 0xff00},
- {0x0abc, 0xff00, 0xff00},
- {0x0ac0, 0x008b, 0x00ff},
- {0x0b08, 0x583f, 0x},
- {0x0b0c, 0x004e, 0x00ff}
-};
-
-static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
- {0x0004, 0x3880, 0xffff},
- {0x0008, 0x, 0x00ff},
- {0x000c, 0x0200, 0xff00},
- {0x0010, 0x1b00, 0xff00},
- {0x0014, 0x6fb8, 0x},
- {0x0018, 0x758000e4, 0x00ff},
- {0x00ac, 0x4400, 0xff00},
- {0x002c, 0x00100800, 0x0000},
- {0x0080, 0x00820082, 0x00ff00ff},
- {0x0084, 0x1d0f0385, 0x}
-
+/**
+ * Array to hold all possible serdes configurations.
+ * Combination for 5 clock settings and 6 baud rates.
+ */
+static struct cfg_entry cfgs[] = {
+ {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .cmu = {
+ {0x, 0x0080, 0x},
+ {0x0014, 0x8282, 0x},
+ {0x0060, 0x00142438, 0x00ff},
+ {0x0064, 0x00c3c700, 0x0000},
+ {0x0078, 0xc000, 0xff00}
+ },
+ .comlane = {
+ {0x0a00, 0x0800, 0xff00},
+ {0x0a08, 0x38a2, 0x},
+ {0x0a30, 0x008a8a00, 0x0000},
+ {0x0a84, 0x0600, 0xff00},
+ {0x0a94, 0x1000, 0xff00},
+ {0x0aa0, 0x8100, 0xff00},
+ {0x0abc, 0xff00, 0xff00},
+ {0x0ac0, 0x008b, 0x00ff},
+ {0x0b08, 0x583f, 0x},
+ {0x0b0c, 0x004e, 0x00ff}
+ },
+ .lane = {
+ {0x0004, 0x3880, 0xffff},
+ {0x0008, 0x, 0x00ff},
+ {0x000c, 0x0200, 0xff00},
+ {0x0010, 0x1b00, 0xff00},
+ {0x0014, 0x6fb8, 0x},
+ {0x0018, 0x758000e4, 0x00ff},
+ {0x00ac, 0x4400, 0xff00},
+ {0x002c, 0x00100800, 0x0000},
+ {0x0080, 0x00820082, 0x00ff00ff},
+ {0x0084, 0x1d0f0385, 0x}
+ },
+ },
};
static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
@@ -105,18 +124,15 @@ static void ks2_serdes_lane_config(u32 base, struct
serdes_cfg *cfg_lane,
cfg_lane[i].val, cfg_lane[i].mask);
}
-static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
+static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32
[U-Boot] [U-boot] [Patch v4 3/4] soc: keystone_serdes: generalize to be used by other sub systems
From: Hao Zhang hzh...@ti.com
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/keystone_serdes.h | 42 +++-
drivers/net/keystone_net.c | 15 ++-
drivers/soc/keystone/keystone_serdes.c | 131 +--
include/configs/ks2_evm.h| 10 +-
4 files changed, 156 insertions(+), 42 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h
b/arch/arm/include/asm/ti-common/keystone_serdes.h
index 2e12b05..2e92411 100644
--- a/arch/arm/include/asm/ti-common/keystone_serdes.h
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -10,6 +10,46 @@
#ifndef __TI_KEYSTONE_SERDES_H__
#define __TI_KEYSTONE_SERDES_H__
-void ks2_serdes_sgmii_156p25mhz_setup(void);
+/* SERDES Reference clock */
+enum ks2_serdes_clock {
+ SERDES_CLOCK_100M, /* 100 MHz */
+ SERDES_CLOCK_122P88M, /* 122.88 MHz */
+ SERDES_CLOCK_125M, /* 125 MHz */
+ SERDES_CLOCK_156P25M, /* 156.25 MHz */
+ SERDES_CLOCK_312P5M,/* 312.5 MHz */
+};
+
+/* SERDES Lane Baud Rate */
+enum ks2_serdes_rate {
+ SERDES_RATE_4P9152G,/* 4.9152 GBaud */
+ SERDES_RATE_5G, /* 5 GBaud */
+ SERDES_RATE_6P144G, /* 6.144 GBaud */
+ SERDES_RATE_6P25G, /* 6.25 GBaud */
+ SERDES_RATE_10p3125g, /* 10.3215 GBaud */
+ SERDES_RATE_12p5g, /* 12.5 GBaud */
+};
+
+/* SERDES Lane Rate Mode */
+enum ks2_serdes_rate_mode {
+ SERDES_FULL_RATE,
+ SERDES_HALF_RATE,
+ SERDES_QUARTER_RATE,
+};
+
+/* SERDES PHY TYPE */
+enum ks2_serdes_interface {
+ SERDES_PHY_SGMII,
+ SERDES_PHY_PCSR,/* XGE SERDES */
+};
+
+struct ks2_serdes {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ enum ks2_serdes_rate_mode rate_mode;
+ enum ks2_serdes_interface intf;
+ u32 loopback;
+};
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 63f3361..8a45fbd 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -554,7 +554,20 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
return 0;
}
+struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .rate_mode = SERDES_QUARTER_RATE,
+ .intf = SERDES_PHY_SGMII,
+ .loopback = 0,
+};
+
static void keystone2_net_serdes_setup(void)
{
- ks2_serdes_sgmii_156p25mhz_setup();
+ ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
+ ks2_serdes_sgmii_156p25mhz,
+ CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+
+ /* wait till setup */
+ udelay(5000);
}
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index 3632c22..84ed9ba 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -7,9 +7,27 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include errno.h
#include common.h
+#include asm/ti-common/keystone_serdes.h
+#define SERDES_CMU_REGS(x) (0x + (0x0c00 * (x)))
#define SERDES_LANE_REGS(x)(0x0200 + (0x200 * (x)))
+#define SERDES_COMLANE_REGS0x0a00
+#define SERDES_WIZ_REGS0x1fc0
+
+#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
+#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
+#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
+#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
+#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
+#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
+#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
+
+#define SERDES_RESET BIT(28)
+#define SERDES_LANE_RESET BIT(29)
+#define SERDES_LANE_LOOPBACK BIT(30)
+#define SERDES_LANE_EN_VAL(x, y, z)(x[y] | (z 26) | (z 10))
struct serdes_cfg {
u32 ofs;
@@ -17,6 +35,18 @@ struct serdes_cfg {
u32 mask;
};
+/* SERDES PHY lane enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_lane_enable[] = {
+ 0xf000f0c0, /* SGMII */
+ 0xf0e9f038, /* PCSR */
+};
+
+/* SERDES PHY PLL enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_pll_enable[] = {
+ 0xe000, /* SGMII */
+ 0xee00, /* PCSR
[U-Boot] [U-boot] [Patch v4 1/4] soc: keystone_serdes: create a separate SGMII SerDes driver
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.
Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/keystone_serdes.h | 15 +++
drivers/Makefile | 2 +
drivers/net/keystone_net.c | 143 +--
drivers/soc/Makefile | 5 +
drivers/soc/keystone/Makefile| 1 +
drivers/soc/keystone/keystone_serdes.c | 127
include/configs/k2hk_evm.h | 3 +
7 files changed, 158 insertions(+), 138 deletions(-)
create mode 100644 arch/arm/include/asm/ti-common/keystone_serdes.h
create mode 100644 drivers/soc/Makefile
create mode 100644 drivers/soc/keystone/Makefile
create mode 100644 drivers/soc/keystone/keystone_serdes.c
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h
b/arch/arm/include/asm/ti-common/keystone_serdes.h
new file mode 100644
index 000..2e12b05
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -0,0 +1,15 @@
+/*
+ * Texas Instruments Keystone SerDes driver
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TI_KEYSTONE_SERDES_H__
+#define __TI_KEYSTONE_SERDES_H__
+
+void ks2_serdes_sgmii_156p25mhz_setup(void);
+
+#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/drivers/Makefile b/drivers/Makefile
index b22b109..fc9b630 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,3 +16,5 @@ obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
obj-y += memory/
obj-y += pwm/
+# SOC specific infrastructure drivers.
+obj-y += soc/
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 33197f9..63f3361 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -14,6 +14,7 @@
#include malloc.h
#include asm/ti-common/keystone_nav.h
#include asm/ti-common/keystone_net.h
+#include asm/ti-common/keystone_serdes.h
unsigned int emac_open;
static unsigned int sys_has_mdio = 1;
@@ -38,6 +39,7 @@ struct rx_buff_desc net_rx_buffs = {
};
static void keystone2_eth_mdio_enable(void);
+static void keystone2_net_serdes_setup(void);
static int gen_get_link_speed(int phy_addr);
@@ -406,7 +408,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
sys_has_mdio =
(eth_priv-sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
- sgmii_serdes_setup_156p25mhz();
+ keystone2_net_serdes_setup();
if (sys_has_mdio)
keystone2_eth_mdio_enable();
@@ -552,142 +554,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
return 0;
}
-void sgmii_serdes_setup_156p25mhz(void)
+static void keystone2_net_serdes_setup(void)
{
- unsigned int cnt;
-
- /*
-* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-* hardware vendor published only register addresses and their values
-* to be used for configuring SerDes. So had to use hardcoded values
-* below.
-*/
- clrsetbits_le32(0x0232a000, 0x, 0x0080);
- clrsetbits_le32(0x0232a014, 0x, 0x8282);
- clrsetbits_le32(0x0232a060, 0x00ff, 0x00142438);
- clrsetbits_le32(0x0232a064, 0x0000, 0x00c3c700);
- clrsetbits_le32(0x0232a078, 0xff00, 0xc000);
-
- clrsetbits_le32(0x0232a204, 0xffff, 0x3880);
- clrsetbits_le32(0x0232a208, 0x00ff, 0x);
- clrsetbits_le32(0x0232a20c, 0xff00, 0x0200);
- clrsetbits_le32(0x0232a210, 0xff00, 0x1b00);
- clrsetbits_le32(0x0232a214, 0x, 0x6fb8);
- clrsetbits_le32(0x0232a218, 0x00ff, 0x758000e4);
- clrsetbits_le32(0x0232a2ac, 0xff00, 0x4400);
- clrsetbits_le32(0x0232a22c, 0x0000, 0x00200800);
- clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a284, 0x, 0x1d0f0385);
-
- clrsetbits_le32(0x0232a404, 0xffff, 0x3880);
- clrsetbits_le32(0x0232a408, 0x00ff, 0x);
- clrsetbits_le32(0x0232a40c, 0xff00, 0x0200);
- clrsetbits_le32(0x0232a410, 0xff00, 0x1b00);
- clrsetbits_le32(0x0232a414, 0x, 0x6fb8);
- clrsetbits_le32(0x0232a418, 0x00ff, 0x758000e4);
- clrsetbits_le32(0x0232a4ac, 0xff00, 0x4400);
- clrsetbits_le32(0x0232a42c, 0x0000, 0x00200800);
- clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a484, 0x, 0x1d0f0385
[U-Boot] [U-boot] [Patch v3 2/4] ARM: keystone: msmc: extend functionality of SES
From: Vitaly Andrianov vita...@ti.com
Add functions to set/get SES PMAX values of Pivilege ID pair.
Also add msmc module definitions.
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/msmc.c| 26 +
arch/arm/include/asm/arch-keystone/hardware.h | 6 ++
arch/arm/include/asm/arch-keystone/msmc.h | 28 +++
3 files changed, 60 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c
b/arch/arm/cpu/armv7/keystone/msmc.c
index 7d8e597..7899141 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -66,3 +66,29 @@ void msmc_share_all_segments(int priv_id)
msmc-ses[priv_id][j].mpaxh = 0xff7ful;
}
}
+
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc-ses[priv_id][ses_pair].mpaxh = src_pfn 12 |
+(size 0x1f) | 0x80;
+ msmc-ses[priv_id][ses_pair].mpaxl = dst_pfn 8 | 0x3f;
+}
+
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ *mpax++ = msmc-ses[priv_id][ses_pair].mpaxl;
+ *mpax = msmc-ses[priv_id][ses_pair].mpaxh;
+}
+
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc-ses[priv_id][ses_pair].mpaxl = *mpax++;
+ msmc-ses[priv_id][ses_pair].mpaxh = *mpax;
+}
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 6e2e939..8e0b879 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -148,6 +148,12 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_MSMC_SEGMENT_QM_PDSP 10
#define KS2_MSMC_SEGMENT_PCIE0 11
+/* MSMC segment size shift bits */
+#define KS2_MSMC_SEG_SIZE_SHIFT12
+#define KS2_MSMC_MAP_SEG_NUM (2 (30 - KS2_MSMC_SEG_SIZE_SHIFT))
+#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE \
+ KS2_MSMC_SEG_SIZE_SHIFT)
+
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h
b/arch/arm/include/asm/arch-keystone/msmc.h
index c320db5..083f5ba 100644
--- a/arch/arm/include/asm/arch-keystone/msmc.h
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -12,6 +12,34 @@
#include asm/arch/hardware.h
+enum mpax_seg_size {
+ MPAX_SEG_4K = 0x0b,
+ MPAX_SEG_8K,
+ MPAX_SEG_16K,
+ MPAX_SEG_32K,
+ MPAX_SEG_64K,
+ MPAX_SEG_128K,
+ MPAX_SEG_256K,
+ MPAX_SEG_512K,
+ MPAX_SEG_1M,
+ MPAX_SEG_2M,
+ MPAX_SEG_4M,
+ MPAX_SEG_8M,
+ MPAX_SEG_16M,
+ MPAX_SEG_32M,
+ MPAX_SEG_64M,
+ MPAX_SEG_128M,
+ MPAX_SEG_256M,
+ MPAX_SEG_512M,
+ MPAX_SEG_1G,
+ MPAX_SEG_2G,
+ MPAX_SEG_4G
+};
+
void msmc_share_all_segments(int priv_id);
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
#endif
--
1.8.3.2
___
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U-Boot@lists.denx.de
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[U-Boot] [U-boot] [Patch v3 0/4] keystone2: ecc: add ddr3 error detection and correction support
This series adds DDR3 ECC support to enable ECC in the DDR3 EMIF controller for Keystone II devices. Based on [U-boot] [Patch v2 0/6] keystone2: add network support for K2E SoC and EVM https://www.mail-archive.com/u-boot@lists.denx.de/msg150359.html v3..v2: - ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr corrected due to some applying warnings. v2..v1: nothing changed, just rebase Hao Zhang (1): ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr Ivan Khoronzhuk (1): dma: ti-edma3: introduce edma3 driver Vitaly Andrianov (2): ARM: keystone: msmc: extend functionality of SES keystone2: ecc: add ddr3 error detection and correction support arch/arm/cpu/armv7/keystone/Makefile | 2 +- arch/arm/cpu/armv7/keystone/cmd_ddr3.c | 248 + arch/arm/cpu/armv7/keystone/ddr3.c | 244 + arch/arm/cpu/armv7/keystone/msmc.c | 26 ++ arch/arm/include/asm/arch-keystone/ddr3.h | 6 + arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 4 + arch/arm/include/asm/arch-keystone/hardware.h | 52 +++ arch/arm/include/asm/arch-keystone/msmc.h | 28 ++ arch/arm/include/asm/ti-common/ti-edma3.h | 121 +++ board/ti/ks2_evm/board.c | 3 + board/ti/ks2_evm/ddr3_k2hk.c | 16 + drivers/dma/Makefile | 1 + drivers/dma/ti-edma3.c | 384 + include/configs/ks2_evm.h | 4 - 14 files changed, 1134 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/cmd_ddr3.c create mode 100644 arch/arm/include/asm/ti-common/ti-edma3.h create mode 100644 drivers/dma/ti-edma3.c -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v3 3/4] keystone2: ecc: add ddr3 error detection and correction support
From: Vitaly Andrianov vita...@ti.com
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.
An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/ddr3.c | 244 +
arch/arm/include/asm/arch-keystone/ddr3.h | 6 +
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 4 +
arch/arm/include/asm/arch-keystone/hardware.h | 46
board/ti/ks2_evm/board.c | 3 +
board/ti/ks2_evm/ddr3_k2hk.c | 16 ++
6 files changed, 319 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 2eabec1..923906a 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -9,9 +9,19 @@
#include asm/io.h
#include common.h
+#include asm/arch/msmc.h
#include asm/arch/ddr3.h
#include asm/arch/psc_defs.h
+#include asm/ti-common/ti-edma3.h
+
+#define DDR3_EDMA_BLK_SIZE_SHIFT 10
+#define DDR3_EDMA_BLK_SIZE (1 DDR3_EDMA_BLK_SIZE_SHIFT)
+#define DDR3_EDMA_BCNT 0x8000
+#define DDR3_EDMA_CCNT 1
+#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
+#define DDR3_EDMA_SLOT_NUM 1
+
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@@ -70,6 +80,240 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config
*emif_cfg)
__raw_writel(emif_cfg-sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
+int ddr3_ecc_support_rmw(u32 base)
+{
+ u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
+
+ /* Check the DDR3 controller ID reg if the controllers
+ supports ECC RMW or not */
+ if (value == 0x40461C02)
+ return 1;
+
+ return 0;
+}
+
+static void ddr3_ecc_config(u32 base, u32 value)
+{
+ u32 data;
+
+ __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
+ udelay(10); /* delay required to synchronize across clock domains */
+
+ if (value KS2_DDR3_ECC_EN) {
+ /* Clear the 1-bit error count */
+ data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+ __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+
+ /* enable the ECC interrupt */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+KS2_DDR3_WR_ECC_ERR_SYS,
+base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
+
+ /* Clear the ECC error interrupt status */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+KS2_DDR3_WR_ECC_ERR_SYS,
+base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+ }
+}
+
+static void ddr3_reset_data(u32 base, u32 ddr3_size)
+{
+ u32 mpax[2];
+ u32 seg_num;
+ u32 seg, blks, dst, edma_blks;
+ struct edma3_slot_config slot;
+ struct edma3_channel_config edma_channel;
+ u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
+
+ /* Setup an edma to copy the 1k block to the entire DDR */
+ puts(\nClear entire DDR3 memory to enable ECC\n);
+
+ /* save the SES MPAX regs */
+ msmc_get_ses_mpax(8, 0, mpax);
+
+ /* setup edma slot 1 configuration */
+ slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+ EDMA3_SLOPT_COMP_CODE(0) |
+ EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+ slot.bcnt = DDR3_EDMA_BCNT;
+ slot.acnt = DDR3_EDMA_BLK_SIZE;
+ slot.ccnt = DDR3_EDMA_CCNT;
+ slot.src_bidx = 0;
+ slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
+ slot.src_cidx = 0;
+ slot.dst_cidx = 0;
+ slot.link = EDMA3_PARSET_NULL_LINK;
+ slot.bcntrld = 0;
+ edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, slot);
+
+ /* configure quik edma channel */
+ edma_channel.slot = DDR3_EDMA_SLOT_NUM;
+ edma_channel.chnum = 0;
+ edma_channel.complete_code = 0;
+ /* event trigger after dst update */
+ edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+ qedma3_start(KS2_EDMA0_BASE, edma_channel);
+
+ /* DDR3 size in segments (4KB seg size) */
+ seg_num = ddr3_size (30 - KS2_MSMC_SEG_SIZE_SHIFT
[U-Boot] [U-boot] [Patch v3 4/4] ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr
From: Hao Zhang hzh...@ti.com
Add ddr3 commands:
test start_addr in hex end_addr in hex - test DDR from start\n
address to end address\n
ddr compare start_addr in hex end_addr in hex size in hex -\n
compare DDR data of (size) bytes from start address to end
address\n
ddr ecc_err addr in hex bit_err in hex - generate bit errors\n
in DDR data at addr, the command will read a 32-bit data\n
from addr, and write (data ^ bit_err) back to addr\n
Delete CONFIG_MAX_UBOOT_MEM_SIZE, as it was supposed to be used
for ddr3 commands and for now it's not needed any more.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 2 +-
arch/arm/cpu/armv7/keystone/cmd_ddr3.c | 248 +
include/configs/ks2_evm.h | 4 -
3 files changed, 249 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/cpu/armv7/keystone/cmd_ddr3.c
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 57f6ea6..ed030db 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -14,5 +14,5 @@ obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
-obj-y += ddr3.o
+obj-y += ddr3.o cmd_ddr3.o
obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
new file mode 100644
index 000..ea78ad8
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
@@ -0,0 +1,248 @@
+/*
+ * Keystone2: DDR3 test commands
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include asm/arch/hardware.h
+#include asm/arch/ddr3.h
+#include common.h
+#include command.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define DDR_REMAP_ADDR 0x8000
+#define ECC_START_ADDR1((DDR_MIN_ADDR - DDR_REMAP_ADDR) 17)
+
+#define ECC_END_ADDR1 (((gd-start_addr_sp - DDR_REMAP_ADDR - \
+CONFIG_STACKSIZE) 17) - 2)
+
+#define DDR_TEST_BURST_SIZE1024
+
+static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
+{
+ u32 index_start, value, index;
+
+ index_start = start_address;
+
+ while (1) {
+ /* Write a pattern */
+ for (index = index_start;
+ index index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel(index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != index) {
+ printf(ddr_memory_test: Failed at address
index = 0x%x value = 0x%x *(index) = 0x%x\n,
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start = end_address)
+ break;
+
+ if (quick)
+ continue;
+
+ /* Write a pattern for complementary values */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 4)
+ __raw_writel((u32)~index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 4) {
+ value = __raw_readl(index);
+ if (value != ~index) {
+ printf(ddr_memory_test: Failed at address
index = 0x%x value = 0x%x *(index) = 0x%x\n,
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start = end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 2)
+ __raw_writew((u16)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 2) {
+ value = __raw_readw(index);
+ if (value != (u16)index
[U-Boot] [U-boot] [Patch v3 1/4] dma: ti-edma3: introduce edma3 driver
The EDMA3 controller’s primary purpose is to service data transfers
that you program between two memory-mapped slave endpoints on the device.
Typical usage includes, but is not limited to the following:
- Servicing software-driven paging transfers (e.g., transfers from external
memory, such as SDRAM to internal device memory, such as DSP L2 SRAM)
- Servicing event-driven peripherals, such as a serial port
- Performing sorting or sub-frame extraction of various data structures
- Offloading data transfers from the main device DSP(s)
- See the device-specific data manual for specific peripherals that are
accessible via the EDMA3 controller
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/ti-edma3.h | 121 ++
drivers/dma/Makefile | 1 +
drivers/dma/ti-edma3.c| 384 ++
3 files changed, 506 insertions(+)
create mode 100644 arch/arm/include/asm/ti-common/ti-edma3.h
create mode 100644 drivers/dma/ti-edma3.c
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h
b/arch/arm/include/asm/ti-common/ti-edma3.h
new file mode 100644
index 000..5adc1da
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -0,0 +1,121 @@
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EDMA3_H_
+#define _EDMA3_H_
+
+#include linux/stddef.h
+
+#define EDMA3_PARSET_NULL_LINK 0x
+
+/*
+ * All parameter RAM set options
+ * opt field in edma3_param_set_config structure
+ */
+#define EDMA3_SLOPT_PRIV_LEVEL BIT(31)
+#define EDMA3_SLOPT_PRIV_ID(id)((0xf (id)) 24)
+#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23)
+#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22)
+#define EDMA3_SLOPT_INTERM_COMP_INT_ENBBIT(21)
+#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20)
+#define EDMA3_SLOPT_COMP_CODE(code)((0x3f (code)) 12)
+#define EDMA3_SLOPT_FIFO_WIDTH_8 0
+#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w 0x7) 8)
+#define EDMA3_SLOPT_STATIC BIT(3)
+#define EDMA3_SLOPT_AB_SYNCBIT(2)
+#define EDMA3_SLOPT_DST_ADDR_CONST_MODEBIT(1)
+#define EDMA3_SLOPT_SRC_ADDR_CONST_MODEBIT(0)
+
+enum edma3_address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum edma3_fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum edma3_sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+/* PaRAM slots are laid out like this */
+struct edma3_slot_layout {
+ u32 opt;
+ u32 src;
+ u32 a_b_cnt;
+ u32 dst;
+ u32 src_dst_bidx;
+ u32 link_bcntrld;
+ u32 src_dst_cidx;
+ u32 ccnt;
+} __packed;
+
+/*
+ * Use this to assign trigger word number of edma3_slot_layout struct.
+ * trigger_word_name - is the exact name from edma3_slot_layout.
+ */
+#define EDMA3_TWORD(trigger_word_name)\
+ (offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
+
+struct edma3_slot_config {
+ u32 opt;
+ u32 src;
+ u32 dst;
+ int bcnt;
+ int acnt;
+ int ccnt;
+ int src_bidx;
+ int dst_bidx;
+ int src_cidx;
+ int dst_cidx;
+ int bcntrld;
+ int link;
+};
+
+struct edma3_channel_config {
+ int slot;
+ int chnum;
+ int complete_code; /* indicate pending complete interrupt */
+ int trigger_slot_word; /* only used for qedma */
+};
+
+void qedma3_start(u32 base, struct edma3_channel_config *cfg);
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
+
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_dest_addr(u32 base, int slot, u32 dst);
+
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_src_addr(u32 base, int slot, u32 src);
+
+void edma3_set_transfer_params
Re: [U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
On 10/20/2014 06:13 PM, Tom Rini wrote: On Wed, Oct 15, 2014 at 02:55:29AM +0300, Ivan Khoronzhuk wrote: From: Hao Zhang hzh...@ti.com This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Hao Zhang hzh...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/cpu/armv7/keystone/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index a8f8aee..a0ecfa2 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -32,6 +32,9 @@ int arch_cpu_init(void) #ifdef CONFIG_SOC_K2E msmc_share_all_segments(13); /* PCIE 1 */ #endif +#ifdef CONFIG_SOC_K2L + msmc_share_all_segments(14); /* PCIE 1 */ +#endif /* * just initialise the COM2 port so that TI specific Where does 13/14 come from and can we just define what that means in a K2-foo specific header so we can always do msmc_share_all_segments(K2_MSMC_SEGMENTS_NR) or whatever? Thanks! Ok, I will update it. But, currently, there is newer version, [U-boot] [Patch v5 0/6] keystone2: add k2l SoC and k2l_evm board support https://www.mail-archive.com/u-boot@lists.denx.de/msg150245.html -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
On 10/20/2014 06:13 PM, Tom Rini wrote:
On Wed, Oct 15, 2014 at 02:55:28AM +0300, Ivan Khoronzhuk wrote:
From: Hao Zhang hzh...@ti.com
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
[snip]
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c
b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95b..9204887 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -72,6 +72,13 @@ U_BOOT_CMD(
pa|ddr3 mult div OD\n
);
#endif
+#ifdef CONFIG_SOC_K2L
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ set pll multiplier and pre divider,
+ pa|arm|ddr3 mult div OD\n
+);
+#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -101,6 +108,9 @@ U_BOOT_CMD(
#ifdef CONFIG_SOC_K2E
See the 'enum clk_e' in the clock-k2e.h for clk indexes\n
#endif
+#ifdef CONFIG_SOC_K2L
+ See the 'enum clk_e' in the clock-k2l.h for clk indexes\n
+#endif
);
I'm not going to block on all of this duplication, but we need to think
how to do this cleaner so that the next K2 variant doesn't expand this
mess further. Thanks!
I'll correct it to one line:
See the 'enum clk_e' in the clock-k2*.h for clk indexes\n
--
Regards,
Ivan Khoronzhuk
___
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U-Boot@lists.denx.de
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[U-Boot] [U-boot] [Patch v3 1/5] soc: add soc specific drivers directory
Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/Makefile | 2 ++ drivers/soc/Makefile | 3 +++ 2 files changed, 5 insertions(+) create mode 100644 drivers/soc/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index b22b109..fc9b630 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -16,3 +16,5 @@ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ obj-y += memory/ obj-y += pwm/ +# SOC specific infrastructure drivers. +obj-y += soc/ diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile new file mode 100644 index 000..1746cd8 --- /dev/null +++ b/drivers/soc/Makefile @@ -0,0 +1,3 @@ +# +# Makefile for the u-boot SOC specific device drivers. +# -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v3 2/5] soc: keystone_serdes: create a separate SGMII SerDes driver
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/keystone_serdes.h | 15 +++
drivers/net/keystone_net.c | 143 +--
drivers/soc/Makefile | 4 +-
drivers/soc/keystone/Makefile| 1 +
drivers/soc/keystone/keystone_serdes.c | 127
include/configs/k2hk_evm.h | 3 +
6 files changed, 154 insertions(+), 139 deletions(-)
create mode 100644 arch/arm/include/asm/ti-common/keystone_serdes.h
create mode 100644 drivers/soc/keystone/Makefile
create mode 100644 drivers/soc/keystone/keystone_serdes.c
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h
b/arch/arm/include/asm/ti-common/keystone_serdes.h
new file mode 100644
index 000..2e12b05
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -0,0 +1,15 @@
+/*
+ * Texas Instruments Keystone SerDes driver
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TI_KEYSTONE_SERDES_H__
+#define __TI_KEYSTONE_SERDES_H__
+
+void ks2_serdes_sgmii_156p25mhz_setup(void);
+
+#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 33197f9..63f3361 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -14,6 +14,7 @@
#include malloc.h
#include asm/ti-common/keystone_nav.h
#include asm/ti-common/keystone_net.h
+#include asm/ti-common/keystone_serdes.h
unsigned int emac_open;
static unsigned int sys_has_mdio = 1;
@@ -38,6 +39,7 @@ struct rx_buff_desc net_rx_buffs = {
};
static void keystone2_eth_mdio_enable(void);
+static void keystone2_net_serdes_setup(void);
static int gen_get_link_speed(int phy_addr);
@@ -406,7 +408,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
sys_has_mdio =
(eth_priv-sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
- sgmii_serdes_setup_156p25mhz();
+ keystone2_net_serdes_setup();
if (sys_has_mdio)
keystone2_eth_mdio_enable();
@@ -552,142 +554,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
return 0;
}
-void sgmii_serdes_setup_156p25mhz(void)
+static void keystone2_net_serdes_setup(void)
{
- unsigned int cnt;
-
- /*
-* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-* hardware vendor published only register addresses and their values
-* to be used for configuring SerDes. So had to use hardcoded values
-* below.
-*/
- clrsetbits_le32(0x0232a000, 0x, 0x0080);
- clrsetbits_le32(0x0232a014, 0x, 0x8282);
- clrsetbits_le32(0x0232a060, 0x00ff, 0x00142438);
- clrsetbits_le32(0x0232a064, 0x0000, 0x00c3c700);
- clrsetbits_le32(0x0232a078, 0xff00, 0xc000);
-
- clrsetbits_le32(0x0232a204, 0xffff, 0x3880);
- clrsetbits_le32(0x0232a208, 0x00ff, 0x);
- clrsetbits_le32(0x0232a20c, 0xff00, 0x0200);
- clrsetbits_le32(0x0232a210, 0xff00, 0x1b00);
- clrsetbits_le32(0x0232a214, 0x, 0x6fb8);
- clrsetbits_le32(0x0232a218, 0x00ff, 0x758000e4);
- clrsetbits_le32(0x0232a2ac, 0xff00, 0x4400);
- clrsetbits_le32(0x0232a22c, 0x0000, 0x00200800);
- clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a284, 0x, 0x1d0f0385);
-
- clrsetbits_le32(0x0232a404, 0xffff, 0x3880);
- clrsetbits_le32(0x0232a408, 0x00ff, 0x);
- clrsetbits_le32(0x0232a40c, 0xff00, 0x0200);
- clrsetbits_le32(0x0232a410, 0xff00, 0x1b00);
- clrsetbits_le32(0x0232a414, 0x, 0x6fb8);
- clrsetbits_le32(0x0232a418, 0x00ff, 0x758000e4);
- clrsetbits_le32(0x0232a4ac, 0xff00, 0x4400);
- clrsetbits_le32(0x0232a42c, 0x0000, 0x00200800);
- clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a484, 0x, 0x1d0f0385);
-
- clrsetbits_le32(0x0232a604, 0xffff, 0x3880);
- clrsetbits_le32(0x0232a608, 0x00ff, 0x);
- clrsetbits_le32(0x0232a60c, 0xff00, 0x0200);
- clrsetbits_le32(0x0232a610, 0xff00, 0x1b00);
- clrsetbits_le32(0x0232a614, 0x, 0x6fb8);
- clrsetbits_le32(0x0232a618, 0x00ff, 0x758000e4);
- clrsetbits_le32(0x0232a6ac, 0xff00, 0x4400);
- clrsetbits_le32(0x0232a62c, 0x0000, 0x00200800
[U-Boot] [U-boot] [Patch v3 4/5] soc: keystone_serdes: generalize to be used by other sub systems
From: Hao Zhang hzh...@ti.com
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/keystone_serdes.h | 42 +++-
drivers/net/keystone_net.c | 15 ++-
drivers/soc/keystone/keystone_serdes.c | 131 +--
include/configs/ks2_evm.h| 10 +-
4 files changed, 156 insertions(+), 42 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h
b/arch/arm/include/asm/ti-common/keystone_serdes.h
index 2e12b05..2e92411 100644
--- a/arch/arm/include/asm/ti-common/keystone_serdes.h
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -10,6 +10,46 @@
#ifndef __TI_KEYSTONE_SERDES_H__
#define __TI_KEYSTONE_SERDES_H__
-void ks2_serdes_sgmii_156p25mhz_setup(void);
+/* SERDES Reference clock */
+enum ks2_serdes_clock {
+ SERDES_CLOCK_100M, /* 100 MHz */
+ SERDES_CLOCK_122P88M, /* 122.88 MHz */
+ SERDES_CLOCK_125M, /* 125 MHz */
+ SERDES_CLOCK_156P25M, /* 156.25 MHz */
+ SERDES_CLOCK_312P5M,/* 312.5 MHz */
+};
+
+/* SERDES Lane Baud Rate */
+enum ks2_serdes_rate {
+ SERDES_RATE_4P9152G,/* 4.9152 GBaud */
+ SERDES_RATE_5G, /* 5 GBaud */
+ SERDES_RATE_6P144G, /* 6.144 GBaud */
+ SERDES_RATE_6P25G, /* 6.25 GBaud */
+ SERDES_RATE_10p3125g, /* 10.3215 GBaud */
+ SERDES_RATE_12p5g, /* 12.5 GBaud */
+};
+
+/* SERDES Lane Rate Mode */
+enum ks2_serdes_rate_mode {
+ SERDES_FULL_RATE,
+ SERDES_HALF_RATE,
+ SERDES_QUARTER_RATE,
+};
+
+/* SERDES PHY TYPE */
+enum ks2_serdes_interface {
+ SERDES_PHY_SGMII,
+ SERDES_PHY_PCSR,/* XGE SERDES */
+};
+
+struct ks2_serdes {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ enum ks2_serdes_rate_mode rate_mode;
+ enum ks2_serdes_interface intf;
+ u32 loopback;
+};
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 63f3361..8a45fbd 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -554,7 +554,20 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
return 0;
}
+struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .rate_mode = SERDES_QUARTER_RATE,
+ .intf = SERDES_PHY_SGMII,
+ .loopback = 0,
+};
+
static void keystone2_net_serdes_setup(void)
{
- ks2_serdes_sgmii_156p25mhz_setup();
+ ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
+ ks2_serdes_sgmii_156p25mhz,
+ CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+
+ /* wait till setup */
+ udelay(5000);
}
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index 3632c22..84ed9ba 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -7,9 +7,27 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include errno.h
#include common.h
+#include asm/ti-common/keystone_serdes.h
+#define SERDES_CMU_REGS(x) (0x + (0x0c00 * (x)))
#define SERDES_LANE_REGS(x)(0x0200 + (0x200 * (x)))
+#define SERDES_COMLANE_REGS0x0a00
+#define SERDES_WIZ_REGS0x1fc0
+
+#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
+#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
+#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
+#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
+#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
+#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
+#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
+
+#define SERDES_RESET BIT(28)
+#define SERDES_LANE_RESET BIT(29)
+#define SERDES_LANE_LOOPBACK BIT(30)
+#define SERDES_LANE_EN_VAL(x, y, z)(x[y] | (z 26) | (z 10))
struct serdes_cfg {
u32 ofs;
@@ -17,6 +35,18 @@ struct serdes_cfg {
u32 mask;
};
+/* SERDES PHY lane enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_lane_enable[] = {
+ 0xf000f0c0, /* SGMII */
+ 0xf0e9f038, /* PCSR */
+};
+
+/* SERDES PHY PLL enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_pll_enable[] = {
+ 0xe000, /* SGMII */
+ 0xee00, /* PCSR
[U-Boot] [U-boot] [Patch v3 0/5] keystone2: serdes: add seredes driver
This patch series adds serdes driver, taking out it from keystone_net driver. v3..v1: - just rebase. Hao Zhang (2): soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations soc: keystone_serdes: generalize to be used by other sub systems Ivan Khoronzhuk (3): soc: add soc specific drivers directory soc: keystone_serdes: create a separate SGMII SerDes driver soc: keystone_serdes: generalize configuration mechanism arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 + arch/arm/include/asm/arch-keystone/hardware.h | 3 + arch/arm/include/asm/ti-common/keystone_serdes.h | 55 ++ drivers/Makefile | 2 + drivers/net/keystone_net.c | 154 ++- drivers/soc/Makefile | 5 + drivers/soc/keystone/Makefile | 1 + drivers/soc/keystone/keystone_serdes.c | 210 + include/configs/k2hk_evm.h | 3 + include/configs/ks2_evm.h | 6 +- 10 files changed, 303 insertions(+), 139 deletions(-) create mode 100644 arch/arm/include/asm/ti-common/keystone_serdes.h create mode 100644 drivers/soc/Makefile create mode 100644 drivers/soc/keystone/Makefile create mode 100644 drivers/soc/keystone/keystone_serdes.c -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v3 3/5] soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations
From: Hao Zhang hzh...@ti.com
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 +
arch/arm/include/asm/arch-keystone/hardware.h | 3 +
drivers/soc/keystone/keystone_serdes.c | 166 +++--
include/configs/ks2_evm.h | 4 +
4 files changed, 94 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 706b21d..28de3f5 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -79,6 +79,9 @@
#define KS2_DDR3B_EMIF_DATA_BASE 0x6000
#define KS2_DDR3B_DDRPHYC 0x02328000
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index b297671..6788001 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -173,6 +173,9 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES_BASE 0x0232a000
+
#ifdef CONFIG_SOC_K2HK
#include asm/arch/hardware-k2hk.h
#endif
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index dc4e78d..3632c22 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -9,92 +9,94 @@
#include common.h
+#define SERDES_LANE_REGS(x)(0x0200 + (0x200 * (x)))
+
+struct serdes_cfg {
+ u32 ofs;
+ u32 val;
+ u32 mask;
+};
+
+static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
+ {0x, 0x0080, 0x},
+ {0x0014, 0x8282, 0x},
+ {0x0060, 0x00142438, 0x00ff},
+ {0x0064, 0x00c3c700, 0x0000},
+ {0x0078, 0xc000, 0xff00}
+};
+
+static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
+ {0x0a00, 0x0800, 0xff00},
+ {0x0a08, 0x38a2, 0x},
+ {0x0a30, 0x008a8a00, 0x0000},
+ {0x0a84, 0x0600, 0xff00},
+ {0x0a94, 0x1000, 0xff00},
+ {0x0aa0, 0x8100, 0xff00},
+ {0x0abc, 0xff00, 0xff00},
+ {0x0ac0, 0x008b, 0x00ff},
+ {0x0b08, 0x583f, 0x},
+ {0x0b0c, 0x004e, 0x00ff}
+};
+
+static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
+ {0x0004, 0x3880, 0xffff},
+ {0x0008, 0x, 0x00ff},
+ {0x000c, 0x0200, 0xff00},
+ {0x0010, 0x1b00, 0xff00},
+ {0x0014, 0x6fb8, 0x},
+ {0x0018, 0x758000e4, 0x00ff},
+ {0x00ac, 0x4400, 0xff00},
+ {0x002c, 0x00100800, 0x0000},
+ {0x0080, 0x00820082, 0x00ff00ff},
+ {0x0084, 0x1d0f0385, 0x}
+
+};
+
+static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
+{
+ writel(((readl(addr) (~mask)) | (value mask)), addr);
+}
+
+static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
+{
+ u32 i;
+
+ for (i = 0; i size; i++)
+ ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
+}
+
+static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
+ u32 size, u32 lane)
+{
+ u32 i;
+
+ for (i = 0; i size; i++)
+ ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
+ cfg_lane[i].val, cfg_lane[i].mask);
+}
+
+static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
+{
+ u32 i;
+
+ ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g,
+ARRAY_SIZE(cfg_cmu_156p25m_5g));
+ ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g,
+ARRAY_SIZE(cfg_comlane_156p25m_5g));
+
+ for (i = 0; i num_lanes; i++)
+ ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g,
+ ARRAY_SIZE(cfg_lane_156p25mhz_5g), i);
+
+ return 0;
+}
+
void ks2_serdes_sgmii_156p25mhz_setup(void)
{
unsigned int cnt;
- /*
-* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-* hardware vendor published only register addresses and their values
-* to be used for configuring SerDes. So had to use hardcoded values
-* below.
-*/
- clrsetbits_le32(0x0232a000, 0x, 0x0080);
- clrsetbits_le32(0x0232a014, 0x, 0x8282);
- clrsetbits_le32(0x0232a060, 0x00ff, 0x00142438
[U-Boot] [U-boot] [Patch v3 5/5] soc: keystone_serdes: generalize configuration mechanism
The cmu, comlane, lane configuration mechanism are similar for sub
systems as well such as PCI or sRIO, but they have different values
based on input clock and output bus rate. According to this compact
driver to simplify adding different configuration settings based
on clock and rate.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/soc/keystone/keystone_serdes.c | 112 +++--
1 file changed, 65 insertions(+), 47 deletions(-)
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index 84ed9ba..dd5eac9 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -29,12 +29,24 @@
#define SERDES_LANE_LOOPBACK BIT(30)
#define SERDES_LANE_EN_VAL(x, y, z)(x[y] | (z 26) | (z 10))
+#define SERDES_CMU_CFG_NUM 5
+#define SERDES_COMLANE_CFG_NUM 10
+#define SERDES_LANE_CFG_NUM10
+
struct serdes_cfg {
u32 ofs;
u32 val;
u32 mask;
};
+struct cfg_entry {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
+ struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
+ struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
+};
+
/* SERDES PHY lane enable configuration value, indexed by PHY interface */
static u32 serdes_cfg_lane_enable[] = {
0xf000f0c0, /* SGMII */
@@ -47,39 +59,46 @@ static u32 serdes_cfg_pll_enable[] = {
0xee00, /* PCSR */
};
-static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
- {0x, 0x0080, 0x},
- {0x0014, 0x8282, 0x},
- {0x0060, 0x00142438, 0x00ff},
- {0x0064, 0x00c3c700, 0x0000},
- {0x0078, 0xc000, 0xff00}
-};
-
-static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
- {0x0a00, 0x0800, 0xff00},
- {0x0a08, 0x38a2, 0x},
- {0x0a30, 0x008a8a00, 0x0000},
- {0x0a84, 0x0600, 0xff00},
- {0x0a94, 0x1000, 0xff00},
- {0x0aa0, 0x8100, 0xff00},
- {0x0abc, 0xff00, 0xff00},
- {0x0ac0, 0x008b, 0x00ff},
- {0x0b08, 0x583f, 0x},
- {0x0b0c, 0x004e, 0x00ff}
-};
-
-static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
- {0x0004, 0x3880, 0xffff},
- {0x0008, 0x, 0x00ff},
- {0x000c, 0x0200, 0xff00},
- {0x0010, 0x1b00, 0xff00},
- {0x0014, 0x6fb8, 0x},
- {0x0018, 0x758000e4, 0x00ff},
- {0x00ac, 0x4400, 0xff00},
- {0x002c, 0x00100800, 0x0000},
- {0x0080, 0x00820082, 0x00ff00ff},
- {0x0084, 0x1d0f0385, 0x}
-
+/**
+ * Array to hold all possible serdes configurations.
+ * Combination for 5 clock settings and 6 baud rates.
+ */
+static struct cfg_entry cfgs[] = {
+ {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .cmu = {
+ {0x, 0x0080, 0x},
+ {0x0014, 0x8282, 0x},
+ {0x0060, 0x00142438, 0x00ff},
+ {0x0064, 0x00c3c700, 0x0000},
+ {0x0078, 0xc000, 0xff00}
+ },
+ .comlane = {
+ {0x0a00, 0x0800, 0xff00},
+ {0x0a08, 0x38a2, 0x},
+ {0x0a30, 0x008a8a00, 0x0000},
+ {0x0a84, 0x0600, 0xff00},
+ {0x0a94, 0x1000, 0xff00},
+ {0x0aa0, 0x8100, 0xff00},
+ {0x0abc, 0xff00, 0xff00},
+ {0x0ac0, 0x008b, 0x00ff},
+ {0x0b08, 0x583f, 0x},
+ {0x0b0c, 0x004e, 0x00ff}
+ },
+ .lane = {
+ {0x0004, 0x3880, 0xffff},
+ {0x0008, 0x, 0x00ff},
+ {0x000c, 0x0200, 0xff00},
+ {0x0010, 0x1b00, 0xff00},
+ {0x0014, 0x6fb8, 0x},
+ {0x0018, 0x758000e4, 0x00ff},
+ {0x00ac, 0x4400, 0xff00},
+ {0x002c, 0x00100800, 0x0000},
+ {0x0080, 0x00820082, 0x00ff00ff},
+ {0x0084, 0x1d0f0385, 0x}
+ },
+ },
};
static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
@@ -105,18 +124,15 @@ static void ks2_serdes_lane_config(u32 base, struct
serdes_cfg *cfg_lane,
cfg_lane[i].val, cfg_lane[i].mask);
}
-static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
+static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32
[U-Boot] [U-boot] [Patch v2 0/5] keystone_net: use MDIO bus and eth PHY frameworks
This patch series optimize keystone_net driver to use MDIO bus and eht PHY frameworks. Based on [U-boot] [Patch v3 0/5] keystone2: serdes: add seredes driver https://www.mail-archive.com/u-boot@lists.denx.de/msg148694.html v2..v1 net: keystone_net: register eth PHYs on MDIO bus - add ability for choosing to configure phy at init or not Ivan Khoronzhuk (5): net: phy: print a number of phy that is not found net: keystone_net: use mdio_reset function net: keystone_net: register MDIO bus net: keystone_net: register eth PHYs on MDIO bus net: keystone_net: use general get link function arch/arm/include/asm/ti-common/keystone_net.h | 1 + drivers/net/keystone_net.c| 171 -- drivers/net/phy/phy.c | 2 +- include/configs/ks2_evm.h | 3 +- 4 files changed, 81 insertions(+), 96 deletions(-) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 2/5] net: keystone_net: use mdio_reset function
Don't use mdio_enable twice while eth open. Also rename it to
keystone2_mdio_reset as more appropriate name.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/keystone_net.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 8a45fbd..3f9650c 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -38,7 +38,6 @@ struct rx_buff_desc net_rx_buffs = {
.rx_flow= 22,
};
-static void keystone2_eth_mdio_enable(void);
static void keystone2_net_serdes_setup(void);
static int gen_get_link_speed(int phy_addr);
@@ -71,7 +70,7 @@ int keystone2_eth_read_mac_addr(struct eth_device *dev)
return 0;
}
-static void keystone2_eth_mdio_enable(void)
+static void keystone2_mdio_reset(void)
{
u_int32_t clkdiv;
@@ -397,7 +396,6 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int
slave_port_num)
/* Eth device open */
static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
{
- u_int32_t clkdiv;
int link;
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev-priv;
@@ -410,9 +408,6 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
keystone2_net_serdes_setup();
- if (sys_has_mdio)
- keystone2_eth_mdio_enable();
-
keystone_sgmii_config(eth_priv-slave_port - 1,
eth_priv-sgmii_link_type);
@@ -440,14 +435,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
hw_config_streaming_switch();
if (sys_has_mdio) {
- /* Init MDIO get link state */
- clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
- writel((clkdiv 0xff) | MDIO_CONTROL_ENABLE |
- MDIO_CONTROL_FAULT, adap_mdio-control)
- ;
-
- /* We need to wait for MDIO to start */
- udelay(1000);
+ keystone2_mdio_reset();
link = keystone_get_link_status(dev);
if (link == 0) {
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v2 1/5] net: phy: print a number of phy that is not found
In case when several Ethernet ports are supported it's convenient to see the number of phy that is not found. Acked-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/net/phy/phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 1d6c14f..99b0b83 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -648,7 +648,7 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, if (phydev) return phydev; } - printf(Phy not found\n); + printf(Phy %d not found\n, ffs(phy_mask) - 1); return phy_device_create(bus, ffs(phy_mask) - 1, 0x, interface); } -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 5/5] net: keystone_net: use general get link function
The phy framework has function to get link, so use it
instead of own implementation.
There is no reason to check SGMII link while sending each
packet, phy link is enough. Check SGMII link only while
ethernet open.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/keystone_net.c | 50 +-
include/configs/ks2_evm.h | 1 -
2 files changed, 5 insertions(+), 46 deletions(-)
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index fa8e1ef..13a1778 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -42,8 +42,6 @@ struct rx_buff_desc net_rx_buffs = {
static void keystone2_net_serdes_setup(void);
-static int gen_get_link_speed(int phy_addr);
-
int keystone2_eth_read_mac_addr(struct eth_device *dev)
{
struct eth_priv_t *eth_priv;
@@ -137,19 +135,6 @@ static int keystone2_mdio_write(struct mii_dev *bus,
return 0;
}
-/* PHY functions for a generic PHY */
-static int gen_get_link_speed(int phy_addr)
-{
- u_int16_t tmp;
-
- tmp = mdio_bus-read(mdio_bus, phy_addr,
-MDIO_DEVAD_NONE, MII_STATUS_REG);
- if (tmp 0x04)
- return 0;
-
- return -1;
-}
-
static void __attribute__((unused))
keystone2_eth_gigabit_enable(struct eth_device *dev)
{
@@ -180,35 +165,8 @@ int keystone_sgmii_link_status(int port)
status = __raw_readl(SGMII_STATUS_REG(port));
- return status SGMII_REG_STATUS_LINK;
-}
-
-
-int keystone_get_link_status(struct eth_device *dev)
-{
- struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev-priv;
- int sgmii_link;
- int link_state = 0;
-#if CONFIG_GET_LINK_STATUS_ATTEMPTS 1
- int j;
-
- for (j = 0; (j CONFIG_GET_LINK_STATUS_ATTEMPTS) (link_state == 0);
-j++) {
-#endif
- sgmii_link =
- keystone_sgmii_link_status(eth_priv-slave_port - 1);
-
- if (sgmii_link) {
- link_state = 1;
-
- if (eth_priv-sgmii_link_type == SGMII_LINK_MAC_PHY)
- if (gen_get_link_speed(eth_priv-phy_addr))
- link_state = 0;
- }
-#if CONFIG_GET_LINK_STATUS_ATTEMPTS 1
- }
-#endif
- return link_state;
+ return (status SGMII_REG_STATUS_LOCK)
+ (status SGMII_REG_STATUS_LINK);
}
int keystone_sgmii_config(int port, int interface)
@@ -490,8 +448,10 @@ static int keystone2_eth_send_packet(struct eth_device
*dev,
{
int ret_status = -1;
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev-priv;
+ struct phy_device *phy_dev = eth_priv-phy_dev;
- if (keystone_get_link_status(dev) == 0)
+ genphy_update_link(phy_dev);
+ if (phy_dev-link == 0)
return -1;
if (cpmac_drv_send((u32 *)packet, length, eth_priv-slave_port) != 0)
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 8d02d18..dcce7c3 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -103,7 +103,6 @@
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 32
#define CONFIG_NET_MULTI
-#define CONFIG_GET_LINK_STATUS_ATTEMPTS5
#define CONFIG_SYS_SGMII_REFCLK_MHZ312
#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
#define CONFIG_SYS_SGMII_RATESCALE 2
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v2 4/5] net: keystone_net: register eth PHYs on MDIO bus
As MDIO bus has been added we can register PHYs with it.
After registration, the PHY driver will be probed according to the
hardware on board.
Startup PHY at the ethernet open.
Use phy_startup() instead of keystone_get_link_status() when eth open,
as it verifies PHY link inside and SGMII link is checked before.
For K2HK evm PHY configuration at init was absent, so don't enable
phy config at init for k2hk evm.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/keystone_net.h | 1 +
drivers/net/keystone_net.c| 24 +---
include/configs/ks2_evm.h | 2 ++
3 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_net.h
b/arch/arm/include/asm/ti-common/keystone_net.h
index e56759d..011c03c 100644
--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -239,6 +239,7 @@ struct eth_priv_t {
int phy_addr;
int slave_port;
int sgmii_link_type;
+ struct phy_device *phy_dev;
};
int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 265530a..fa8e1ef 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -10,6 +10,7 @@
#include command.h
#include net.h
+#include phy.h
#include miiphy.h
#include malloc.h
#include asm/ti-common/keystone_nav.h
@@ -398,8 +399,8 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int
slave_port_num)
/* Eth device open */
static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
{
- int link;
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev-priv;
+ struct phy_device *phy_dev = eth_priv-phy_dev;
debug(+ emac_open\n);
@@ -439,8 +440,8 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
if (sys_has_mdio) {
keystone2_mdio_reset(mdio_bus);
- link = keystone_get_link_status(dev);
- if (link == 0) {
+ phy_startup(phy_dev);
+ if (phy_dev-link == 0) {
ksnav_close(netcp_pktdma);
qm_close();
return -1;
@@ -461,6 +462,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
/* Eth device close */
void keystone2_eth_close(struct eth_device *dev)
{
+ struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev-priv;
+ struct phy_device *phy_dev = eth_priv-phy_dev;
+
debug(+ emac_close\n);
if (!emac_open)
@@ -470,6 +474,7 @@ void keystone2_eth_close(struct eth_device *dev)
ksnav_close(netcp_pktdma);
qm_close();
+ phy_shutdown(phy_dev);
emac_open = 0;
@@ -522,6 +527,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
{
int res;
struct eth_device *dev;
+ struct phy_device *phy_dev;
dev = malloc(sizeof(struct eth_device));
if (dev == NULL)
@@ -556,6 +562,18 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
return res;
}
+ /* Create phy device and bind it with driver */
+#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+ phy_dev = phy_connect(mdio_bus, eth_priv-phy_addr,
+ dev, PHY_INTERFACE_MODE_SGMII);
+ phy_config(phy_dev);
+#else
+ phy_dev = phy_find_by_mask(mdio_bus, 1 eth_priv-phy_addr,
+ PHY_INTERFACE_MODE_SGMII);
+ phy_dev-dev = dev;
+#endif
+ eth_priv-phy_dev = phy_dev;
+
return 0;
}
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 7fbb648..8d02d18 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -94,6 +94,8 @@
#define CONFIG_SYS_SPI2_NUM_CS 4
/* Network Configuration */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v2 3/5] net: keystone_net: register MDIO bus
Currently MDIO framework is not used to configure Ethernet PHY.
As result some of already implemented functions are duplicated.
So register MDIO bus in order to use it. On that stage it's just
registered, it'll be used as we start to use PHY framework.
Use mdio bus read/write/reset functions in the driver.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/keystone_net.c | 93 +++---
1 file changed, 55 insertions(+), 38 deletions(-)
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 3f9650c..265530a 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -17,6 +17,7 @@
#include asm/ti-common/keystone_serdes.h
unsigned int emac_open;
+static struct mii_dev *mdio_bus;
static unsigned int sys_has_mdio = 1;
#ifdef KEYSTONE2_EMAC_GIG_ENABLE
@@ -42,10 +43,6 @@ static void keystone2_net_serdes_setup(void);
static int gen_get_link_speed(int phy_addr);
-/* EMAC Addresses */
-static volatile struct mdio_regs *adap_mdio =
- (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
-
int keystone2_eth_read_mac_addr(struct eth_device *dev)
{
struct eth_priv_t *eth_priv;
@@ -70,64 +67,67 @@ int keystone2_eth_read_mac_addr(struct eth_device *dev)
return 0;
}
-static void keystone2_mdio_reset(void)
+/* MDIO */
+
+static int keystone2_mdio_reset(struct mii_dev *bus)
{
- u_int32_t clkdiv;
+ u_int32_t clkdiv;
+ struct mdio_regs *adap_mdio = bus-priv;
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
- writel((clkdiv 0x) |
- MDIO_CONTROL_ENABLE |
- MDIO_CONTROL_FAULT |
- MDIO_CONTROL_FAULT_ENABLE,
+ writel((clkdiv 0x) | MDIO_CONTROL_ENABLE |
+ MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
adap_mdio-control);
while (readl(adap_mdio-control) MDIO_CONTROL_IDLE)
;
+
+ return 0;
}
-/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
-int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t
*data)
+/**
+ * keystone2_mdio_read - read a PHY register via MDIO interface.
+ * Blocks until operation is complete.
+ */
+static int keystone2_mdio_read(struct mii_dev *bus,
+ int addr, int devad, int reg)
{
- int tmp;
+ int tmp;
+ struct mdio_regs *adap_mdio = bus-priv;
while (readl(adap_mdio-useraccess0) MDIO_USERACCESS0_GO)
;
- writel(MDIO_USERACCESS0_GO |
- MDIO_USERACCESS0_WRITE_READ |
- ((reg_num 0x1f) 21) |
- ((phy_addr 0x1f) 16),
+ writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
+ ((reg 0x1f) 21) | ((addr 0x1f) 16),
adap_mdio-useraccess0);
/* Wait for command to complete */
while ((tmp = readl(adap_mdio-useraccess0)) MDIO_USERACCESS0_GO)
;
- if (tmp MDIO_USERACCESS0_ACK) {
- *data = tmp 0x;
- return 0;
- }
+ if (tmp MDIO_USERACCESS0_ACK)
+ return tmp 0x;
- *data = -1;
return -1;
}
-/*
- * Write to a PHY register via MDIO inteface.
+/**
+ * keystone2_mdio_write - write to a PHY register via MDIO interface.
* Blocks until operation is complete.
*/
-int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t
data)
+static int keystone2_mdio_write(struct mii_dev *bus,
+ int addr, int devad, int reg, u16 val)
{
+ struct mdio_regs *adap_mdio = bus-priv;
+
while (readl(adap_mdio-useraccess0) MDIO_USERACCESS0_GO)
;
- writel(MDIO_USERACCESS0_GO |
- MDIO_USERACCESS0_WRITE_WRITE |
- ((reg_num 0x1f) 21) |
- ((phy_addr 0x1f) 16) |
- (data 0x),
- adap_mdio-useraccess0);
+ writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
+ ((reg 0x1f) 21) | ((addr 0x1f) 16) |
+ (val 0x), adap_mdio-useraccess0);
/* Wait for command to complete */
while (readl(adap_mdio-useraccess0) MDIO_USERACCESS0_GO)
@@ -139,12 +139,12 @@ int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t
reg_num, u_int16_t data)
/* PHY functions for a generic PHY */
static int gen_get_link_speed(int phy_addr)
{
- u_int16_t tmp;
+ u_int16_t tmp;
- if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, tmp))
- (tmp 0x04)) {
+ tmp = mdio_bus-read(mdio_bus, phy_addr,
+MDIO_DEVAD_NONE, MII_STATUS_REG);
+ if (tmp 0x04)
return 0;
- }
return -1;
}
@@ -156,8 +156,10 @@ static void __attribute__((unused))
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev
[U-Boot] [U-boot] [Patch v2 0/6] keystone2: add network support for K2E SoC and EVM
These patches add network support for Keystne2 Edison SoC boards. Based on [U-boot] [Patch v2 0/5] keystone_net: use MDIO bus and eth PHY frameworks http://patchwork.ozlabs.org/patch/322289/ v2..v1 ARM: keystone: clock: add support for K2E SoCs - firstly added Hao Zhang (1): board: k2e_evm: add network support Ivan Khoronzhuk (5): ARM: keystone2: keysonte_nav: add support for K2E SoC net: keystone_serdes: add keystone K2E SoC support net: keystone_net: add Keystone2 K2E SoC support net: keystone_net: increase PHY auto negotiate time ARM: keystone: clock: add support for K2E SoCs arch/arm/cpu/armv7/keystone/clock.c | 17 -- arch/arm/include/asm/arch-keystone/clock.h| 1 + arch/arm/include/asm/arch-keystone/hardware-k2e.h | 20 +++ board/ti/ks2_evm/board.c | 1 + board/ti/ks2_evm/board_k2e.c | 68 ++- drivers/net/keystone_net.c| 47 ++-- include/configs/k2e_evm.h | 11 include/configs/ks2_evm.h | 1 + 8 files changed, 156 insertions(+), 10 deletions(-) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 1/6] ARM: keystone2: keysonte_nav: add support for K2E SoC
Keystone2 Edison SoC uses the same keystone navigator, but uses different NETCP PktDMA definitions. This patch adds required definitions. Acked-by: Vitaly Andrianov vita...@ti.com Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index 62172a4..f09aa93 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -41,4 +41,17 @@ /* Number of DSP cores */ #define KS2_NUM_DSPS 1 +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 +#define KS2_NETCP_PDMA_TX_BASE 0x24187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x24188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE0x24189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE4002 +#define KS2_NETCP_PDMA_TX_SND_QUEUE896 + #endif -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 4/6] net: keystone_net: increase PHY auto negotiate time
The new Marvel PHY (88E1514) used on K2L/K2E EVM requires longer time
to auto negotiate with SoC's SGMII port.
It can take about 3 sec to up the PHY after reset, so add code to
expose sgmii auto negotiation waiting process.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/keystone_net.c | 36 +++-
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 1186188..c8681d0 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -11,6 +11,7 @@
#include net.h
#include phy.h
+#include errno.h
#include miiphy.h
#include malloc.h
#include asm/ti-common/keystone_nav.h
@@ -30,6 +31,7 @@ static unsigned int sys_has_mdio = 1;
#define RX_BUFF_NUMS 24
#define RX_BUFF_LEN1520
#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
+#define SGMII_ANEG_TIMEOUT 4000
static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
@@ -169,7 +171,7 @@ int keystone_sgmii_link_status(int port)
(status SGMII_REG_STATUS_LINK);
}
-int keystone_sgmii_config(int port, int interface)
+int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
{
unsigned int i, status, mask;
unsigned int mr_adv_ability, control;
@@ -230,11 +232,35 @@ int keystone_sgmii_config(int port, int interface)
if (control SGMII_REG_CONTROL_AUTONEG)
mask |= SGMII_REG_STATUS_AUTONEG;
- for (i = 0; i 1000; i++) {
+ status = __raw_readl(SGMII_STATUS_REG(port));
+ if ((status mask) == mask)
+ return 0;
+
+ printf(\n%s Waiting for SGMII auto negotiation to complete,
+ phy_dev-dev-name);
+ while ((status mask) != mask) {
+ /*
+* Timeout reached ?
+*/
+ if (i SGMII_ANEG_TIMEOUT) {
+ puts( TIMEOUT !\n);
+ phy_dev-link = 0;
+ return 0;
+ }
+
+ if (ctrlc()) {
+ puts(user interrupt!\n);
+ phy_dev-link = 0;
+ return -EINTR;
+ }
+
+ if ((i++ % 500) == 0)
+ printf(.);
+
+ udelay(1000); /* 1 ms */
status = __raw_readl(SGMII_STATUS_REG(port));
- if ((status mask) == mask)
- break;
}
+ puts( done\n);
return 0;
}
@@ -374,7 +400,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
keystone2_net_serdes_setup();
- keystone_sgmii_config(eth_priv-slave_port - 1,
+ keystone_sgmii_config(phy_dev, eth_priv-slave_port - 1,
eth_priv-sgmii_link_type);
udelay(1);
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v2 3/6] net: keystone_net: add Keystone2 K2E SoC support
The Keystone2 Edison SoC uses the same keystone net driver. This patch adds opportunity to use it by K2E SoCs. Acked-by: Vitaly Andrianov vita...@ti.com Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 3 +++ drivers/net/keystone_net.c| 5 + 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index 4eac5f8..ab0d5f9 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -58,4 +58,7 @@ #define KS2_NETCP_PDMA_RX_RCV_QUEUE4002 #define KS2_NETCP_PDMA_TX_SND_QUEUE896 +/* NETCP */ +#define KS2_NETCP_BASE 0x2400 + #endif diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 43c263e..1186188 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -289,6 +289,11 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) writel(cfg-max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); writel(cfg-ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); +#ifdef CONFIG_K2E_EVM + /* Map RX packet flow priority to 0 */ + writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); +#endif + return ret; } -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 5/6] ARM: keystone: clock: add support for K2E SoCs
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/clock.c| 17 +
arch/arm/include/asm/arch-keystone/clock.h | 1 +
board/ti/ks2_evm/board.c | 1 +
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/keystone/clock.c
b/arch/arm/cpu/armv7/keystone/clock.c
index 47fc893..d13fbc1 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
tmp = ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj 8) PLL_BWADJ_HI_MASK);
- /* set PLL Select (bit 13) for PASS PLL */
- if (data-pll == PASS_PLL)
- tmp |= PLLCTL_PAPLL;
-
__raw_writel(tmp, keystone_pll_regs[data-pll].reg1);
/* Reset bit: bit 14 for both DDR3 PASS PLL */
@@ -261,3 +257,16 @@ inline int get_max_arm_speed(void)
return get_max_speed((read_efuse_bootrom() 16) 0x, arm_speeds);
}
#endif
+
+void pass_pll_pa_clk_enable(void)
+{
+ u32 reg;
+
+ reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+
+ reg |= PLLCTL_PAPLL;
+ writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+
+ /* wait till clock is enabled */
+ sdelay(15000);
+}
diff --git a/arch/arm/include/asm/arch-keystone/clock.h
b/arch/arm/include/asm/arch-keystone/clock.h
index bc31267..9480e62 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -50,6 +50,7 @@ void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
+void pass_pll_pa_clk_enable(void);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 279ec8e..8991786 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -77,6 +77,7 @@ int board_eth_init(bd_t *bis)
return -1;
if (psc_enable_module(KS2_LPSC_CRYPTO))
return -1;
+ pass_pll_pa_clk_enable();
port_num = get_num_eth_ports();
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v2 6/6] board: k2e_evm: add network support
From: Hao Zhang hzh...@ti.com
This patch adds network support code and enables keystone_net
driver usage for k2e_evm evaluation board.
Acked-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
board/ti/ks2_evm/board_k2e.c | 68 +++-
include/configs/k2e_evm.h| 8 ++
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 810a8e2..43dfc48 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -10,6 +10,7 @@
#include common.h
#include asm/arch/ddr3.h
#include asm/arch/hardware.h
+#include asm/ti-common/keystone_net.h
DECLARE_GLOBAL_DATA_PTR;
@@ -35,10 +36,75 @@ static struct pll_init_data core_pll_config[] = {
CORE_PLL_1500,
};
-
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name= K2E_EMAC0,
+ .rx_flow = 0,
+ .phy_addr= 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name= K2E_EMAC1,
+ .rx_flow = 8,
+ .phy_addr= 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name= K2E_EMAC2,
+ .rx_flow = 16,
+ .phy_addr= 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name= K2E_EMAC3,
+ .rx_flow = 24,
+ .phy_addr= 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name= K2E_EMAC4,
+ .rx_flow = 32,
+ .phy_addr= 4,
+ .slave_port = 5,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name= K2E_EMAC5,
+ .rx_flow = 40,
+ .phy_addr= 5,
+ .slave_port = 6,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name= K2E_EMAC6,
+ .rx_flow = 48,
+ .phy_addr= 6,
+ .slave_port = 7,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name= K2E_EMAC7,
+ .rx_flow = 56,
+ .phy_addr= 7,
+ .slave_port = 8,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index fd45d61..7c8065a 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -34,6 +34,14 @@
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
+/* Network */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
+#define CONFIG_TI_KSNAV
+#define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS9
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v2 2/6] net: keystone_serdes: add keystone K2E SoC support
Keystone2 Edison SoC uses the same keystone SerDes driver. This patch adds support for K2E SoCs. Acked-by: Vitaly Andrianov vita...@ti.com Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 4 drivers/net/keystone_net.c| 6 ++ include/configs/k2e_evm.h | 3 +++ include/configs/ks2_evm.h | 1 + 4 files changed, 14 insertions(+) diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index f09aa93..4eac5f8 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -38,6 +38,10 @@ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02324000 +#define KS2_LANES_PER_SGMII_SERDES 4 + /* Number of DSP cores */ #define KS2_NUM_DSPS 1 diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 13a1778..43c263e 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -551,6 +551,12 @@ static void keystone2_net_serdes_setup(void) ks2_serdes_sgmii_156p25mhz, CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#ifdef CONFIG_SOC_K2E + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#endif + /* wait till setup */ udelay(5000); } diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 3502d10..fd45d61 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -34,4 +34,7 @@ /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K +/* SerDes */ +#define CONFIG_TI_KEYSTONE_SERDES + #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index dcce7c3..a92ab04 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -140,6 +140,7 @@ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASEKS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CONFIG_KSNET_SERDES_SGMII2_BASEKS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMIIKS2_LANES_PER_SGMII_SERDES /* AEMIF */ -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch v3 0/5] keystone2: serdes: add seredes driver
On 10/17/2014 08:38 PM, Ivan Khoronzhuk wrote: This patch series adds serdes driver, taking out it from keystone_net driver. v3..v1: - just rebase. is based on [U-boot] [Patch v2 0/5] keystone2: generalize keystone_net driver usage https://www.mail-archive.com/u-boot@lists.denx.de/msg148032.html -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch v3 0/5] keystone2: serdes: add seredes driver
On 10/17/2014 10:00 PM, Ivan Khoronzhuk wrote: On 10/17/2014 08:38 PM, Ivan Khoronzhuk wrote: This patch series adds serdes driver, taking out it from keystone_net driver. v3..v1: - just rebase. is based on [U-boot] [Patch v2 0/5] keystone2: generalize keystone_net driver usage https://www.mail-archive.com/u-boot@lists.denx.de/msg148032.html Oh sorry, get a wrong link http://u-boot.10912.n7.nabble.com/U-boot-Patch-v2-0-5-keystone2-generalize-keystone-net-driver-usage-td190624.html -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch v2 0/5] keystone_net: use MDIO bus and eth PHY frameworks
On 10/17/2014 08:44 PM, Ivan Khoronzhuk wrote: This patch series optimize keystone_net driver to use MDIO bus and eht PHY frameworks. Based on [U-boot] [Patch v3 0/5] keystone2: serdes: add seredes driver https://www.mail-archive.com/u-boot@lists.denx.de/msg148694.html link update https://www.mail-archive.com/u-boot@lists.denx.de/msg150347.html -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch v2 0/6] keystone2: add network support for K2E SoC and EVM
On 10/17/2014 09:01 PM, Ivan Khoronzhuk wrote: These patches add network support for Keystne2 Edison SoC boards. Based on [U-boot] [Patch v2 0/5] keystone_net: use MDIO bus and eth PHY frameworks http://patchwork.ozlabs.org/patch/322289/ link update https://www.mail-archive.com/u-boot@lists.denx.de/msg150350.html -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch v2 0/4] keystone2: ecc: add ddr3 error detection and correction support
On 10/17/2014 01:52 AM, Ivan Khoronzhuk wrote: This series adds the DDR3 ECC support to enable ECC in the DDR3 EMIF controller for Keystone II devices. Based on [U-boot] [Patch 0/5] keystone2: add network support for K2E SoC and EVM https://www.mail-archive.com/u-boot@lists.denx.de/msg148985.html link update [U-boot] [Patch v2 0/6] keystone2: add network support for K2E SoC and EVM https://www.mail-archive.com/u-boot@lists.denx.de/msg150359.html -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 3/4] keystone2: ecc: add ddr3 error detection and correction support
From: Vitaly Andrianov vita...@ti.com
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.
An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/ddr3.c | 244 +
arch/arm/include/asm/arch-keystone/ddr3.h | 6 +
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 4 +
arch/arm/include/asm/arch-keystone/hardware.h | 46
board/ti/ks2_evm/board.c | 3 +
board/ti/ks2_evm/ddr3_k2hk.c | 16 ++
6 files changed, 319 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 2eabec1..923906a 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -9,9 +9,19 @@
#include asm/io.h
#include common.h
+#include asm/arch/msmc.h
#include asm/arch/ddr3.h
#include asm/arch/psc_defs.h
+#include asm/ti-common/ti-edma3.h
+
+#define DDR3_EDMA_BLK_SIZE_SHIFT 10
+#define DDR3_EDMA_BLK_SIZE (1 DDR3_EDMA_BLK_SIZE_SHIFT)
+#define DDR3_EDMA_BCNT 0x8000
+#define DDR3_EDMA_CCNT 1
+#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
+#define DDR3_EDMA_SLOT_NUM 1
+
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@@ -70,6 +80,240 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config
*emif_cfg)
__raw_writel(emif_cfg-sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
+int ddr3_ecc_support_rmw(u32 base)
+{
+ u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
+
+ /* Check the DDR3 controller ID reg if the controllers
+ supports ECC RMW or not */
+ if (value == 0x40461C02)
+ return 1;
+
+ return 0;
+}
+
+static void ddr3_ecc_config(u32 base, u32 value)
+{
+ u32 data;
+
+ __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
+ udelay(10); /* delay required to synchronize across clock domains */
+
+ if (value KS2_DDR3_ECC_EN) {
+ /* Clear the 1-bit error count */
+ data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+ __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+
+ /* enable the ECC interrupt */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+KS2_DDR3_WR_ECC_ERR_SYS,
+base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
+
+ /* Clear the ECC error interrupt status */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+KS2_DDR3_WR_ECC_ERR_SYS,
+base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+ }
+}
+
+static void ddr3_reset_data(u32 base, u32 ddr3_size)
+{
+ u32 mpax[2];
+ u32 seg_num;
+ u32 seg, blks, dst, edma_blks;
+ struct edma3_slot_config slot;
+ struct edma3_channel_config edma_channel;
+ u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
+
+ /* Setup an edma to copy the 1k block to the entire DDR */
+ puts(\nClear entire DDR3 memory to enable ECC\n);
+
+ /* save the SES MPAX regs */
+ msmc_get_ses_mpax(8, 0, mpax);
+
+ /* setup edma slot 1 configuration */
+ slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+ EDMA3_SLOPT_COMP_CODE(0) |
+ EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+ slot.bcnt = DDR3_EDMA_BCNT;
+ slot.acnt = DDR3_EDMA_BLK_SIZE;
+ slot.ccnt = DDR3_EDMA_CCNT;
+ slot.src_bidx = 0;
+ slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
+ slot.src_cidx = 0;
+ slot.dst_cidx = 0;
+ slot.link = EDMA3_PARSET_NULL_LINK;
+ slot.bcntrld = 0;
+ edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, slot);
+
+ /* configure quik edma channel */
+ edma_channel.slot = DDR3_EDMA_SLOT_NUM;
+ edma_channel.chnum = 0;
+ edma_channel.complete_code = 0;
+ /* event trigger after dst update */
+ edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+ qedma3_start(KS2_EDMA0_BASE, edma_channel);
+
+ /* DDR3 size in segments (4KB seg size) */
+ seg_num = ddr3_size (30 - KS2_MSMC_SEG_SIZE_SHIFT
[U-Boot] [U-boot] [Patch v2 1/4] dma: ti-edma3: introduce edma3 driver
The EDMA3 controller’s primary purpose is to service data transfers
that you program between two memory-mapped slave endpoints on the device.
Typical usage includes, but is not limited to the following:
- Servicing software-driven paging transfers (e.g., transfers from external
memory, such as SDRAM to internal device memory, such as DSP L2 SRAM)
- Servicing event-driven peripherals, such as a serial port
- Performing sorting or sub-frame extraction of various data structures
- Offloading data transfers from the main device DSP(s)
- See the device-specific data manual for specific peripherals that are
accessible via the EDMA3 controller
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/ti-edma3.h | 121 ++
drivers/dma/Makefile | 1 +
drivers/dma/ti-edma3.c| 384 ++
3 files changed, 506 insertions(+)
create mode 100644 arch/arm/include/asm/ti-common/ti-edma3.h
create mode 100644 drivers/dma/ti-edma3.c
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h
b/arch/arm/include/asm/ti-common/ti-edma3.h
new file mode 100644
index 000..5adc1da
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -0,0 +1,121 @@
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EDMA3_H_
+#define _EDMA3_H_
+
+#include linux/stddef.h
+
+#define EDMA3_PARSET_NULL_LINK 0x
+
+/*
+ * All parameter RAM set options
+ * opt field in edma3_param_set_config structure
+ */
+#define EDMA3_SLOPT_PRIV_LEVEL BIT(31)
+#define EDMA3_SLOPT_PRIV_ID(id)((0xf (id)) 24)
+#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23)
+#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22)
+#define EDMA3_SLOPT_INTERM_COMP_INT_ENBBIT(21)
+#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20)
+#define EDMA3_SLOPT_COMP_CODE(code)((0x3f (code)) 12)
+#define EDMA3_SLOPT_FIFO_WIDTH_8 0
+#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w 0x7) 8)
+#define EDMA3_SLOPT_STATIC BIT(3)
+#define EDMA3_SLOPT_AB_SYNCBIT(2)
+#define EDMA3_SLOPT_DST_ADDR_CONST_MODEBIT(1)
+#define EDMA3_SLOPT_SRC_ADDR_CONST_MODEBIT(0)
+
+enum edma3_address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum edma3_fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum edma3_sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+/* PaRAM slots are laid out like this */
+struct edma3_slot_layout {
+ u32 opt;
+ u32 src;
+ u32 a_b_cnt;
+ u32 dst;
+ u32 src_dst_bidx;
+ u32 link_bcntrld;
+ u32 src_dst_cidx;
+ u32 ccnt;
+} __packed;
+
+/*
+ * Use this to assign trigger word number of edma3_slot_layout struct.
+ * trigger_word_name - is the exact name from edma3_slot_layout.
+ */
+#define EDMA3_TWORD(trigger_word_name)\
+ (offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
+
+struct edma3_slot_config {
+ u32 opt;
+ u32 src;
+ u32 dst;
+ int bcnt;
+ int acnt;
+ int ccnt;
+ int src_bidx;
+ int dst_bidx;
+ int src_cidx;
+ int dst_cidx;
+ int bcntrld;
+ int link;
+};
+
+struct edma3_channel_config {
+ int slot;
+ int chnum;
+ int complete_code; /* indicate pending complete interrupt */
+ int trigger_slot_word; /* only used for qedma */
+};
+
+void qedma3_start(u32 base, struct edma3_channel_config *cfg);
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
+
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_dest_addr(u32 base, int slot, u32 dst);
+
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_src_addr(u32 base, int slot, u32 src);
+
+void edma3_set_transfer_params
[U-Boot] [U-boot] [Patch v2 0/4] keystone2: ecc: add ddr3 error detection and correction support
This series adds the DDR3 ECC support to enable ECC in the DDR3 EMIF controller for Keystone II devices. Based on [U-boot] [Patch 0/5] keystone2: add network support for K2E SoC and EVM https://www.mail-archive.com/u-boot@lists.denx.de/msg148985.html v2..v1: - nothing changed just rebased Hao Zhang (1): ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr Ivan Khoronzhuk (1): dma: ti-edma3: introduce edma3 driver Vitaly Andrianov (2): ARM: keystone: msmc: extend functionality of SES keystone2: ecc: add ddr3 error detection and correction support arch/arm/cpu/armv7/keystone/Makefile | 2 +- arch/arm/cpu/armv7/keystone/cmd_ddr3.c | 247 + arch/arm/cpu/armv7/keystone/ddr3.c | 244 + arch/arm/cpu/armv7/keystone/msmc.c | 26 ++ arch/arm/include/asm/arch-keystone/ddr3.h | 6 + arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 4 + arch/arm/include/asm/arch-keystone/hardware.h | 52 +++ arch/arm/include/asm/arch-keystone/msmc.h | 28 ++ arch/arm/include/asm/ti-common/ti-edma3.h | 121 +++ board/ti/ks2_evm/board.c | 3 + board/ti/ks2_evm/ddr3_k2hk.c | 16 + drivers/dma/Makefile | 1 + drivers/dma/ti-edma3.c | 384 + include/configs/ks2_evm.h | 4 - 14 files changed, 1133 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/cmd_ddr3.c create mode 100644 arch/arm/include/asm/ti-common/ti-edma3.h create mode 100644 drivers/dma/ti-edma3.c -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 2/4] ARM: keystone: msmc: extend functionality of SES
From: Vitaly Andrianov vita...@ti.com
Add functions to set/get SES PMAX values of Pivilege ID pair.
Also add msmc module definitions.
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/msmc.c| 26 +
arch/arm/include/asm/arch-keystone/hardware.h | 6 ++
arch/arm/include/asm/arch-keystone/msmc.h | 28 +++
3 files changed, 60 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c
b/arch/arm/cpu/armv7/keystone/msmc.c
index 7d8e597..7899141 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -66,3 +66,29 @@ void msmc_share_all_segments(int priv_id)
msmc-ses[priv_id][j].mpaxh = 0xff7ful;
}
}
+
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc-ses[priv_id][ses_pair].mpaxh = src_pfn 12 |
+(size 0x1f) | 0x80;
+ msmc-ses[priv_id][ses_pair].mpaxl = dst_pfn 8 | 0x3f;
+}
+
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ *mpax++ = msmc-ses[priv_id][ses_pair].mpaxl;
+ *mpax = msmc-ses[priv_id][ses_pair].mpaxh;
+}
+
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc-ses[priv_id][ses_pair].mpaxl = *mpax++;
+ msmc-ses[priv_id][ses_pair].mpaxh = *mpax;
+}
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 6788001..d2bd6cb 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -165,6 +165,12 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_MSMC_CTRL_BASE 0x0bc0
#define KS2_MSMC_DATA_BASE 0x0c00
+/* MSMC segment size shift bits */
+#define KS2_MSMC_SEG_SIZE_SHIFT12
+#define KS2_MSMC_MAP_SEG_NUM (2 (30 - KS2_MSMC_SEG_SIZE_SHIFT))
+#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE \
+ KS2_MSMC_SEG_SIZE_SHIFT)
+
/* USB */
#define KS2_USB_SS_BASE0x0268
#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x1)
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h
b/arch/arm/include/asm/arch-keystone/msmc.h
index c320db5..083f5ba 100644
--- a/arch/arm/include/asm/arch-keystone/msmc.h
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -12,6 +12,34 @@
#include asm/arch/hardware.h
+enum mpax_seg_size {
+ MPAX_SEG_4K = 0x0b,
+ MPAX_SEG_8K,
+ MPAX_SEG_16K,
+ MPAX_SEG_32K,
+ MPAX_SEG_64K,
+ MPAX_SEG_128K,
+ MPAX_SEG_256K,
+ MPAX_SEG_512K,
+ MPAX_SEG_1M,
+ MPAX_SEG_2M,
+ MPAX_SEG_4M,
+ MPAX_SEG_8M,
+ MPAX_SEG_16M,
+ MPAX_SEG_32M,
+ MPAX_SEG_64M,
+ MPAX_SEG_128M,
+ MPAX_SEG_256M,
+ MPAX_SEG_512M,
+ MPAX_SEG_1G,
+ MPAX_SEG_2G,
+ MPAX_SEG_4G
+};
+
void msmc_share_all_segments(int priv_id);
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
#endif
--
1.8.3.2
___
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[U-Boot] [U-boot] [Patch v2 4/4] ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr
From: Hao Zhang hzh...@ti.com
Add ddr3 commands:
test start_addr in hex end_addr in hex - test DDR from start\n
address to end address\n
ddr compare start_addr in hex end_addr in hex size in hex -\n
compare DDR data of (size) bytes from start address to end
address\n
ddr ecc_err addr in hex bit_err in hex - generate bit errors\n
in DDR data at addr, the command will read a 32-bit data\n
from addr, and write (data ^ bit_err) back to addr\n
Delete CONFIG_MAX_UBOOT_MEM_SIZE, as it was supposed to be used
for ddr3 commands and for now it's not needed any more.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 2 +-
arch/arm/cpu/armv7/keystone/cmd_ddr3.c | 247 +
include/configs/ks2_evm.h | 4 -
3 files changed, 248 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/cpu/armv7/keystone/cmd_ddr3.c
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 57f6ea6..ed030db 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -14,5 +14,5 @@ obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
-obj-y += ddr3.o
+obj-y += ddr3.o cmd_ddr3.o
obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
new file mode 100644
index 000..e85027b
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
@@ -0,0 +1,247 @@
+/*
+ * Keystone2: DDR3 test commands
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include asm/arch/hardware.h
+#include asm/arch/ddr3.h
+#include common.h
+#include command.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define DDR_REMAP_ADDR 0x8000
+#define ECC_START_ADDR1((DDR_MIN_ADDR - DDR_REMAP_ADDR) 17)
+
+#define ECC_END_ADDR1 (((gd-start_addr_sp - DDR_REMAP_ADDR - \
+CONFIG_STACKSIZE) 17) - 2)
+
+#define DDR_TEST_BURST_SIZE1024
+
+static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
+{
+ u32 index_start, value, index;
+
+ index_start = start_address;
+
+ while (1) {
+ /* Write a pattern */
+ for (index = index_start;
+ index index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel(index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != index) {
+ printf(ddr_memory_test: Failed at address
index = 0x%x value = 0x%x *(index) = 0x%x\n,
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start = end_address)
+ break;
+
+ if (quick)
+ continue;
+
+ /* Write a pattern for complementary values */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 4)
+ __raw_writel((u32)~index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 4) {
+ value = __raw_readl(index);
+ if (value != ~index) {
+ printf(ddr_memory_test: Failed at address
index = 0x%x value = 0x%x *(index) = 0x%x\n,
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start = end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 2)
+ __raw_writew((u16)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+index index_start + DDR_TEST_BURST_SIZE;
+index += 2) {
+ value = __raw_readw(index);
+ if (value != (u16)index
[U-Boot] [U-boot] [Patch v5 0/6] keystone2: add k2l SoC and k2l_evm board support
This patch series adds Keystone II Lamar (K2L) SoC and k2l_evm board support. Based on [U-boot] [Patch v2] keystone: usb: add support of usb xhci https://patchwork.ozlabs.org/patch/386506/ v5..v4 - ARM: keystone2: spl: move board specific code this patch replace ARM: keystone2: spl: add K2L SoC support as result of moving board specific code to board directory. v4..v3 - keystone2: k2l-evm: add board support remove dimm name reading v3..v2 - keystone2: k2l-evm: add board support Add maintainers information Enable SPL by default v2..v1 Rebased according to changes of c338f09e965a300ddd78af73e86c4af4c9464ce4 keystone: kconfig: move board select menu and common settings Hao Zhang (6): ARM: keystone2: add K2L device hardware definitions keystone2: clock: add K2L clock definitions and commands keystone2: msmc: add MSMC cache coherency support for K2L SOC ARM: keystone2: spl: move board specific code keystone2: enable OSR clock domain for K2L SoC keystone2: k2l-evm: add board support arch/arm/cpu/armv7/keystone/Kconfig| 3 + arch/arm/cpu/armv7/keystone/Makefile | 2 +- arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 + arch/arm/cpu/armv7/keystone/cmd_clock.c| 10 ++ arch/arm/cpu/armv7/keystone/init.c | 52 arch/arm/cpu/armv7/keystone/spl.c | 53 arch/arm/include/asm/arch-keystone/clock-k2l.h | 94 ++ arch/arm/include/asm/arch-keystone/clock.h | 4 + arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 - arch/arm/include/asm/arch-keystone/hardware-k2l.h | 99 +++ arch/arm/include/asm/arch-keystone/hardware.h | 14 +++ arch/arm/include/asm/arch-keystone/spl.h | 12 -- board/ti/ks2_evm/Kconfig | 16 +++ board/ti/ks2_evm/MAINTAINERS | 2 + board/ti/ks2_evm/Makefile | 2 + board/ti/ks2_evm/board.c | 19 +++ board/ti/ks2_evm/board.h | 1 + board/ti/ks2_evm/board_k2e.c | 11 ++ board/ti/ks2_evm/board_k2hk.c | 12 ++ board/ti/ks2_evm/board_k2l.c | 72 +++ board/ti/ks2_evm/ddr3_cfg.c| 36 ++ board/ti/ks2_evm/ddr3_cfg.h| 3 + board/ti/ks2_evm/ddr3_k2l.c| 38 ++ configs/k2l_evm_defconfig | 4 + include/configs/k2l_evm.h | 37 ++ 25 files changed, 668 insertions(+), 68 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c delete mode 100644 arch/arm/cpu/armv7/keystone/spl.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h delete mode 100644 arch/arm/include/asm/arch-keystone/spl.h create mode 100644 board/ti/ks2_evm/board_k2l.c create mode 100644 board/ti/ks2_evm/ddr3_k2l.c create mode 100644 configs/k2l_evm_defconfig create mode 100644 include/configs/k2l_evm.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v5 1/6] ARM: keystone2: add K2L device hardware definitions
From: Hao Zhang hzh...@ti.com
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 -
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 74 ++
arch/arm/include/asm/arch-keystone/hardware.h | 13
3 files changed, 87 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 43c2c42..2db806c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644
index 000..3402d0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,74 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x2600
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DFE_IQN_SYS 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PAKS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMACKS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO9
+#define KS2_LPSC_PCIE0 10
+#define KS2_LPSC_PCIE1 11
+#define KS2_LPSC_JESD_MISC 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_DDUC4X_CFR2X_BB 27
+#define KS2_LPSC_FFTC_A28
+#define KS2_LPSC_OSR 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 37
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_VCP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DPD4X 48
+#define KS2_LPSC_FFTC_B49
+#define KS2_LPSC_IQN_AIL 50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
+#define KS2_NETCP_PDMA_TX_BASE 0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE896
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index c1642a5..adae69e 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -143,6 +143,7 @@ typedef volatile unsigned int *dv_reg_p;
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
#define KS2_QM_BASE_ADDRESS0x23a8
@@ -177,6 +178,10 @@ typedef volatile unsigned int *dv_reg_p;
#include asm/arch/hardware-k2e.h
#endif
+#ifdef CONFIG_SOC_K2L
+#include asm/arch/hardware-k2l.h
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
@@ -194,6 +199,14 @@ static inline int cpu_is_k2e(void)
return (part_no == 0xb9a6) ? 1 : 0
[U-Boot] [U-boot] [Patch v5 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
From: Hao Zhang hzh...@ti.com This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Hao Zhang hzh...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/cpu/armv7/keystone/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index a8f8aee..a0ecfa2 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -32,6 +32,9 @@ int arch_cpu_init(void) #ifdef CONFIG_SOC_K2E msmc_share_all_segments(13); /* PCIE 1 */ #endif +#ifdef CONFIG_SOC_K2L + msmc_share_all_segments(14); /* PCIE 1 */ +#endif /* * just initialise the COM2 port so that TI specific -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v5 6/6] keystone2: k2l-evm: add board support
From: Hao Zhang hzh...@ti.com
This patch adds Keystone II Lammar (K2L) EVM board support.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Kconfig| 3 ++
arch/arm/include/asm/arch-keystone/clock-k2l.h | 6 +++
board/ti/ks2_evm/Kconfig | 16 ++
board/ti/ks2_evm/MAINTAINERS | 2 +
board/ti/ks2_evm/Makefile | 2 +
board/ti/ks2_evm/board_k2l.c | 72 ++
board/ti/ks2_evm/ddr3_cfg.c| 36 +
board/ti/ks2_evm/ddr3_cfg.h| 3 ++
board/ti/ks2_evm/ddr3_k2l.c| 38 ++
configs/k2l_evm_defconfig | 4 ++
include/configs/k2l_evm.h | 37 +
11 files changed, 219 insertions(+)
create mode 100644 board/ti/ks2_evm/board_k2l.c
create mode 100644 board/ti/ks2_evm/ddr3_k2l.c
create mode 100644 configs/k2l_evm_defconfig
create mode 100644 include/configs/k2l_evm.h
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig
b/arch/arm/cpu/armv7/keystone/Kconfig
index 24d0cbe..91211fd 100644
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ b/arch/arm/cpu/armv7/keystone/Kconfig
@@ -9,6 +9,9 @@ config TARGET_K2HK_EVM
config TARGET_K2E_EVM
bool TI Keystone 2 Edison EVM
+config TARGET_K2L_EVM
+ bool TI Keystone 2 Lamar EVM
+
endchoice
config SYS_CPU
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h
b/arch/arm/include/asm/arch-keystone/clock-k2l.h
index 8cacee0..b3f4e71 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h
@@ -69,7 +69,9 @@ enum {
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
@@ -78,8 +80,12 @@ enum {
#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1000{TETRIS_PLL, 114, 7, 2}
#define TETRIS_PLL_1167{TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1198{TETRIS_PLL, 39, 2, 2}
#define TETRIS_PLL_1228{TETRIS_PLL, 20, 1, 2}
+#define TETRIS_PLL_1352{TETRIS_PLL, 22, 1, 2}
+#define TETRIS_PLL_1401{TETRIS_PLL, 114, 5, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index 3108782..36c31ff 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -29,3 +29,19 @@ config SYS_CONFIG_NAME
default k2hk_evm
endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+ string
+ default ks2_evm
+
+config SYS_VENDOR
+ string
+ default ti
+
+config SYS_CONFIG_NAME
+ string
+ default k2l_evm
+
+endif
diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS
index 595a80a..87c36c9 100644
--- a/board/ti/ks2_evm/MAINTAINERS
+++ b/board/ti/ks2_evm/MAINTAINERS
@@ -6,3 +6,5 @@ F: include/configs/k2hk_evm.h
F: configs/k2hk_evm_defconfig
F: include/configs/k2e_evm.h
F: configs/k2e_evm_defconfig
+F: include/configs/k2l_evm.h
+F: configs/k2l_evm_defconfig
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 00f1164..071dbee 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
new file mode 100644
index 000..559d20c
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -0,0 +1,72 @@
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/ddr3.h
+#include asm/arch/hardware.h
+#include asm/ti-common/ti-aemif.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 12288,
+ [alt_core_clk] = 1,
+ [pa_clk]= 12288,
+ [tetris_clk]= 12288,
+ [ddr3_clk] = 1,
+ [pcie_clk] = 1,
+ [sgmii_clk] = 15625,
+ [usb_clk] = 1,
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_1000
[U-Boot] [U-boot] [Patch v5 5/6] keystone2: enable OSR clock domain for K2L SoC
From: Hao Zhang hzh...@ti.com
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/init.c| 49 +++
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 25
arch/arm/include/asm/arch-keystone/hardware.h | 1 +
3 files changed, 75 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/init.c
b/arch/arm/cpu/armv7/keystone/init.c
index a0ecfa2..2228132 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
#include asm/arch/msmc.h
#include asm/arch/clock.h
#include asm/arch/hardware.h
+#include asm/arch/psc_defs.h
void chip_configuration_unlock(void)
{
@@ -20,6 +21,53 @@ void chip_configuration_unlock(void)
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+ u32 i;
+ u32 j;
+ u32 val;
+ u32 base = KS2_OSR_CFG_BASE;
+ u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+ /* Enable the OSR clock domain */
+ psc_enable_module(KS2_LPSC_OSR);
+
+ /* Disable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++) {
+ val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+ (KS2_OSR_ECC_CTRL KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+ writel(val , base + KS2_OSR_ECC_VEC);
+
+ /**
+* wait till read is done.
+* Print should be added after earlyprintk support is added.
+*/
+ for (j = 0; j 1; j++) {
+ val = readl(base + KS2_OSR_ECC_VEC);
+ if (val KS2_OSR_ECC_VEC_RD_DONE)
+ break;
+ }
+
+ ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+ KS2_OSR_ECC_CTRL_CHK;
+
+ writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+ writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+ }
+
+ /* Reset OSR memory to all zeros */
+ for (i = 0; i KS2_OSR_SIZE; i += 4)
+ writel(0, KS2_OSR_DATA_BASE + i);
+
+ /* Enable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++)
+ writel(ecc_ctrl[i] |
+ KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
@@ -34,6 +82,7 @@ int arch_cpu_init(void)
#endif
#ifdef CONFIG_SOC_K2L
msmc_share_all_segments(14); /* PCIE 1 */
+ osr_init();
#endif
/*
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index 3402d0c..dfde040 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -57,6 +57,31 @@
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+/* OSR */
+#define KS2_OSR_DATA_BASE 0x7000 /* OSR data base */
+#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
+#define KS2_OSR_ECC_VEC0x08/* ECC Vector
reg */
+#define KS2_OSR_ECC_CTRL 0x14/* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RDBIT(15) /* trigger a
read op */
+#define KS2_OSR_ECC_VEC_RD_DONEBIT(24) /* read
complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_ENBIT(0) /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS 4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE 0x10
+
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 4
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index adae69e..29f7bf1 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -163,6 +163,7 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc0
+#define KS2_MSMC_DATA_BASE 0x0c00
/* USB */
#define KS2_USB_SS_BASE0x0268
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v5 4/6] ARM: keystone2: spl: move board specific code
From: Hao Zhang hzh...@ti.com
The initialization of PLLs is a part of board specific code, so
move it appropriate places.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 1 -
arch/arm/cpu/armv7/keystone/spl.c| 53
arch/arm/include/asm/arch-keystone/spl.h | 12
board/ti/ks2_evm/board.c | 19
board/ti/ks2_evm/board.h | 1 +
board/ti/ks2_evm/board_k2e.c | 11 +++
board/ti/ks2_evm/board_k2hk.c| 12
7 files changed, 43 insertions(+), 66 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/keystone/spl.c
delete mode 100644 arch/arm/include/asm/arch-keystone/spl.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 4750371..57f6ea6 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -14,6 +14,5 @@ obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
-obj-$(CONFIG_SPL_BUILD)+= spl.o
obj-y += ddr3.o
obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/spl.c
b/arch/arm/cpu/armv7/keystone/spl.c
deleted file mode 100644
index d4b0e9b..000
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * common spl init code
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, www.ti.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include common.h
-#include config.h
-#include ns16550.h
-#include malloc.h
-#include spl.h
-#include spi_flash.h
-
-#include asm/u-boot.h
-#include asm/utils.h
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_K2HK_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_799,
- TETRIS_PLL_500,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_800,
-};
-#endif
-
-void spl_init_keystone_plls(void)
-{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
-}
-
-void spl_board_init(void)
-{
- spl_init_keystone_plls();
- preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-#if defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#else
- puts(Unknown boot device\n);
- hang();
-#endif
-}
diff --git a/arch/arm/include/asm/arch-keystone/spl.h
b/arch/arm/include/asm/arch-keystone/spl.h
deleted file mode 100644
index a7102d5..000
--- a/arch/arm/include/asm/arch-keystone/spl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012-2014
- * Texas Instruments, www.ti.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_SPI2
-
-#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index dfe7be6..c07d284 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -9,6 +9,7 @@
#include board.h
#include common.h
+#include spl.h
#include exports.h
#include fdt_support.h
#include asm/arch/ddr3.h
@@ -83,6 +84,24 @@ int board_eth_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts(Unknown boot device\n);
+ hang();
+#endif
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT) defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index d91ef73..7a613ac 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -15,5 +15,6 @@
extern struct eth_priv_t eth_priv_cfg[];
int get_num_eth_ports(void);
+void spl_init_keystone_plls(void);
#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 5472a43..810a8e2 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -52,3 +52,14 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_800,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index 6fb3d21..d7dd292 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -100,3 +100,15 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v5 2/6] keystone2: clock: add K2L clock definitions and commands
From: Hao Zhang hzh...@ti.com
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 1 +
arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 +
arch/arm/cpu/armv7/keystone/cmd_clock.c| 10 ++
arch/arm/include/asm/arch-keystone/clock-k2l.h | 88
arch/arm/include/asm/arch-keystone/clock.h | 4 +
5 files changed, 241 insertions(+)
create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c
create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 3d8fb70..4750371 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,6 +10,7 @@ obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c
b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644
index 000..1c5e4d5
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/clock.h
+#include asm/arch/clock_defs.h
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = (((tmp PLLM_MULT_HI_SMASK) 6) |
+ (pllctl_reg_read(pll, mult)
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl)
+ PLL_CLKOD_SHIFT) PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+ if (!(tmp PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = ((tmp PLL_MULT_SHIFT) PLL_MULT_MASK) + 1;
+ output_div = ((tmp PLL_CLKOD_SHIFT)
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk:return pll_freq_get(TETRIS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case
[U-Boot] [U-boot] [Patch v4 0/6] keystone2: add k2l SoC and k2l_evm board support
This patch series adds Keystone II Lamar (K2L) SoC and k2l_evm board support. Based on [U-boot] [Patch v2] keystone: usb: add support of usb xhci https://patchwork.ozlabs.org/patch/386506/ v4..v3 - keystone2: k2l-evm: add board support remove dimm name reading v3..v2 - keystone2: k2l-evm: add board support Add maintainers information Enable SPL by default v2..v1 Rebased according to changes of c338f09e965a300ddd78af73e86c4af4c9464ce4 keystone: kconfig: move board select menu and common settings Hao Zhang (6): ARM: keystone2: add K2L device hardware definitions keystone2: clock: add K2L clock definitions and commands keystone2: msmc: add MSMC cache coherency support for K2L SOC ARM: keystone2: spl: add K2L SoC support keystone2: enable OSR clock domain for K2L SoC keystone2: k2l-evm: add board support arch/arm/cpu/armv7/keystone/Kconfig| 3 + arch/arm/cpu/armv7/keystone/Makefile | 1 + arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 + arch/arm/cpu/armv7/keystone/cmd_clock.c| 10 ++ arch/arm/cpu/armv7/keystone/init.c | 52 arch/arm/cpu/armv7/keystone/spl.c | 7 ++ arch/arm/include/asm/arch-keystone/clock-k2l.h | 94 ++ arch/arm/include/asm/arch-keystone/clock.h | 4 + arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 - arch/arm/include/asm/arch-keystone/hardware-k2l.h | 99 +++ arch/arm/include/asm/arch-keystone/hardware.h | 14 +++ board/ti/ks2_evm/Kconfig | 16 +++ board/ti/ks2_evm/MAINTAINERS | 2 + board/ti/ks2_evm/Makefile | 2 + board/ti/ks2_evm/board_k2l.c | 60 + board/ti/ks2_evm/ddr3_cfg.c| 36 ++ board/ti/ks2_evm/ddr3_cfg.h| 3 + board/ti/ks2_evm/ddr3_k2l.c| 43 +++ configs/k2l_evm_defconfig | 4 + include/configs/k2l_evm.h | 37 ++ 20 files changed, 625 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h create mode 100644 board/ti/ks2_evm/board_k2l.c create mode 100644 board/ti/ks2_evm/ddr3_k2l.c create mode 100644 configs/k2l_evm_defconfig create mode 100644 include/configs/k2l_evm.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v4 1/6] ARM: keystone2: add K2L device hardware definitions
From: Hao Zhang hzh...@ti.com
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 -
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 74 ++
arch/arm/include/asm/arch-keystone/hardware.h | 13
3 files changed, 87 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 43c2c42..2db806c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644
index 000..3402d0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,74 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x2600
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DFE_IQN_SYS 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PAKS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMACKS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO9
+#define KS2_LPSC_PCIE0 10
+#define KS2_LPSC_PCIE1 11
+#define KS2_LPSC_JESD_MISC 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_DDUC4X_CFR2X_BB 27
+#define KS2_LPSC_FFTC_A28
+#define KS2_LPSC_OSR 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 37
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_VCP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DPD4X 48
+#define KS2_LPSC_FFTC_B49
+#define KS2_LPSC_IQN_AIL 50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
+#define KS2_NETCP_PDMA_TX_BASE 0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE896
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index c1642a5..adae69e 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -143,6 +143,7 @@ typedef volatile unsigned int *dv_reg_p;
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
#define KS2_QM_BASE_ADDRESS0x23a8
@@ -177,6 +178,10 @@ typedef volatile unsigned int *dv_reg_p;
#include asm/arch/hardware-k2e.h
#endif
+#ifdef CONFIG_SOC_K2L
+#include asm/arch/hardware-k2l.h
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
@@ -194,6 +199,14 @@ static inline int cpu_is_k2e(void)
return (part_no == 0xb9a6) ? 1 : 0
[U-Boot] [U-boot] [Patch v4 4/6] ARM: keystone2: spl: add K2L SoC support
From: Hao Zhang hzh...@ti.com
Add Keystone II Lamar (K2L) SoC support.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/spl.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/spl.c
b/arch/arm/cpu/armv7/keystone/spl.c
index d4b0e9b..6a3adf4 100644
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ b/arch/arm/cpu/armv7/keystone/spl.c
@@ -31,6 +31,13 @@ static struct pll_init_data spl_pll_config[] = {
};
#endif
+#ifdef CONFIG_K2L_EVM
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_491,
+};
+#endif
+
void spl_init_keystone_plls(void)
{
init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v4 5/6] keystone2: enable OSR clock domain for K2L SoC
From: Hao Zhang hzh...@ti.com
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/init.c| 49 +++
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 25
arch/arm/include/asm/arch-keystone/hardware.h | 1 +
3 files changed, 75 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/init.c
b/arch/arm/cpu/armv7/keystone/init.c
index a0ecfa2..2228132 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
#include asm/arch/msmc.h
#include asm/arch/clock.h
#include asm/arch/hardware.h
+#include asm/arch/psc_defs.h
void chip_configuration_unlock(void)
{
@@ -20,6 +21,53 @@ void chip_configuration_unlock(void)
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+ u32 i;
+ u32 j;
+ u32 val;
+ u32 base = KS2_OSR_CFG_BASE;
+ u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+ /* Enable the OSR clock domain */
+ psc_enable_module(KS2_LPSC_OSR);
+
+ /* Disable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++) {
+ val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+ (KS2_OSR_ECC_CTRL KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+ writel(val , base + KS2_OSR_ECC_VEC);
+
+ /**
+* wait till read is done.
+* Print should be added after earlyprintk support is added.
+*/
+ for (j = 0; j 1; j++) {
+ val = readl(base + KS2_OSR_ECC_VEC);
+ if (val KS2_OSR_ECC_VEC_RD_DONE)
+ break;
+ }
+
+ ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+ KS2_OSR_ECC_CTRL_CHK;
+
+ writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+ writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+ }
+
+ /* Reset OSR memory to all zeros */
+ for (i = 0; i KS2_OSR_SIZE; i += 4)
+ writel(0, KS2_OSR_DATA_BASE + i);
+
+ /* Enable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++)
+ writel(ecc_ctrl[i] |
+ KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
@@ -34,6 +82,7 @@ int arch_cpu_init(void)
#endif
#ifdef CONFIG_SOC_K2L
msmc_share_all_segments(14); /* PCIE 1 */
+ osr_init();
#endif
/*
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index 3402d0c..dfde040 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -57,6 +57,31 @@
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+/* OSR */
+#define KS2_OSR_DATA_BASE 0x7000 /* OSR data base */
+#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
+#define KS2_OSR_ECC_VEC0x08/* ECC Vector
reg */
+#define KS2_OSR_ECC_CTRL 0x14/* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RDBIT(15) /* trigger a
read op */
+#define KS2_OSR_ECC_VEC_RD_DONEBIT(24) /* read
complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_ENBIT(0) /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS 4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE 0x10
+
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 4
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index adae69e..29f7bf1 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -163,6 +163,7 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc0
+#define KS2_MSMC_DATA_BASE 0x0c00
/* USB */
#define KS2_USB_SS_BASE0x0268
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
From: Hao Zhang hzh...@ti.com This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Hao Zhang hzh...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/cpu/armv7/keystone/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index a8f8aee..a0ecfa2 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -32,6 +32,9 @@ int arch_cpu_init(void) #ifdef CONFIG_SOC_K2E msmc_share_all_segments(13); /* PCIE 1 */ #endif +#ifdef CONFIG_SOC_K2L + msmc_share_all_segments(14); /* PCIE 1 */ +#endif /* * just initialise the COM2 port so that TI specific -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
From: Hao Zhang hzh...@ti.com
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 1 +
arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 +
arch/arm/cpu/armv7/keystone/cmd_clock.c| 10 ++
arch/arm/include/asm/arch-keystone/clock-k2l.h | 88
arch/arm/include/asm/arch-keystone/clock.h | 4 +
5 files changed, 241 insertions(+)
create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c
create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 3d8fb70..4750371 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,6 +10,7 @@ obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c
b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644
index 000..1c5e4d5
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/clock.h
+#include asm/arch/clock_defs.h
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = (((tmp PLLM_MULT_HI_SMASK) 6) |
+ (pllctl_reg_read(pll, mult)
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl)
+ PLL_CLKOD_SHIFT) PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+ if (!(tmp PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = ((tmp PLL_MULT_SHIFT) PLL_MULT_MASK) + 1;
+ output_div = ((tmp PLL_CLKOD_SHIFT)
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk:return pll_freq_get(TETRIS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case
