Hi,
> > > - if (ret)
> > > + if (ret == -ENOENT)
> > > + return -ENOPKG;
>
> We normally use -ENOENT for this sort of thing.
That's the way select_ramdisk() is documented. It was actually
introduced by yourself in commit e4c92879
oot again:
fastboot --base 0x4100 --header-version 2 --dtb /path/to/dtb \
--cmdline "root=/dev/mmcblk0p1 rootwait" boot path/to/Image
Signed-off-by: Michael Walle
---
boot/image-android.c | 7 +++
boot/image-board.c | 4 +++-
include/image.h | 2 +-
3 files changed,
error in the (valid) case that there is no ramdisk in the image.
With this, I'm able to boot a linux kernel using fastboot again:
fastboot --base 0x4100 --header-version 2 --dtb /path/to/dtb \
--cmdline "root=/dev/mmcblk0p1 rootwait" boot path/to/Image
Signed-off-by: Micha
.
While at it, correct the comment above the calculation.
Signed-off-by: Michael Walle
---
drivers/spi/spi-sunxi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index f110a8b7658..81f1298adea 100644
--- a/drivers/spi/spi
igns the CDR2 calculation with the linux driver.
Suggested-by: Andre Przywara
Signed-off-by: Michael Walle
---
drivers/spi/spi-sunxi.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index bfb402902b8..f110a8b7658 100644
> > - if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
> > + if (div != 1 && ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1))) {
> > div /= 2;
>
> This is still not fully correct, is it? If I ask for 10 MHz, the
> algorithm should select 8 MHz (24/3) or actually 6 MHz (24/4), but it
>
whole max_hz handling.
>
> Looks good to me, I verified this by timing the read, this patch indeed
> significantly increases the performance. Also changing the limit in the
> DT gets reflected in the driver and in the read speed. Also verified
> that the values read from the SPI flash a
Right now, the maximal transfer speed from an SPI flash on a V3s is
about 240kb/s. That is pretty slow. It turns out, that due to an
error u-boot is setting the maximum frequency to 1MHz. By fixing
that another bug is unearthed: one cannot set a clock divider of 1:1
due to the handling between CDR
.
While at it, correct the comment above the calculation.
Signed-off-by: Michael Walle
---
drivers/spi/spi-sunxi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index bfb402902b8..3048ab0ecf7 100644
--- a/drivers/spi/spi
flash reads are very slow with just about 215kb/s.
In fact, the SPI uclass will already take care of everything and we just
have to clamp the frequency to the values the driver/hardware supports.
Thus, drop the whole max_hz handling.
Signed-off-by: Michael Walle
---
drivers/
CDR1 and CDR2 handling. By fixing that
I achieved loading speeds of about 1.5MB/s.
Michael Walle (2):
spi: sunxi: drop max_hz handling
spi: sunxi: fix clock divider calculation for max frequency setting
drivers/spi/spi-sunxi.c | 28 +++-
1 file changed, 15 insertions
Due to the lazy probing, the gadget driver might not be probed when the
u-boot cli is active. In this case the "ums" command won't work, for
example. If enabled, probe the USB gadget during board_init().
Signed-off-by: Michael Walle
---
board/sunxi/board.c | 4
1 file change
On Tue May 14, 2024 at 1:43 AM CEST, Michael Walle wrote:
> The V3s is identical regarding register layout, clocks and resets to
> the sun6i variants. Therefore, we can just add the MACH_SUN8I_V3S to
> the sun6i compatible ones.
>
> SPI boot was tested on a custom board with a Gig
Hi,
On Mon May 13, 2024 at 10:56 PM CEST, Michael Walle wrote:
> Add network support for the V3s which only supports the internal
> PHY. Adding support was straight forward. The emac driver just needs
> the compatible string and some platform data and the clock driver
> needs to know
On Tue Jun 4, 2024 at 9:47 AM CEST, Christian Loehle wrote:
> On 6/3/24 22:28, Tim Harvey wrote:
> > On Mon, Jun 3, 2024 at 1:18 AM Christian Loehle
> > wrote:
> >>
> >> On 5/31/24 21:47, Tim Harvey wrote:
> >>> Greetings,
> >>>
> >>> I'm seeing an issue on an imx8mm board (imx8mm-venice-gw73xx) w
The V3s is identical regarding register layout, clocks and resets to
the sun6i variants. Therefore, we can just add the MACH_SUN8I_V3S to
the sun6i compatible ones.
SPI boot was tested on a custom board with a Gigadevice GD25Q64 8MiB
SPI flash.
Signed-off-by: Michael Walle
---
arch/arm/mach
Add the compatible string for the emac found on the V3s SoC. The SoC
only supports the internal PHY. There are no (R)MII signals on any pins.
Signed-off-by: Michael Walle
---
drivers/net/sun8i_emac.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/sun8i_emac.c b/drivers
Add the clock gate registers as well as the reset register bits for the
EMAC and EPHY for the V3s. These are needed by the sun8i network driver.
Signed-off-by: Michael Walle
---
drivers/clk/sunxi/clk_v3s.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/sunxi/clk_v3s.c b
custom board.
Michael Walle (2):
clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC
net: sun8i_emac: add support for the V3s
drivers/clk/sunxi/clk_v3s.c | 6 ++
drivers/net/sun8i_emac.c| 7 +++
2 files changed, 13 insertions(+)
--
2.39.2
On Wed May 1, 2024 at 4:41 AM CEST, Tom Rini wrote:
> Remove from this board vendor directory and when needed
> add missing include files directly.
>
> Signed-off-by: Tom Rini
Acked-by: Michael Walle
On Wed May 1, 2024 at 4:42 AM CEST, Tom Rini wrote:
> Remove from this board vendor directory and when needed
> add missing include files directly.
>
> Signed-off-by: Tom Rini
Acked-by: Michael Walle
Hi,
On Thu Apr 25, 2024 at 8:19 AM CEST, Ilias Apalodimas wrote:
> I've cc'ed all the people I could find in board specific MAINTAINER files.
> Can you respond to Richard with the proper company name & board name
> so we can bind the following GUIDs to a vendor properly?
> Richard any guidance on
On Wed Mar 6, 2024 at 5:19 PM CET, Michael Walle wrote:
> Use the new device devicetree files in dts/upstream/ and delete the old
> ones. Still keep the -u-boot.dtsi with all u-boot specifics around.
>
> There is one catch and that is fsl-ls1028a-kontron-sl28-var3.dts which
> i
Hi,
On Fri Apr 12, 2024 at 5:03 AM CEST, Neha Malcom Francis wrote:
> On 05/04/24 13:12, Michael Walle wrote:
> > On Thu Apr 4, 2024 at 11:10 AM CEST, Neha Malcom Francis wrote:
> >> But again in the interest of time... this would mean this cleaning up
> >> effort be
&
Hi,
On Thu Apr 4, 2024 at 11:10 AM CEST, Neha Malcom Francis wrote:
> But again in the interest of time... this would mean this cleaning up effort
> be
> kept on hold. If we can agree to move to using the generator later as the
> final
> solution, can we pick up this series for now?
Agreed. I
Hi,
> > > > > And on top of that, it will just be a base board and there will
> > > > > likely be some carrier device trees (overlay? I'm not sure yet).
> > > > >
> > > > > As far as I can tell, you've put the memory configuration into the
> > > > > device tree, so I'll probably need to switch be
size.
Fixes: 38922b1f4acc ("net: ti: am65-cpsw: Add support for multi port
independent MAC mode")
Signed-off-by: Michael Walle
---
drivers/net/ti/am65-cpsw-nuss.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti
On Thu Mar 28, 2024 at 4:09 PM CET, Tom Rini wrote:
> On Mon, Jan 01, 2024 at 10:07:47PM +0100, Marek Vasut wrote:
>
> > Configure LEDs on BCM54210E so they would blink on activity
> > and indicate link speed. Without this the LEDs are always on
> > if cable is plugged in.
> >
> > Signed-off-by: M
Hi,
On Thu Mar 28, 2024 at 12:18 PM CET, Neha Malcom Francis wrote:
> On 27-Mar-24 8:03 PM, Michael Walle wrote:
> > On Wed Mar 27, 2024 at 8:01 AM CET, Neha Malcom Francis wrote:
> >> On 26/03/24 19:18, Michael Walle wrote:
> >>> On Fri Mar 22, 2024 at 2:10 PM
bx81lifxcat.dts: No such
> file or directory
...
Are you sure you want to have all this text in the commit log?
You seem to have forgotten my tag:
Tested-by: Michael Walle # on lschv2
Hi,
On Wed Mar 27, 2024 at 8:01 AM CET, Neha Malcom Francis wrote:
> On 26/03/24 19:18, Michael Walle wrote:
> > On Fri Mar 22, 2024 at 2:10 PM CET, Neha Malcom Francis wrote:
> >> Clean up templatized boot binaries for all K3 boards. This includes
> >> modifyin
Hi,
On Fri Mar 22, 2024 at 2:10 PM CET, Neha Malcom Francis wrote:
> Clean up templatized boot binaries for all K3 boards. This includes
> modifying the k3-binman.dtsi to use SPL_BOARD_DTB, BOARD_DESCRIPTION and
> UBOOT_BOARD_DESCRIPTION from the files that include it to further reuse
> code.
>
>
ey have to look.
Signed-off-by: Michael Walle
---
tools/binman/etype/ti_board_config.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/etype/ti_board_config.py
b/tools/binman/etype/ti_board_config.py
index 2c3bb8f7b56..c10d66edcb1 100644
--- a/too
rom arch/arm/dts/ directory.
Thanks for taking care.
> Signed-off-by: Tony Dinh
Tested-by: Michael Walle # on lschlv2
lsxl should work too as it is just different in memory and cpu
frequency settings.
> ---
>
> arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi | 6 --
> ar
this only differ in the compatible and the (human readable)
model name.
Signed-off-by: Michael Walle
---
I'll send a patch to linux to add the var3.dts, then I'll add the
correct var3 dts again.
---
.../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 59
.../arm/dts/fsl-ls1028a-kontron
Hi,
On Wed Mar 6, 2024 at 3:56 AM CET, Marek Vasut wrote:
> > I'd argue if one wants to use the locking at all, you have to set
> > UNLOCK_ALL=n. Otherwise, the bootloader might come alone and just
> > clear your locking bits again. Clearing the WPS bit there is just
> > one more thing which IMHO
On Tue Mar 5, 2024 at 7:54 PM CET, Marek Vasut wrote:
> On 3/5/24 5:55 PM, Michael Walle wrote:
>
> [...]
>
> >>>>>> Clearing this SR3 WPS bit fixes that problem, both in U-Boot and in
> >>>>>> Linux, since Linux that is booted afterwa
On Tue Mar 5, 2024 at 5:28 PM CET, Marek Vasut wrote:
> On 3/5/24 4:53 PM, Michael Walle wrote:
> > On Tue Mar 5, 2024 at 4:37 PM CET, Marek Vasut wrote:
> >> On 3/5/24 1:50 PM, Michael Walle wrote:
> >>> On Tue Mar 5, 2024 at 1:31 PM CET, Marek Vasut wrote:
> >
On Tue Mar 5, 2024 at 4:37 PM CET, Marek Vasut wrote:
> On 3/5/24 1:50 PM, Michael Walle wrote:
> > Hi Marek,
>
> Hi,
>
> > On Tue Mar 5, 2024 at 1:31 PM CET, Marek Vasut wrote:
> >> On 3/5/24 9:55 AM, Michael Walle wrote:
> >>> On Mon Mar 4, 2024 a
Hi Marek,
On Tue Mar 5, 2024 at 1:31 PM CET, Marek Vasut wrote:
> On 3/5/24 9:55 AM, Michael Walle wrote:
> > On Mon Mar 4, 2024 at 5:16 PM CET, Marek Vasut wrote:
> >> Some Winbond SPI NORs have special SR3 register which is
> >> used among other things to c
[+ linux-mtd ]
Hi Marek,
On Mon Mar 4, 2024 at 5:16 PM CET, Marek Vasut wrote:
> Some Winbond SPI NORs have special SR3 register which is
> used among other things to control whether non-standard
> "Individual Block/Sector Write Protection" (WPS bit)
> locking scheme is activated. This non-standa
Using CONFIG_EXTRA_ENV_SETTINGS should be good enough to provide
the fallback defaults. However, the users can still mess the things
up,
but again, they can do that already in many places.
I disagree. In my case that is a last resort recovery. And it should
work in any case. Even if the user
Hi,
Using CONFIG_EXTRA_ENV_SETTINGS should be good enough to provide
the fallback defaults. However, the users can still mess the things
up,
but again, they can do that already in many places.
I disagree. In my case that is a last resort recovery. And it should
work in any case. Even if the
>> This is simply awesome, but I see one possible issue -- the need to have
>> proper environment variables defined for a particular board or device,
>> to make the buttons work as expected. Obviously, those environment
>> variables can be absent or can become missing for numerous reasons.
>
> Is
Hi Mark,
> Any runtime device drivers for variable storage should not be in the
> U-Boot runtime but live in the secure world (e.g. OP-TEE) FF-A is the
> new ARM protocol for talking to the secure world and hence fits into
> the picture.
What if I just want a simple embedded boot stack where I
Hi Heinrich,
> Any runtime device drivers for variable storage should not be in the
> U-Boot runtime but live in the secure world (e.g. OP-TEE) FF-A is the
> new ARM protocol for talking to the secure world and hence fits into
> the picture.
What if I just want a simple embedded boot stack where
Hi,
+static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int
argc,
+ char *const argv[])
+{
..
+ printf("Caution! OTP data bits can't be erased! Continue
(y/n)?\n");
Please note, that with current SPI-NOR flashes this is not true and
there is usually some kind of
+static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
..
+ printf("Caution! OTP data bits can't be erased! Continue (y/n)?\n");
Please note, that with current SPI-NOR flashes this is not true and
there is usually some
Hi,
I'm still not sure why that compatible is needed. Also I'd need to
change
the label which might break user space apps looking for that specific
name.
Also, our board might have u-boot/spl or u-boot/spl/bl31/bl32, right
now
that's something which depends on an u-boot configuration variable
Hi,
>> >> Add a compatible string for binman, so we can extend fixed-partitions
>> >> in various ways.
>> >
>> > I've been thinking at the proper way to describe the binman partitions.
>> > I am wondering if we should really extend the fixed-partitions
>> > schema. This description is really bas
Hi,
>> Add a compatible string for binman, so we can extend fixed-partitions
>> in various ways.
>
> I've been thinking at the proper way to describe the binman partitions.
> I am wondering if we should really extend the fixed-partitions
> schema. This description is really basic and kind of sup
Hi,
>> Add a compatible string for binman, so we can extend fixed-partitions
>> in various ways.
>
> I've been thinking at the proper way to describe the binman partitions.
> I am wondering if we should really extend the fixed-partitions
> schema. This description is really basic and kind of supp
Hi,
The mails are bouncing with
550 5.1.1 User Unknown (in reply to RCPT TO command)
Remove the entry and mark the ARM STM STV0991 arch as Orphan.
Signed-off-by: Michael Walle
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
CCing other ST people, maybe someone want to take over instead
Hi,
> This series adjusts binman to enforce just 4 extensions for output
> images:
>
>.bin
>.rom
>.itb
>.img
>
> Other extensions will produce an error. With this rule observed,
> buildman
> can keep the required files.
How does this work? I didn't get all the patches from this
The mails are bouncing with
550 5.1.1 User Unknown (in reply to RCPT TO command)
Remove the entry and mark the ARM STM STV0991 arch as Orphan.
Signed-off-by: Michael Walle
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
CCing other ST people, maybe someone want to take over instead
Am 2023-08-24 05:02, schrieb Simon Glass:
A '.update' extension is not allowed anymore, so change it.
Signed-off-by: Simon Glass
Looks good to me, as it is just an intermediate binary.
Acked-by: Michael Walle
Hi,
This series adjusts binman to enforce just 4 extensions for output
images:
.bin
.rom
.itb
.img
Other extensions will produce an error. With this rule observed,
buildman
can keep the required files.
How does this work? I didn't get all the patches from this series, which
m
Hi,
> + printf("Disabling WDT\n");
> + writel(0, 0x10007000);
Please don't use magic numbers. Also, I guess this should be a
real watchdog driver and u-boot will take care of disabling it
if the user wants to.
> +
> + printf("Enabling SCP SRAM\n");
> + for (unsigned int val = 0xF
If the use of MTD is restricted to passive serial, this is OK with me.
Yeah, but that is not how upstream things work. You need to also think
of any other use cases.
These are the things I want to achieve.
* transfer data using the SPI driver and not use board files.
For that, the FPGA shou
Sorry, I didn't follow this too closely. Do you have some pointers?
I just saw your latest mail. Thanks.
-michael
Am 2023-02-21 11:42, schrieb Ulf Samuelsson:
Den 2023-02-21 kl. 10:08, skrev Michael Walle:
If it is right or wrong to use that as an MTD is a matter of
opinion.
I am still hoping the MTD maintainer would provide input here.
I might be missing something, but what is the reasoning here, to add
>> If it is right or wrong to use that as an MTD is a matter of opinion.
>
> I am still hoping the MTD maintainer would provide input here.
I might be missing something, but what is the reasoning here, to add this
to the mtd subsystem? One is saving space, but I agree with Marek, this
isn't a val
Am 2023-02-13 09:43, schrieb Stefan Roese:
On 2/10/23 22:08, Tony Dinh wrote:
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is
required for this board to boot over UART with kwboot. Enable this in
kirkwood-pogoplug-series-4-u-boot.dtsi.
Signed-off-by: Tony Dinh
Reviewed-
Am 2023-02-08 12:29, schrieb Oliver Graute:
Am 08.02.2023 um 09:32 schrieb Michael Walle :
Am 2023-02-08 08:38, schrieb Oliver Graute:
if the rtc button cell is on low voltage this can result in a
permanent
bootloop in u-boot because V2F Register is permanent set.
### Warning: temperature
Am 2023-02-08 08:38, schrieb Oliver Graute:
if the rtc button cell is on low voltage this can result in a permanent
bootloop in u-boot because V2F Register is permanent set.
### Warning: temperature compensation has stopped
### Warning: Voltage low, data is invalid
resetting ...
With this patch
Basically I want the following:
(1) board boots with watchdog enabled
(2) u-boot services watchdog
(3a) booting embedded linux with booti (watchdog enabled) or
(3b) booting generic OS with bootefi (watchdog disabled)
The missing case is booting an embedded linux with bootefi, which
would be nice
Honestly, not really? Some good number of SoCs will start the
watchdog
in ROM and these are also the ones that don't allow you to turn it
off.
I hope not, that sounds really risky. How would you debug such a
platform?
_Every single_ custom piece of industrial (as opposed to
consumer-grade)
>>> Honestly, not really? Some good number of SoCs will start the watchdog
>>> in ROM and these are also the ones that don't allow you to turn it off.
>>
>> I hope not, that sounds really risky. How would you debug such a platform?
>
> _Every single_ custom piece of industrial (as opposed to consu
> When DM_SERIAL is enabled, the device-tree property dm-pre-reloc is
> required to boot over UART with kwboot. Enable this in a Kirkwood
> common u-boot dtsi.
My (dev) board unfortunately, have a bootloader which can't boot over
serial.
This is feature of Marvell BootROM and does not require a
Hi Tony,
Am 2023-02-01 02:11, schrieb Tony Dinh:
When DM_SERIAL is enabled, the device-tree property dm-pre-reloc is
required to boot over UART with kwboot. Enable this in a Kirkwood
common u-boot dtsi.
My (dev) board unfortunately, have a bootloader which can't boot over
serial. Could you ela
Am 2023-01-18 14:08, schrieb Marek Vasut:
On 1/18/23 13:43, Michael Walle wrote:
Am 2023-01-18 13:18, schrieb Marek Vasut:
On 1/18/23 13:12, Michael Walle wrote:
[...]
@@ -411,12 +405,11 @@ static int __maybe_unused
pinctrl_post_bind(struct udevice *dev)
}
/*
- * If
Am 2023-01-18 13:18, schrieb Marek Vasut:
On 1/18/23 13:12, Michael Walle wrote:
[...]
@@ -411,12 +405,11 @@ static int __maybe_unused
pinctrl_post_bind(struct udevice *dev)
}
/*
- * If set_state callback is set, we assume this pinctrl driver is
the
- * full implementation
Fix the copy and paste error.
Signed-off-by: Michael Walle
---
drivers/pinctrl/pinctrl-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index e6cd0889b0..23a1504716 100644
--- a/drivers/pinctrl
Don't define an empty version for pinconfig_post_bind(). Just guard the
call and let the linker garbage collection do the rest. This way, we
also don't have to do any guesswork.
Signed-off-by: Michael Walle
---
drivers/pinctrl/pinctrl-uclass.c | 17 +
1 file
which
was ignored before) to -ENOSYS.
Signed-off-by: Michael Walle
---
The real underlying problem is that the pinctrl_select_state_simple()
doesn't really work before relocation. This implementation calls
uclass_get_device() which will try to probe the pinctrl, but that device
might not be
Hi,
Am 2023-01-10 11:54, schrieb Rafał Miłecki:
From: Rafał Miłecki
U-Boot environment variables are stored in ASCII format so "ethaddr"
requires parsing into binary to make it work with Ethernet interfaces.
This includes support for indexes to support #nvmem-cell-cells = <1>.
Signed-off-by:
Hi,
Am 2023-01-05 18:10, schrieb Rafał Miłecki:
From: Rafał Miłecki
Sometimes reading NVMEM cell value involves some data reformatting. It
requires passing updated size value to the caller. Support that.
Wouldn't it make more sense to convert that driver to
proper nvmem layouts, where
(1) y
So leaving 4-byte switched by UBoot SPI chip made it unusable to
RockChip Bootrom. I found this by dumping Bootrom and decompiling it.
>>
>> Sync with engineer working on these area, and get below:
>>
>> Yes, this "4-byte addressing problem in SPI" issue is in SoCs including
>> rk3328, th
The wget command uses TCP, but fails to select PROT_TCP in Kconfig.
Instead it selects the non-existing symbol TCP. Fix the typo.
Signed-off-by: Michael Walle
---
cmd/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index d93731f2af
The compiler complains about the missing declaration of print_size():
net/wget.c:415:3: warning: implicit declaration of function ‘print_size’
[-Wimplicit-function-declaration]
Fix it.
Signed-off-by: Michael Walle
---
net/wget.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/wget.c b
>> On 12/9/22 04:55, Tony Dinh wrote:
>> > Hi Simon et al,
>> >
>> > (Resend to include u-boot mailing list)
>> >
>> > I'm in the process of converting Kirkwood boards to use DM SERIAL. I
>> > could not seem to get it to work, having tried adding
>> > CONFIG_DM_SERIAL, and also playing with various
Hi,
>> I'm not really happy with this approach. It's not that upstream doesn't
>> have aliases now, it's that it has different aliases, right? That's why
>> they won't accept these?
>
> imx6q.dtsi does have the default mmc aliases:
>
> mmc0 = &usdhc1;
> mmc1 = &usdhc2;
> mmc2 = &usdhc3;
> mmc3
Am 2022-11-28 07:59, schrieb Rafał Miłecki:
From: Rafał Miłecki
Pass whole NVMEM cell struct and length pointer as arguments to
callback
functions.
This allows:
1. Cells content to be modified based on more info
Some cells (identified by their names) contain specific data that
needs f
>> ethernet {
>> nvmem-cells = <&mac_address>;
>> nvmem-cell-names = "mac-address";
>> };
>>
>> You'll need 2022.07 for this I think. This is the same method which
>> Linux uses. I added this specificly to be able to load MAC addresses
>> from EEPROMs without needing to hard code stuff i
Am 2022-09-04 02:02, schrieb Tony Dinh:
Hi Stefan,
Sorry, that message was prematurely sent (fat finger). Please see the
continuation below.
On Sat, Sep 3, 2022 at 4:43 PM Tony Dinh wrote:
Hi Stefan,
On Sat, Sep 3, 2022 at 3:44 AM Stefan Roese wrote:
>
> Hi Tony,
>
> On 03.09.22 11:44, Ton
Am 2022-09-02 08:25, schrieb Stefan Roese:
While testing on some Kirkwood platforms it was noticed that the timer
did not function correctly all the time. The driver did not correctly
handle 32bit timer value wrap arounds. Using the timer_conv_64()
conversion function fixes this issue.
Fixes: e
Am 2022-09-01 10:53, schrieb Stefan Roese:
As there is no Orion5 based target in mainline U-Boot any more, let's
completely remove the support for this pretty old Marvell platform.
Signed-off-by: Stefan Roese
Cc: Tony Dinh
Cc: Pali Rohár
Cc: Michael Walle
--- a/drivers/net/Kconfig
Am 2022-08-30 13:53, schrieb Stefan Roese:
Now that the new timer support is available for these platforms, let's
select this IF for all these platforms. This way it's not necessary
that each board changes it's config header.
Signed-off-by: Stefan Roese
---
arch/arm/Kconfig
Am 2022-08-30 13:53, schrieb Stefan Roese:
Add timer_get_boot_us() to support boards, that have CONFIG_BOOTSTAGE
enabled, like pogo_v4.
Signed-off-by: Stefan Roese
---
drivers/timer/orion-timer.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/timer/orion-ti
Hi,
>On 24.08.22 00:33, Pali Rohár wrote:
>> Hello Stefan! Now when U-Boot contains new orion-timer.c driver, which
>> Michael wrote, I think that it mvebu platform should switch to use it.
>> Because build process for armada boards prints deprecation warning that
>> new timer is not being used. C
Am 2022-08-23 17:01, schrieb Stefan Roese:
Applied to u-boot-marvell/master, with my small fix for the ds109
board
Great! Thanks, Stefan.
-michael
During startup the SPL will print where the u-boot proper is read from.
Instead of using the default names, provide more user friendly names.
Signed-off-by: Michael Walle
---
board/kontron/sl28/spl.c | 16
1 file changed, 16 insertions(+)
diff --git a/board/kontron/sl28/spl.c
The frequency of the system counter is static which is given by the
COUNTER_FREQUENCY option. Remove COUNTER_FREQUENCY_REAL.
Signed-off-by: Michael Walle
---
include/configs/kontron_sl28.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/kontron_sl28.h b/include/configs
Depending on the boot source, set different CLI prompts. This will help
the user to figure out in which mode the bootloader was started. There
are two special modes: failsafe and SDHC boot.
Signed-off-by: Michael Walle
---
board/kontron/sl28/sl28.c | 20
configs
The board is able to boot from the following source:
- user-updateble SPI flash
- write-protected part of the same SPI flash
- eMMC
- SD card
Implement the needed function hooks to support all of these boot
sources.
Signed-off-by: Michael Walle
---
board/kontron/sl28/common.c| 22
By default the OCRAM is marked as secure. While the SPL runs in EL3 and
thus can access it, DMA devices cannot. Mark the whole OCRAM as
non-secure.
This will fix MMC and SD card boot on LS1028A when using SPL instead of
TF-A.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape
- dynamic prompts
- various cleanups
changes since v2:
- only mark secure ram on layerscape SoCs which actually have it.
changes since v1:
- rebased onto the latest master
Michael Walle (5):
armv8: layerscape: spl: mark OCRAM as non-secure
board: sl28: implement additional bootsources
board
>On 8/18/2022 6:40 AM, Tom Rini wrote:
>> On Wed, Aug 17, 2022 at 02:26:32AM +, Peng Fan (OSS) wrote:
>>
>>> Hi Tom,
>>>
>>> Please pull fsl-qoriq-2022-8-17
>>>
>>> CI:
>>> https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/13155
>>
>> First, applied to u-boot/master, than
Use the common kernel_addr_r, ramdisk_addr_r and fdt_addr_r variable
names.
Signed-off-by: Michael Walle
---
include/configs/lsxl.h | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
Just enabling the Kconfig option for DM_ETH and DM_MDIO is enough.
Additionally, we can remove the old hardcoded config.
Signed-off-by: Michael Walle
---
configs/lschlv2_defconfig | 2 ++
configs/lsxhl_defconfig | 2 ++
include/configs/lsxl.h| 8
3 files changed, 4 insertions
1 - 100 of 1002 matches
Mail list logo