[RESEND PATCH v5 9/11] ARM: socfpga: Add initial support for ic-automation Moritz III
Add initial support for ic-automation Moritz III, which is
an Cyclone V SOM with ethernet, usb, uart. Booting via
sd-card or flash is supported.
Changes for v5:
- fixed random ethaddr at failure
- fixed comments
Changes for v4:
- re-sort list alphabetically
- c style comments
Changes for v3:
- Resend via git send-email
Changes for v2:
- Coding Style cleanup
Signed-off-by: Nico Becker
---
arch/arm/dts/Makefile | 1 +
...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi | 45 ++
.../dts/socfpga_cyclone5_ica_moritz_iii.dts | 123
arch/arm/mach-socfpga/Kconfig | 8 +
board/ic-automation/moritz_iii/MAINTAINERS| 8 +
board/ic-automation/moritz_iii/Makefile | 8 +
.../moritz_iii/moritz_iii_board.c | 127
.../moritz_iii/qts/iocsr_config.h | 658 ++
.../moritz_iii/qts/pinmux_config.h| 218 ++
.../ic-automation/moritz_iii/qts/pll_config.h | 83 +++
.../moritz_iii/qts/sdram_config.h | 344 +
board/ic-automation/moritz_iii/socfpga.c | 5 +
configs/socfpga_moritz_iii_defconfig | 75 ++
include/configs/socfpga_ica_moritz_iii.h | 46 ++
14 files changed, 1749 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
create mode 100644 board/ic-automation/moritz_iii/Makefile
create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
create mode 100644 board/ic-automation/moritz_iii/socfpga.c
create mode 100644 configs/socfpga_moritz_iii_defconfig
create mode 100644 include/configs/socfpga_ica_moritz_iii.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..6fbedfe3b3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -352,6 +352,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb\
socfpga_cyclone5_de10_nano.dtb \
+ socfpga_cyclone5_ica_moritz_iii.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
new file mode 100644
index 00..3ba01d1fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = "/soc/spi@ff705000";
+ udc0 =
+ };
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
new file mode 100644
index 00..d81f8ea5bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "ic-automation Moritz III";
+ compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5",
"altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x4000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+* to be added to the gmac1 device tree blob.
+*/
+ ethernet0 =
+ };
+
+ fpga_bridge3: fpga_bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+
[RESEND PATCH v5] Add board support for ic-automation Moritz III
Add board support for ic-automation Moritz III
Changes for v5:
- fixed random ethaddr at failure
- fixed comments
Changes for v4:
- re-sort list alphabetically
- c style comments
Changes for v3:
- Resend via git send-email
Changes for v2:
- Coding Style cleanup
Signed-off-by: Nico Becker
---
arch/arm/dts/Makefile | 1 +
...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi | 45 ++
.../dts/socfpga_cyclone5_ica_moritz_iii.dts | 123
arch/arm/mach-socfpga/Kconfig | 8 +
board/ic-automation/moritz_iii/MAINTAINERS| 8 +
board/ic-automation/moritz_iii/Makefile | 8 +
.../moritz_iii/moritz_iii_board.c | 127
.../moritz_iii/qts/iocsr_config.h | 658 ++
.../moritz_iii/qts/pinmux_config.h| 218 ++
.../ic-automation/moritz_iii/qts/pll_config.h | 83 +++
.../moritz_iii/qts/sdram_config.h | 344 +
board/ic-automation/moritz_iii/socfpga.c | 5 +
configs/socfpga_moritz_iii_defconfig | 75 ++
include/configs/socfpga_ica_moritz_iii.h | 46 ++
14 files changed, 1749 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
create mode 100644 board/ic-automation/moritz_iii/Makefile
create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
create mode 100644 board/ic-automation/moritz_iii/socfpga.c
create mode 100644 configs/socfpga_moritz_iii_defconfig
create mode 100644 include/configs/socfpga_ica_moritz_iii.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..6fbedfe3b3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -352,6 +352,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb\
socfpga_cyclone5_de10_nano.dtb \
+ socfpga_cyclone5_ica_moritz_iii.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
new file mode 100644
index 00..3ba01d1fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = "/soc/spi@ff705000";
+ udc0 =
+ };
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
new file mode 100644
index 00..d81f8ea5bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "ic-automation Moritz III";
+ compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5",
"altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x4000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+* to be added to the gmac1 device tree blob.
+*/
+ ethernet0 =
+ };
+
+ fpga_bridge3: fpga_bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+
[PATCH v5] arm: socfpga: add board support for ic-automation Moritz III
Changes for v5:
- fixed random ethaddr at failure
- fixed comments
Changes for v4:
- re-sort list alphabetically
- c style comments
Changes for v3:
- Resend via git send-email
Changes for v2:
- Coding Style cleanup
Signed-off-by: Nico Becker
---
arch/arm/dts/Makefile | 1 +
...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi | 45 ++
.../dts/socfpga_cyclone5_ica_moritz_iii.dts | 123
arch/arm/mach-socfpga/Kconfig | 8 +
board/ic-automation/moritz_iii/MAINTAINERS| 8 +
board/ic-automation/moritz_iii/Makefile | 8 +
.../moritz_iii/moritz_iii_board.c | 127
.../moritz_iii/qts/iocsr_config.h | 658 ++
.../moritz_iii/qts/pinmux_config.h| 218 ++
.../ic-automation/moritz_iii/qts/pll_config.h | 83 +++
.../moritz_iii/qts/sdram_config.h | 344 +
board/ic-automation/moritz_iii/socfpga.c | 5 +
configs/socfpga_moritz_iii_defconfig | 75 ++
include/configs/socfpga_ica_moritz_iii.h | 46 ++
14 files changed, 1749 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
create mode 100644 board/ic-automation/moritz_iii/Makefile
create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
create mode 100644 board/ic-automation/moritz_iii/socfpga.c
create mode 100644 configs/socfpga_moritz_iii_defconfig
create mode 100644 include/configs/socfpga_ica_moritz_iii.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..6fbedfe3b3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -352,6 +352,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb\
socfpga_cyclone5_de10_nano.dtb \
+ socfpga_cyclone5_ica_moritz_iii.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
new file mode 100644
index 00..3ba01d1fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = "/soc/spi@ff705000";
+ udc0 =
+ };
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
new file mode 100644
index 00..d81f8ea5bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "ic-automation Moritz III";
+ compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5",
"altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x4000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+* to be added to the gmac1 device tree blob.
+*/
+ ethernet0 =
+ };
+
+ fpga_bridge3: fpga_bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+
[PATCH v4] arm: socfpga: add board support for ic-automation Moritz III
Hello, sorry for the e-mail again. i check the repo today, but the board is still missing. can you tell me how long it take to push it in the main branch? will it be there in future, or was the patch rejected. thanks a lot, i wish you a great start into the week.
[PATCH v4] arm: socfpga: add board support for ic-automation Moritz III
add board support for the moritz III from ic-automation
Changes for v4:
- re-sort list alphabetically
- c style comments
Changes for v3:
- Resend via git send-email
Changes for v2:
- Coding Style cleanup
Signed-off-by: Nico Becker
---
arch/arm/dts/Makefile | 1 +
...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi | 45 ++
.../dts/socfpga_cyclone5_ica_moritz_iii.dts | 123
arch/arm/mach-socfpga/Kconfig | 8 +
board/ic-automation/moritz_iii/MAINTAINERS| 8 +
board/ic-automation/moritz_iii/Makefile | 8 +
.../moritz_iii/moritz_iii_board.c | 126
.../moritz_iii/qts/iocsr_config.h | 658 ++
.../moritz_iii/qts/pinmux_config.h| 218 ++
.../ic-automation/moritz_iii/qts/pll_config.h | 83 +++
.../moritz_iii/qts/sdram_config.h | 344 +
board/ic-automation/moritz_iii/socfpga.c | 5 +
configs/socfpga_moritz_iii_defconfig | 74 ++
include/configs/socfpga_ica_moritz_iii.h | 46 ++
14 files changed, 1747 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
create mode 100644 board/ic-automation/moritz_iii/Makefile
create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
create mode 100644 board/ic-automation/moritz_iii/socfpga.c
create mode 100644 configs/socfpga_moritz_iii_defconfig
create mode 100644 include/configs/socfpga_ica_moritz_iii.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..6fbedfe3b3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -352,6 +352,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb\
socfpga_cyclone5_de10_nano.dtb \
+ socfpga_cyclone5_ica_moritz_iii.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
new file mode 100644
index 00..3ba01d1fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = "/soc/spi@ff705000";
+ udc0 =
+ };
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
new file mode 100644
index 00..d81f8ea5bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "ic-automation Moritz III";
+ compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5",
"altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x4000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+* to be added to the gmac1 device tree blob.
+*/
+ ethernet0 =
+ };
+
+ fpga_bridge3: fpga_bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name
[PATCH v3] arm: socfpga: add board support for ic-automation moritz III
Changes for v3:
- Resend via git send-email
Changes for v2:
- Coding Style cleanup
Signed-off-by: Nico Becker
---
arch/arm/dts/Makefile | 3 +-
...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi | 45 ++
.../dts/socfpga_cyclone5_ica_moritz_iii.dts | 123
arch/arm/mach-socfpga/Kconfig | 8 +
board/ic-automation/moritz_iii/MAINTAINERS| 8 +
board/ic-automation/moritz_iii/Makefile | 8 +
.../moritz_iii/moritz_iii_board.c | 126
.../moritz_iii/qts/iocsr_config.h | 658 ++
.../moritz_iii/qts/pinmux_config.h| 218 ++
.../ic-automation/moritz_iii/qts/pll_config.h | 83 +++
.../moritz_iii/qts/sdram_config.h | 344 +
board/ic-automation/moritz_iii/socfpga.c | 5 +
configs/socfpga_moritz_iii_defconfig | 74 ++
include/configs/socfpga_ica_moritz_iii.h | 46 ++
14 files changed, 1748 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
create mode 100644 board/ic-automation/moritz_iii/Makefile
create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
create mode 100644 board/ic-automation/moritz_iii/socfpga.c
create mode 100644 configs/socfpga_moritz_iii_defconfig
create mode 100644 include/configs/socfpga_ica_moritz_iii.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..198ad36686 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -356,7 +356,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
- socfpga_stratix10_socdk.dtb
+ socfpga_stratix10_socdk.dtb \
+ socfpga_cyclone5_ica_moritz_iii.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
new file mode 100644
index 00..3ba01d1fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = "/soc/spi@ff705000";
+ udc0 =
+ };
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
new file mode 100644
index 00..d81f8ea5bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "ic-automation Moritz III";
+ compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5",
"altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x4000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+* to be added to the gmac1 device tree blob.
+*/
+ ethernet0 =
+ };
+
+ fpga_bridge3: fpga_bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-
[PATCH v2] arm: socfpga: add board support for ic-automation moritz III
add board support for the moritz iii board from ic-automation
sorry for the first version.
thanks a lot
greetings
From 452de78b389a2516b8df12ef68da73edece4ca65 Mon Sep 17 00:00:00 2001
From: Nico Becker
Date: Mon, 15 Jun 2020 14:18:35 +0200
Subject: [PATCH v2] add board support for ic-automation GmbH Moritz III
Changes for v2:
- Coding Style cleanup
Signed-off-by: Nico Becker
---
arch/arm/dts/Makefile | 3 +-
...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi | 45 ++
.../dts/socfpga_cyclone5_ica_moritz_iii.dts | 123
arch/arm/mach-socfpga/Kconfig | 8 +
board/ic-automation/moritz_iii/MAINTAINERS | 8 +
board/ic-automation/moritz_iii/Makefile | 8 +
.../moritz_iii/moritz_iii_board.c | 126
.../moritz_iii/qts/iocsr_config.h | 658 ++
.../moritz_iii/qts/pinmux_config.h | 218 ++
.../ic-automation/moritz_iii/qts/pll_config.h | 83 +++
.../moritz_iii/qts/sdram_config.h | 344 +
board/ic-automation/moritz_iii/socfpga.c | 5 +
configs/socfpga_moritz_iii_defconfig | 74 ++
include/configs/socfpga_ica_moritz_iii.h | 46 ++
14 files changed, 1748 insertions(+), 1 deletion(-)
create mode 100644
arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
create mode 100644 board/ic-automation/moritz_iii/Makefile
create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
create mode 100644 board/ic-automation/moritz_iii/socfpga.c
create mode 100644 configs/socfpga_moritz_iii_defconfig
create mode 100644 include/configs/socfpga_ica_moritz_iii.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..198ad36686 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -356,7 +356,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb \
- socfpga_stratix10_socdk.dtb
+ socfpga_stratix10_socdk.dtb \
+ socfpga_cyclone5_ica_moritz_iii.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
new file mode 100644
index 00..3ba01d1fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = "/soc/spi@ff705000";
+ udc0 =
+ };
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
new file mode 100644
index 00..d81f8ea5bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "ic-automation Moritz III";
+ compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5",
"altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x4000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 =
+ };
+
+ fpga_bridge3: fpga_bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <33
Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot
Am 12.06.2020 um 22:27 schrieb Dinh Nguyen: On 6/12/20 6:41 AM, Marek Vasut wrote: On 6/12/20 1:04 PM, Nico Becker wrote: Am 12.06.2020 um 07:51 schrieb Nico Becker: Am 11.06.2020 um 03:51 schrieb Tan, Ley Foon: -Original Message- From: Dinh Nguyen Sent: Thursday, June 11, 2020 2:55 AM To: Marek Vasut ; Nico Becker ; u-boot@lists.denx.de Cc: simon.k.r.goldschm...@gmail.com; Tan, Ley Foon Subject: Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot On 6/10/20 8:23 AM, Marek Vasut wrote: On 6/10/20 3:21 PM, Nico Becker wrote: Am 10.06.2020 um 15:19 schrieb Marek Vasut: On 6/10/20 3:14 PM, Nico Becker wrote: if i remove the arm,shared-override option in the dts file, the kernel boot without an error. With the option the kernel boots with the following error: dmesg --level=err L2C-310: enabling full line of zeros but not enabled in Cortex-A9 i ve no idea why the parameter have an effect on that. i try several kernels, allays the same behavior. diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index eda558f2fe..c2173416c7 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -719,7 +719,6 @@ arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; - arm,shared-override; arm,double-linefill = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <1>; Do you use latest u-boot/master or some older version ? Which one? sorry, i forget it. i use v2020.01 Should be OK I think. Hm, I suspect this is another fun with the ACTLR/CPACR registers, like 937db7188e3a5ab8f802eff9b57854189379667a . Ley, any ideas ? I just tested with 2020.07-rc4-00022-gbe79009f3b along with linux v5.7, and I no longer see the error. Yes, I also just tested 2020.04 uboot and 5.4.23-lts kernel, also didn't see this error. What kernel version you are using? Regards Ley Foon hello, i use kernel 4.14.126-rt62-ltsi. greetings i try the u-boot version v2020.07-rc4 without the patch, and everything seems okay, no error at boot. i ve no idea why the error at boot time is gone with the 2020.07-rc4 version. does anyone have any idea why? thanks, greetings You can try git bisect between the two versions to find out which patch caused this. This is the patch that fixed it: commit f62782fb2999dd8109a3ffe9ee0a51e54ab034ab Author: Ley Foon Tan Date: Fri Apr 17 14:45:35 2020 +0800 cache: l2x0: Fix write to incorrect shared-override bit The existing code write bit-0 for shared attribute override enable bit. It should be bit-22 based on cache controller specification [1]. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf Signed-off-by: Ley Foon Tan Dinh hello, thanks a lot! i try the git bisect method, i was 13 builds away. next time i check first the changelog greetings
Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot
Am 12.06.2020 um 07:51 schrieb Nico Becker: Am 11.06.2020 um 03:51 schrieb Tan, Ley Foon: -Original Message- From: Dinh Nguyen Sent: Thursday, June 11, 2020 2:55 AM To: Marek Vasut ; Nico Becker ; u-boot@lists.denx.de Cc: simon.k.r.goldschm...@gmail.com; Tan, Ley Foon Subject: Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot On 6/10/20 8:23 AM, Marek Vasut wrote: On 6/10/20 3:21 PM, Nico Becker wrote: Am 10.06.2020 um 15:19 schrieb Marek Vasut: On 6/10/20 3:14 PM, Nico Becker wrote: if i remove the arm,shared-override option in the dts file, the kernel boot without an error. With the option the kernel boots with the following error: dmesg --level=err L2C-310: enabling full line of zeros but not enabled in Cortex-A9 i ve no idea why the parameter have an effect on that. i try several kernels, allays the same behavior. diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index eda558f2fe..c2173416c7 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -719,7 +719,6 @@ arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; - arm,shared-override; arm,double-linefill = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <1>; Do you use latest u-boot/master or some older version ? Which one? sorry, i forget it. i use v2020.01 Should be OK I think. Hm, I suspect this is another fun with the ACTLR/CPACR registers, like 937db7188e3a5ab8f802eff9b57854189379667a . Ley, any ideas ? I just tested with 2020.07-rc4-00022-gbe79009f3b along with linux v5.7, and I no longer see the error. Yes, I also just tested 2020.04 uboot and 5.4.23-lts kernel, also didn't see this error. What kernel version you are using? Regards Ley Foon hello, i use kernel 4.14.126-rt62-ltsi. greetings i try the u-boot version v2020.07-rc4 without the patch, and everything seems okay, no error at boot. i ve no idea why the error at boot time is gone with the 2020.07-rc4 version. does anyone have any idea why? thanks, greetings
[PATCH] arm: socfpga: add board support for ic-automation moritz III
rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <1320>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <900>;
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ speed-mode = <0>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c@1{
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ mcp_rtc: rtc@6F{
+ compatible = "microchip,mcp7941x";
+ reg = <0x6F>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+ speed-mode = <0>;
+
+ gpioexp@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ };
+
+ e2prom@50 {
+ compatible = "at,24c01";
+ reg = <0x50>;
+ };
+
+ tempsens@48 {
+ compatible = "ti,tmp108";
+ reg = <0x48>;
+ };
+};
+
+ {
+ vmmc-supply = <_3_3v>;
+ vqmmc-supply = <_3_3v>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a3699e82a1..c6039ac07d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -151,6 +151,11 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_ICA_MORITZ_III
+ bool "ic-automation Moritz III (Cyclone V)"
+ select BOARD_LATE_INIT
+ select TARGET_SOCFPGA_CYCLONE5
+
endchoice
config SYS_BOARD
@@ -170,6 +175,7 @@ config SYS_BOARD
default "sr1500" if TARGET_SOCFPGA_SR1500
default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+ default "moritz_iii" if TARGET_SOCFPGA_ICA_MORITZ_III
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
@@ -186,6 +192,7 @@ config SYS_VENDOR
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "ic-automation" if TARGET_SOCFPGA_ICA_MORITZ_III
config SYS_SOC
default "socfpga"
@@ -207,6 +214,7 @@ config SYS_CONFIG_NAME
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+ default "socfpga_ica_moritz_iii" if TARGET_SOCFPGA_ICA_MORITZ_III
source "board/keymile/Kconfig"
diff --git a/board/ic-automation/moritz_iii/MAINTAINERS
b/board/ic-automation/moritz_iii/MAINTAINERS
new file mode 100644
index 00..29e705524e
--- /dev/null
+++ b/board/ic-automation/moritz_iii/MAINTAINERS
@@ -0,0 +1,8 @@
+MORITZ III BOARD
+M: Nico Becker
+S: Maintained
+F: board/ic-automation/moritz_iii/
+F: include/configs/socfpga_ica_moritz_iii.h
+F: configs/socfpga_moritz_iii_defconfig
+F: arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
+F: arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
diff --git a/board/ic-automation/moritz_iii/Makefile
b/board/ic-automation/moritz_iii/Makefile
new file mode 100644
index 00..3577c94928
--- /dev/null
+++ b/board/ic-automation/moritz_iii/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+# (C) Copyright 2010, Thomas Chou
+
+obj-y := socfpga.o
+obj-y := moritz_iii_board.o
\ No newline at end of file
diff --git a/board/ic-automation/moritz_iii/moritz_iii_board.c
b/board/ic-automation/moritz_iii/moritz_iii_board.c
new file mode 100644
index 00..de56bf3a73
--- /dev/null
+++ b/board/ic-automation/moritz_iii/moritz_iii_board.c
@@ -0,0 +1,128 @@
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define I2C_BUS_NUM 1
+#define EEPROM_ADDR 0x50
+#define GPIO_ADDR 0x20
+
+#define SERIALNUMBER_LENGTH 8
+#define MAC_LENGTH 6
+#define CRC32_LENGTH 4
+#define OVERALL_LENGTH (SERIALNUMBER_LENGTH+MAC_LENGTH+CRC32_LENGTH)
+
+int board_late_init(void)
+{
+ u8 mac[MAC_LENGTH];
+ char serial[SERIALNUMBER_LENGTH+1];
+ u8 eeprom_data[OVERALL_LENGTH];
+ u32 calc_crc32;
+ u32* read_crc32;
+ u8 w_data;
+ int error;
+ u8 registers[] = {0x02, 0x03, 0x06, 0x07};
+
+ for(i
Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot
Am 11.06.2020 um 03:51 schrieb Tan, Ley Foon: -Original Message- From: Dinh Nguyen Sent: Thursday, June 11, 2020 2:55 AM To: Marek Vasut ; Nico Becker ; u-boot@lists.denx.de Cc: simon.k.r.goldschm...@gmail.com; Tan, Ley Foon Subject: Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot On 6/10/20 8:23 AM, Marek Vasut wrote: On 6/10/20 3:21 PM, Nico Becker wrote: Am 10.06.2020 um 15:19 schrieb Marek Vasut: On 6/10/20 3:14 PM, Nico Becker wrote: if i remove the arm,shared-override option in the dts file, the kernel boot without an error. With the option the kernel boots with the following error: dmesg --level=err L2C-310: enabling full line of zeros but not enabled in Cortex-A9 i ve no idea why the parameter have an effect on that. i try several kernels, allays the same behavior. diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index eda558f2fe..c2173416c7 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -719,7 +719,6 @@ arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; - arm,shared-override; arm,double-linefill = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <1>; Do you use latest u-boot/master or some older version ? Which one? sorry, i forget it. i use v2020.01 Should be OK I think. Hm, I suspect this is another fun with the ACTLR/CPACR registers, like 937db7188e3a5ab8f802eff9b57854189379667a . Ley, any ideas ? I just tested with 2020.07-rc4-00022-gbe79009f3b along with linux v5.7, and I no longer see the error. Yes, I also just tested 2020.04 uboot and 5.4.23-lts kernel, also didn't see this error. What kernel version you are using? Regards Ley Foon hello, i use kernel 4.14.126-rt62-ltsi. greetings
Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot
Am 10.06.2020 um 15:19 schrieb Marek Vasut: On 6/10/20 3:14 PM, Nico Becker wrote: if i remove the arm,shared-override option in the dts file, the kernel boot without an error. With the option the kernel boots with the following error: dmesg --level=err L2C-310: enabling full line of zeros but not enabled in Cortex-A9 i ve no idea why the parameter have an effect on that. i try several kernels, allays the same behavior. diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index eda558f2fe..c2173416c7 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -719,7 +719,6 @@ arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; - arm,shared-override; arm,double-linefill = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <1>; Do you use latest u-boot/master or some older version ? Which one? sorry, i forget it. i use v2020.01
[PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot
if i remove the arm,shared-override option in the dts file, the kernel boot without an error. With the option the kernel boots with the following error: dmesg --level=err L2C-310: enabling full line of zeros but not enabled in Cortex-A9 i ve no idea why the parameter have an effect on that. i try several kernels, allays the same behavior. diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index eda558f2fe..c2173416c7 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -719,7 +719,6 @@ arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; - arm,shared-override; arm,double-linefill = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <1>;
altera intel cyclone v / error: enabling full line of zeros but not enabled in Cortex-A9
hi, i have an error message booting linux kernel v4.15 with the u-boot v2020.01 on an cylcone v with arm core. the error message is: L2C-310: enabling full line of zeros but not enabled in Cortex-A9, that is not a warning or an message it is an error. before the update to the version v2020.01, we use the version v2017.09. i get the following message: L2C-310 full line of zeros enabled for Cortex-A9, no error message. we use our own board with an altera cyclone v, i try severall default configs, i got the same error. it is very hard to find the source code to enable the full line support in u-boot. 8.2.3. Write full line of zeros Setting bit [3] of the ACTLR enables this feature. can somebody help me? thanks a lot
Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Am 06.02.2020 um 14:00 schrieb Marek Vasut:
On 2/6/20 1:57 PM, Nico Becker wrote:
Am 06.02.2020 um 12:53 schrieb Marek Vasut:
On 2/6/20 11:50 AM, Nico Becker wrote:
Hello,
Hi,
after removing the function socfpga_sdram_apply_static_cfg() in
misc_gen5 we can not use the FPGA2SDRAM bridge.
Without the apply static cfg the kernel crash every time,
if we try to write @ the fpga2sdram bridge. After an soft reset
everything is working.
If we add the socfpga_sdram_apply_static_cfg() in the
u-boot source code, everything is fine.
Now we can use the fpga2sdram bridge after power on.
Our setup:
- u-boot v2020.01
- load and write fpga firmware
- enable bridges
- boot linux
I have found some information at
<https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge>
<http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html>
Can you send a patch which fixes this for you, with Fixes: tag ?
Then it would be clear what you changed.
Thanks
Hello,
the code was removed @ commit c5f4b805.
Did you read the commit message of that commit and what problem that was
solving ? Clearly, reverting the commit isn't the way to go. We need to
find a way to unbreak this for you, while not break other platforms.
I attached my patch, sorry for the format, i am new in this.
[...]
Hi,
yes i read the commit message.
but i found no other option to enable the sdram bridges,
without crashes/hanging up linux, with the removed source code.
i ve found some more information @intel
<https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html>
Intel talk about an bridge_enable_handoff in my opionion
the cmd set the sram aply cfg
/* add signle command to enable all bridges based on handoff */
setenv("bridge_enable_handoff",
"mw $fpgaintf ${fpgaintf_handoff}; "
"go $fpga2sdram_apply; "
"mw $fpga2sdram ${fpga2sdram_handoff}; "
"mw $axibridge ${axibridge_handoff}; "
"mw $l3remap ${l3remap_handoff} ");
setenv_addr("fpga2sdram_apply", (void *)sdram_applycfg_uboot);
/*
* Relocate the sdram_applycfg_ocram function to OCRAM and call it
*/
ENTRY(sdram_applycfg_uboot)
PUSH{r4-r11, lr}/* save registers per AAPCS */
ldr r1, =sdram_applycfg_ocram
ldr r2, =CONFIG_SYS_INIT_RAM_ADDR
mov r3, r2
ldmia r1!, {r4 - r11}
stmia r3!, {r4 - r11}
ldmia r1!, {r4 - r11} /* copy more in case code added */
stmia r3!, {r4 - r11} /* in the future */
ldmia r1!, {r4 - r11} /* copy more in case code added */
stmia r3!, {r4 - r11} /* in the future */
dsb
isb
blx r2 /* jump to OCRAM */
POP {r4-r11, pc}
ENDPROC(sdram_applycfg_uboot)
it could be an option to write the fpga firmware with u-boot,
and do a soft reset.
boot u-boot
check fpga configuration state
not configured write firmware reset
if configured boot linux
i ll check howto to determine the fpga configuration state
and try this.
Thanks
--
Nico Becker
ic-automation GmbH
Alexander-Diehl-Straße 2a
D-55130 Mainz
Tel:+49-(0)6131-62718-24
Fax:+49-(0)6131-62718-10
email: n.bec...@ic-automation.de
Web:http://www.ic-automation.de
Geschäftsführer: Dr. Stefan Becker
HRB 7283, Amtsgericht Mainz
Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Am 06.02.2020 um 12:53 schrieb Marek Vasut:
On 2/6/20 11:50 AM, Nico Becker wrote:
Hello,
Hi,
after removing the function socfpga_sdram_apply_static_cfg() in
misc_gen5 we can not use the FPGA2SDRAM bridge.
Without the apply static cfg the kernel crash every time,
if we try to write @ the fpga2sdram bridge. After an soft reset
everything is working.
If we add the socfpga_sdram_apply_static_cfg() in the
u-boot source code, everything is fine.
Now we can use the fpga2sdram bridge after power on.
Our setup:
- u-boot v2020.01
- load and write fpga firmware
- enable bridges
- boot linux
I have found some information at
<https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge>
<http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html>
Can you send a patch which fixes this for you, with Fixes: tag ?
Then it would be clear what you changed.
Thanks
Hello,
the code was removed @ commit c5f4b805.
I attached my patch, sorry for the format, i am new in this.
Thanks a lot
---
arch/arm/mach-socfpga/misc_gen5.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 22042d0de0..19c6d24170 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -213,6 +213,35 @@ static struct socfpga_reset_manager
*reset_manager_base =
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+static void socfpga_sdram_apply_static_cfg(void)
+{
+ const u32 applymask = 0x8;
+ u32 val = readl(_ctrl->static_cfg) | applymask;
+
+ /*
+* SDRAM staticcfg register specific:
+* When applying the register setting, the CPU must not access
+* SDRAM. Luckily for us, we can abuse i-cache here to help us
+* circumvent the SDRAM access issue. The idea is to make sure
+* that the code is in one full i-cache line by branching past
+* it and back. Once it is in the i-cache, we execute the core
+* of the code and apply the register settings.
+*
+* The code below uses 7 instructions, while the Cortex-A9 has
+* 32-byte cachelines, thus the limit is 8 instructions total.
+*/
+ asm volatile(
+ ".align5 \n"
+ " b 2f \n"
+ "1:str %0, [%1]\n"
+ " dsb \n"
+ " isb \n"
+ " b 3f \n"
+ "2:b 1b \n"
+ "3:nop \n"
+ : : "r"(val), "r"(_ctrl->static_cfg) : "memory", "cc");
+}
+
void do_bridge_reset(int enable, unsigned int mask)
{
int i;
@@ -227,6 +256,7 @@ void do_bridge_reset(int enable, unsigned int mask)
}
writel(iswgrp_handoff[2], _regs->fpgaintfgrp_module);
+ socfpga_sdram_apply_static_cfg();
writel(iswgrp_handoff[3], _ctrl->fpgaport_rst);
writel(iswgrp_handoff[0], _manager_base->brg_mod_reset);
writel(iswgrp_handoff[1], _regs->remap);
@@ -236,6 +266,7 @@ void do_bridge_reset(int enable, unsigned int mask)
} else {
writel(0, _regs->fpgaintfgrp_module);
writel(0, _ctrl->fpgaport_rst);
+ socfpga_sdram_apply_static_cfg();
writel(0x7, _manager_base->brg_mod_reset);
writel(1, _regs->remap);
}
--
2.20.1
[U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Hello, after removing the function socfpga_sdram_apply_static_cfg() in misc_gen5 we can not use the FPGA2SDRAM bridge. Without the apply static cfg the kernel crash every time, if we try to write @ the fpga2sdram bridge. After an soft reset everything is working. If we add the socfpga_sdram_apply_static_cfg() in the u-boot source code, everything is fine. Now we can use the fpga2sdram bridge after power on. Our setup: - u-boot v2020.01 - load and write fpga firmware - enable bridges - boot linux I have found some information at <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> -- Best regards Nico Becker
