nd VID for such flashes. A writesize > 1 is an
> indication of an ECC-ed flash.
>
> This patch replicates the following upstream linux commit:
> f669e74be820 ("ubi: Do not zero out EC and VID on ECC-ed NOR flashes")
>
> Acked-by: Tudor Ambarus
> Signed-off-by: Ta
+ spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_4],
> + 0, 8, SPINOR_OP_READ_1_1_4,
> + SNOR_PROTO_1_1_4);
> + } else {
> + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
> +
On Tue, Apr 09 2024, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> The 6th ID byte is needed to distiguish S25FL-S and S25FS-S families.
>
> Signed-off-by: Takahiro Kuwano
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Kuwano
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
t;s25fs256s", 0x010219, 0x4d0181, 64 * 1024, 512,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
--
Regards,
Pratyush Yadav
CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
> + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
> + }
> +
> + /* Set up dummy cycles. */
> + dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
> + if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
uld be better if you get rid of
cadence_qspi_set_protocol() entirely. I see no point in carrying the
state around. Wherever you use priv->dtr or priv->inst_width, etc. you
also have access to the spi_mem_op. You can derive that information from
the op. Something to fix when you have some free time on your han
On Mon, Feb 20 2023, Dhruva Gole wrote:
> This should have been op->data.buswidth instead as we check for octal
> bus width for the data related ops
> Also add explanation for why there is checks for 8D even data bytes
>
> Cc: Pratyush Yadav
> Signed-off-by: Dhruva Gole
<= instead?
> mode = CQSPI_STIG_READ;
> else
> mode = CQSPI_READ;
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
the cmd byte. Absence of addr bytes will obviously fail
> to read correct data from flash register that maybe requested by flash
> driver because the controller doesn't even specify which address of the
> flash register the read is being requested from.
>
> Signed-off-by: Dhruva Gole
On 07/11/22 06:46PM, Gole, Dhruva wrote:
> Hey Pratyush,
>
> On 11/7/2022 4:16 AM, Pratyush Yadav wrote:
> > Hi Dhruva :-)
> >
> > On 25/10/22 11:50AM, Dhruva Gole wrote:
> > > Remove the extra conditions that cause some cases to fail prematurely
> >
op->data.buswidth instead. That would be a
welcome fix indeed :-)
You can also put my explanation for why this exists in a comment here so
other people reading this code can also get to know this.
> - return false;
> -
> return spi_mem_check_buswidth(slave, op);
> }
> EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
On 26/07/22 10:27AM, Xavier Drudis Ferran wrote:
>
> Thank you for your time looking at the patch.
>
> El Tue, Jul 26, 2022 at 12:43:06PM +0530, Pratyush Yadav deia:
> >
> > Please don't put the changelog in the commit message. Put it below the 3
> > dash
e commit 5752d6ae8daa ("spi:
> spi-mem: add spi_mem_dtr_supports_op()") by Pratyush Yadav.
>
> So try a few modes until SNOR_PROTO_1_1_1 works and then remember the
> reset_proto. This tries to be useful for other boards, but I still
> don't know any other that needs
alloc'ed bounce buffer which is
> the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c).
>
> Signed-off-by: Vaishnav Achath
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
& MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
> BOOT_MODE_B_SHIFT);
> +
> + return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
> +}
> +
> +/* both OSPI and QSPI flash are in CS0 */
> +u32 spl_spi_boot_cs(void)
> +{
> + return 0;
> +}
> +
I don't think we need to hard-cod
> weakly defined in common/spl/spl_spi.c.
>
> Signed-off-by: Vaishnav Achath
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
t (*octal_dtr_enable)(struct spi_nor *nor);
> int (*ready)(struct spi_nor *nor);
>
> + struct {
> + struct spi_mem_dirmap_desc *rdesc;
> + struct spi_mem_dirmap_desc *wdesc;
> + } dirmap;
> +
> void *priv;
> char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
> /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
> @@ -584,6 +591,17 @@ device_node *spi_nor_get_flash_node(struct spi_nor *nor)
> }
> #endif /* __UBOOT__ */
>
> +/**
> + * spi_nor_setup_op() - Set up common properties of a spi-mem op.
> + * @nor: pointer to a 'struct spi_nor'
> + * @op: pointer to the 'struct spi_mem_op' whose
> properties
> + * need to be initialized.
> + * @proto: the protocol from which the properties need to be set.
> + */
> +void spi_nor_setup_op(const struct spi_nor *nor,
> + struct spi_mem_op *op,
> + const enum spi_nor_protocol proto);
> +
> /**
> * spi_nor_scan() - scan the SPI NOR
> * @nor: the spi_nor structure
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
by: Chin-Ting Kuo
> Signed-off-by: Sean Anderson
Have not looked at it too closely, but the idea sounds good to me.
Acked-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
everting this to v1 for now. I'll try to look at
it later if I ever get some time to spare.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ise continue the previous
> behavior.
>
> Cc: Jagan Teki
> Signed-off-by: Tom Rini
> ---
> Changes in v2:
> - Use IS_ENABLED(...) per Pratyush
Thanks.
For J721E, J7200, J721S2, and cadence_qspi
Reviewed-by: Pratyush Yadav
[...]
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 31/03/22 01:41PM, Tom Rini wrote:
> On Thu, Mar 31, 2022 at 10:00:52PM +0530, Pratyush Yadav wrote:
> > +Vignesh
> >
> > Hi Tom,
> >
> > On 30/03/22 06:07PM, Tom Rini wrote:
> > > This is a little tricky since SoCFPGA has code to determine this as
I_REF_CLK
> +#ifdef CONFIG_HAS_CQSPI_REF_CLK
> plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
> +#elif defined(CONFIG_ARCH_SOCFPGA)
> + plat->ref_clk_hz = cm_get_qspi_controller_clk_hz();
While you are here, please change all this to use if (IS_ENABLED())
instead.
> #else
> return ret;
> #endif
[...]
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
he SPI flash to fail.
>
> Fix the op_len calculation in dw_spi_mem_ops(). Doing so results in
> working SPI flash on the canaan k210 board.
>
> Fixes: d15de623013c ("spi: spi-mem: allow specifying a command's extension")
> Signed-off-by: Niklas Cassel
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ng at spi-nor-ids.c, the flash is defined like this:
> INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
> SECT_4K | SPI_NOR_DUAL_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>
>
> So it appears that after your patch, the bytes are coming in the wrong order.
>
>
> Any suggestions?
>
>
> Kind regards,
> Niklas
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
SI flash
> devices while inside the U-Boot SPL / using spi-nor-tiny.c.
Please don't attach patches, send them inline. This makes it easier to
review it. See the mailing list archive [0] for some examples.
[0] https://lore.kernel.org/u-boot/
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
, SECT_4K |
> > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > + { INFO("mx25uw12345g", 0xc28438, 0, 4 * 1024, 4096, SECT_4K |
> > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > + { INFO("mx25uw6445g",0xc28137, 0, 2 * 1024, 4096, SECT_4K |
> > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > + { INFO("mx25uw6345g",0xc28437, 0, 2 * 1024, 4096, SECT_4K |
> > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
>
> You need to at least specify which of these flashes support SFDP (describing
> the
> supported tables) and which not, otherwise this will become a maintenance
> burden.
> Best would be to dump all the SFDP tables for all the flashes.
>
> My general feeling is that we should re-sync u-boot's SPI NOR subsystem with
> the
> one on linux sooner or later, or the code will become harder to maintain.
> Volunteers, thoughts? :)
I think that would be very nice indeed. But unfortunately I do not have
any bandwidth to spare right now for this.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ng Octal DTR support to kernel and U-Boot SPI NOR, I did
consider parsing this table. But I dropped the idea at the time because
the table guarantees to only use 20 dummy cycles for reads and operation
at 100 MHz (or higher if supported). But this does not guarantee that we
can run the flash at the maximum speed possible. For example, for
Spansion S28 flash we can only go up to 166 MHz with 20 dummy cycles.
For getting 200 MHz we need at least 23 dummy cycles.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
avendra
> Reviewed-by: Dave Gerlach
> Tested-by: Keerthy
Acked-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 17/12/21 06:27AM, tudor.amba...@microchip.com wrote:
> On 12/16/21 8:45 PM, Pratyush Yadav wrote:
> >>>>
> >>>>>
> >>>>>> SFDP signature to determine the mode in which the flash is configured:
> >>>>>> '''
Hi Tudor,
I am not sure if you have sent a re-roll of this series. I am catching
back up on my email backlog.
On 15/11/21 05:44AM, tudor.amba...@microchip.com wrote:
> On 11/12/21 3:13 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless
Hi Marek,
On 28/11/21 10:56PM, Marek Vasut wrote:
> On 10/7/21 2:46 PM, Marek Vasut wrote:
> > On 10/7/21 2:40 PM, Pratyush Yadav wrote:
> > > On 23/09/21 10:00PM, Marek Vasut wrote:
> > > > On 9/23/21 8:53 PM, Pratyush Yadav wrote:
> > > >
Hi Marek,
On 25/10/21 10:25PM, Marek Vasut wrote:
> On 10/25/21 9:53 PM, Pratyush Yadav wrote:
> > On 08/10/21 06:06PM, Jagan Teki wrote:
> > > On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote:
> > > >
> > > > On 9/15/21 10:28 AM, Pratyush Yadav w
ported, so they are no longer
static.
Tested with Cypress S28HS512T and Micron MT35XU512ABA.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/sf_internal.h | 4 +++
drivers/mtd/spi/spi-nor-core.c | 57 --
drivers/mtd/spi/spi-nor-ids.c | 42
On 10/11/21 08:44AM, tudor.amba...@microchip.com wrote:
> On 11/9/21 9:26 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Hi Tudor,
>
> Hi, Pratyush,
>
> Thanks for rev
; fixup hook should be used instead, where SNOR_F_SOFT_RESET should
> be set.
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
struct spi_nor *nor)
>*/
> udelay(SPI_NOR_SRST_SLEEP_LEN);
>
> -out:
> - nor->cmd_ext_type = ext;
> - return ret;
> + return 0;
> }
> #endif /* CONFIG_SPI_FLASH_SOFT_RESET */
>
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
f ROM hands it to us in
> - * Octal DTR mode.
> - *
> - * To accommodate cases where there is more than one flash on a board,
> - * and only one of them needs a soft reset, failure to reset is not
> - * made fatal, and we still try to read ID if possible.
> - */
> - spi_nor_soft_reset(nor);
> -#endif /* CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT */
> -
> info = spi_nor_read_id(nor);
> if (IS_ERR_OR_NULL(info))
> return -ENOENT;
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 08/10/21 06:06PM, Jagan Teki wrote:
> On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote:
> >
> > On 9/15/21 10:28 AM, Pratyush Yadav wrote:
> > > On 14/09/21 08:22PM, Marek Vasut wrote:
> > >> On 9/14/21 7:42 PM, Pratyush Yadav wrote:
> >
0xc28938, 0, 4 * 1024, 4096, SECT_4K |
> SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> + { INFO("mx25uw12345g", 0xc28438, 0, 4 * 1024, 4096, SECT_4K |
> SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> + { INFO("mx25uw6445g",0xc28137, 0, 2 * 1024, 4096, SECT_4K |
> SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> + { INFO("mx25uw6345g",0xc28437, 0, 2 * 1024, 4096, SECT_4K |
> SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> #endif
>
> #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
> --
> 2.17.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
eck for SPI_NOR_4B_OPCODES to fit whatever your flash needs
instead of adding it again.
> /* Send all the required SPI flash commands to initialize device */
> ret = spi_nor_init(nor);
> if (ret)
> --
> 2.17.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
e flash in
-* its default protocol mode assuming no non-volatile configuration was
-* set. This will let us detect the flash even if ROM hands it to us in
-* Octal DTR mode.
-*
-* To accommodate cases where there is more than one flash on a board,
- * and only
e file's changelog looking for people who might be able to help."
>
> Totally appreciate that this is inferred by the change - thanks also for the
> maintainer advice.
You're welcome :-). One more tip: avoid top posting [0].
[0] https://www.idallen.com/topposting.html
>
>
("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES) },
> + { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> #endif
> #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
> /* Macronix */
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
c the subsystem maintainers so that they can see the
patch and review and apply it. You can use `./scripts/get_maintainer.pl
` to get the list of people who need to be in Cc.
Adding Jagan and Vignesh for this patch.
Anyway, with the Tested-by trailer dropped,
Acked-by: Pratyush Yadav
> ---
>
On 23/09/21 10:00PM, Marek Vasut wrote:
> On 9/23/21 8:53 PM, Pratyush Yadav wrote:
> > On 14/09/21 05:28AM, Marek Vasut wrote:
> > > Set the SF page size, erase block size and total size as an environment
> > > variable after "sf probe". This lets us discer
On 01/10/21 11:25AM, Marek Behún wrote:
> On Tue, 28 Sep 2021 22:29:11 +0530
> Pratyush Yadav wrote:
>
> > On 25/09/21 07:33PM, Marek Behún wrote:
> > > From: Marek Behún
> > >
> > > This check is already done in mtdcore's mtd_erase(), no reason to do
re use, the fixups is assigned for S25FS-S family.
>
> The datasheet can be found in the following link.
> https://www.cypress.com/file/216376/download
>
> Tested on Xilinx Zynq-7000 FPGA board.
>
> Signed-off-by: Takahiro Kuwano
Acked-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
len %lld\n", (long long)instr->addr,
> (long long)instr->len);
>
> - if (!instr->len)
> - return 0;
> -
> div_u64_rem(instr->len, mtd->erasesize, );
> if (rem)
> return -EINVAL;
> --
> 2.32.0
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
Masami Hiramatsu
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 25/09/21 07:33PM, Marek Behún wrote:
> From: Marek Behún
>
> The spi_nor_erase() function does not check return value of the
> write_enable() call. Fix this.
This is the case for many more calls for write_enable(), but we can fix
them later I suppose.
Reviewed-by: Pr
/* Send all the required SPI flash commands to initialize device */
> ret = spi_nor_init(nor);
> if (ret)
> --
> 2.17.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
; + env_set_hex("sf_pagesize", nor->page_size);
> print_size(nor->erase_size, ", total ");
> + env_set_hex("sf_erasesize", nor->erase_size);
> print_size(nor->size, "");
> + env_set_hex("sf_size", nor->size);
> puts("\n");
> #endif
>
> --
> 2.33.0
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
Hi Simon,
On 19/09/21 03:49PM, Simon Glass wrote:
> Update this code to use IS_ENABLED() instead.
>
> Signed-off-by: Simon Glass
>
> Reviewed-by: Pratyush Yadav
Nitpick: Trailers shouldn't have a blank line between them. I see it for
this patch and 4/5 as well. It probably
> +}
> +
> +static struct spi_nor_fixups s25fs_s_fixups = {
> + .default_init = s25fs_s_default_init,
> + .post_bfpt = s25fs_s_post_bfpt_fixup,
> + .post_sfdp = s25fs_s_post_sfdp_fixup,
> +};
> +
> static int s25hx_t_mdp_ready(struct spi_nor *nor)
> {
> u32 addr;
> @@ -3644,6 +3740,11 @@ void spi_nor_set_fixups(struct spi_nor *nor)
> break;
> }
> }
> +
> + /* For FS-S (family ID = 0x81) */
> + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION &&
> + nor->info->id[5] == 0x81)
> + nor->fixups = _s_fixups;
Ok.
> #endif
>
> #ifdef CONFIG_SPI_FLASH_S28HS512T
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ange this to
if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) && !strcmp())
> + if (!strcmp(nor->info->name, "s25fl256l"))
> + nor->fixups = _fixups;
> +#endif
*sigh* we really need to find a better way to specify fixups. Let me see
if I can figure something out. In the meantime, this should be fine.
> #endif
>
> #ifdef CONFIG_SPI_FLASH_S28HS512T
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> USE_CLSR) },
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
MD_EXT_INVERT
> + nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
> +#endif
Avoid using #ifdef. You can replace it with
if (CONFIG_IS_ENABLED(SPI_NOR_CMD_EXT_INVERT))
nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
else
nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
>
On 14/09/21 08:22PM, Marek Vasut wrote:
> On 9/14/21 7:42 PM, Pratyush Yadav wrote:
> > On 14/09/21 05:22AM, Marek Vasut wrote:
> > > Wait for the read/write transfer finish bit get actually cleared,
> > > this does not happen immediately on at least SoCFPGA Gen5.
> &
dummy bytes in such a case.
>
> Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes")
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Vignesh R
> Cc: Pratyush Yadav
> ---
> drivers/spi/cadence_qspi_apb.c | 3 +++
> 1 file chang
On 14/09/21 05:22AM, Marek Vasut wrote:
> Wait for the read/write transfer finish bit get actually cleared,
> this does not happen immediately on at least SoCFPGA Gen5.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Vignesh R
> Cc: Pratyush Yadav
> ---
> dri
8_8_8_DTR);
> + ret = spi_mem_exec_op(nor->spi, );
> + if (ret) {
> + dev_warn(nor->dev, "Software reset failed: %d\n", ret);
> + goto out;
> + }
> +
> + udelay(SPI_NOR_SRST_SLEEP_LEN);
> +
> out:
> nor->cmd_ext_type = ext;
> return ret;
> --
> 2.17.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
G_MXIC_OPI_DTR_DIS 0x1 /* Disable Octal DTR */
> +#define SPINOR_REG_MXIC_CR2_DC 0x0300 /* For setting
> dummy cycles */
> +#define SPINOR_REG_MXIC_DC_200x0 /* Setting
> dummy cycles to 20 */
> +#define MXIC_MAX_DC 20 /* Maximum value of
> dummy cycles */
>
> /* Used for Spansion flashes only. */
> #define SPINOR_OP_BRWR 0x17/* Bank register write */
> --
> 2.17.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
ocated for two buffers, each bytes in size. At typical
> +size is 64KB to 1MB. The offset and size must be aligned to an erase
> boundary.
> +
> +Note that this test will fail if any part of the SPI flash is
> write-protected.
> +
> +
> +Examples
> +
> +
> +This first exam
t; at `addr' to flash at
> `offset'\n"
> " or to start of mtd
> `partition'\n"
> "sf protect lock/unlock sector len - protect/unprotect 'len' bytes
> starting\n"
> - "
_1_1);
>
> - if (!(info->flags & SPI_NOR_NO_FR)) {
> - params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
> + if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
> spi_nor_set_read_settings(>reads[SNOR_CMD_READ_FAST],
>
FAST;
> + if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
> spi_nor_set_read_settings(>reads[SNOR_CMD_READ_FAST],
> 0, 8, SPINOR_OP_READ_FAST,
> SNOR_PROTO_1_1_1);
> - }
The patch looks good to me other than the point above.
>
> if (info->flags & SPI_NOR_DUAL_READ) {
> params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
s = params->hwcaps.mask but I
think having SNOR_HWCAPS_ALL here to signify that we are assuming
controller supports everything is not a bad idea IMO.
With the above comment updated,
Reviewed-by: Pratyush Yadav
Thanks.
>
> /* X-X-X modes are not supported yet, mask them all. */
ata.nbytes,
> slave->max_write_size - len);
> + }
>
> if (!op->data.nbytes)
> return -EINVAL;
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
yet, mask them all. */
*hwcaps &= ~SNOR_HWCAPS_X_X_X;
Can you please test and confirm if it does indeed fix the issue for you?
> rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
> if (rdidx >= 0 &&
> spi_nor_check_readop(nor, >reads[rdidx]))
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 28/07/21 06:13PM, Bin Meng wrote:
> Hi Pratyush,
>
> On Sat, Jun 26, 2021 at 3:20 AM Pratyush Yadav wrote:
> >
> > The spi-mem layer provides a spi_mem_supports_op() function to check
> > whether a specific operation is supported by the controller or not.
> >
ntroller")
> Signed-off-by: Michael Walle
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
you
seem to be terminating them at 60.
Other than this,
Reviewed-by: Pratyush Yadav
>
> Signed-off-by: Patrick Wildt
> ---
> include/mux.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/mux.h b/include/mux.h
> index 23844f480a..
On 28/06/21 12:09PM, Jagan Teki wrote:
> On Sun, Jun 27, 2021 at 2:05 PM Pratyush Yadav wrote:
> >
> > On 26/06/21 02:44PM, Jagan Teki wrote:
> > > On Sat, Jun 26, 2021 at 12:47 AM Pratyush Yadav wrote:
> > > >
> > > > spi_mem_default_su
On 26/06/21 02:44PM, Jagan Teki wrote:
> On Sat, Jun 26, 2021 at 12:47 AM Pratyush Yadav wrote:
> >
> > spi_mem_default_supports_op() rejects DTR ops by default to ensure that
> > the controller drivers that haven't been updated with DTR support
> > continue to reje
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav
versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig| 8 ++
drivers/mtd/spi/spi-nor-core.c | 187 +
drivers/mtd/spi/spi-nor-ids.c | 3 +
include/linux/mtd/spi-nor.h
KiB sectors till the end.
Let the flash-specific erase functions erase less than the requested
length in case of the 4 or 128 KiB sectors and report the number of
bytes erased back to the calling function.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 16 +++-
1 f
used.
Signed-off-by: Takahiro Kuwano
Signed-off-by: Pratyush Yadav
[p.ya...@ti.com: Refactor the function to be compatible with nor->erase,
make 4K opcode customizable, call spi_nor_setup_op() before executing
the op.]
---
drivers/mtd/spi/spi-nor-core.c | 61 ++
ven if ROM hands it to us in Octal
DTR mode.
To accommodate cases where there is more than one flash on a board, and
only one of them needs a soft reset, failure to reset is not made fatal,
and we still try to read ID if possible.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig
assumes that we don't set any non-volatile bits anywhere,
and the flash doesn't have any non-volatile Octal DTR mode
configuration.
Since spi-nor-tiny doesn't (and likely shouldn't) have
spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does
nothing.
Signed-off-by: Pratyush Yadav
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
include/linux/mtd/spi
o abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-cor
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33 insertions
mode read 2 bytes and discard the second. This shows
no side effects with the two flashes I tested: Micron mt35xu512aba and
Cypress s28hs512t.
Update Read FSR to mimic Read SR because they share the same
characteristics.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 60
dummy cycles for a fast octal DTR read are set to 20. Since
there is no simple way of determining the dummy cycles needed for the
fast read command, flashes that use a different value should update it
in their flash-specific hooks.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c
there is no data to write.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 24c6b8c4a3..d795ecbc9f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers
uct
spi_nor_fixups in nor->info. This is not possible in U-Boot because the
spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c.
Since spi-nor-tiny shouldn't have those fixup hooks populated, add a
separate function that lets flashes populate their fixup hooks.
Signed-off-by: Pratyush
-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index c2eae885e4..5a65597616 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor
d "inverse" extensions are supported.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 5a65597616..d9af5cbf97 100644
--- a/dri
phases need to be either DTR or STR.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 178 +
include/linux/mtd/spi-nor.h| 50 ++---
3 files changed, 175 insertions(+), 54 deletions(-)
diff --git
: Rework hwcaps
selection for the spi-mem case, 2019-08-06)
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig| 9 ++
drivers/mtd/spi/spi-nor-core.c | 244 ++---
drivers/spi/spi-mem-nodm.c | 62 +
include/linux/mtd/spi-nor.h| 17 ++-
4
ons to avoid forward declarations.
Inspired by the Linux kernel's setup() hook.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 84 +++
drivers/mtd/spi/spi-nor-tiny.c | 22
include/linux/mtd/spi-nor.h| 192 ++---
3 files changed,
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
spi-mem take care of polling the SR.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 39 -
drivers/spi/cadence_qspi.h | 14 +-
drivers/spi/cadence_qspi_apb.c | 286 ++---
3 files changed, 313 insertions(+), 26 deletions(-)
diff --git
324f78dfb442b82365548b657ec4e6974c677502.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6af9c675a4..bfe7ea55c4 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 4
drivers
. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 26
(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 32
to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav
---
drivers/spi/mtk_snfi_spi.c | 3 +--
drivers/spi/spi-mem-nodm.c | 4 ++--
drivers/spi/spi-mem.c | 13 +++--
include/spi-mem.h | 6 +-
4 files ch
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