Re: [U-Boot] [EXT] Re: [PATCH 1/2] drivers/mtd/spi: Enable 4B opcodes for SPANSION s25fl512s
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Wednesday, April 24, 2019 10:08 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de;
> ja...@openedev.com
> Cc: Ashish Kumar
> Subject: [EXT] Re: [PATCH 1/2] drivers/mtd/spi: Enable 4B opcodes for
> SPANSION s25fl512s
>
> Caution: EXT Email
>
> Hi.
>
> On 24-Apr-19 6:10 PM, Rajat Srivastava wrote:
> > From: Ashish Kumar
> >
> > Signed-off-by: Ashish Kumar
> > ---
> > drivers/mtd/spi/spi-nor-ids.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c
> > b/drivers/mtd/spi/spi-nor-ids.c index ec929760ee..a89c1910d9 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -177,7 +177,7 @@ const struct flash_info spi_nor_ids[] = {
> > { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
> > { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> > - { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> > + { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256,
> > + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR |
> > + SPI_NOR_4B_OPCODES) },
>
> You should not be needing this change to enable 4 Byte opcodes. From
> spi-nor-core.c:
>
>
> if (nor->addr_width) {
> /* already configured from SFDP */
> } else if (info->addr_width) {
> nor->addr_width = info->addr_width;
> } else if (mtd->size > SZ_16M) { #ifndef CONFIG_SPI_FLASH_BAR
> /* enable 4-byte addressing if the device exceeds 16MiB */
> nor->addr_width = 4;
> if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
> info->flags & SPI_NOR_4B_OPCODES)
> spi_nor_set_4byte_opcodes(nor, info); #else
> /* Configure the BAR - discover bank cmds and read current bank */
> nor->addr_width = 3;
> ret = read_bar(nor, info);
> if (ret < 0)
> return ret;
> #endif
> }
> [...]
>
>
> So as long as SPI_FLASH_BAR is not set, 4 Byte opcodes are used by default
> with Spansion flashes >16M size. If that's not the case, then we need to root
> cause the actual bug instead of adding SPI_NOR_4B_OPCODES to s25fl512s
You are right. I've tested without using SPI_NOR_4B_OPCODES flag and it is
working now. Deprecating this patch now.
Regards
Rajat
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[U-Boot] [PATCH v2] fsl_qspi: Improve QSPI driver to incorporate 4 byte commands
Previously, the SPI framework supported only 3-byte opcodes
but the FSL QSPI controller used to deal with flashes that
work with 4-byte opcodes. As a workaround to resolve this,
for every 3-byte opcodes sent by framework FSL QSPI driver
used to explicitly send corresponding 4-byte opcodes.
Now the framework has been updated to send 4-byte opcodes
and FSL QSPI driver needs correction. This change will be
applicable for the following defconfig where we disable
CONFIG_FLASH_BAR:
LS1088A, LS1046A, LS1043A, LS1012A, LS2088A defconfigs
Signed-off-by: Ashish Kumar
Signed-off-by: Rajat Srivastava
---
Changes in v2:
- Update commit message
- Reduce patchset to one patch
- This patch is no more applicable:
https://patchwork.ozlabs.org/patch/1090122/
drivers/spi/fsl_qspi.c | 45 +-
1 file changed, 31 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1598c4f698..217005f525 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -26,7 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK GENMASK(23, 0)
+#define OFFSET_BITS_MASK GENMASK(27, 0)
+#define OFFSET_BITS_MASK_24GENMASK(23, 0)
#define FLASH_STATUS_WEL 0x02
@@ -754,7 +755,8 @@ static void qspi_op_erase(struct fsl_qspi_priv *priv)
while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
;
- if (priv->cur_seqid == QSPI_CMD_SE) {
+ if ((priv->cur_seqid == QSPI_CMD_SE_4B) ||
+ (priv->cur_seqid == QSPI_CMD_SE)) {
qspi_write32(priv->flags, >ipcr,
(SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
} else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
@@ -775,31 +777,44 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int
bitlen,
u32 txbuf;
WATCHDOG_RESET();
-
if (dout) {
if (flags & SPI_XFER_BEGIN) {
priv->cur_seqid = *(u8 *)dout;
- memcpy(, dout, 4);
+ if (FSL_QSPI_FLASH_SIZE > SZ_16M && bytes > 4)
+ memcpy(, dout + 1, 4);
+ else
+ memcpy(, dout, 4);
}
if (flags == SPI_XFER_END) {
priv->sf_addr = wr_sfaddr;
- qspi_op_write(priv, (u8 *)dout, bytes);
- return 0;
+ if (priv->cur_seqid == QSPI_CMD_PP ||
+ priv->cur_seqid == QSPI_CMD_PP_4B ||
+ priv->cur_seqid == QSPI_CMD_WRAR) {
+ qspi_op_write(priv, (u8 *)dout, bytes);
+ return 0;
+ }
}
- if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
- priv->cur_seqid == QSPI_CMD_RDAR) {
+ if ((priv->cur_seqid == QSPI_CMD_FAST_READ) ||
+ (priv->cur_seqid == QSPI_CMD_FAST_READ_4B)) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
+ } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
+ priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK_24;
} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
- (priv->cur_seqid == QSPI_CMD_BE_4K)) {
+ priv->cur_seqid == QSPI_CMD_SE_4B) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
qspi_op_erase(priv);
+ } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
+ priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK_24;
+ qspi_op_erase(priv);
} else if (priv->cur_seqid == QSPI_CMD_PP ||
- priv->cur_seqid == QSPI_CMD_WRAR) {
+ priv->cur_seqid == QSPI_CMD_PP_4B) {
wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
+ } else if (priv->cur_seqid == QSPI_CMD_WRAR) {
+ wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK_24;
} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
-(priv->cur_seqid == QSPI_CMD_WREAR)) {
+ (priv->cur_seqid == QSPI_CMD_WREAR)) {
#ifdef CONFIG_SPI_FLASH_BAR
wr_sfaddr = 0;
#endif
@@ -807,7 +822,8 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int
bitlen,
}
if (din) {
- if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
+ if ((priv->cur_seqid == QSPI_CMD_FAST_READ) ||
+ (priv->cur_seqid == QSPI_CMD_FAST_READ_4B)) {
#ifdef CONFIG_SYS_FSL_QSPI_A
Re: [U-Boot] [EXT] Re: [PATCH 2/2] fsl_qspi: Improve QSPI driver to incorporate 4 byte commands
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Wednesday, April 24, 2019 10:17 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de;
> ja...@openedev.com
> Cc: Ashish Kumar
> Subject: [EXT] Re: [PATCH 2/2] fsl_qspi: Improve QSPI driver to incorporate 4
> byte commands
>
> Caution: EXT Email
>
> On 24-Apr-19 6:10 PM, Rajat Srivastava wrote:
> > Signed-off-by: Ashish Kumar
> > Signed-off-by: Rajat Srivastava
>
> Commit message is missing.
I'll add proper commit message in the next patch version.
> But from $patch subject, I infer that $patch is
> adding new feature and not actually fixing something broken?
Earlier the framework was designed to work for only 3-byte opcodes but our
controller supports flashes of size greater than 16 MB. As a workaround,
FSL QSPI driver used to explicitly send 4-byte opcodes for 3-byte opcodes sent
by
framework to the flash. Also there used to exist a temporary patch for framework
which never got accepted In upstream.
Now the new framework supports 4-byte opcodes and FSL QSPI driver needs
correction. I am not introducing any new feature. I am just fixing the driver
to suit the current framework.
Please let me know your feedback.
Regards
Rajat
> If so, you should move the driver over to use spi-mem APIs instead of adding
> more features and hard coding more flash specific commands in the driver.
> This makes driver duplicate more of spi-nor core code. I discourage adding
> new features w/o moving driver over to spi-mem. IMHO, converting the
> driver would not be a huge effort. And I believe its already done in kernel.
>
> Regards
> Vignesh
>
> > ---
> > drivers/spi/fsl_qspi.c | 38 +-
> > 1 file changed, 25 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 1598c4f698..1d26c6344b 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
> > #define TX_BUFFER_SIZE 0x40
> > #endif
> >
> > -#define OFFSET_BITS_MASK GENMASK(23, 0)
> > +#define OFFSET_BITS_MASK GENMASK(27, 0)
> >
> > #define FLASH_STATUS_WEL 0x02
> >
> > @@ -754,7 +754,8 @@ static void qspi_op_erase(struct fsl_qspi_priv *priv)
> > while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
> > ;
> >
> > - if (priv->cur_seqid == QSPI_CMD_SE) {
> > + if ((priv->cur_seqid == QSPI_CMD_SE_4B) ||
> > + (priv->cur_seqid == QSPI_CMD_SE)) {
> > qspi_write32(priv->flags, >ipcr,
> >(SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
> > } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { @@ -775,31
> > +776,40 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
> > u32 txbuf;
> >
> > WATCHDOG_RESET();
> > -
> > if (dout) {
> > if (flags & SPI_XFER_BEGIN) {
> > priv->cur_seqid = *(u8 *)dout;
> > - memcpy(, dout, 4);
> > + if (FSL_QSPI_FLASH_SIZE > SZ_16M && bytes > 4)
> > + memcpy(, dout + 1, 4);
> > + else
> > + memcpy(, dout, 4);
> > }
> >
> > if (flags == SPI_XFER_END) {
> > priv->sf_addr = wr_sfaddr;
> > - qspi_op_write(priv, (u8 *)dout, bytes);
> > - return 0;
> > + if (priv->cur_seqid == QSPI_CMD_PP ||
> > + priv->cur_seqid == QSPI_CMD_PP_4B ||
> > + priv->cur_seqid == QSPI_CMD_WRAR) {
> > + qspi_op_write(priv, (u8 *)dout, bytes);
> > + return 0;
> > + }
> > }
> >
> > - if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
> > - priv->cur_seqid == QSPI_CMD_RDAR) {
> > + if ((priv->cur_seqid == QSPI_CMD_FAST_READ) ||
> > + (priv->cur_seqid == QSPI_CMD_FAST_READ_4B) ||
> > + (priv->cur_seqid == QSPI_CMD_RDAR)) {
> > priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
> > } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
> > -(priv->cur_seqid == QSPI_CMD_BE_4K)) {
> > +priv->cur_seqid == QSPI_CMD_SE_4B ||
&g
[U-Boot] [PATCH] configs: lx2160a: change env location to SPI_FLASH
Change env location to SPI_FLASH. Signed-off-by: Rajesh Bhagat Signed-off-by: Rajat Srivastava --- configs/lx2160ardb_tfa_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 2dc49c7f5d..2a2609f80b 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/5] ls1088ardb: qspi: tfa: Enable config to write aligned data to TxFIFO
Enable config in LS1088A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Pankit Garg Signed-off-by: Rajat Srivastava --- configs/ls1088ardb_tfa_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index b41f577be4..93fbbf36d7 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -40,6 +40,7 @@ CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_SPI_FLASH_BAR is not set CONFIG_E1000=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/5] Kconfig: qspi: Add SPI_ALIGNED_TXFIFO config details
From: Ashish Kumar This config makes driver send only 16 bytes aligned data to TxFIFO while writing on flash. Signed-off-by: Rajat Srivastava Signed-off-by: Ashish Kumar --- drivers/spi/Kconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fb794adae7..80621027df 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -33,6 +33,15 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config FSL_SPI_ALIGNED_TXFIFO + bool "Write only 16 Bytes aligned data on TxFIFO" + depends on FSL_QSPI + help + For some boards, Freescale controller needs driver to fill TxFIFO + till 16 bytes to trigger data transfer, in case of flash write. + This config enables the Freescale QSPI driver to send 16 bytes + aligned data to TxFIFO while performing flash write operation. + config ATCSPI200_SPI bool "Andestech ATCSPI200 SPI driver" help -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/5] ls2088a: qspi: Enable config to write aligned data to TxFIFO
From: Ashish Kumar Enable config in LS2088A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Rajat Srivastava Signed-off-by: Ashish Kumar --- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index dd001db858..5f63e4f62b 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 2beb047dcf..55640bbc14 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -54,6 +54,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/5] ls2080a: qspi: Enable config to write aligned data to TxFIFO
From: Ashish Kumar Enable config in LS2080A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Rajat Srivastava Signed-off-by: Ashish Kumar --- configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 6741c82d4c..1c5727aeb3 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -62,6 +62,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index fd57245ddb..0f2fbd8a93 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index e89eaa91a7..e812ecd7d5 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -60,6 +60,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/5] ls1088a: qspi: Enable config to write aligned data to TxFIFO
From: Ashish Kumar Enable config in LS1088A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Rajat Srivastava Signed-off-by: Ashish Kumar --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 1 + configs/ls1088aqds_qspi_defconfig| 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig| 1 + configs/ls1088ardb_qspi_defconfig| 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + 7 files changed, 7 insertions(+) diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 08d10a5cef..9bd864ca2c 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 22b3de15da..2671371f52 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 11a34b2294..cddd9ba0be 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index d9220d4be0..d034288c55 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 611a761af1..303828d577 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -38,6 +38,7 @@ CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 4e8ab6e584..c361e77d0a 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_SCSI_AHCI=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 1a15045b10..667df54117 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -47,6 +47,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] qspi: Add code to send only aligned data to TxFIFO
Some Freescale QSPI controllers require driver to send only 16 bytes
aligned data to TxFIFO while performing flash write operation. The extra
data is not actually written on flash. The patch enables driver to send
16 bytes aligned data to TxFIFO, provided the config is enabled.
The reason behind this behaviour of controller is still not clear and
discussion with hardware team is ongoing. The patch will be updated
before sending it to upstream.
Signed-off-by: Rajat Srivastava
---
drivers/spi/fsl_qspi.c | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1d26c6344b..b93e89ff32 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -676,20 +676,35 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8
*txbuf, u32 len)
tx_size = (len > TX_BUFFER_SIZE) ?
TX_BUFFER_SIZE : len;
- size = tx_size / 16;
+ size = tx_size / 4;
+ for (i = 0; i < size; i++) {
+ memcpy(, txbuf, 4);
+ data = qspi_endian_xchg(data);
+ qspi_write32(priv->flags, >tbdr, data);
+ txbuf += 4;
+ }
+#if defined(CONFIG_FSL_SPI_ALIGNED_TXFIFO)
/*
-* There must be atleast 128bit data
-* available in TX FIFO for any pop operation
+* There must be at least 16 bytes of data
+* available in TX FIFO for any POP operation
*/
- if (tx_size % 16)
- size++;
- for (i = 0; i < size * 4; i++) {
+ size = (((tx_size/16) + 1) * 4) - size;
+ for (i = 0; i < size; i++) {
+ data = 0;
memcpy(, txbuf, 4);
data = qspi_endian_xchg(data);
qspi_write32(priv->flags, >tbdr, data);
txbuf += 4;
}
-
+#else
+ size = tx_size % 4;
+ if (size) {
+ data = 0;
+ memcpy(, txbuf, size);
+ data = qspi_endian_xchg(data);
+ qspi_write32(priv->flags, >tbdr, data);
+ }
+#endif
qspi_write32(priv->flags, >ipcr,
(seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
--
2.17.1
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[U-Boot] [PATCH 1/3] configs: Unset CONFIG_SPI_BAR for all LS1088A defconfigs
From: Ashish Kumar Signed-off-by: Ashish Kumar Signed-off-by: Rajat Srivastava --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 1 + configs/ls1088aqds_qspi_defconfig| 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088aqds_tfa_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig| 1 + configs/ls1088ardb_qspi_defconfig| 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + 10 files changed, 10 insertions(+) diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 0254a861d8..08d10a5cef 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -16,6 +16,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x300 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 9160de255d..22b3de15da 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +# CONFIG_SPI_FLASH_BAR is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 6a9577aba2..11a34b2294 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -20,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x300 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 891810a583..863d9c3361 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -17,6 +17,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x300 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 78aec38a12..d9220d4be0 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 5503a71d3c..611a761af1 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_CMD_SETEXPR is not set CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index b53f212125..4e8ab6e584 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index a7cdead46e..1a15045b10 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=
[U-Boot] [PATCH 3/3] configs: Unset CONFIG_SPI_BAR for all LS2080A/LS2081A defconfigs
Signed-off-by: Rajat Srivastava --- configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2081ardb_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + 8 files changed, 8 insertions(+) diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 170c2ce15f..6741c82d4c 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index a3e35bd77d..fd57245ddb 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index d4c64a52f1..e89eaa91a7 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index d7c8a5613c..f2b8db6cb4 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 3fedbc2038..dd001db858 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -13,6 +13,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index ff1f95f081..2beb047dcf 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 058b3dd938..ee3a83a075 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index e15156be3e..74fdbbeb8d 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CO
[U-Boot] [PATCH 2/3] configs: Unset CONFIG_SPI_BAR for all LS1046A defconfigs
Signed-off-by: Rajat Srivastava --- configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig| 1 + configs/ls1046aqds_tfa_defconfig| 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_qspi_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig| 1 + configs/ls1046ardb_tfa_defconfig| 1 + 11 files changed, 11 insertions(+) diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 4cc19fe7ac..1e9a6c7480 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -12,6 +12,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=155.quadspi:2m(uboot),14m(free)" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index a7620d23ad..180a36c952 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=155.quadspi:2m(uboot),14m(free)" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index ede5df6224..60a7b13205 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=6000.nor:2m@0x10(nor_bank0_uboot),40m@0x110(nor_bank0_fit),7m(nor_bank0_user),2m@0x410(nor_bank4_uboot),40m@0x510(nor_bank4_fit),-(nor_bank4_user);7e80.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 4b45289869..cdad734fc9 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=155.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" # CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_MISC_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 27309bfa33..882170c9f7 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -32,6 +32,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index d2850480d6..48b44a87a1 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -33,6 +33,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 975cc580bd..c10a007fcc 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_MTDPARTS_DEFAULT="mtdparts=155.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" # CONFIG_SPL_EFI_PARTITION is not set +# CONFIG_SPI_FLASH_BAR is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 643a52039a..eb50146b33 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_CACH
[U-Boot] [PATCH 2/2] fsl_qspi: Improve QSPI driver to incorporate 4 byte commands
Signed-off-by: Ashish Kumar
Signed-off-by: Rajat Srivastava
---
drivers/spi/fsl_qspi.c | 38 +-
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1598c4f698..1d26c6344b 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK GENMASK(23, 0)
+#define OFFSET_BITS_MASK GENMASK(27, 0)
#define FLASH_STATUS_WEL 0x02
@@ -754,7 +754,8 @@ static void qspi_op_erase(struct fsl_qspi_priv *priv)
while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
;
- if (priv->cur_seqid == QSPI_CMD_SE) {
+ if ((priv->cur_seqid == QSPI_CMD_SE_4B) ||
+ (priv->cur_seqid == QSPI_CMD_SE)) {
qspi_write32(priv->flags, >ipcr,
(SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
} else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
@@ -775,31 +776,40 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int
bitlen,
u32 txbuf;
WATCHDOG_RESET();
-
if (dout) {
if (flags & SPI_XFER_BEGIN) {
priv->cur_seqid = *(u8 *)dout;
- memcpy(, dout, 4);
+ if (FSL_QSPI_FLASH_SIZE > SZ_16M && bytes > 4)
+ memcpy(, dout + 1, 4);
+ else
+ memcpy(, dout, 4);
}
if (flags == SPI_XFER_END) {
priv->sf_addr = wr_sfaddr;
- qspi_op_write(priv, (u8 *)dout, bytes);
- return 0;
+ if (priv->cur_seqid == QSPI_CMD_PP ||
+ priv->cur_seqid == QSPI_CMD_PP_4B ||
+ priv->cur_seqid == QSPI_CMD_WRAR) {
+ qspi_op_write(priv, (u8 *)dout, bytes);
+ return 0;
+ }
}
- if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
- priv->cur_seqid == QSPI_CMD_RDAR) {
+ if ((priv->cur_seqid == QSPI_CMD_FAST_READ) ||
+ (priv->cur_seqid == QSPI_CMD_FAST_READ_4B) ||
+ (priv->cur_seqid == QSPI_CMD_RDAR)) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
- (priv->cur_seqid == QSPI_CMD_BE_4K)) {
+ priv->cur_seqid == QSPI_CMD_SE_4B ||
+ priv->cur_seqid == QSPI_CMD_BE_4K) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
qspi_op_erase(priv);
} else if (priv->cur_seqid == QSPI_CMD_PP ||
+ priv->cur_seqid == QSPI_CMD_PP_4B ||
priv->cur_seqid == QSPI_CMD_WRAR) {
wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
-(priv->cur_seqid == QSPI_CMD_WREAR)) {
+ (priv->cur_seqid == QSPI_CMD_WREAR)) {
#ifdef CONFIG_SPI_FLASH_BAR
wr_sfaddr = 0;
#endif
@@ -807,7 +817,8 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int
bitlen,
}
if (din) {
- if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
+ if ((priv->cur_seqid == QSPI_CMD_FAST_READ) ||
+ (priv->cur_seqid == QSPI_CMD_FAST_READ_4B)) {
#ifdef CONFIG_SYS_FSL_QSPI_AHB
qspi_ahb_read(priv, din, bytes);
#else
@@ -815,10 +826,11 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int
bitlen,
#endif
} else if (priv->cur_seqid == QSPI_CMD_RDAR) {
qspi_op_read(priv, din, bytes);
- } else if (priv->cur_seqid == QSPI_CMD_RDID)
+ } else if (priv->cur_seqid == QSPI_CMD_RDID) {
qspi_op_rdid(priv, din, bytes);
- else if (priv->cur_seqid == QSPI_CMD_RDSR)
+ } else if (priv->cur_seqid == QSPI_CMD_RDSR) {
qspi_op_rdsr(priv, din, bytes);
+ }
#ifdef CONFIG_SPI_FLASH_BAR
else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
(priv->cur_seqid == QSPI_CMD_RDEAR)) {
--
2.17.1
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[U-Boot] [PATCH 1/2] drivers/mtd/spi: Enable 4B opcodes for SPANSION s25fl512s
From: Ashish Kumar
Signed-off-by: Ashish Kumar
---
drivers/mtd/spi/spi-nor-ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index ec929760ee..a89c1910d9 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -177,7 +177,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
{ INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
- { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+ { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR | SPI_NOR_4B_OPCODES) },
{ INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
--
2.17.1
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[U-Boot] [RESEND PATCH v2] mtd: spi: Improve spi_nor_write_data() implementation
Maximum write size in a single write operation in
spi_nor_write_data() function can be equal to slave
tx buffer, which is adjusted in spi_mem_adjust_op_size()
and write operation gets fragmented.
Previously data write for the above fragmentation
didn't incorporate write enable and status checks.
It was sent to flash at page offsets only.
Signed-off-by: Rajat Srivastava
---
Changes in v2:
Incorporating review comments given by Vignesh.
[PATCH v1]: https://patchwork.ozlabs.org/patch/1078183/
drivers/mtd/spi/spi-nor-core.c | 28 ++--
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index c4e2f6a08f..8e754d445d 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -116,7 +116,6 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(len, buf, 1));
- size_t remaining = len;
int ret;
/* get transfer protocols. */
@@ -127,22 +126,19 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op.addr.nbytes = 0;
- while (remaining) {
- op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
- ret = spi_mem_adjust_op_size(nor->spi, );
- if (ret)
- return ret;
+ op.data.nbytes = len < UINT_MAX ? len : UINT_MAX;
+ ret = spi_mem_adjust_op_size(nor->spi, );
+ if (ret)
+ return ret;
- ret = spi_mem_exec_op(nor->spi, );
- if (ret)
- return ret;
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
- op.addr.val += op.data.nbytes;
- remaining -= op.data.nbytes;
- op.data.buf.out += op.data.nbytes;
- }
+ op.addr.val += op.data.nbytes;
+ op.data.buf.out += op.data.nbytes;
- return len;
+ return op.data.nbytes;
}
/*
@@ -1101,10 +1097,6 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t
to, size_t len,
goto write_err;
*retlen += written;
i += written;
- if (written != page_remain) {
- ret = -EIO;
- goto write_err;
- }
}
write_err:
--
2.17.1
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[U-Boot] [PATCH v4 2/2] fsl-lsch3: soc: Enable AHB read support for Flexspi controller
Enable AHB support for Flexspi controller interface meaning
memory can be accessed via md command using absolute addresses
Signed-off-by: Yogesh Gaur
Signed-off-by: Ashish Kumar
Signed-off-by: Rajat Srivastava
---
v4:
- Remove unnecessary dependencies of FSPI_AHB_EN_4BYTE config
- Enable this config by default
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 9
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 44 +++
.../arm/include/asm/arch-fsl-layerscape/soc.h | 7 +++
3 files changed, 60 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f48481f465..5151308f96 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -374,6 +374,15 @@ config QSPI_AHB_INIT
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
+config FSPI_AHB_EN_4BYTE
+ bool "Enable 4-byte Fast Read command for AHB mode"
+ default y
+ help
+ The default setting for FlexSPI AHB bus just supports 3-byte
addressing.
+ But some FlexSPI flash sizes are up to 64MBytes.
+ This flag enables fast read command for AHB mode and modifies required
+ LUT to support full FlexSPI flash.
+
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 06f3edb302..a38f3ebb47 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -644,6 +644,47 @@ void fsl_lsch2_early_init_f(void)
}
#endif
+#ifdef CONFIG_FSPI_AHB_EN_4BYTE
+int fspi_ahb_init(void)
+{
+ /* Enable 4bytes address support and fast read */
+ u32 *fspi_lut, lut_key, *fspi_key;
+
+ fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
+ fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
+
+ lut_key = in_be32(fspi_key);
+
+ if (lut_key == SYS_NXP_FSPI_LUTKEY) {
+ /* That means the register is BE */
+ out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+ /* Unlock the lut table */
+ out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
+ /* Create READ LUT */
+ out_be32(fspi_lut, 0x0820040c);
+ out_be32(fspi_lut + 1, 0x24003008);
+ out_be32(fspi_lut + 2, 0x);
+ /* Lock the lut table */
+ out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+ out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
+ } else {
+ /* That means the register is LE */
+ out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+ /* Unlock the lut table */
+ out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
+ /* Create READ LUT */
+ out_le32(fspi_lut, 0x0820040c);
+ out_le32(fspi_lut + 1, 0x24003008);
+ out_le32(fspi_lut + 2, 0x);
+ /* Lock the lut table */
+ out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+ out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_QSPI_AHB_INIT
/* Enable 4bytes address support and fast read */
int qspi_ahb_init(void)
@@ -827,6 +868,9 @@ int board_late_init(void)
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
#endif
+#ifdef CONFIG_FSPI_AHB_EN_4BYTE
+ fspi_ahb_init();
+#endif
return 0;
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 7d95c4e2f5..a09d382112 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -133,6 +133,13 @@ void init_pfe_scfg_dcfg_regs(void);
int qspi_ahb_init(void);
#endif
+#ifdef CONFIG_FSPI_AHB_EN_4BYTE
+#define SYS_NXP_FSPI_LUTCR_LOCK0x0001
+#define SYS_NXP_FSPI_LUTCR_UNLOCK 0x0002
+#define SYS_NXP_FSPI_LUTKEY0x5AF05AF0
+int fspi_ahb_init(void);
+#endif
+
void cpu_name(char *name);
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
void erratum_a009635(void);
--
2.17.1
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[U-Boot] [PATCH v3 1/2] fsl-lsch3: Add FlexSPI address space in immap_lsch3
Signed-off-by: Priyanka Jain Signed-off-by: Sriram Dash Signed-off-by: Ashish Kumar Signed-off-by: Rajat Srivastava --- v3: No change. Rebased to top. arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88ab2f..d7a84e9ea0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -23,7 +23,13 @@ #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x0030) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x0031) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x0037) +#ifndef CONFIG_NXP_LSCH3_2 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c) +#else +#define SYS_NXP_FSPI_ADDR (CONFIG_SYS_IMMR + 0x010c) +#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18 +#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200 +#endif #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x0114) #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0124) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [EXT] Re: [PATCH v2] mtd: spi: Improve spi_nor_write_data() implementation
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Wednesday, April 17, 2019 6:18 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de;
> tr...@konsulko.com; marek.va...@gmail.com;
> marek.vasut+rene...@gmail.com; ja...@openedev.com
> Cc: Ashish Kumar
> Subject: [EXT] Re: [PATCH v2] mtd: spi: Improve spi_nor_write_data()
> implementation
>
> WARNING: This email was created outside of NXP. DO NOT CLICK links or
> attachments unless you recognize the sender and know the content is safe.
>
>
>
> On 16/04/19 5:29 PM, Rajat Srivastava wrote:
> > Maximum write size in a single write operation in
> > spi_nor_write_data() function can be equal to slave tx buffer, which
> > is adjusted in spi_mem_adjust_op_size() and write operation gets
> > fragmented.
> >
> > Previously data write for the above fragmentation didn't incorporate
> > write enable and status checks.
> > It was sent to flash at page offsets only.
> >
> > Signed-off-by: Rajat Srivastava
> > ---
> > Changes in v2:
> > Incorporating review comments given by Vignesh.
> > [PATCH v1]:
> >
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> >
> hwork.ozlabs.org%2Fpatch%2F1078183%2Fdata=02%7C01%7Crajat.sri
> vast
> >
> ava%40nxp.com%7C774c432160da4264b0a308d6c332e381%7C686ea1d3bc2b
> 4c6fa92
> >
> cd99c5c301635%7C0%7C0%7C636911020672017024sdata=Kl3XDugF05y
> g4UiLk
> > rrBptYDm2TFTZMFhIMOEF9Znjw%3Dreserved=0
>
> Changes look good as such, but I cannot seem to apply these patch locally as
> mbox for testing. Looking at mail source, it seems to be sent in binary format
> instead of plain text. Could you resend in plain text?
This looks like an issue with using outlook.office365.com as smtp server, since
the
the patch is getting corrupt even when I am sending it again.
I'm working with IT team here to resolve this.
Regards
Rajat
>
> >
> > drivers/mtd/spi/spi-nor-core.c | 28 ++--
> > 1 file changed, 10 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c
> > b/drivers/mtd/spi/spi-nor-core.c index c4e2f6a08f..8e754d445d 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -116,7 +116,6 @@ static ssize_t spi_nor_write_data(struct spi_nor
> *nor, loff_t to, size_t len,
> > SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
> > SPI_MEM_OP_NO_DUMMY,
> > SPI_MEM_OP_DATA_OUT(len, buf, 1));
> > - size_t remaining = len;
> > int ret;
> >
> > /* get transfer protocols. */
> > @@ -127,22 +126,19 @@ static ssize_t spi_nor_write_data(struct spi_nor
> *nor, loff_t to, size_t len,
> > if (nor->program_opcode == SPINOR_OP_AAI_WP && nor-
> >sst_write_second)
> > op.addr.nbytes = 0;
> >
> > - while (remaining) {
> > - op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
> > - ret = spi_mem_adjust_op_size(nor->spi, );
> > - if (ret)
> > - return ret;
> > + op.data.nbytes = len < UINT_MAX ? len : UINT_MAX;
> > + ret = spi_mem_adjust_op_size(nor->spi, );
> > + if (ret)
> > + return ret;
> >
> > - ret = spi_mem_exec_op(nor->spi, );
> > - if (ret)
> > - return ret;
> > + ret = spi_mem_exec_op(nor->spi, );
> > + if (ret)
> > + return ret;
> >
> > - op.addr.val += op.data.nbytes;
> > - remaining -= op.data.nbytes;
> > - op.data.buf.out += op.data.nbytes;
> > - }
> > + op.addr.val += op.data.nbytes;
> > + op.data.buf.out += op.data.nbytes;
> >
> > - return len;
> > + return op.data.nbytes;
> > }
> >
> > /*
> > @@ -1101,10 +1097,6 @@ static int spi_nor_write(struct mtd_info *mtd,
> loff_t to, size_t len,
> > goto write_err;
> > *retlen += written;
> > i += written;
> > - if (written != page_remain) {
> > - ret = -EIO;
> > - goto write_err;
> > - }
> > }
> >
> > write_err:
> >
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[U-Boot] [RESEND PATCH v2] mtd: spi: Improve spi_nor_write_data() implementation
Maximum write size in a single write operation in
spi_nor_write_data() function can be equal to slave
tx buffer, which is adjusted in spi_mem_adjust_op_size()
and write operation gets fragmented.
Previously data write for the above fragmentation
didn't incorporate write enable and status checks.
It was sent to flash at page offsets only.
Signed-off-by: Rajat Srivastava
---
Changes in v2:
Incorporating review comments given by Vignesh.
[PATCH v1]: https://patchwork.ozlabs.org/patch/1078183
drivers/mtd/spi/spi-nor-core.c | 28 ++--
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index c4e2f6a08f..8e754d445d 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -116,7 +116,6 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(len, buf, 1));
- size_t remaining = len;
int ret;
/* get transfer protocols. */
@@ -127,22 +126,19 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op.addr.nbytes = 0;
- while (remaining) {
- op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
- ret = spi_mem_adjust_op_size(nor->spi, );
- if (ret)
- return ret;
+ op.data.nbytes = len < UINT_MAX ? len : UINT_MAX;
+ ret = spi_mem_adjust_op_size(nor->spi, );
+ if (ret)
+ return ret;
- ret = spi_mem_exec_op(nor->spi, );
- if (ret)
- return ret;
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
- op.addr.val += op.data.nbytes;
- remaining -= op.data.nbytes;
- op.data.buf.out += op.data.nbytes;
- }
+ op.addr.val += op.data.nbytes;
+ op.data.buf.out += op.data.nbytes;
- return len;
+ return op.data.nbytes;
}
/*
@@ -1101,10 +1097,6 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t
to, size_t len,
goto write_err;
*retlen += written;
i += written;
- if (written != page_remain) {
- ret = -EIO;
- goto write_err;
- }
}
write_err:
--
2.17.1
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[U-Boot] [RESEND PATCH v2] mtd: spi: Improve spi_nor_write_data() implementation
Maximum write size in a single write operation in
spi_nor_write_data() function can be equal to slave
tx buffer, which is adjusted in spi_mem_adjust_op_size()
and write operation gets fragmented.
Previously data write for the above fragmentation
didn't incorporate write enable and status checks.
It was sent to flash at page offsets only.
Signed-off-by: Rajat Srivastava
---
Changes in v2:
Incorporating review comments given by Vignesh.
[PATCH v1]: https://patchwork.ozlabs.org/patch/1078183/
drivers/mtd/spi/spi-nor-core.c | 28 ++--
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index c4e2f6a08f..8e754d445d 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -116,7 +116,6 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(len, buf, 1));
- size_t remaining = len;
int ret;
/* get transfer protocols. */
@@ -127,22 +126,19 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op.addr.nbytes = 0;
- while (remaining) {
- op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
- ret = spi_mem_adjust_op_size(nor->spi, );
- if (ret)
- return ret;
+ op.data.nbytes = len < UINT_MAX ? len : UINT_MAX;
+ ret = spi_mem_adjust_op_size(nor->spi, );
+ if (ret)
+ return ret;
- ret = spi_mem_exec_op(nor->spi, );
- if (ret)
- return ret;
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
- op.addr.val += op.data.nbytes;
- remaining -= op.data.nbytes;
- op.data.buf.out += op.data.nbytes;
- }
+ op.addr.val += op.data.nbytes;
+ op.data.buf.out += op.data.nbytes;
- return len;
+ return op.data.nbytes;
}
/*
@@ -1101,10 +1097,6 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t
to, size_t len,
goto write_err;
*retlen += written;
i += written;
- if (written != page_remain) {
- ret = -EIO;
- goto write_err;
- }
}
write_err:
--
2.14.1
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Re: [U-Boot] [EXT] Re: [PATCH] mtd: spi: Improve data write functionality
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Friday, April 12, 2019 1:01 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de;
> tr...@konsulko.com; marek.va...@gmail.com;
> marek.vasut+rene...@gmail.com; ja...@openedev.com
> Cc: Ashish Kumar
> Subject: [EXT] Re: [PATCH] mtd: spi: Improve data write functionality
>
> WARNING: This email was created outside of NXP. DO NOT CLICK links or
> attachments unless you recognize the sender and know the content is safe.
>
>
>
> On 05/04/19 2:24 PM, Rajat Srivastava wrote:
> > Incorporate write enable and status check in the write data function
> > itself.
> >
> > Formerly, Write data function used to break the data to be written
> > into smaller chunks and used to send the smaller chunks without write
> > enable or status check for every iteration.
> >
> > Signed-off-by: Rajat Srivastava
> > ---
> > While writing any data to a SPI flash every write transaction shall be
> > preceded by a WRITE_ENABLE command and shall be followed by a
> > READ_STATUS process (to check if the flash is not busy).
> > This sequence can be roughly represented as:
> > 1. write_enable //issue write enable command 2.
> > execute_write_operation //write data to flash or register 3.
> > spi_nor_wait_till_ready //read status of flash
> >
> > The current framework has two types of write operation:
> > 1. write to register (nor->write_reg)
> > 2. write data to flash memory (nor->write)
> >
> > There seems to be an issue in writing data to flash memory for which
> > the framework uses spi_nor_write_data() function.
> > Before every call to spi_nor_write_data() function the framework sends
> > a WRITE_ENABLE command and later checks if the flash is busy.
> > However, the spi_nor_write_data() function which executes the data
> > write to flash, breaks the data into smaller chunks. For all of these
> > small transactions there is only a single WRITE_ENABLE command issued
> > and a single check made for status, which breaks the write operation.
> > Only the first chunk of the whole data is successfully written on to
> > the flash.
> >
> > This patch fixes the bug making the spi_nor_write_data() function
> > issue WRITE_ENABLE command and status checks with every write
> > transactions.
> >
> > Without this patch write in fsl_qspi.c driver is broken.
> >
>
> I see this is mainly because fsl-qspi uses slave->max_write_size to restrict
> max write size which leads to fragmentation of traffic as part of
> spi_mem_adjust_op_size().
> So, could you please remove while() loop in spi_nor_write_data(), return
> actual number of data bytes that is written and make
> spi_nor_write() loop around until all the data has been written?
>
Please find the v2 of this patch at https://patchwork.ozlabs.org/patch/1086262/
Regards
Rajat
> Regards
> Vignesh
>
>
> > drivers/mtd/spi/spi-nor-core.c | 30 +-
> > 1 file changed, 9 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c
> > b/drivers/mtd/spi/spi-nor-core.c index c4e2f6a08f..757163369b 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -23,6 +23,9 @@
> >
> > #include "sf_internal.h"
> >
> > +static int spi_nor_wait_till_ready(struct spi_nor *nor); static int
> > +write_enable(struct spi_nor *nor);
> > +
> > /* Define max times to check status register before we give up. */
> >
> > /*
> > @@ -128,6 +131,8 @@ static ssize_t spi_nor_write_data(struct spi_nor
> *nor, loff_t to, size_t len,
> > op.addr.nbytes = 0;
> >
> > while (remaining) {
> > + write_enable(nor);
> > +
> > op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
> > ret = spi_mem_adjust_op_size(nor->spi, );
> > if (ret)
> > @@ -137,6 +142,10 @@ static ssize_t spi_nor_write_data(struct spi_nor
> *nor, loff_t to, size_t len,
> > if (ret)
> > return ret;
> >
> > + ret = spi_nor_wait_till_ready(nor);
> > + if (ret)
> > + return ret;
> > +
> > op.addr.val += op.data.nbytes;
> > remaining -= op.data.nbytes;
> > op.data.buf.out += op.data.nbytes; @@ -961,14 +970,10 @@
> > static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
> > for (actual = 0; actual < len; actua
[U-Boot] [PATCH v2] mtd: spi: Improve spi_nor_write_data() implementation
Maximum write size in a single write operation in
spi_nor_write_data() function can be equal to slave
tx buffer, which is adjusted in spi_mem_adjust_op_size()
and write operation gets fragmented.
Previously data write for the above fragmentation
didn't incorporate write enable and status checks.
It was sent to flash at page offsets only.
Signed-off-by: Rajat Srivastava
---
Changes in v2:
Incorporating review comments given by Vignesh.
[PATCH v1]: https://patchwork.ozlabs.org/patch/1078183/
drivers/mtd/spi/spi-nor-core.c | 28 ++--
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index c4e2f6a08f..8e754d445d 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -116,7 +116,6 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(len, buf, 1));
- size_t remaining = len;
int ret;
/* get transfer protocols. */
@@ -127,22 +126,19 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op.addr.nbytes = 0;
- while (remaining) {
- op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
- ret = spi_mem_adjust_op_size(nor->spi, );
- if (ret)
- return ret;
+ op.data.nbytes = len < UINT_MAX ? len : UINT_MAX;
+ ret = spi_mem_adjust_op_size(nor->spi, );
+ if (ret)
+ return ret;
- ret = spi_mem_exec_op(nor->spi, );
- if (ret)
- return ret;
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
- op.addr.val += op.data.nbytes;
- remaining -= op.data.nbytes;
- op.data.buf.out += op.data.nbytes;
- }
+ op.addr.val += op.data.nbytes;
+ op.data.buf.out += op.data.nbytes;
- return len;
+ return op.data.nbytes;
}
/*
@@ -1101,10 +1097,6 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t
to, size_t len,
goto write_err;
*retlen += written;
i += written;
- if (written != page_remain) {
- ret = -EIO;
- goto write_err;
- }
}
write_err:
--
2.14.1
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[U-Boot] [PATCH] mtd: spi: Improve data write functionality
Incorporate write enable and status check in the write data
function itself.
Formerly, Write data function used to break the data to be
written into smaller chunks and used to send the smaller
chunks without write enable or status check for every iteration.
Signed-off-by: Rajat Srivastava
---
While writing any data to a SPI flash every write transaction
shall be preceded by a WRITE_ENABLE command and shall be
followed by a READ_STATUS process (to check if the flash is
not busy).
This sequence can be roughly represented as:
1. write_enable //issue write enable command
2. execute_write_operation //write data to flash or register
3. spi_nor_wait_till_ready //read status of flash
The current framework has two types of write operation:
1. write to register (nor->write_reg)
2. write data to flash memory (nor->write)
There seems to be an issue in writing data to flash memory for which
the framework uses spi_nor_write_data() function.
Before every call to spi_nor_write_data() function the framework
sends a WRITE_ENABLE command and later checks if the flash is busy.
However, the spi_nor_write_data() function which executes the data
write to flash, breaks the data into smaller chunks. For all of
these small transactions there is only a single WRITE_ENABLE
command issued and a single check made for status, which breaks
the write operation. Only the first chunk of the whole data is
successfully written on to the flash.
This patch fixes the bug making the spi_nor_write_data() function
issue WRITE_ENABLE command and status checks with every write
transactions.
Without this patch write in fsl_qspi.c driver is broken.
drivers/mtd/spi/spi-nor-core.c | 30 +-
1 file changed, 9 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index c4e2f6a08f..757163369b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -23,6 +23,9 @@
#include "sf_internal.h"
+static int spi_nor_wait_till_ready(struct spi_nor *nor);
+static int write_enable(struct spi_nor *nor);
+
/* Define max times to check status register before we give up. */
/*
@@ -128,6 +131,8 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
op.addr.nbytes = 0;
while (remaining) {
+ write_enable(nor);
+
op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
ret = spi_mem_adjust_op_size(nor->spi, );
if (ret)
@@ -137,6 +142,10 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
if (ret)
return ret;
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ return ret;
+
op.addr.val += op.data.nbytes;
remaining -= op.data.nbytes;
op.data.buf.out += op.data.nbytes;
@@ -961,14 +970,10 @@ static int sst_write_byteprogram(struct spi_nor *nor,
loff_t to, size_t len,
for (actual = 0; actual < len; actual++) {
nor->program_opcode = SPINOR_OP_BP;
- write_enable(nor);
/* write one byte. */
ret = nor->write(nor, to, 1, buf + actual);
if (ret < 0)
goto sst_write_err;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto sst_write_err;
to++;
}
@@ -989,8 +994,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
if (spi->mode & SPI_TX_BYTE)
return sst_write_byteprogram(nor, to, len, retlen, buf);
- write_enable(nor);
-
nor->sst_write_second = false;
actual = to % 2;
@@ -1002,9 +1005,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
ret = nor->write(nor, to, 1, buf);
if (ret < 0)
goto sst_write_err;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto sst_write_err;
}
to += actual;
@@ -1016,9 +1016,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
ret = nor->write(nor, to, 2, buf + actual);
if (ret < 0)
goto sst_write_err;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto sst_write_err;
to += 2;
nor->sst_write_second = true;
}
@@ -1031,15 +1028,10 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
/* Write out trailing byte if it exists. */
if (actual != len) {
- write_enable(nor);
-
nor->program_opcode = SPINOR_OP_BP;
ret = nor->write(nor, to, 1, buf + a
Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI framework
> -Original Message-
> From: Vignesh R
> Sent: Friday, November 16, 2018 8:56 PM
> To: Rajat Srivastava ; Simon Goldschmidt
> ; U-Boot Mailing List b...@lists.denx.de>
> Cc: Jagan Teki
> Subject: Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI
> framework
>
> On 16-Nov-18 6:29 PM, Rajat Srivastava wrote:
> >> On Fri, Nov 16, 2018 at 11:19 AM Vignesh R wrote:
> >>> On 16/11/18 3:10 PM, Rajat Srivastava wrote:
> >>>>> Hi Rajat,
> >>>>>
> >>>>> On 13/11/18 5:30 PM, Rajat Srivastava wrote:
> >>>>>> Add support for JESD216 rev B standard JEDEC Serial Flash
> >>>>>> Discoverable Parameters (SFDP) tables to dynamically initialize
> >>>>>> flash size, page size and address width of the flash. More
> >>>>>> parameters can be added as per requirement.
> >>>>>> SFDP parsing is made default but already existing method for
> >>>>>> parsing these parameters are not deprecated.
> >>>>>> A flag is created to skip SFDP parsing for a particular flash, if
> >>>>>> required.
> >>>>>>
> >>>>>> SFDP data lets us auto-detect the addressing mode supported by
> >>>>>> the flash which helps us access the flash using 4-byte address.
> >>>>>>
> >>>>>> Add a new argument in spi_flash_addr() function to create
> >>>>>> commands with 3-byte or 4-byte address depending on the SFDP
> data
> >>>>>> read. Add pointer to struct spi_flash in struct spi_slave so that
> >>>>>> driver can have access to SFDP data.
> >>>>>>
> >>>>>> Introduce new structures and functions to read and parse SFDP data.
> >>>>>> This is loosely based on Linux SFDP framework.
> >>>>>>
> >>>>>> Signed-off-by: Rajat Srivastava
> >>>>>> ---
> >>>>>> Changes in v2:
> >>>>>> - Make SFDP parsing the default method.
> >>>>>> - Change SPI_FLASH_USE_SFDP flag to SPI_FLASH_USE_SFDP to
> >> provide
> >>>>>> an option to skip SFDP parsing for a particular flash.
> >>>>>> ---
> >>>>>
> >>>>> [...]
> >>>>>> +static int spi_flash_parse_bfpt(struct spi_flash *flash,
> >>>>>> + const struct sfdp_parameter_header
> >>>>> *bfpt_header) {
> >>>>>> + struct sfdp_bfpt bfpt;
> >>>>>> + size_t len;
> >>>>>> + int i, err;
> >>>>>> + u32 addr;
> >>>>>> +
> >>>>>> + /* JESD216 Basic Flash Parameter Table length is at least 9
> DWORDs.
> >>>>> */
> >>>>>> + if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
> >>>>>> + return -EINVAL;
> >>>>>> +
> >>>>>> + /* Read the Basic Flash Parameter Table. */
> >>>>>> + len = min_t(size_t, sizeof(bfpt),
> >>>>>> + bfpt_header->length * sizeof(u32));
> >>>>>> + addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
> >>>>>> + memset(, 0, sizeof(bfpt));
> >>>>>> + err = spi_flash_read_sfdp(flash, addr, len, );
> >>>>>> + if (err < 0)
> >>>>>> + return err;
> >>>>>> +
> >>>>>> + /* Fix endianness of the BFPT DWORDs. */
> >>>>>> + for (i = 0; i < BFPT_DWORD_MAX; i++)
> >>>>>> + bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
> >>>>>> +
> >>>>>> + /* Number of address bytes. */
> >>>>>> + switch (bfpt.dwords[BFPT_DWORD(1)] &
> >>>>> BFPT_DWORD1_ADDRESS_BYTES_MASK) {
> >>>>>> + case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
> >>>>>> + flash->addr_width = 3;
> >>>>>> + break;
> >>>>>> +
> >>>>>> + case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
> >>>>>> + printf("SF: Flash defaults to 3-Byte mode; enters 4-Byte
> >>>>>> ");
> >>>>>> + printf("mode on command\n");
> >>>>>> + /*
Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI framework
> -Original Message-
> From: Simon Goldschmidt
> Sent: Friday, November 16, 2018 3:53 PM
> To: vigne...@ti.com
> Cc: Rajat Srivastava ; U-Boot Mailing List b...@lists.denx.de>; Jagan Teki
> Subject: Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI
> framework
>
> On Fri, Nov 16, 2018 at 11:19 AM Vignesh R wrote:
> >
> >
> >
> > On 16/11/18 3:10 PM, Rajat Srivastava wrote:
> > >> Hi Rajat,
> > >>
> > >> On 13/11/18 5:30 PM, Rajat Srivastava wrote:
> > >>> Add support for JESD216 rev B standard JEDEC Serial Flash
> > >>> Discoverable Parameters (SFDP) tables to dynamically initialize
> > >>> flash size, page size and address width of the flash. More
> > >>> parameters can be added as per requirement.
> > >>> SFDP parsing is made default but already existing method for
> > >>> parsing these parameters are not deprecated.
> > >>> A flag is created to skip SFDP parsing for a particular flash, if
> > >>> required.
> > >>>
> > >>> SFDP data lets us auto-detect the addressing mode supported by the
> > >>> flash which helps us access the flash using 4-byte address.
> > >>>
> > >>> Add a new argument in spi_flash_addr() function to create commands
> > >>> with 3-byte or 4-byte address depending on the SFDP data read. Add
> > >>> pointer to struct spi_flash in struct spi_slave so that driver can
> > >>> have access to SFDP data.
> > >>>
> > >>> Introduce new structures and functions to read and parse SFDP data.
> > >>> This is loosely based on Linux SFDP framework.
> > >>>
> > >>> Signed-off-by: Rajat Srivastava
> > >>> ---
> > >>> Changes in v2:
> > >>> - Make SFDP parsing the default method.
> > >>> - Change SPI_FLASH_USE_SFDP flag to SPI_FLASH_USE_SFDP to
> provide
> > >>> an option to skip SFDP parsing for a particular flash.
> > >>> ---
> > >>
> > >> [...]
> > >>> +static int spi_flash_parse_bfpt(struct spi_flash *flash,
> > >>> + const struct sfdp_parameter_header
> > >> *bfpt_header) {
> > >>> + struct sfdp_bfpt bfpt;
> > >>> + size_t len;
> > >>> + int i, err;
> > >>> + u32 addr;
> > >>> +
> > >>> + /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs.
> > >> */
> > >>> + if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
> > >>> + return -EINVAL;
> > >>> +
> > >>> + /* Read the Basic Flash Parameter Table. */
> > >>> + len = min_t(size_t, sizeof(bfpt),
> > >>> + bfpt_header->length * sizeof(u32));
> > >>> + addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
> > >>> + memset(, 0, sizeof(bfpt));
> > >>> + err = spi_flash_read_sfdp(flash, addr, len, );
> > >>> + if (err < 0)
> > >>> + return err;
> > >>> +
> > >>> + /* Fix endianness of the BFPT DWORDs. */
> > >>> + for (i = 0; i < BFPT_DWORD_MAX; i++)
> > >>> + bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
> > >>> +
> > >>> + /* Number of address bytes. */
> > >>> + switch (bfpt.dwords[BFPT_DWORD(1)] &
> > >> BFPT_DWORD1_ADDRESS_BYTES_MASK) {
> > >>> + case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
> > >>> + flash->addr_width = 3;
> > >>> + break;
> > >>> +
> > >>> + case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
> > >>> + printf("SF: Flash defaults to 3-Byte mode; enters 4-Byte ");
> > >>> + printf("mode on command\n");
> > >>> + /*
> > >>> +* By default, 4-byte addressing mode is set.
> > >>> +* To enforce 3-byte addressing mode, set
> > >>> + addrwd_3_in_use
> > >> flag
> > >>> +* in struct spi_flash for every command.
> > >>> +*/
> > >>> + flash->addr_width = 4;
> > >>> + break;
> > >>> +
> > >>> + case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
> > >>> +
Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI framework
> -Original Message-
> From: Vignesh R
> Sent: Thursday, November 15, 2018 2:52 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de
> Cc: ja...@openedev.com
> Subject: Re: [U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI
> framework
>
> Hi Rajat,
>
> On 13/11/18 5:30 PM, Rajat Srivastava wrote:
> > Add support for JESD216 rev B standard JEDEC Serial Flash Discoverable
> > Parameters (SFDP) tables to dynamically initialize flash size, page
> > size and address width of the flash. More parameters can be added as
> > per requirement.
> > SFDP parsing is made default but already existing method for parsing
> > these parameters are not deprecated.
> > A flag is created to skip SFDP parsing for a particular flash, if
> > required.
> >
> > SFDP data lets us auto-detect the addressing mode supported by the
> > flash which helps us access the flash using 4-byte address.
> >
> > Add a new argument in spi_flash_addr() function to create commands
> > with 3-byte or 4-byte address depending on the SFDP data read. Add
> > pointer to struct spi_flash in struct spi_slave so that driver can
> > have access to SFDP data.
> >
> > Introduce new structures and functions to read and parse SFDP data.
> > This is loosely based on Linux SFDP framework.
> >
> > Signed-off-by: Rajat Srivastava
> > ---
> > Changes in v2:
> > - Make SFDP parsing the default method.
> > - Change SPI_FLASH_USE_SFDP flag to SPI_FLASH_USE_SFDP to provide an
> > option to skip SFDP parsing for a particular flash.
> > ---
>
> [...]
> > +static int spi_flash_parse_bfpt(struct spi_flash *flash,
> > + const struct sfdp_parameter_header
> *bfpt_header) {
> > + struct sfdp_bfpt bfpt;
> > + size_t len;
> > + int i, err;
> > + u32 addr;
> > +
> > + /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs.
> */
> > + if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
> > + return -EINVAL;
> > +
> > + /* Read the Basic Flash Parameter Table. */
> > + len = min_t(size_t, sizeof(bfpt),
> > + bfpt_header->length * sizeof(u32));
> > + addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
> > + memset(, 0, sizeof(bfpt));
> > + err = spi_flash_read_sfdp(flash, addr, len, );
> > + if (err < 0)
> > + return err;
> > +
> > + /* Fix endianness of the BFPT DWORDs. */
> > + for (i = 0; i < BFPT_DWORD_MAX; i++)
> > + bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
> > +
> > + /* Number of address bytes. */
> > + switch (bfpt.dwords[BFPT_DWORD(1)] &
> BFPT_DWORD1_ADDRESS_BYTES_MASK) {
> > + case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
> > + flash->addr_width = 3;
> > + break;
> > +
> > + case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
> > + printf("SF: Flash defaults to 3-Byte mode; enters 4-Byte ");
> > + printf("mode on command\n");
> > + /*
> > +* By default, 4-byte addressing mode is set.
> > +* To enforce 3-byte addressing mode, set addrwd_3_in_use
> flag
> > +* in struct spi_flash for every command.
> > +*/
> > + flash->addr_width = 4;
> > + break;
> > +
> > + case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
> > + flash->addr_width = 4;
> > + break;
> > +
>
> I see your are updating flash->addr_width to 4 bytes here. But I don't see
> any code in this patch that changes flash->read_cmd (and write/erase
> cmds) to use 4B addressing opcodes. Also, I dont see any code that bypasses
> BAR register configuration when CONFIG_SPI_FLASH_BAR is defined and
> SFDP is available.
We don't have any flash that supports CONFIG_SPI_FLASH_BAR. What do you
suggest, shall we skip SFDP parsing in case CONFIG_SPI_FLASH_BAR is defined?
> This patch will most certainly break SPI controller drivers(like
> cadence_qspi.c) that expect sf layer to provide correct read opcode and
> address width information, since there will be mismatch wrt opcode used
> and number of address byte sent.
> Not sure how this patch was tested, but I guess fsl_qspi modifies read
> opcode internal to the driver and gets away with it.
> Please modify the patch to update read_cmd/erase_cmd/write_cmd to use
> 4 byte addressing opcodes
If the flash supports only supports 4-byte opcodes then there will be no
mismatch
wrt opcode used and number of address bytes sent since all of the opcodes that
the flash suppo
[U-Boot] [PATCH v2 1/2] mtd/spi: Add JEDEC SFDP support in SPI framework
Add support for JESD216 rev B standard JEDEC Serial
Flash Discoverable Parameters (SFDP) tables to
dynamically initialize flash size, page size and
address width of the flash. More parameters can be
added as per requirement.
SFDP parsing is made default but already existing
method for parsing these parameters are not deprecated.
A flag is created to skip SFDP parsing for a particular
flash, if required.
SFDP data lets us auto-detect the addressing mode
supported by the flash which helps us access the
flash using 4-byte address.
Add a new argument in spi_flash_addr() function to create
commands with 3-byte or 4-byte address depending on the
SFDP data read. Add pointer to struct spi_flash in struct
spi_slave so that driver can have access to SFDP data.
Introduce new structures and functions to read and parse
SFDP data. This is loosely based on Linux SFDP framework.
Signed-off-by: Rajat Srivastava
---
Changes in v2:
- Make SFDP parsing the default method.
- Change SPI_FLASH_USE_SFDP flag to SPI_FLASH_USE_SFDP to
provide an option to skip SFDP parsing for a particular flash.
---
drivers/mtd/spi/sf_internal.h | 4 +
drivers/mtd/spi/spi_flash.c | 301 +++---
include/spi.h | 2 +
include/spi_flash.h | 120 +
4 files changed, 406 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 26f5c7c995..87f05a88ba 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -26,7 +26,9 @@ enum spi_nor_option_flags {
};
#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_4B_ADDR_LEN 4
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
+#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
/* CFI Manufacture ID's */
@@ -62,6 +64,7 @@ enum spi_nor_option_flags {
#define CMD_READ_STATUS1 0x35
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_READ_SFDP 0x5a
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
@@ -144,6 +147,7 @@ struct spi_flash_info {
#define RD_DUALBIT(5) /* use Dual Read */
#define RD_QUADIO BIT(6) /* use Quad IO Read */
#define RD_DUALIO BIT(7) /* use Dual IO Read */
+#define SPI_FLASH_SKIP_SFDPBIT(8) /* parse SFDP to get flash info */
#define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO |
RD_DUALIO)
};
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index a87bacd4ac..f8bd8fac54 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -20,12 +20,24 @@
#include "sf_internal.h"
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd)
{
/* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
+ int i;
+
+ /* Remember to unset addrwd_3_in_use */
+ if (flash->addrwd_3_in_use) {
+ flash->addr_width = SPI_FLASH_3B_ADDR_LEN;
+ debug("SF: addrwd_3_in_use flag needs to be reset to false ");
+ debug("after the intended command is triggered to flash.\n");
+ }
+
+ flash->cmd_len = 1 + flash->addr_width;
+
+ for (i = flash->cmd_len - 1; i > 0; i--) {
+ cmd[i] = addr;
+ addr = addr >> 8;
+ }
}
static int read_sr(struct spi_flash *flash, u8 *rs)
@@ -314,7 +326,7 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size, erase_addr;
- u8 cmd[SPI_FLASH_CMD_LEN];
+ u8 cmd[SPI_FLASH_CMD_MAX_LEN];
int ret = -1;
erase_size = flash->erase_size;
@@ -344,12 +356,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len)
if (ret < 0)
return ret;
#endif
- spi_flash_addr(erase_addr, cmd);
+ spi_flash_addr(flash, erase_addr, cmd);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], erase_addr);
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ ret = spi_flash_write_common(flash, cmd, flash->cmd_len,
+NULL, 0);
if (ret < 0) {
debug("SF: erase failed\n");
break;
@@ -373,7 +386,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chun
[U-Boot] [PATCH v2 2/2] fsl_qspi: Access flash above 16MB using SFDP
Add functionality to read SFDP parameters in fsl_qspi driver.
Also, use the address width information from SFDP to enable
flash access above 16 MB.
Introduce a way to access parent structure by adding pointer
to struct spi_slave in struct fsl_qspi_priv.
Signed-off-by: Rajat Srivastava
---
Changes in v2:
- none
---
drivers/spi/fsl_qspi.c | 103 +
1 file changed, 96 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1598c4f698..615f36e351 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK GENMASK(23, 0)
+#define SET_BITS_MASK(X) GENMASK(X, 0)
#define FLASH_STATUS_WEL 0x02
@@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#define SEQID_WRAR 13
#define SEQID_RDAR 14
+#define SEQID_RDSFDP 15
/* QSPI CMD */
#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
@@ -57,6 +58,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
#define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
#define QSPI_CMD_RDID 0x9f/* Read JEDEC ID */
+#define QSPI_CMD_RDSFDP0x5a/* Read SFDP parameters from
flash */
/* Used for Micron, winbond and Macronix flashes */
#defineQSPI_CMD_WREAR 0xc5/* EAR register write */
@@ -132,6 +134,7 @@ struct fsl_qspi_priv {
u32 flash_num;
u32 num_chipselect;
struct fsl_qspi_regs *regs;
+ void *spi_slave;
};
@@ -363,6 +366,19 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
qspi_write32(priv->flags, >lut[lut_base + 1],
OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+ /* Read SFDP information */
+ lut_base = SEQID_RDSFDP * 4;
+ qspi_write32(priv->flags, >lut[lut_base],
+OPRND0(QSPI_CMD_RDSFDP) | PAD0(LUT_PAD1) |
+INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+ qspi_write32(priv->flags, >lut[lut_base + 1],
+OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
+OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
+INSTR1(LUT_READ));
+ qspi_write32(priv->flags, >lut[lut_base + 2], 0);
+ qspi_write32(priv->flags, >lut[lut_base + 3], 0);
+
/* Lock the LUT */
qspi_write32(priv->flags, >lutkey, LUT_KEY_VALUE);
qspi_write32(priv->flags, >lckcr, QSPI_LCKCR_LOCK);
@@ -562,6 +578,61 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32
*rxbuf, u32 len)
qspi_write32(priv->flags, >mcr, mcr_reg);
}
+static void qspi_op_rdsfdp(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
+{
+ struct fsl_qspi_regs *regs = priv->regs;
+ u32 mcr_reg, data;
+ int i, size;
+ u32 to_or_from;
+ u32 seqid;
+
+ seqid = SEQID_RDSFDP;
+
+ mcr_reg = qspi_read32(priv->flags, >mcr);
+ qspi_write32(priv->flags, >mcr,
+QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ qspi_write32(priv->flags, >rbct, QSPI_RBCT_RXBRD_USEIPS);
+
+ to_or_from = priv->sf_addr + priv->cur_amba_base;
+
+ while (len > 0) {
+ WATCHDOG_RESET();
+
+ qspi_write32(priv->flags, >sfar, to_or_from);
+
+ size = (len > RX_BUFFER_SIZE) ?
+ RX_BUFFER_SIZE : len;
+
+ qspi_write32(priv->flags, >ipcr,
+(seqid << QSPI_IPCR_SEQID_SHIFT) |
+size);
+ while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
+ ;
+
+ to_or_from += size;
+ len -= size;
+
+ i = 0;
+ while ((size < RX_BUFFER_SIZE) && (size > 0)) {
+ data = qspi_read32(priv->flags, >rbdr[i]);
+ data = qspi_endian_xchg(data);
+ if (size < 4)
+ memcpy(rxbuf, , size);
+ else
+ memcpy(rxbuf, , 4);
+ rxbuf++;
+ size -= 4;
+ i++;
+ }
+ qspi_write32(priv->flags, >mcr,
+qspi_read32(priv->flags, >mcr) |
+QSPI_MCR_CLR_RXF_MASK);
+ }
+
+ qspi_write32(priv->flags, >mcr, mcr_reg);
+}
+
/* If not use AHB read, read data from ip interface */
static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *
[U-Boot] [PATCH v2 0/2] Read SFDP parameters and access flash above 16MB
Add functionality to read and parse SFDP parameters to auto-detect flash size, page size and address width of flash. This enables flash access above 16MB using 4-byte addressing mode. Add driver support to get SFDP information of flash and use it to access flash above 16MB. --- Changes in v2: - Make SFDP parsing the default way to read flash parameters. - Change SPI_FLASH_USE_SFDP flag to SPI_FLASH_SKIP_SFDP to provide an option to skip SFDP parsing for a particular flash. - Convert patch-set of 3 patches to 2 patches. --- Rajat Srivastava (2): mtd/spi: Add JEDEC SFDP support in SPI framework fsl_qspi: Access flash above 16MB using SFDP drivers/mtd/spi/sf_internal.h | 4 + drivers/mtd/spi/spi_flash.c | 301 +++--- drivers/spi/fsl_qspi.c| 103 ++- include/spi.h | 2 + include/spi_flash.h | 120 + 5 files changed, 502 insertions(+), 28 deletions(-) -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] Read SFDP parameters and access flash above 16MB
> -Original Message- > From: Simon Goldschmidt > Sent: Wednesday, October 31, 2018 1:09 PM > To: Rajat Srivastava ; U-Boot Mailing List b...@lists.denx.de> > Cc: Jagan Teki > Subject: Re: [U-Boot] [PATCH 0/3] Read SFDP parameters and access flash > above 16MB > > On Tue, Oct 30, 2018 at 9:35 PM Simon Goldschmidt > wrote: > > > > On 17.10.2018 13:27, Rajat Srivastava wrote: > > > Add functionality to read and parse SFDP parameters to auto-detect > > > flash size, page size and address width of flash. This enables > > > flash access above 16MB using 4-byte addressing mode. > > > > > > Add driver support to get SFDP information of flash and use it to > > > access flash above 16MB. > > > > > > Enable reading and parsing of SFDP parameters for Spansion's > > > s25fs512 flash to auto-detect its size, its page size and the > > > addressing mode it supports. > > > > Why do you need driver-specific code to read the sfdp parameters? > > Wouldn't it be much cleaner to solve this from spi_flash.c only? > > > > If so, just adding the 'spi_flash_parse_sfdp()' function on top of > > Stefan's patch should work? > > > > I tried testing this patch, but just like for Stefan, but it just didn't > > work for me and I failed to see some simple steps to adjust my spi > > driver to make it work. > > And taking this further, would it make sense to add a config option > that dumps the whole flash chip table and only uses SFDP? Then we > could save a lot of space in SPL for boards where reading SFDP is > enough. Does the whole flash chip table mean the table that consists CFI information as well as SFDP information? If that's so, could you please elaborate where would we dump and save this table? And how will this help in saving space in SPL? Rajat > > Simon > > > > > Simon > > > > > > > > Rajat Srivastava (3): > > >mtd/spi: Add JEDEC SFDP support in SPI framework > > >fsl_qspi: Access flash above 16MB using SFDP > > >spi_flash_ids: Enable SFDP parsing for s25fs512 flash > > > > > > drivers/mtd/spi/sf_internal.h | 4 + > > > drivers/mtd/spi/spi_flash.c | 297 > +--- > > > drivers/mtd/spi/spi_flash_ids.c | 3 +- > > > drivers/spi/fsl_qspi.c | 103 +- > > > include/spi.h | 2 + > > > include/spi_flash.h | 120 > > > 6 files changed, 501 insertions(+), 28 deletions(-) > > > > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] mtd/spi: Add JEDEC SFDP support in SPI framework
> -Original Message-
> From: Simon Goldschmidt
> Sent: Wednesday, October 31, 2018 2:51 PM
> To: Rajat Srivastava
> Cc: vigne...@ti.com; U-Boot Mailing List ; Jagan Teki
>
> Subject: Re: [U-Boot] [PATCH 1/3] mtd/spi: Add JEDEC SFDP support in SPI
> framework
>
> On Wed, Oct 31, 2018 at 10:01 AM Rajat Srivastava
> wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Vignesh R
> > > Sent: Wednesday, October 31, 2018 1:47 PM
> > > To: Rajat Srivastava ; u-boot@lists.denx.de
> > > Cc: ja...@openedev.com
> > > Subject: Re: [U-Boot] [PATCH 1/3] mtd/spi: Add JEDEC SFDP support in
> SPI
> > > framework
> > >
> > >
> > >
> > > On 17/10/18 4:58 PM, Rajat Srivastava wrote:
> > > > Add support for JESD216 rev B standard JEDEC Serial Flash Discoverable
> > > > Parameters (SFDP) tables to dynamically initialize flash size, page
> > > > size and address width of the flash. More parameters can be added as
> > > > per requirement.
> > > > Already existing method for parsing these parameters are not
> > > > deprecated, which can be done once most flash start using SFDP data.
> > > >
> > > > SFDP data lets us auto-detect the addressing mode supported by the
> > > > flash which helps us access the flash using 4-byte address.
> > > >
> > > > Add a new argument in spi_flash_addr() function to create commands
> > > > with 3-byte or 4-byte address depending on the SFDP data read. Add
> > > > pointer to struct spi_flash in struct spi_slave so that driver can
> > > > have access to SFDP data.
> > > >
> > > > Introduce new structures and functions to read and parse SFDP data.
> > > > This is loosely based on Linux SFDP framework.
> > > >
> > > > Signed-off-by: Rajat Srivastava
> > > > ---
> > > > drivers/mtd/spi/sf_internal.h | 4 +
> > > > drivers/mtd/spi/spi_flash.c | 297
> > > +++---
> > > > include/spi.h | 2 +
> > > > include/spi_flash.h | 120 +
> > > > 4 files changed, 403 insertions(+), 20 deletions(-)
> > > >
> > > > diff --git a/drivers/mtd/spi/sf_internal.h
> > > > b/drivers/mtd/spi/sf_internal.h index 26f5c7c995..1bb4431d84 100644
> > > > --- a/drivers/mtd/spi/sf_internal.h
> > > > +++ b/drivers/mtd/spi/sf_internal.h
> > > > @@ -26,7 +26,9 @@ enum spi_nor_option_flags { };
> > > >
> > > > #define SPI_FLASH_3B_ADDR_LEN 3
> > > > +#define SPI_FLASH_4B_ADDR_LEN 4
> > > > #define SPI_FLASH_CMD_LEN (1 +
> > > SPI_FLASH_3B_ADDR_LEN)
> > > > +#define SPI_FLASH_CMD_MAX_LEN (1 +
> > > SPI_FLASH_4B_ADDR_LEN)
> > > > #define SPI_FLASH_16MB_BOUN0x100
> > > >
> > > > /* CFI Manufacture ID's */
> > > > @@ -62,6 +64,7 @@ enum spi_nor_option_flags {
> > > > #define CMD_READ_STATUS1 0x35
> > > > #define CMD_READ_CONFIG0x35
> > > > #define CMD_FLAG_STATUS0x70
> > > > +#define CMD_READ_SFDP 0x5a
> > > >
> > > > /* Bank addr access commands */
> > > > #ifdef CONFIG_SPI_FLASH_BAR
> > > > @@ -144,6 +147,7 @@ struct spi_flash_info {
> > > > #define RD_DUALBIT(5) /* use Dual Read */
> > > > #define RD_QUADIO BIT(6) /* use Quad IO Read */
> > > > #define RD_DUALIO BIT(7) /* use Dual IO Read */
> > > > +#define SPI_FLASH_USE_SFDP BIT(8) /* parse SFDP to get flash info
> > > */
> > >
> > > I suggest to SFDP not be a opt-in but default option like Linux kernel,
> since
> > > that's SFDP is a standard. If flash does not support SFDP that can be
> detected
> > > by looking for SFPD signature and code can fallback gracefully. If a flash
> has a
> > > broken SFDP table then such parts can use "SPI_FLASH_BROKEN_SFDP"
> flag
> > > or something. That way we don't need to add above flag to almost all
> flash
> > > entries here.
> >
> > You are correct. But, currently no drivers have implementation to send
> READ SFDP
> > command from their respective drivers. Once most have migrated to SFDP
> standard
> > then we can change this flag (makin
Re: [U-Boot] [PATCH 1/3] mtd/spi: Add JEDEC SFDP support in SPI framework
> -Original Message-
> From: Vignesh R
> Sent: Wednesday, October 31, 2018 1:47 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de
> Cc: ja...@openedev.com
> Subject: Re: [U-Boot] [PATCH 1/3] mtd/spi: Add JEDEC SFDP support in SPI
> framework
>
>
>
> On 17/10/18 4:58 PM, Rajat Srivastava wrote:
> > Add support for JESD216 rev B standard JEDEC Serial Flash Discoverable
> > Parameters (SFDP) tables to dynamically initialize flash size, page
> > size and address width of the flash. More parameters can be added as
> > per requirement.
> > Already existing method for parsing these parameters are not
> > deprecated, which can be done once most flash start using SFDP data.
> >
> > SFDP data lets us auto-detect the addressing mode supported by the
> > flash which helps us access the flash using 4-byte address.
> >
> > Add a new argument in spi_flash_addr() function to create commands
> > with 3-byte or 4-byte address depending on the SFDP data read. Add
> > pointer to struct spi_flash in struct spi_slave so that driver can
> > have access to SFDP data.
> >
> > Introduce new structures and functions to read and parse SFDP data.
> > This is loosely based on Linux SFDP framework.
> >
> > Signed-off-by: Rajat Srivastava
> > ---
> > drivers/mtd/spi/sf_internal.h | 4 +
> > drivers/mtd/spi/spi_flash.c | 297
> +++---
> > include/spi.h | 2 +
> > include/spi_flash.h | 120 +
> > 4 files changed, 403 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/sf_internal.h
> > b/drivers/mtd/spi/sf_internal.h index 26f5c7c995..1bb4431d84 100644
> > --- a/drivers/mtd/spi/sf_internal.h
> > +++ b/drivers/mtd/spi/sf_internal.h
> > @@ -26,7 +26,9 @@ enum spi_nor_option_flags { };
> >
> > #define SPI_FLASH_3B_ADDR_LEN 3
> > +#define SPI_FLASH_4B_ADDR_LEN 4
> > #define SPI_FLASH_CMD_LEN (1 +
> SPI_FLASH_3B_ADDR_LEN)
> > +#define SPI_FLASH_CMD_MAX_LEN (1 +
> SPI_FLASH_4B_ADDR_LEN)
> > #define SPI_FLASH_16MB_BOUN0x100
> >
> > /* CFI Manufacture ID's */
> > @@ -62,6 +64,7 @@ enum spi_nor_option_flags {
> > #define CMD_READ_STATUS1 0x35
> > #define CMD_READ_CONFIG0x35
> > #define CMD_FLAG_STATUS0x70
> > +#define CMD_READ_SFDP 0x5a
> >
> > /* Bank addr access commands */
> > #ifdef CONFIG_SPI_FLASH_BAR
> > @@ -144,6 +147,7 @@ struct spi_flash_info {
> > #define RD_DUALBIT(5) /* use Dual Read */
> > #define RD_QUADIO BIT(6) /* use Quad IO Read */
> > #define RD_DUALIO BIT(7) /* use Dual IO Read */
> > +#define SPI_FLASH_USE_SFDP BIT(8) /* parse SFDP to get flash info
> */
>
> I suggest to SFDP not be a opt-in but default option like Linux kernel, since
> that's SFDP is a standard. If flash does not support SFDP that can be detected
> by looking for SFPD signature and code can fallback gracefully. If a flash
> has a
> broken SFDP table then such parts can use "SPI_FLASH_BROKEN_SFDP" flag
> or something. That way we don't need to add above flag to almost all flash
> entries here.
You are correct. But, currently no drivers have implementation to send READ SFDP
command from their respective drivers. Once most have migrated to SFDP standard
then we can change this flag (making it the default mode).
Is it possible that a flash that supports SFDP parameter reading can send some
incorrect
signature? In that case I'll have to add an alternate path for fail scenario.
>
> Regards
> Vignesh
>
> > #define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO
> | RD_DUALIO)
> > };
> >
> > diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> > index a87bacd4ac..5d2728cc00 100644
> > --- a/drivers/mtd/spi/spi_flash.c
> > +++ b/drivers/mtd/spi/spi_flash.c
> > @@ -20,12 +20,24 @@
> >
> > #include "sf_internal.h"
> >
> > -static void spi_flash_addr(u32 addr, u8 *cmd)
> > +static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8
> > +*cmd)
> > {
> > /* cmd[0] is actual command */
> > - cmd[1] = addr >> 16;
> > - cmd[2] = addr >> 8;
> > - cmd[3] = addr >> 0;
> > + int i;
> > +
> > + /* Remember to unset addrwd_3_in_use */
> > + if (flash->addrwd_3_in_use) {
> > + flash->addr_width = SPI_FLASH_3B_ADDR_LEN;
> > +
Re: [U-Boot] [PATCH 0/3] Read SFDP parameters and access flash above 16MB
> -Original Message- > From: Simon Goldschmidt > Sent: Wednesday, October 31, 2018 2:06 AM > To: Rajat Srivastava ; u-boot@lists.denx.de > Cc: ja...@openedev.com > Subject: Re: [U-Boot] [PATCH 0/3] Read SFDP parameters and access flash > above 16MB > > On 17.10.2018 13:27, Rajat Srivastava wrote: > > Add functionality to read and parse SFDP parameters to auto-detect > > flash size, page size and address width of flash. This enables > > flash access above 16MB using 4-byte addressing mode. > > > > Add driver support to get SFDP information of flash and use it to > > access flash above 16MB. > > > > Enable reading and parsing of SFDP parameters for Spansion's > > s25fs512 flash to auto-detect its size, its page size and the > > addressing mode it supports. > > Why do you need driver-specific code to read the sfdp parameters? > Wouldn't it be much cleaner to solve this from spi_flash.c only? That would have been cleaner only if it was possible. To read SFDP parameters of any flash, a READ_SFDP (0x5A) command needs to be sent to flash. The mtd framework does not allow sending any command to any flash directly from mtd layer. Any transaction initiated from mtd framework will call spi_xfer() function of the respective SPI driver which will further send the actual command to flash. Linux has also implemented reading SFDP parameters functionality in a similar way. > If so, just adding the 'spi_flash_parse_sfdp()' function on top of > Stefan's patch should work? > > I tried testing this patch, but just like for Stefan, but it just didn't > work for me and I failed to see some simple steps to adjust my spi > driver to make it work. You can see these patches for SFDP implementation in SPI driver: https://patchwork.ozlabs.org/patch/985329/ https://patchwork.ozlabs.org/patch/985328/ You, basically, need to send: - 0x5A command (READ_SFDP command) - 3-byte address (address will be provided by framework) - 8 dummy cycles > > Simon > > > > > Rajat Srivastava (3): > >mtd/spi: Add JEDEC SFDP support in SPI framework > >fsl_qspi: Access flash above 16MB using SFDP > >spi_flash_ids: Enable SFDP parsing for s25fs512 flash > > > > drivers/mtd/spi/sf_internal.h | 4 + > > drivers/mtd/spi/spi_flash.c | 297 > +--- > > drivers/mtd/spi/spi_flash_ids.c | 3 +- > > drivers/spi/fsl_qspi.c | 103 +- > > include/spi.h | 2 + > > include/spi_flash.h | 120 > > 6 files changed, 501 insertions(+), 28 deletions(-) > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
Hi Stefan > -Original Message- > From: Stefan Roese > Sent: Friday, October 26, 2018 3:42 PM > To: Rajat Srivastava ; York Sun > ; Jagan Teki > Cc: u-boot@lists.denx.de; simon.k.r.goldschm...@gmail.com; Ashish Kumar > > Subject: Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs > standard 3-byte mode) > > Hi Rajat, > > On 26.10.18 11:59, Rajat Srivastava wrote: > > > > >> From what I read, Rajat's method is to extend the controller driver > >> to support read SFDP and default to 4-byte mode if supported, or > >> overwritten by user's flag. Stefan's method is to read 4-byte status > >> bit and doesn't change controller driver. > >> > >> Is the default value of this 4-byte status bit valid and correct for > >> all cases? > >> > >> Rajat, without your patch set, does Stefan's solution work for your board? > >> > >> York > > > > No. Stefan's changes are specific to his boards and is not applicable > > on ours. > > Stefan's patch is to support only certain flash that are factory > > strapped to work in 4-byte addressing modes only and will default to > > old method if such a flash is not found. > > That is not 100% correct. The flash does not need to be "factory strapped" to > this 4-byte mode. It needs to be configured to this 4-byte mode. And this is > also the case for example, when the ROM bootloader configures the flash > this way or a soft-reboot (without hard flash chip reset) reboots into U-Boot > after the flash was configured to 4-byte mode in Linux. > > And it supports multiple vendors and can easily be extended to support > more. The only thing needed is the detection of the 3-byte vs 4-byte address > mode. But please note that it currently does not actively switch from 3-byte > to 4-byte mode. This could be added though if needed / wanted. Spansion flashes (on our boards) support both 3-byte and 4-byte addressing modes which needs active switching. What could be added to your patch is already supported in SFDP method. SFDP also provides information about page size, flash density, read/write/erase commands, etc, in addition to getting information about address width supported by flash. > > > The flashes on our > > boards (and also other vendor's board) will not work with Stefan's > > patch. > > > > My patch can handle flashes with address widths of 3-byte, 4-byte or > > both. It also takes a more generic path (as opposed to supporting only > > specific flash models) by parsing SFDP standard parameters and then > > deciding what address width is to be used. > > I still don't see why each and every SPI controller driver needs to be > extended to support this SFDP parameter reading. Can't this be handled by > some generic (read common) code part in the SPI flash infrastructure? The generic (read common) code part in the SPI flash infrastructure also lands on respective SPI drivers which ultimately sends the commands to flash. Currently every SPI driver has support for basic read command (which is called after "generic read common code") but no driver has support for SFDP reading, which is what needs to be added. Also, only the drivers that want to make use of SFDP needs to extend support for SFDP parameter reading. I am reiterating that this is how SFDP parsing has been implemented in Linux as well and this is the generic way. Driver support is absolutely required because SPI framework cannot directly send any command to any flash. Thanks Rajat > > Thanks, > Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
Hi Jagan
> -Original Message-
> From: Rajat Srivastava
> Sent: Thursday, October 25, 2018 2:59 PM
> To: 'Stefan Roese' ; ja...@openedev.com;
> simon.k.r.goldschm...@gmail.com
> Cc: Ashish Kumar ; u-boot@lists.denx.de; York Sun
>
> Subject: RE: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs
> standard 3-byte mode)
>
> Hi Stefan
>
> > -Original Message-
> > From: Stefan Roese
> > Sent: Tuesday, October 23, 2018 10:31 PM
> > To: Rajat Srivastava ; ja...@openedev.com;
> > simon.k.r.goldschm...@gmail.com
> > Cc: Ashish Kumar ; u-boot@lists.denx.de
> > Subject: Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode
> > (vs standard 3-byte mode)
> >
> > Hi Rajat,
> >
> > On 23.10.18 07:17, Rajat Srivastava wrote:
> > >> -Original Message-
> > >> From: Stefan Roese [mailto:s...@denx.de]
> > >> Sent: Monday, October 22, 2018 12:45 PM
> > >> To: Rajat Srivastava <mailto:rajat.srivast...@nxp.com>;
> > >> mailto:ja...@openedev.com; mailto:simon.k.r.goldschm...@gmail.com
> > >> Cc: Ashish Kumar <mailto:ashish.ku...@nxp.com>;
> > >> mailto:u-boot@lists.denx.de
> > >> Subject: Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte
> > >> mode (vs standard 3-byte mode)
> > >>
> > >> Hi Rajat,
> > >>
> > >> On 17.10.18 13:52, Rajat Srivastava wrote:
> > >>> Hi Stefan
> > >>>
> > >>> Sorry for top-posting.
> > >>>
> > >>> Why can't we read SFDP parameters from flash and auto-detect
> > >>> 3-byte/4-byte addressing mode?
> > >>> Using address width information we can support both types of flash
> > >>> i.e. flashes supporting 3-byte addressing mode as well as flashes
> > >>> supporting 4-byte addressing mode.
> > >>
> > >> Our flash supports 3- and 4-byte addressing mode. But this special
> > >> chip is factory strapped to only support 4-byte mode, even though
> > >> its device ID tells us that it should support also 3-byte mode.
> > >> This current pretty simple patch enables the use of this flash with
> > >> very limited code additions. It also helps others (Simon on
> > >> SoCFPGA) with their issues regarding 3-byte vs 4-byte mode -
> > >> especially in regard to the bootrom and its setup.
> > >
> > > If you look into my patch, for the flashes that support both 3-byte
> > > and 4-byte addressing modes, the default addressing mode is set to
> > > 4-byte. In such case if the user wants to send a command in 3-byte
> > > mode then he has to set a flag. So SFDP path will be able to handle
> > > the special chip that is factory strapped to 4-byte addressing mode.
> > >
> > > Code snippet from patch which handles 3-byte/4-byte/both addressing
> modes:
> > > + switch (bfpt.dwords[BFPT_DWORD(1)] &
> > BFPT_DWORD1_ADDRESS_BYTES_MASK) {
> > > +case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: // flashes with
> > > + 3-byte
> > addressing
> > > +flash->addr_width = 3;
> > > +break;
> > > +case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4: // flashes with both
> > > + 3 or
> > 4 byte
> > > +printf("SF: Flash defaults to 3-Byte mode; enters 4-Byte
> > > ");
> > > +printf("mode on command\n");
> > > +/*
> > > + * By default, 4-byte addressing mode is set.
> > > + * To enforce 3-byte addressing mode, set addrwd_3_in_use
> flag
> > > + * in struct spi_flash for every command.
> > > + */
> > > +flash->addr_width = 4;
> > > +break;
> > > + case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: // flashes with
> > > + 4-byte
> > addressing
> > > +flash->addr_width = 4;
> > > +break;
> > >
> > >>
> > >>> I've floated a similar patch in U-boot that reads and parses SFDP
> > >>> parameters from flash and auto-detects its addressing mode. It
> > >>> send commands according to the address width it detects.
> > >>> Please find the patch set at:
> > >>>
> > >>
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > ch
> > >
Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
> -Original Message- > From: York Sun > Sent: Thursday, October 25, 2018 9:20 PM > To: Stefan Roese > Cc: u-boot@lists.denx.de; Jagan Teki ; Rajat > Srivastava ; simon.k.r.goldschm...@gmail.com; > Ashish Kumar > Subject: Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs > standard 3-byte mode) > > Guys, > > Let get back to the original thread. Since Rajat's first reply, the > message id has been changed. All the comments were not captured by > patchwork. > > On 10/11/18 07:50, Stefan Roese wrote: > > Some SPI NOR chips only support 4-byte mode addressing. Here the > default > > 3-byte mode does not work and leads to incorrect accesses. This patch > > now reads the 4-byte mode status bit (in this case in the CR register > > of the Macronix SPI NOR) and configures the SPI transfers accordingly. > > > > This was noticed on the LinkIt Smart 7688 modul, which is equipped with > > an Macronix MX25L25635F device. But this device does *NOT* support > > switching to 3-byte mode via the EX4B command. > > > > This should also work when the bootrom configures the SPI flash to > > 4-byte mode and runs U-Boot after this. U-Boot should dectect this > > mode (if the 4-byte mode detection is available for this chip) and > > use the correct OPs in this case. > > From what I read, Rajat's method is to extend the controller driver to > support read SFDP and default to 4-byte mode if supported, or > overwritten by user's flag. Stefan's method is to read 4-byte status bit > and doesn't change controller driver. > > Is the default value of this 4-byte status bit valid and correct for all > cases? > > Rajat, without your patch set, does Stefan's solution work for your board? > > York No. Stefan's changes are specific to his boards and is not applicable on ours. Stefan's patch is to support only certain flash that are factory strapped to work in 4-byte addressing modes only and will default to old method if such a flash is not found. The flashes on our boards (and also other vendor's board) will not work with Stefan's patch. My patch can handle flashes with address widths of 3-byte, 4-byte or both. It also takes a more generic path (as opposed to supporting only specific flash models) by parsing SFDP standard parameters and then deciding what address width is to be used. - Rajat ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
Hi Stefan
> -Original Message-
> From: Stefan Roese
> Sent: Tuesday, October 23, 2018 10:31 PM
> To: Rajat Srivastava ; ja...@openedev.com;
> simon.k.r.goldschm...@gmail.com
> Cc: Ashish Kumar ; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs
> standard 3-byte mode)
>
> Hi Rajat,
>
> On 23.10.18 07:17, Rajat Srivastava wrote:
> >> -Original Message-
> >> From: Stefan Roese [mailto:s...@denx.de]
> >> Sent: Monday, October 22, 2018 12:45 PM
> >> To: Rajat Srivastava <mailto:rajat.srivast...@nxp.com>;
> >> mailto:ja...@openedev.com;
> >> mailto:simon.k.r.goldschm...@gmail.com
> >> Cc: Ashish Kumar <mailto:ashish.ku...@nxp.com>; mailto:u-boot@lists.denx.de
> >> Subject: Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs
> >> standard 3-byte mode)
> >>
> >> Hi Rajat,
> >>
> >> On 17.10.18 13:52, Rajat Srivastava wrote:
> >>> Hi Stefan
> >>>
> >>> Sorry for top-posting.
> >>>
> >>> Why can't we read SFDP parameters from flash and auto-detect
> >>> 3-byte/4-byte addressing mode?
> >>> Using address width information we can support both types of flash
> >>> i.e. flashes supporting 3-byte addressing mode as well as flashes
> >>> supporting 4-byte addressing mode.
> >>
> >> Our flash supports 3- and 4-byte addressing mode. But this special
> >> chip is factory strapped to only support 4-byte mode, even though
> >> its device ID tells us that it should support also 3-byte mode.
> >> This current pretty simple patch enables the use of this flash
> >> with very limited code additions. It also helps others (Simon on
> >> SoCFPGA) with their issues regarding 3-byte vs 4-byte mode -
> >> especially in regard to the bootrom and its setup.
> >
> > If you look into my patch, for the flashes that support both
> > 3-byte and 4-byte addressing modes, the default addressing mode is set to
> > 4-byte. In such case if the user wants to send a command in 3-byte mode
> > then he has to set a flag. So SFDP path will be able to handle the special
> > chip that is factory strapped to 4-byte addressing mode.
> >
> > Code snippet from patch which handles 3-byte/4-byte/both addressing modes:
> > + switch (bfpt.dwords[BFPT_DWORD(1)] &
> BFPT_DWORD1_ADDRESS_BYTES_MASK) {
> > +case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: // flashes with 3-byte
> addressing
> > +flash->addr_width = 3;
> > +break;
> > +case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4: // flashes with both 3 or
> 4 byte
> > +printf("SF: Flash defaults to 3-Byte mode; enters 4-Byte
> > ");
> > +printf("mode on command\n");
> > +/*
> > + * By default, 4-byte addressing mode is set.
> > + * To enforce 3-byte addressing mode, set addrwd_3_in_use
> > flag
> > + * in struct spi_flash for every command.
> > + */
> > +flash->addr_width = 4;
> > +break;
> > + case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: // flashes with 4-byte
> addressing
> > +flash->addr_width = 4;
> > +break;
> >
> >>
> >>> I've floated a similar patch in U-boot that reads and parses SFDP
> >>> parameters from flash and auto-detects its addressing mode. It send
> >>> commands according to the address width it detects.
> >>> Please find the patch set at:
> >>>
> >>
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> >>
> work.ozlabs.org%2Fcover%2F985326%2Fdata=02%7C01%7Crajat.srivast
> >>
> ava%40nxp.com%7C56b81d26a6954324bebd08d637ee0c35%7C686ea1d3bc2b4
> >>
> c6fa92cd99c5c301635%7C0%7C0%7C636757892882342025sdata=M2aU
> >>
> WUxSn9wmlBlYj336%2Bay5rwOddG%2Br7Qn5kH%2Bf1uw%3Dreserved=
> >> 0
> >>>
> >>
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> >>
> work.ozlabs.org%2Fpatch%2F985327%2Fdata=02%7C01%7Crajat.srivast
> >>
> ava%40nxp.com%7C56b81d26a6954324bebd08d637ee0c35%7C686ea1d3bc2b4
> >>
> c6fa92cd99c5c301635%7C0%7C0%7C636757892882342025sdata=IIzUJuI
> >> 9nL5Wn7K5uAqjig9edpW6YIIcSOExNJNB5qE%3Dreserved=0
> >>>
> >>
> https://emea01.safelinks.protection.outlook.com/
Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
Hi Stefan
> -Original Message-
> From: Stefan Roese [mailto:s...@denx.de]
> Sent: Monday, October 22, 2018 12:45 PM
> To: Rajat Srivastava ; ja...@openedev.com;
> simon.k.r.goldschm...@gmail.com
> Cc: Ashish Kumar ; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs
> standard 3-byte mode)
>
> Hi Rajat,
>
> On 17.10.18 13:52, Rajat Srivastava wrote:
> > Hi Stefan
> >
> > Sorry for top-posting.
> >
> > Why can't we read SFDP parameters from flash and auto-detect
> > 3-byte/4-byte addressing mode?
> > Using address width information we can support both types of flash
> > i.e. flashes supporting 3-byte addressing mode as well as flashes
> > supporting 4-byte addressing mode.
>
> Our flash supports 3- and 4-byte addressing mode. But this special
> chip is factory strapped to only support 4-byte mode, even though
> its device ID tells us that it should support also 3-byte mode.
> This current pretty simple patch enables the use of this flash
> with very limited code additions. It also helps others (Simon on
> SoCFPGA) with their issues regarding 3-byte vs 4-byte mode -
> especially in regard to the bootrom and its setup.
If you look into my patch, for the flashes that support both
3-byte and 4-byte addressing modes, the default addressing mode is set to
4-byte. In such case if the user wants to send a command in 3-byte mode
then he has to set a flag. So SFDP path will be able to handle the special
chip that is factory strapped to 4-byte addressing mode.
Code snippet from patch which handles 3-byte/4-byte/both addressing modes:
+ switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
+case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: // flashes with 3-byte
addressing
+flash->addr_width = 3;
+break;
+case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4: // flashes with both 3 or 4 byte
+printf("SF: Flash defaults to 3-Byte mode; enters 4-Byte ");
+printf("mode on command\n");
+/*
+ * By default, 4-byte addressing mode is set.
+ * To enforce 3-byte addressing mode, set addrwd_3_in_use flag
+ * in struct spi_flash for every command.
+ */
+flash->addr_width = 4;
+break;
+ case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: // flashes with 4-byte
addressing
+flash->addr_width = 4;
+break;
>
> > I've floated a similar patch in U-boot that reads and parses SFDP
> > parameters from flash and auto-detects its addressing mode. It send
> > commands according to the address width it detects.
> > Please find the patch set at:
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.ozlabs.org%2Fcover%2F985326%2Fdata=02%7C01%7Crajat.srivast
> ava%40nxp.com%7C56b81d26a6954324bebd08d637ee0c35%7C686ea1d3bc2b4
> c6fa92cd99c5c301635%7C0%7C0%7C636757892882342025sdata=M2aU
> WUxSn9wmlBlYj336%2Bay5rwOddG%2Br7Qn5kH%2Bf1uw%3Dreserved=
> 0
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F985327%2Fdata=02%7C01%7Crajat.srivast
> ava%40nxp.com%7C56b81d26a6954324bebd08d637ee0c35%7C686ea1d3bc2b4
> c6fa92cd99c5c301635%7C0%7C0%7C636757892882342025sdata=IIzUJuI
> 9nL5Wn7K5uAqjig9edpW6YIIcSOExNJNB5qE%3Dreserved=0
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F985329%2Fdata=02%7C01%7Crajat.srivast
> ava%40nxp.com%7C56b81d26a6954324bebd08d637ee0c35%7C686ea1d3bc2b4
> c6fa92cd99c5c301635%7C0%7C0%7C636757892882342025sdata=N5qQJ
> E1776Wb3siJApPDCkUyY4vn0ZVLjCebn4hi6bk%3Dreserved=0
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F985328%2Fdata=02%7C01%7Crajat.srivast
> ava%40nxp.com%7C56b81d26a6954324bebd08d637ee0c35%7C686ea1d3bc2b4
> c6fa92cd99c5c301635%7C0%7C0%7C636757892882342025sdata=tC%2F
> %2FsGVwV%2FrHBPX1gJ5TNYmVnJOL13XpAjgP87w3%2Bx0%3Dreserved
> =0
>
> I've just applied your 3 patches and have added SFDP support for
> our equipped SPI chip (with my patch not applied):
>
> - {"mx25l25635f",INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP) },
> + {"mx25l25635f",INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | SPI_FLASH_USE_SFDP) },
>
> This does not seem to work though:
Simply adding SPI_FLASH_USE_SFDP flag is not enough to make SFDP work. You'll
need to add the driver code corresponding to the mtd layer code (in spi_flash.c)
[U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
Hi Stefan
Sorry for top-posting.
Why can't we read SFDP parameters from flash and auto-detect 3-byte/4-byte
addressing mode?
Using address width information we can support both types of flash i.e. flashes
supporting 3-byte addressing mode as well as flashes supporting 4-byte
addressing mode.
I've floated a similar patch in U-boot that reads and parses SFDP parameters
from flash and auto-detects its addressing mode. It send commands according to
the address width it detects.
Please find the patch set at:
https://patchwork.ozlabs.org/cover/985326/
https://patchwork.ozlabs.org/patch/985327/
https://patchwork.ozlabs.org/patch/985329/
https://patchwork.ozlabs.org/patch/985328/
Thanks
Rajat
> -Original Message-
> From: U-Boot On Behalf Of Stefan Roese
> Sent: Thursday, October 11, 2018 8:20 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki
> Subject: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs
> standard 3-byte mode)
>
> Some SPI NOR chips only support 4-byte mode addressing. Here the
> default 3- byte mode does not work and leads to incorrect accesses.
> This patch now reads the 4-byte mode status bit (in this case in the
> CR register of the Macronix SPI
> NOR) and configures the SPI transfers accordingly.
>
> This was noticed on the LinkIt Smart 7688 modul, which is equipped
> with an Macronix MX25L25635F device. But this device does *NOT*
> support switching to 3-byte mode via the EX4B command.
>
> This should also work when the bootrom configures the SPI flash to
> 4-byte mode and runs U-Boot after this. U-Boot should dectect this
> mode (if the 4-byte mode detection is available for this chip) and use the
> correct OPs in this case.
>
> Signed-off-by: Stefan Roese
> Cc: Jagan Teki
> Tested-by: Simon Goldschmidt
> ---
> v3:
> - Rebased on latest version (merge conflict because of new patches
> from Simon Glass)
> - Added Tested-by tag from Simon Goldschmidt
>
> v2:
> - Integrated STMICRO 4-byte detection from Simon
>
> drivers/mtd/spi/sf_internal.h | 3 +-
> drivers/mtd/spi/spi_flash.c | 131 --
> include/spi_flash.h | 5 ++
> 3 files changed, 118 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/mtd/spi/sf_internal.h
> b/drivers/mtd/spi/sf_internal.h index
> 4f63cacc64..eb076401d1 100644
> --- a/drivers/mtd/spi/sf_internal.h
> +++ b/drivers/mtd/spi/sf_internal.h
> @@ -26,7 +26,8 @@ enum spi_nor_option_flags { };
>
> #define SPI_FLASH_3B_ADDR_LEN3
> -#define SPI_FLASH_CMD_LEN(1 + SPI_FLASH_3B_ADDR_LEN)
> +#define SPI_FLASH_4B_ADDR_LEN4
> +#define SPI_FLASH_CMD_MAX_LEN(1 +
> SPI_FLASH_4B_ADDR_LEN)
> #define SPI_FLASH_16MB_BOUN 0x100
>
> /* CFI Manufacture ID's */
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 9230060364..b22eea2d1c 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -20,12 +20,19 @@
>
> #include "sf_internal.h"
>
> -static void spi_flash_addr(u32 addr, u8 *cmd)
> +static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8
> +*cmd)
> {
> /* cmd[0] is actual command */
> - cmd[1] = addr >> 16;
> - cmd[2] = addr >> 8;
> - cmd[3] = addr >> 0;
> + if (flash->in_4byte_mode) {
> + cmd[1] = addr >> 24;
> + cmd[2] = addr >> 16;
> + cmd[3] = addr >> 8;
> + cmd[4] = addr >> 0;
> + } else {
> + cmd[1] = addr >> 16;
> + cmd[2] = addr >> 8;
> + cmd[3] = addr >> 0;
> + }
> }
>
> static int read_sr(struct spi_flash *flash, u8 *rs) @@ -110,6 +117,72
> @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif
>
> +#if defined(CONFIG_SPI_FLASH_MACRONIX)
> +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) {
> + int ret;
> + u8 cr;
> + u8 cmd;
> +
> + cmd = 0x15; /* Macronix: read configuration register RDCR */
> + ret = spi_flash_read_common(flash, , 1, , 1);
> + if (ret < 0) {
> + debug("SF: fail to read config register\n");
> + return false;
> + }
> +
> + /* Return true, if 4-byte mode is enabled */
> + if (cr & BIT(5))
> + return true;
> +
> + return false;
> +}
> +#else
> +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) {
> + return false;
> +}
> +#endif
> +
> +#if defined(CONFIG_SPI_FLASH_STMICRO) static bool
> +flash_in_4byte_mode_stmicro(struct spi_flash *flash) {
> + int ret;
> + u8 fsr;
> + u8 cmd;
> +
> + cmd = 0x70; /* STMicro/Micron: read flag status register */
> + ret = spi_flash_read_common(flash, , 1, , 1);
> + if (ret < 0) {
> + debug("SF: fail to read config register\n");
> + return false;
> + }
> +
> + /* Return true, if 4-byte mode is enabled */
> + if (fsr & BIT(0))
> + return true;
> +
> + return false;
[U-Boot] [PATCH 2/3] fsl_qspi: Access flash above 16MB using SFDP
Add functionality to read SFDP parameters in fsl_qspi driver.
Also, use the address width information from SFDP to enable
flash access above 16 MB.
Introduce a way to access parent structure by adding pointer
to struct spi_slave in struct fsl_qspi_priv.
Signed-off-by: Rajat Srivastava
---
drivers/spi/fsl_qspi.c | 103 +
1 file changed, 96 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1598c4f698..615f36e351 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK GENMASK(23, 0)
+#define SET_BITS_MASK(X) GENMASK(X, 0)
#define FLASH_STATUS_WEL 0x02
@@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#define SEQID_WRAR 13
#define SEQID_RDAR 14
+#define SEQID_RDSFDP 15
/* QSPI CMD */
#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
@@ -57,6 +58,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
#define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
#define QSPI_CMD_RDID 0x9f/* Read JEDEC ID */
+#define QSPI_CMD_RDSFDP0x5a/* Read SFDP parameters from
flash */
/* Used for Micron, winbond and Macronix flashes */
#defineQSPI_CMD_WREAR 0xc5/* EAR register write */
@@ -132,6 +134,7 @@ struct fsl_qspi_priv {
u32 flash_num;
u32 num_chipselect;
struct fsl_qspi_regs *regs;
+ void *spi_slave;
};
@@ -363,6 +366,19 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
qspi_write32(priv->flags, >lut[lut_base + 1],
OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+ /* Read SFDP information */
+ lut_base = SEQID_RDSFDP * 4;
+ qspi_write32(priv->flags, >lut[lut_base],
+OPRND0(QSPI_CMD_RDSFDP) | PAD0(LUT_PAD1) |
+INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+ qspi_write32(priv->flags, >lut[lut_base + 1],
+OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
+OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
+INSTR1(LUT_READ));
+ qspi_write32(priv->flags, >lut[lut_base + 2], 0);
+ qspi_write32(priv->flags, >lut[lut_base + 3], 0);
+
/* Lock the LUT */
qspi_write32(priv->flags, >lutkey, LUT_KEY_VALUE);
qspi_write32(priv->flags, >lckcr, QSPI_LCKCR_LOCK);
@@ -562,6 +578,61 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32
*rxbuf, u32 len)
qspi_write32(priv->flags, >mcr, mcr_reg);
}
+static void qspi_op_rdsfdp(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
+{
+ struct fsl_qspi_regs *regs = priv->regs;
+ u32 mcr_reg, data;
+ int i, size;
+ u32 to_or_from;
+ u32 seqid;
+
+ seqid = SEQID_RDSFDP;
+
+ mcr_reg = qspi_read32(priv->flags, >mcr);
+ qspi_write32(priv->flags, >mcr,
+QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ qspi_write32(priv->flags, >rbct, QSPI_RBCT_RXBRD_USEIPS);
+
+ to_or_from = priv->sf_addr + priv->cur_amba_base;
+
+ while (len > 0) {
+ WATCHDOG_RESET();
+
+ qspi_write32(priv->flags, >sfar, to_or_from);
+
+ size = (len > RX_BUFFER_SIZE) ?
+ RX_BUFFER_SIZE : len;
+
+ qspi_write32(priv->flags, >ipcr,
+(seqid << QSPI_IPCR_SEQID_SHIFT) |
+size);
+ while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
+ ;
+
+ to_or_from += size;
+ len -= size;
+
+ i = 0;
+ while ((size < RX_BUFFER_SIZE) && (size > 0)) {
+ data = qspi_read32(priv->flags, >rbdr[i]);
+ data = qspi_endian_xchg(data);
+ if (size < 4)
+ memcpy(rxbuf, , size);
+ else
+ memcpy(rxbuf, , 4);
+ rxbuf++;
+ size -= 4;
+ i++;
+ }
+ qspi_write32(priv->flags, >mcr,
+qspi_read32(priv->flags, >mcr) |
+QSPI_MCR_CLR_RXF_MASK);
+ }
+
+ qspi_write32(priv->flags, >mcr, mcr_reg);
+}
+
/* If not use AHB read, read data from ip interface */
static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
{
@@ -772,14 +
[U-Boot] [PATCH 3/3] spi_flash_ids: Enable SFDP parsing for s25fs512 flash
Signed-off-by: Rajat Srivastava
---
drivers/mtd/spi/spi_flash_ids.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index ad0a0c8150..db4a93c7f5 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -113,7 +113,8 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL |
WR_QPP) },
{"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL |
WR_QPP | SECT_4K) },
{"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL |
WR_QPP) },
- {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL |
WR_QPP | SECT_4K) },
+ {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL |
+WR_QPP | SECT_4K | SPI_FLASH_USE_SFDP) },
{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL |
WR_QPP) },
{"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL |
WR_QPP) },
{"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL |
WR_QPP) },
--
2.14.1
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[U-Boot] [PATCH 1/3] mtd/spi: Add JEDEC SFDP support in SPI framework
Add support for JESD216 rev B standard JEDEC Serial
Flash Discoverable Parameters (SFDP) tables to
dynamically initialize flash size, page size and
address width of the flash. More parameters can be
added as per requirement.
Already existing method for parsing these parameters
are not deprecated, which can be done once most flash
start using SFDP data.
SFDP data lets us auto-detect the addressing mode
supported by the flash which helps us access the
flash using 4-byte address.
Add a new argument in spi_flash_addr() function to create
commands with 3-byte or 4-byte address depending on the
SFDP data read. Add pointer to struct spi_flash in struct
spi_slave so that driver can have access to SFDP data.
Introduce new structures and functions to read and parse
SFDP data. This is loosely based on Linux SFDP framework.
Signed-off-by: Rajat Srivastava
---
drivers/mtd/spi/sf_internal.h | 4 +
drivers/mtd/spi/spi_flash.c | 297 +++---
include/spi.h | 2 +
include/spi_flash.h | 120 +
4 files changed, 403 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 26f5c7c995..1bb4431d84 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -26,7 +26,9 @@ enum spi_nor_option_flags {
};
#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_4B_ADDR_LEN 4
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
+#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
/* CFI Manufacture ID's */
@@ -62,6 +64,7 @@ enum spi_nor_option_flags {
#define CMD_READ_STATUS1 0x35
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_READ_SFDP 0x5a
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
@@ -144,6 +147,7 @@ struct spi_flash_info {
#define RD_DUALBIT(5) /* use Dual Read */
#define RD_QUADIO BIT(6) /* use Quad IO Read */
#define RD_DUALIO BIT(7) /* use Dual IO Read */
+#define SPI_FLASH_USE_SFDP BIT(8) /* parse SFDP to get flash info */
#define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO |
RD_DUALIO)
};
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index a87bacd4ac..5d2728cc00 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -20,12 +20,24 @@
#include "sf_internal.h"
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd)
{
/* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
+ int i;
+
+ /* Remember to unset addrwd_3_in_use */
+ if (flash->addrwd_3_in_use) {
+ flash->addr_width = SPI_FLASH_3B_ADDR_LEN;
+ debug("SF: addrwd_3_in_use flag needs to be reset to false ");
+ debug("after the intended command is triggered to flash.\n");
+ }
+
+ flash->cmd_len = 1 + flash->addr_width;
+
+ for (i = flash->cmd_len - 1; i > 0; i--) {
+ cmd[i] = addr;
+ addr = addr >> 8;
+ }
}
static int read_sr(struct spi_flash *flash, u8 *rs)
@@ -314,7 +326,7 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size, erase_addr;
- u8 cmd[SPI_FLASH_CMD_LEN];
+ u8 cmd[SPI_FLASH_CMD_MAX_LEN];
int ret = -1;
erase_size = flash->erase_size;
@@ -344,12 +356,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len)
if (ret < 0)
return ret;
#endif
- spi_flash_addr(erase_addr, cmd);
+ spi_flash_addr(flash, erase_addr, cmd);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], erase_addr);
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ ret = spi_flash_write_common(flash, cmd, flash->cmd_len,
+NULL, 0);
if (ret < 0) {
debug("SF: erase failed\n");
break;
@@ -373,7 +386,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
- u8 cmd[SPI_FLASH_CMD_LEN];
+ u8 cmd[SPI_FLASH_CMD_MAX_LEN];
int ret = -1;
page_size = flash->page_size;
@@ -406,13 +419,13 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
[U-Boot] [PATCH 0/3] Read SFDP parameters and access flash above 16MB
Add functionality to read and parse SFDP parameters to auto-detect flash size, page size and address width of flash. This enables flash access above 16MB using 4-byte addressing mode. Add driver support to get SFDP information of flash and use it to access flash above 16MB. Enable reading and parsing of SFDP parameters for Spansion's s25fs512 flash to auto-detect its size, its page size and the addressing mode it supports. Rajat Srivastava (3): mtd/spi: Add JEDEC SFDP support in SPI framework fsl_qspi: Access flash above 16MB using SFDP spi_flash_ids: Enable SFDP parsing for s25fs512 flash drivers/mtd/spi/sf_internal.h | 4 + drivers/mtd/spi/spi_flash.c | 297 +--- drivers/mtd/spi/spi_flash_ids.c | 3 +- drivers/spi/fsl_qspi.c | 103 +- include/spi.h | 2 + include/spi_flash.h | 120 6 files changed, 501 insertions(+), 28 deletions(-) -- 2.14.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] spi: fsl_qspi: Introduce is_controller_busy function
Some SoCs have different endianness of QSPI IP if compared
to endianness of core. The function is_controller_busy()
checks if the QSPI controller is busy or not, considering
the endianness of the QSPI IP.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Reviewed-by: York Sun <york@nxp.com>
---
drivers/spi/fsl_qspi.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index c201c7f823..e264709a3f 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -156,6 +156,25 @@ static void qspi_write32(u32 flags, u32 *addr, u32 val)
out_be32(addr, val) : out_le32(addr, val);
}
+static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
+{
+ u32 val;
+ const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
+QSPI_SR_IP_ACC_MASK;
+ unsigned int retry = 5;
+
+ do {
+ val = qspi_read32(priv->flags, >regs->sr);
+
+ if ((~val & mask) == mask)
+ return 0;
+
+ udelay(1);
+ } while (--retry);
+
+ return -ETIMEDOUT;
+}
+
/* QSPI support swapping the flash read/write data
* in hardware for LS102xA, but not for VF610 */
static inline u32 qspi_endian_xchg(u32 data)
@@ -1020,11 +1039,7 @@ static int fsl_qspi_probe(struct udevice *bus)
priv->num_chipselect = plat->num_chipselect;
/* make sure controller is not busy anywhere */
- ret = wait_for_bit_le32(>regs->sr,
- QSPI_SR_BUSY_MASK |
- QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK,
- false, 100, false);
+ ret = is_controller_busy(priv);
if (ret) {
debug("ERROR : The controller is busy\n");
@@ -1187,11 +1202,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
priv = dev_get_priv(bus);
/* make sure controller is not busy anywhere */
- ret = wait_for_bit_le32(>regs->sr,
- QSPI_SR_BUSY_MASK |
- QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK,
- false, 100, false);
+ ret = is_controller_busy(priv);
if (ret) {
debug("ERROR : The controller is busy\n");
--
2.14.1
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Re: [U-Boot] [PATCH] ls1088a: qspi: Enable XIP mode above 16 MB addresses
> -Original Message- > From: York Sun > Sent: Tuesday, February 06, 2018 10:38 PM > To: Rajat Srivastava <rajat.srivast...@nxp.com>; u-boot@lists.denx.de > Subject: Re: [PATCH] ls1088a: qspi: Enable XIP mode above 16 MB addresses > > On 02/06/2018 02:59 AM, Rajat Srivastava wrote: > > > > > > > >> How do you put the image into it to begin with? Don't tell me you > >> were using an external tool or a hacked version of older U-Boot. > >> > > This patch enables data read above 16MB using AHB (on Uboot prompt) > > and does not involve our QSPI driver. It is equivalent to reading from DDR > > via > cp or md commands. > > Whereas writing to flash is possible via IPS mode which involves our > > driver (using sf commands). > > > OK. So we are still far away to have the full flash supported. > AHB Write is not supported by QSPI hardware. Rajat ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ls1088a: qspi: Enable XIP mode above 16 MB addresses
> -Original Message- > From: York Sun > Sent: Monday, February 05, 2018 10:20 PM > To: Rajat Srivastava <rajat.srivast...@nxp.com>; u-boot@lists.denx.de > Subject: Re: [PATCH] ls1088a: qspi: Enable XIP mode above 16 MB addresses > > On 02/04/2018 09:37 PM, Rajat Srivastava wrote: > > > > > >> -Original Message- > >> From: York Sun > >> Sent: Friday, February 02, 2018 9:29 PM > >> To: Rajat Srivastava <rajat.srivast...@nxp.com>; u-boot@lists.denx.de > >> Subject: Re: [PATCH] ls1088a: qspi: Enable XIP mode above 16 MB > >> addresses > >> > >> On 02/02/2018 04:07 AM, Rajat Srivastava wrote: > >>> Currently in LS1088A, XIP mode in QSPI works up to 16 MB addresses. > >>> This patch enables QSPI support in XIP mode for addresses above 16 > >>> MB as well. > >> > >> Can you write to QSPI above 16MB address? > > > > No, I think execute in place (XIP) itself means we can only read. > > Please suggest if I shall change the patch description. > > > > How do you put the image into it to begin with? Don't tell me you were using > an > external tool or a hacked version of older U-Boot. > This patch enables data read above 16MB using AHB (on Uboot prompt) and does not involve our QSPI driver. It is equivalent to reading from DDR via cp or md commands. Whereas writing to flash is possible via IPS mode which involves our driver (using sf commands). ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ls1088a: qspi: Enable XIP mode above 16 MB addresses
> -Original Message- > From: York Sun > Sent: Friday, February 02, 2018 9:29 PM > To: Rajat Srivastava <rajat.srivast...@nxp.com>; u-boot@lists.denx.de > Subject: Re: [PATCH] ls1088a: qspi: Enable XIP mode above 16 MB addresses > > On 02/02/2018 04:07 AM, Rajat Srivastava wrote: > > Currently in LS1088A, XIP mode in QSPI works up to 16 MB addresses. > > This patch enables QSPI support in XIP mode for addresses above 16 MB > > as well. > > Can you write to QSPI above 16MB address? No, I think execute in place (XIP) itself means we can only read. Please suggest if I shall change the patch description. Rajat ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Disable hybrid mode for SPANSION S25FS-S family
> -Original Message- > From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > Sent: Tuesday, October 31, 2017 1:32 PM > To: Rajat Srivastava <rajat.srivast...@nxp.com> > Cc: u-boot@lists.denx.de; York Sun <york@nxp.com>; Suresh Gupta > <suresh.gu...@nxp.com> > Subject: Re: [PATCH 0/2] Disable hybrid mode for SPANSION S25FS-S family > > On Mon, Oct 30, 2017 at 5:23 PM, Rajat Srivastava <rajat.srivast...@nxp.com> > wrote: > >> On Mon, Oct 30, 2017 at 11:52 AM, Jagan Teki > >> <jagannadh.t...@gmail.com> > >> wrote: > >> > On Mon, Oct 16, 2017 at 12:54 PM, Rajat Srivastava > >> > <rajat.srivast...@nxp.com> wrote: > >> >> The S25FS-S family physical sectors may be configured as a hybrid > >> >> combination of eight 4-kB parameter sectors at the top or bottom > >> >> of the address space with all but one of the remaining sectors > >> >> being uniform size. The default status of the flash is the hybrid > >> >> architecture. > >> >> > >> >> Since the parameter sectors and the uniform sectors have different > >> >> erase commands, it is a problem to implement erase functionality > >> >> for hybrid mode in current U-boot code. Also, enabling hybrid mode > >> >> doesn't provide any significant benefit. > >> > > >> > I think I've asked this question before, keeping the state of the > >> > flash remains same. Can't erase parameter and uniform sectors > >> > individually during operations like > >> > - parameter sectors with erase commands (20h or 21h) > >> > - uniform sectors with erase commands (D8h or DCh) > >> > >> I understand that even we can do parameter and uniform sectors > >> individually with the help of offsets we still have 224. Any idea why > >> we need hybrid mode with this off 244 sector size? if require we can even > write cypress on this case. > >> > > Hi Jagan > > > > I am not aware of usage of the remaining 244 sector area. We will discuss > > this > with Cypress. > > > > Moreover, do you have any idea where we apply offset based checks in code? > And if we do apply checks, will that look good with current Uboot code? > > I think no one is going to use hybrid mode and even if someone wants to, > > they > can modify the code. > > We can change the erase opcode based on the offsets in erase ops, since if we > disable hybrid now, if someone want to re-enable for another reason (say some > kind of protection PB, not sure) will end-up conflict. Better we can ask > Cypress > about this and mean while we can post this change on spi-nor Linux for further > discussion. > Thanks Jagan. I am working on creating a similar patch in Linux. Best regards Rajat ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Disable hybrid mode for SPANSION S25FS-S family
> On Mon, Oct 30, 2017 at 11:52 AM, Jagan Teki <jagannadh.t...@gmail.com> > wrote: > > On Mon, Oct 16, 2017 at 12:54 PM, Rajat Srivastava > > <rajat.srivast...@nxp.com> wrote: > >> The S25FS-S family physical sectors may be configured as a hybrid > >> combination of eight 4-kB parameter sectors at the top or bottom of > >> the address space with all but one of the remaining sectors being > >> uniform size. The default status of the flash is the hybrid > >> architecture. > >> > >> Since the parameter sectors and the uniform sectors have different > >> erase commands, it is a problem to implement erase functionality for > >> hybrid mode in current U-boot code. Also, enabling hybrid mode > >> doesn't provide any significant benefit. > > > > I think I've asked this question before, keeping the state of the > > flash remains same. Can't erase parameter and uniform sectors > > individually during operations like > > - parameter sectors with erase commands (20h or 21h) > > - uniform sectors with erase commands (D8h or DCh) > > I understand that even we can do parameter and uniform sectors individually > with the help of offsets we still have 224. Any idea why we need hybrid mode > with this off 244 sector size? if require we can even write cypress on this > case. > Hi Jagan I am not aware of usage of the remaining 244 sector area. We will discuss this with Cypress. Moreover, do you have any idea where we apply offset based checks in code? And if we do apply checks, will that look good with current Uboot code? I think no one is going to use hybrid mode and even if someone wants to, they can modify the code. Thanks Rajat ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] sf: Fix s25fs512s erase size and remove SECT_4K flag
As per data sheet, S25FS512S support uniform sector option
or erase size of 256 kbytes and Page Programming buffer of
256 or 512 Bytes. So, flag SECT_4K has no significance for
this flash.
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
---
drivers/mtd/spi/spi_flash_ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index 13f64e7..f47f96c 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -103,7 +103,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL |
WR_QPP) },
{"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL |
WR_QPP | SECT_4K) },
{"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL |
WR_QPP) },
- {"s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, RD_FULL |
WR_QPP | SECT_4K) },
+ {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL |
WR_QPP) },
{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL |
WR_QPP) },
{"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL |
WR_QPP) },
{"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL |
WR_QPP) },
--
2.7.4
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[U-Boot] [PATCH 1/2] sf: Disable hybrid mode for SPANSION S25FS-S family
The S25FS-S family physical sectors may be configured as a hybrid
combination of eight 4-kB parameter sectors at the top or bottom
of the address space with all but one of the remaining sectors
being uniform size.
The default status of the flash is the hybrid architecture.
The parameter sectors and the uniform sectors have different erase
commands.
This patch disables the hybrid sector architecture. The flash will
have uniform sector size and uniform erase command.
This configuration is temporary and the flash will revert to hybrid
architecture after power on reset.
Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
---
drivers/mtd/spi/sf_internal.h | 7 +
drivers/mtd/spi/spi_flash.c | 65 +++
2 files changed, 72 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 839cdbe..228960c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -63,6 +63,12 @@ enum spi_nor_option_flags {
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+/* Spansion specific commands */
+#ifdef CONFIG_SPI_FLASH_SPANSION
+#define CMD_SPANSION_RDAR 0x65
+#define CMD_SPANSION_WRAR 0x71
+#endif
+
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
# define CMD_BANKADDR_BRWR 0x17
@@ -99,6 +105,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t
len,
#define JEDEC_MFR(info)((info)->id[0])
#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
#define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
+#define JEDEC_FAM_ID(info) ((info)->id[5])
#define SPI_FLASH_MAX_ID_LEN 6
struct spi_flash_info {
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 34f6888..5152afd 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -937,6 +937,45 @@ int spi_flash_decode_fdt(struct spi_flash *flash)
}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_s25fss_disable_hybrid_mode(struct spi_slave *spi)
+{
+ u8 cmd[4];
+ u32 offset = 0x84; /* CR3V register offset */
+ u8 cr3v;
+ int ret;
+
+ cmd[0] = CMD_SPANSION_RDAR;
+ cmd[1] = offset >> 16;
+ cmd[2] = offset >> 8;
+ cmd[3] = offset >> 0;
+
+ ret = spi_flash_cmd_read(spi, cmd, 4, , 1);
+ if (ret)
+ return -EIO;
+
+ /* CR3V bit3: 4-KB Erase */
+ if (cr3v & 0x8)
+ return 0;
+
+ cmd[0] = CMD_SPANSION_WRAR;
+ cr3v |= 0x8;
+ ret = spi_flash_cmd_write(spi, cmd, 4, , 1);
+ if (ret)
+ return -EIO;
+
+ cmd[0] = CMD_SPANSION_RDAR;
+ ret = spi_flash_cmd_read(spi, cmd, 4, , 1);
+ if (ret)
+ return -EIO;
+
+ if (!(cr3v & 0x8))
+ return -EFAULT;
+
+ return 0;
+}
+#endif
+
int spi_flash_scan(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
@@ -1034,6 +1073,32 @@ int spi_flash_scan(struct spi_flash *flash)
/* Now erase size becomes valid sector size */
flash->sector_size = flash->erase_size;
+#ifdef CONFIG_SPI_FLASH_SPANSION
+ /*
+* The S25FS-S family physical sectors may be configured as a
+* hybrid combination of eight 4-kB parameter sectors
+* at the top or bottom of the address space with all
+* but one of the remaining sectors being uniform size.
+* The Parameter Sector Erase commands (20h or 21h) must
+* be used to erase the 4-kB parameter sectors individually.
+* The Sector (uniform sector) Erase commands (D8h or DCh)
+* must be used to erase any of the remaining
+* sectors, including the portion of highest or lowest address
+* sector that is not overlaid by the parameter sectors.
+* The uniform sector erase command has no effect on parameter sectors.
+* The following code removes the 4-kB parameter sectors from the
+* address map i.e. it disables the hybrid mode so that all sectors are
+* uniform size.
+*/
+
+ if ((JEDEC_ID(info) == 0x0219 || JEDEC_ID(info) == 0x0220) &&
+ (JEDEC_EXT(info) & 0xff00) == 0x4d00 &&
+ JEDEC_FAM_ID(info) == 0x81) {
+ ret = spansion_s25fss_disable_hybrid_mode(spi);
+ if (ret)
+ return ret;
+ }
+#endif
/* Look for read commands */
flash->read_cmd = CMD_READ_ARRAY_FAST;
if (spi->mode & SPI_RX_SLOW)
--
2.7.4
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[U-Boot] [PATCH 0/2] Disable hybrid mode for SPANSION S25FS-S family
The S25FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors at the top or bottom of the address space with all but one of the remaining sectors being uniform size. The default status of the flash is the hybrid architecture. Since the parameter sectors and the uniform sectors have different erase commands, it is a problem to implement erase functionality for hybrid mode in current U-boot code. Also, enabling hybrid mode doesn't provide any significant benefit. There is a configuration option to disable the hybrid mode so that all sectors are of uniform size (256 kbytes). This set of patches disables the above mentioned hybrid mode in Spansion S25FS-S family of flashes. Rajat Srivastava (2): sf: Disable hybrid mode for SPANSION S25FS-S family sf: Fix s25fs512s erase size and remove SECT_4K flag drivers/mtd/spi/sf_internal.h | 7 + drivers/mtd/spi/spi_flash.c | 65 + drivers/mtd/spi/spi_flash_ids.c | 2 +- 3 files changed, 73 insertions(+), 1 deletion(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/4] armv8/fsl-layerscape: add dwc3 gadget driver support
From: Rajesh Bhagat <rajesh.bha...@nxp.com> Adds support for dwc3 gadget driver for ARM v8 platform of layerscape series. Currently this patch has been tested for LS1043A Rajat Srivastava (3): usb: dwc3: Add helper functions to enable snooping and burst settings armv8/fsl-layerscape: add dwc3 gadget driver support armv8/fsl-layerscape: enable dwc3 gadget driver support Rajesh Bhagat (1): usb: ums: support multiple controllers using controller_index arch/arm/cpu/armv8/fsl-layerscape/soc.c| 93 ++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++ cmd/usb_mass_storage.c | 2 +- drivers/usb/dwc3/core.c| 45 +++ drivers/usb/dwc3/core.h| 7 ++ drivers/usb/gadget/f_mass_storage.c| 11 ++- include/configs/ls1043aqds.h | 15 include/usb_mass_storage.h | 2 +- 8 files changed, 177 insertions(+), 4 deletions(-) -- 2.6.2.198.g614a2ac ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/4] usb: ums: support multiple controllers using controller_index
From: Rajesh Bhagat <rajesh.bha...@nxp.com>
Adds a new field in fsg_common namely controller_index to support
multiple controllers usb gadget support.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Acked-by: Lukasz Majewski <l.majew...@samsung.com>
---
Changes in v3
- None
Changes for v2:
- Changes type of fsg_main_thread argument to unsigned int
cmd/usb_mass_storage.c | 2 +-
drivers/usb/gadget/f_mass_storage.c | 11 +--
include/usb_mass_storage.h | 2 +-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index b05913a..bf80d37 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
while (1) {
usb_gadget_handle_interrupts(controller_index);
- rc = fsg_main_thread(NULL);
+ rc = fsg_main_thread(controller_index);
if (rc) {
/* Check I/O error */
if (rc == -EIO)
diff --git a/drivers/usb/gadget/f_mass_storage.c
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..27ca5fe 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -362,6 +362,7 @@ struct fsg_common {
char inquiry_string[8 + 16 + 4 + 1];
struct kref ref;
+ unsigned int controller_index;
};
struct fsg_config {
@@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
k = 0;
}
- usb_gadget_handle_interrupts(0);
+ usb_gadget_handle_interrupts(common->controller_index);
}
common->thread_wakeup_needed = 0;
return rc;
@@ -2402,10 +2403,14 @@ static void handle_exception(struct fsg_common *common)
/*-*/
-int fsg_main_thread(void *common_)
+int fsg_main_thread(unsigned int controller_index)
{
int ret;
struct fsg_common *common = the_fsg_common;
+
+ /* update the controller_index */
+ common->controller_index = controller_index;
+
/* The main loop */
do {
if (exception_in_progress(common)) {
@@ -2476,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct
fsg_common *common,
common->ops = NULL;
common->private_data = NULL;
+ common->controller_index = 0;
common->gadget = gadget;
common->ep0 = gadget->ep0;
@@ -2770,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
fsg_common->ops = NULL;
fsg_common->private_data = NULL;
+ fsg_common->controller_index = 0;
the_fsg_common = fsg_common;
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 8229f62..f21cc7a 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -28,6 +28,6 @@ struct ums {
int fsg_init(struct ums *ums_devs, int count);
void fsg_cleanup(void);
-int fsg_main_thread(void *);
+int fsg_main_thread(unsigned int);
int fsg_add(struct usb_configuration *c);
#endif /* __USB_MASS_STORAGE_H__ */
--
2.6.2.198.g614a2ac
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[U-Boot] [PATCH v3 3/4] armv8/fsl-layerscape: add dwc3 gadget driver support
Implements the dwc3 gadget driver support for LS1043
platform, and performs below operations:
1. Enables snooping support for DWC3 controller.
2. Enables cache coherency in LS1043 platform.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Reviewed-by: Lukasz Majewski <l.majew...@samsung.com>
---
Changes in v3:
- None
Changes in v2:
- Moves DWC3 driver specific code to helper functions
- Calls helper functions in SoC specific implementation
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 93 ++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++
2 files changed, 99 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..cc07524 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -17,6 +17,10 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#include
#endif
+#include
+#include
+#include
+
DECLARE_GLOBAL_DATA_PTR;
@@ -318,9 +322,18 @@ void fsl_lsch2_early_init_f(void)
#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /* Make SEC and USB reads and writes snoopable */
+#if defined(CONFIG_LS1043A)
+ setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+SCFG_SNPCNFGCR_USB3WRSNP);
+#else
/* Make SEC reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP);
+#endif
/*
* Enable snoop requests and DVM message requests for
@@ -336,6 +349,86 @@ void fsl_lsch2_early_init_f(void)
}
#endif
+#ifdef CONFIG_USB_DWC3
+
+#if defined(CONFIG_LS1043A)
+static struct dwc3_device dwc3_device_data0 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+};
+
+static struct dwc3_device dwc3_device_data1 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 1,
+};
+
+static struct dwc3_device dwc3_device_data2 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+ dwc3_uboot_handle_interrupt(index);
+ return 0;
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ switch (init) {
+ case USB_INIT_DEVICE:
+ switch (index) {
+#if defined(CONFIG_LS1043A)
+ case 0:
+ dwc3_uboot_init(_device_data0);
+ break;
+ case 1:
+ dwc3_uboot_init(_device_data1);
+ break;
+ case 2:
+ dwc3_uboot_init(_device_data2);
+ break;
+#endif
+ default:
+ printf("Invalid Controller Index\n");
+ return -1;
+ }
+#if defined(CONFIG_LS1043A)
+ dwc3_core_incr_burst_enable(index, 0xf, 0xf);
+ dwc3_core_set_snooping(index, true);
+#endif
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ switch (init) {
+ case USB_INIT_DEVICE:
+#if defined(CONFIG_LS1043A)
+ dwc3_uboot_exit(index);
+#endif
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+#endif
+
+
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 57b99d4..13ba1a6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -328,6 +328,12 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SECRDSNP0x8000
#define SCFG_SNPCNFGCR_SECWRSNP0x4000
+#define SCFG_SNPCNFGCR_USB1RDSNP 0x0020
+#define SCFG_SNPCNFGCR_USB1WRSNP 0x0010
+#define SCFG_SNPCNFGCR_USB2RDSNP 0x8000
+#define SCFG_SNPCNFGCR_USB2WRSNP 0x0001
+#define SCFG_SNPCNFGCR_USB3RDSNP 0x2000
+#define SCFG_SNPCNFGCR_USB3WRSNP 0x4000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
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[U-Boot] [PATCH v3 2/4] usb: dwc3: Add helper functions to enable snooping and burst settings
Adds helper functions to enable snooping and outstanding burst beat
settings.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
Changes in v3:
- Changed operator for code cleanup
Changes in v2:
- Removes SoC specific flags and added helper functions
drivers/usb/dwc3/core.c | 45 +
drivers/usb/dwc3/core.h | 7 +++
2 files changed, 52 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 85cc96a..4ac599a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
#define DWC3_ALIGN_MASK(16 - 1)
+void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
+int breq_limit)
+{
+ struct dwc3 *dwc;
+ u32 reg;
+
+ list_for_each_entry(dwc, _list, list) {
+ if (dwc->index != index)
+ continue;
+
+ /*
+* Change burst beat and outstanding pipelined
+* transfers requests
+*/
+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+ reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
+ reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
+ break;
+ }
+}
+
+void dwc3_core_set_snooping(int index, bool snoop)
+{
+ struct dwc3 *dwc;
+ u32 reg;
+
+ list_for_each_entry(dwc, _list, list) {
+ if (dwc->index != index)
+ continue;
+
+ /* Enable/Disable snooping */
+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+ if (snoop)
+ reg |= DWC3_SNOOP_ENABLE;
+ else
+ reg &= ~DWC3_SNOOP_ENABLE;
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+ break;
+ }
+}
+
/**
* dwc3_uboot_init - dwc3 core uboot initialization code
* @dwc3_dev: struct dwc3_device containing initialization data
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 72d2fcd..455e7fa 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -593,6 +593,13 @@ struct dwc3_hwparams {
/* HWPARAMS7 */
#define DWC3_RAM1_DEPTH(n) ((n) & 0x)
+/* GSBUSCFG0 */
+#define DWC3_SNOOP_ENABLE (0x)
+#define DWC3_INCR_BTYPE_MASK (0xff)
+
+/* GSBUSCFG1 */
+#define DWC3_BREQ_LIMIT_MASK (0xf00)
+
struct dwc3_request {
struct usb_request request;
struct list_headlist;
--
2.6.2.198.g614a2ac
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[U-Boot] [PATCH v3 4/4] armv8/fsl-layerscape: enable dwc3 gadget driver support
Enables dwc3 gadget driver support on LS1043QDS platform. Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com> Reviewed-by: Lukasz Majewski <l.majew...@samsung.com> --- Changes in v3: - None Changes in v2: - None include/configs/ls1043aqds.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index af1f73d..8c99641 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -394,6 +394,21 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_USB_MAX_CONTROLLER_COUNT3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE + +#define CONFIG_USB_DWC3 +#define CONFIG_USB_DWC3_GADGET + +#define CONFIG_USB_GADGET +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor" +#define CONFIG_G_DNL_VENDOR_NUM 0x0471 +#define CONFIG_G_DNL_PRODUCT_NUM 0x1234 +#define CONFIG_USB_GADGET_DUALSPEED + +/* USB Gadget ums command */ +#define CONFIG_CMD_USB_MASS_STORAGE #endif /* -- 2.6.2.198.g614a2ac ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/4] armv8/fsl-layerscape: add dwc3 gadget driver support
Implements the dwc3 gadget driver support for LS1043
platform, and performs below operations:
1. Enables snooping support for DWC3 controller.
2. Enables cache coherency in LS1043 platform.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Reviewed-by: Lukasz Majewski <l.majew...@samsung.com>
---
Changes in v2:
- Moves DWC3 driver specific code to helper functions
- Calls helper functions in SoC specific implementation
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 93 ++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++
2 files changed, 99 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..cc07524 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -17,6 +17,10 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#include
#endif
+#include
+#include
+#include
+
DECLARE_GLOBAL_DATA_PTR;
@@ -318,9 +322,18 @@ void fsl_lsch2_early_init_f(void)
#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /* Make SEC and USB reads and writes snoopable */
+#if defined(CONFIG_LS1043A)
+ setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+SCFG_SNPCNFGCR_USB3WRSNP);
+#else
/* Make SEC reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP);
+#endif
/*
* Enable snoop requests and DVM message requests for
@@ -336,6 +349,86 @@ void fsl_lsch2_early_init_f(void)
}
#endif
+#ifdef CONFIG_USB_DWC3
+
+#if defined(CONFIG_LS1043A)
+static struct dwc3_device dwc3_device_data0 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+};
+
+static struct dwc3_device dwc3_device_data1 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 1,
+};
+
+static struct dwc3_device dwc3_device_data2 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+ dwc3_uboot_handle_interrupt(index);
+ return 0;
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ switch (init) {
+ case USB_INIT_DEVICE:
+ switch (index) {
+#if defined(CONFIG_LS1043A)
+ case 0:
+ dwc3_uboot_init(_device_data0);
+ break;
+ case 1:
+ dwc3_uboot_init(_device_data1);
+ break;
+ case 2:
+ dwc3_uboot_init(_device_data2);
+ break;
+#endif
+ default:
+ printf("Invalid Controller Index\n");
+ return -1;
+ }
+#if defined(CONFIG_LS1043A)
+ dwc3_core_incr_burst_enable(index, 0xf, 0xf);
+ dwc3_core_set_snooping(index, true);
+#endif
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ switch (init) {
+ case USB_INIT_DEVICE:
+#if defined(CONFIG_LS1043A)
+ dwc3_uboot_exit(index);
+#endif
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+#endif
+
+
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 57b99d4..13ba1a6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -328,6 +328,12 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SECRDSNP0x8000
#define SCFG_SNPCNFGCR_SECWRSNP0x4000
+#define SCFG_SNPCNFGCR_USB1RDSNP 0x0020
+#define SCFG_SNPCNFGCR_USB1WRSNP 0x0010
+#define SCFG_SNPCNFGCR_USB2RDSNP 0x8000
+#define SCFG_SNPCNFGCR_USB2WRSNP 0x0001
+#define SCFG_SNPCNFGCR_USB3RDSNP 0x2000
+#define SCFG_SNPCNFGCR_USB3WRSNP 0x4000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
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[U-Boot] [PATCH v2 2/4] usb: dwc3: Add helper functions to enable snooping and burst settings
Adds helper functions to enable snooping and outstanding burst beat
settings.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
Changes in v2:
- Removes SoC specific flags and added helper functions
drivers/usb/dwc3/core.c | 45 +
drivers/usb/dwc3/core.h | 7 +++
2 files changed, 52 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 85cc96a..0b3c596 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
#define DWC3_ALIGN_MASK(16 - 1)
+void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
+int breq_limit)
+{
+ struct dwc3 *dwc;
+ u32 reg;
+
+ list_for_each_entry(dwc, _list, list) {
+ if (dwc->index != index)
+ continue;
+
+ /*
+* Change burst beat and outstanding pipelined
+* transfers requests
+*/
+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+ reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
+ reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
+ break;
+ }
+}
+
+void dwc3_core_set_snooping(int index, bool snoop)
+{
+ struct dwc3 *dwc;
+ u32 reg;
+
+ list_for_each_entry(dwc, _list, list) {
+ if (dwc->index != index)
+ continue;
+
+ /* Enable/Disable snooping */
+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+ if (snoop)
+ reg = reg | DWC3_SNOOP_ENABLE;
+ else
+ reg = reg & ~DWC3_SNOOP_ENABLE;
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+ break;
+ }
+}
+
/**
* dwc3_uboot_init - dwc3 core uboot initialization code
* @dwc3_dev: struct dwc3_device containing initialization data
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 72d2fcd..455e7fa 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -593,6 +593,13 @@ struct dwc3_hwparams {
/* HWPARAMS7 */
#define DWC3_RAM1_DEPTH(n) ((n) & 0x)
+/* GSBUSCFG0 */
+#define DWC3_SNOOP_ENABLE (0x)
+#define DWC3_INCR_BTYPE_MASK (0xff)
+
+/* GSBUSCFG1 */
+#define DWC3_BREQ_LIMIT_MASK (0xf00)
+
struct dwc3_request {
struct usb_request request;
struct list_headlist;
--
2.6.2.198.g614a2ac
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[U-Boot] [PATCH v2 4/4] armv8/fsl-layerscape: enable dwc3 gadget driver support
Enables dwc3 gadget driver support on LS1043QDS platform. Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com> --- Changes in v2: - None include/configs/ls1043aqds.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index af1f73d..8c99641 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -394,6 +394,21 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_USB_MAX_CONTROLLER_COUNT3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE + +#define CONFIG_USB_DWC3 +#define CONFIG_USB_DWC3_GADGET + +#define CONFIG_USB_GADGET +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor" +#define CONFIG_G_DNL_VENDOR_NUM 0x0471 +#define CONFIG_G_DNL_PRODUCT_NUM 0x1234 +#define CONFIG_USB_GADGET_DUALSPEED + +/* USB Gadget ums command */ +#define CONFIG_CMD_USB_MASS_STORAGE #endif /* -- 2.6.2.198.g614a2ac ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] usb: ums: support multiple controllers using controller_index
From: Rajesh Bhagat <rajesh.bha...@nxp.com>
Adds a new field in fsg_common namely controller_index to support
multiple controllers usb gadget support.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
Changes for v2:
- Changes type of fsg_main_thread argument to unsigned int
cmd/usb_mass_storage.c | 2 +-
drivers/usb/gadget/f_mass_storage.c | 11 +--
include/usb_mass_storage.h | 2 +-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index b05913a..bf80d37 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
while (1) {
usb_gadget_handle_interrupts(controller_index);
- rc = fsg_main_thread(NULL);
+ rc = fsg_main_thread(controller_index);
if (rc) {
/* Check I/O error */
if (rc == -EIO)
diff --git a/drivers/usb/gadget/f_mass_storage.c
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..27ca5fe 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -362,6 +362,7 @@ struct fsg_common {
char inquiry_string[8 + 16 + 4 + 1];
struct kref ref;
+ unsigned int controller_index;
};
struct fsg_config {
@@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
k = 0;
}
- usb_gadget_handle_interrupts(0);
+ usb_gadget_handle_interrupts(common->controller_index);
}
common->thread_wakeup_needed = 0;
return rc;
@@ -2402,10 +2403,14 @@ static void handle_exception(struct fsg_common *common)
/*-*/
-int fsg_main_thread(void *common_)
+int fsg_main_thread(unsigned int controller_index)
{
int ret;
struct fsg_common *common = the_fsg_common;
+
+ /* update the controller_index */
+ common->controller_index = controller_index;
+
/* The main loop */
do {
if (exception_in_progress(common)) {
@@ -2476,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct
fsg_common *common,
common->ops = NULL;
common->private_data = NULL;
+ common->controller_index = 0;
common->gadget = gadget;
common->ep0 = gadget->ep0;
@@ -2770,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
fsg_common->ops = NULL;
fsg_common->private_data = NULL;
+ fsg_common->controller_index = 0;
the_fsg_common = fsg_common;
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 8229f62..f21cc7a 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -28,6 +28,6 @@ struct ums {
int fsg_init(struct ums *ums_devs, int count);
void fsg_cleanup(void);
-int fsg_main_thread(void *);
+int fsg_main_thread(unsigned int);
int fsg_add(struct usb_configuration *c);
#endif /* __USB_MASS_STORAGE_H__ */
--
2.6.2.198.g614a2ac
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[U-Boot] [PATCH v2 0/4] armv8/fsl-layerscape: add dwc3 gadget driver support
From: Rajesh Bhagat <rajesh.bha...@nxp.com> Adds support for dwc3 gadget driver for ARM v8 platform of layerscape series. Currently this patch has been tested for LS1043A Rajat Srivastava (3): usb: dwc3: Add helper functions to enable snooping and burst settings armv8/fsl-layerscape: add dwc3 gadget driver support armv8/fsl-layerscape: enable dwc3 gadget driver support Rajesh Bhagat (1): usb: ums: support multiple controllers using controller_index arch/arm/cpu/armv8/fsl-layerscape/soc.c| 93 ++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++ cmd/usb_mass_storage.c | 2 +- drivers/usb/dwc3/core.c| 45 +++ drivers/usb/dwc3/core.h| 7 ++ drivers/usb/gadget/f_mass_storage.c| 11 ++- include/configs/ls1043aqds.h | 15 include/usb_mass_storage.h | 2 +- 8 files changed, 177 insertions(+), 4 deletions(-) -- 2.6.2.198.g614a2ac ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] usb: ums: support multiple controllers using controller_index
From: Rajesh Bhagat <rajesh.bha...@nxp.com>
Adds a new field in fsg_common namely controller_index to support
multiple controllers usb gadget support.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
cmd/usb_mass_storage.c | 2 +-
drivers/usb/gadget/f_mass_storage.c | 10 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index b05913a..1c955f8 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
while (1) {
usb_gadget_handle_interrupts(controller_index);
- rc = fsg_main_thread(NULL);
+ rc = fsg_main_thread(_index);
if (rc) {
/* Check I/O error */
if (rc == -EIO)
diff --git a/drivers/usb/gadget/f_mass_storage.c
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..cc3e4af 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -362,6 +362,7 @@ struct fsg_common {
char inquiry_string[8 + 16 + 4 + 1];
struct kref ref;
+ unsigned int controller_index;
};
struct fsg_config {
@@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
k = 0;
}
- usb_gadget_handle_interrupts(0);
+ usb_gadget_handle_interrupts(common->controller_index);
}
common->thread_wakeup_needed = 0;
return rc;
@@ -2406,6 +2407,11 @@ int fsg_main_thread(void *common_)
{
int ret;
struct fsg_common *common = the_fsg_common;
+
+ /* update the controller_index */
+ if (common_)
+ common->controller_index = *(unsigned int *)common_;
+
/* The main loop */
do {
if (exception_in_progress(common)) {
@@ -2476,6 +2482,7 @@ static struct fsg_common *fsg_common_init(struct
fsg_common *common,
common->ops = NULL;
common->private_data = NULL;
+ common->controller_index = 0;
common->gadget = gadget;
common->ep0 = gadget->ep0;
@@ -2770,6 +2777,7 @@ int fsg_add(struct usb_configuration *c)
fsg_common->ops = NULL;
fsg_common->private_data = NULL;
+ fsg_common->controller_index = 0;
the_fsg_common = fsg_common;
--
1.9.1
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[U-Boot] [PATCH 2/3] armv8/fsl-layerscape: add dwc3 gadget driver support
From: Rajesh Bhagat <rajesh.bha...@nxp.com>
Implements the dwc3 gadget driver support for LS1043
platform, and performs below operations:
1. Enables snooping support for DWC3 controller.
2. Enables cache coherency in LS1043 platform.
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 87 +-
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++
.../include/asm/arch-fsl-layerscape/sys_proto.h| 11 +++
drivers/usb/dwc3/core.c| 12 +++
4 files changed, 114 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..84b973d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -17,6 +17,10 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#include
#endif
+#include
+#include
+#include
+
DECLARE_GLOBAL_DATA_PTR;
@@ -318,9 +322,12 @@ void fsl_lsch2_early_init_f(void)
#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
- /* Make SEC reads and writes snoopable */
+ /* Make SEC and USB reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-SCFG_SNPCNFGCR_SECWRSNP);
+SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+SCFG_SNPCNFGCR_USB3WRSNP);
/*
* Enable snoop requests and DVM message requests for
@@ -336,6 +343,82 @@ void fsl_lsch2_early_init_f(void)
}
#endif
+#ifdef CONFIG_USB_DWC3
+
+#if defined(CONFIG_LS1043A)
+static struct dwc3_device dwc3_device_data0 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+};
+
+static struct dwc3_device dwc3_device_data1 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 1,
+};
+
+static struct dwc3_device dwc3_device_data2 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+ dwc3_uboot_handle_interrupt(index);
+ return 0;
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ switch (init) {
+ case USB_INIT_DEVICE:
+ switch (index) {
+#if defined(CONFIG_LS1043A)
+ case 0:
+ dwc3_uboot_init(_device_data0);
+ break;
+
+ case 1:
+ dwc3_uboot_init(_device_data1);
+ break;
+ case 2:
+ dwc3_uboot_init(_device_data2);
+ break;
+#endif
+ default:
+ printf("Invalid Controller Index\n");
+ return -1;
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ switch (init) {
+ case USB_INIT_DEVICE:
+#if defined(CONFIG_LS1043A)
+ dwc3_uboot_exit(index);
+#endif
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+#endif
+
+
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 57b99d4..13ba1a6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -328,6 +328,12 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SECRDSNP0x8000
#define SCFG_SNPCNFGCR_SECWRSNP0x4000
+#define SCFG_SNPCNFGCR_USB1RDSNP 0x0020
+#define SCFG_SNPCNFGCR_USB1WRSNP 0x0010
+#define SCFG_SNPCNFGCR_USB2RDSNP 0x8000
+#define SCFG_SNPCNFGCR_USB2WRSNP 0x0001
+#define SCFG_SNPCNFGCR_USB3RDSNP 0x2000
+#define SCFG_SNPCNFGCR_USB3WRSNP 0x4000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
new file mode 100644
index 000..252c676
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-Licen
[U-Boot] [PATCH 0/3] armv8/fsl-layerscape: add dwc3 gadget driver support
Adds support for dwc3 gadget driver for ARM v8 platform of layerscape series. Currently this patch has been tested for LS1043A. Rajat Srivastava (3): usb: ums: support multiple controllers using controller_index armv8/fsl-layerscape: add dwc3 gadget driver support armv8/fsl-layerscape: enable dwc3 gadget driver support arch/arm/cpu/armv8/fsl-layerscape/soc.c| 87 +- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++ .../include/asm/arch-fsl-layerscape/sys_proto.h| 11 +++ cmd/usb_mass_storage.c | 2 +- drivers/usb/dwc3/core.c| 12 +++ drivers/usb/gadget/f_mass_storage.c| 10 ++- include/configs/ls1043aqds.h | 15 7 files changed, 139 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] armv8/fsl-layerscape: enable dwc3 gadget driver support
From: Rajesh Bhagat <rajesh.bha...@nxp.com> Enables dwc3 gadget driver support on LS1043QDS platform. Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com> --- include/configs/ls1043aqds.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index af1f73d..8c99641 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -394,6 +394,21 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_USB_MAX_CONTROLLER_COUNT3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE + +#define CONFIG_USB_DWC3 +#define CONFIG_USB_DWC3_GADGET + +#define CONFIG_USB_GADGET +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor" +#define CONFIG_G_DNL_VENDOR_NUM 0x0471 +#define CONFIG_G_DNL_PRODUCT_NUM 0x1234 +#define CONFIG_USB_GADGET_DUALSPEED + +/* USB Gadget ums command */ +#define CONFIG_CMD_USB_MASS_STORAGE #endif /* -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] usb: Add new command to regress USB devices
This patch adds a new 'usb regress' command, that can be used to
regress test a USB device. It performs the following operations:
1. starts the USB device
2. performs read/write operations
3. stops the USB device
4. verifies the contents of read/write operations
Sample Output:
=> usb regress 8100 8200 32m
regressing USB..
starting USB...
USB0: Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
stopping USB..
verifying data on addresses 0x8100 and 0x8200
Total of 65536 word(s) were the same
Signed-off-by: Rajat Srivastava <rajat.srivast...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
common/cmd_usb.c | 174 ++-
1 file changed, 173 insertions(+), 1 deletion(-)
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index a540b42..25fdeab 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_USB_STORAGE
static int usb_stor_curr_dev = -1; /* current device */
@@ -616,6 +617,167 @@ static int usb_device_info(void)
}
#endif
+static unsigned long calc_blockcount(char * const size)
+{
+ unsigned long value, multiplier;
+ int size_len = strlen(size);
+ char unit;
+
+ /* extract the unit of size passed */
+ unit = size[size_len - 1];
+ /* updating the source string to remove unit */
+ size[size_len - 1] = '\0';
+
+ value = simple_strtoul(size, NULL, 10);
+ if (value <= 0) {
+ printf("invalid size\n");
+ return 0;
+ }
+
+ if (unit == 'G' || unit == 'g') {
+ multiplier = 2 * 1024 * 1024;
+ } else if (unit == 'M' || unit == 'm') {
+ multiplier = 2 * 1024;
+ } else if (unit == 'K' || unit == 'k') {
+ multiplier = 2;
+ } else if (unit == 'B' || unit == 'b') {
+ if (value % 512 != 0) {
+ printf("size can only be multiples of 512 bytes\n");
+ return 0;
+ }
+ multiplier = 1;
+ value /= 512;
+ } else {
+ printf("syntax mismatch\n");
+ return 0;
+ }
+
+ return value * multiplier;
+}
+
+static int usb_read_write_verify(unsigned long w_addr, unsigned long r_addr,
+ unsigned long cnt)
+{
+ cmd_tbl_t *c;
+ char str[3][16];
+ char *ptr[4] = { "cmp", str[0], str[1], str[2] };
+
+ c = find_cmd("cmp");
+ if (!c) {
+ printf("compare command not found\n");
+ return -1;
+ }
+ printf("verifying data on addresses 0x%lx and 0x%lx\n", w_addr, r_addr);
+ sprintf(str[0], "%lx", w_addr);
+ sprintf(str[1], "%lx", r_addr);
+ sprintf(str[2], "%lx", cnt);
+ (c->cmd)(c, 0, 4, ptr);
+ return 0;
+}
+
+
+static int do_usb_regress(int argc, char * const argv[])
+{
+ unsigned long loopcount, iteration;
+ unsigned long w_addr, r_addr, cnt, n;
+ unsigned long blk = 0;
+ extern char usb_started;
+
+#ifdef CONFIG_USB_STORAGE
+ block_dev_desc_t *stor_dev;
+#endif
+
+ if (argc < 5 || argc > 6) {
+ printf("syntax mismatch\n");
+ return -1;
+ }
+
+ if (argc == 5)
+ loopcount = 1;
+ else
+ loopcount = simple_strtoul(argv[5], NULL, 10);
+
+ if (loopcount <= 0) {
+ printf("syntax mismatch\n");
+ return -1;
+ }
+
+ cnt = calc_blockcount(argv[4]);
+ if (cnt == 0)
+ return -1;
+
+ iteration = loopcount;
+ while (loopcount--) {
+ if (argc > 5)
+ printf("\niteration #%lu\n\n", iteration - loopcount);
+
+ /* start USB */
+ if (usb_started) {
+ printf("USB already started\n");
+ } else {
+ printf("starting USB...\n");
+ do_usb_start();
+ }
+ if (!usb_started) {
+ printf("USB did not start\n");
+ return -1;
+ }
+ if (usb_stor_curr_dev < 0) {
+ printf("no current device selected\nstopping USB...\n");
+ usb_stop();
+ return -1;
+ }
+
+#ifdef CONF
