Re: [PATCH v2] driver: spi: add bcm iproc qspi support.
On Wed, Oct 20, 2021 at 4:31 AM Roman Bacik wrote: > > From: Rayagonda Kokatanur > > IPROC qspi driver supports both BSPI and MSPI modes. > > Signed-off-by: Rayagonda Kokatanur > Signed-off-by: Bharat Gooty > Acked-by: Rayagonda Kokatanur > > Signed-off-by: Roman Bacik > --- > > Changes in v2: > - remove include spi-nor.h > - define and use named BITs for writing register values > - removed bspi_set_4byte_mode() method > > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/iproc_qspi.c | 712 +++ > drivers/spi/iproc_qspi.h | 20 ++ > 4 files changed, 739 insertions(+) > create mode 100644 drivers/spi/iproc_qspi.c > create mode 100644 drivers/spi/iproc_qspi.h > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index d07e9a28af82..e76fadef32dd 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -178,6 +178,12 @@ config ICH_SPI > access the SPI NOR flash on platforms embedding this Intel > ICH IP core. > > +config IPROC_QSPI > + bool "QSPI driver for BCM iProc QSPI Controller" > + help > + This selects the BCM iProc QSPI controller. > + This driver support spi flash single, quad and memory reads. > + > config KIRKWOOD_SPI > bool "Marvell Kirkwood SPI Driver" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index d2f24bccefd3..869763187062 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -33,6 +33,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o > obj-$(CONFIG_FSL_ESPI) += fsl_espi.o > obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o > obj-$(CONFIG_ICH_SPI) += ich.o > +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o > obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o > obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o > obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o > diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c > new file mode 100644 > index ..91afeb54fc57 > --- /dev/null > +++ b/drivers/spi/iproc_qspi.c > @@ -0,0 +1,712 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2020-2021 Broadcom > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "iproc_qspi.h" > + > +/* 175MHz */ > +#define QSPI_AXI_CLK 17500 > +#define QSPI_DEF_SCK_FREQ 5000 > +#define QSPI_WAIT_TIMEOUT_MS 200U > +#define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3)) > + > +/* Chip attributes */ > +#define SPBR_MIN 8U > +#define SPBR_MAX 255U > +#define NUM_CDRAM 16U > + > +#define CDRAM_PCS0 2 > +#define CDRAM_CONT BIT(7) > +#define CDRAM_BITS_EN BIT(6) > +#define CDRAM_QUAD_MODEBIT(8) > +#define CDRAM_RBIT_INPUT BIT(10) > +#define MSPI_SPE BIT(6) > +#define MSPI_CONT_AFTER_CMDBIT(7) > + > +/* Register fields */ > +#define MSPI_SPCR0_MSB_BITS_8 0x0020 > +#define BSPI_RAF_CONTROL_START_MASK0x0001 > +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x0001 > +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK0x0002 > +#define BSPI_BITS_PER_PHASE_ADDR_MARK 0x0001 > +#define BSPI_BITS_PER_CYCLE_DATA_SHIFT 0 > +#define BSPI_BITS_PER_CYCLE_ADDR_SHIFT 16 > +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT3 > +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT1 > +#define BSPI_STRAP_OVERRIDE_SHIFT 0 > + > +/* MSPI registers */ > +#define MSPI_SPCR0_LSB_REG 0x000 > +#define MSPI_SPCR0_MSB_REG 0x004 > +#define MSPI_SPCR1_LSB_REG 0x008 > +#define MSPI_SPCR1_MSB_REG 0x00c > +#define MSPI_NEWQP_REG 0x010 > +#define MSPI_ENDQP_REG 0x014 > +#define MSPI_SPCR2_REG 0x018 > +#define MSPI_STATUS_REG0x020 > +#define MSPI_CPTQP_REG 0x024 > +#define MSPI_TXRAM_REG 0x040 > +#define MSPI_RXRAM_REG 0x0c0 > +#define MSPI_CDRAM_REG 0x140 > +#define MSPI_WRITE_LOCK_REG0x180 > +#define MSPI_DISABLE_FLUSH_GEN_REG 0x184 > + > +/* BSPI registers */ &g
Re: [PATCH 1/1] Revert "arm64: Layerscape: Survive LPI one-way reset workaround"
On Mon, Sep 13, 2021 at 11:29 AM Priyanka Jain (OSS)
wrote:
>
>
>
> >-Original Message-
> >From: U-Boot On Behalf Of Z.Q. Hou
> >Sent: Friday, September 10, 2021 12:13 PM
> >To: Tom Rini ; u-boot@lists.denx.de;
> >rayagonda.kokata...@broadcom.com
> >Cc: Priyanka Jain
> >Subject: RE: [PATCH 1/1] Revert "arm64: Layerscape: Survive LPI one-way reset
> >workaround"
> >
> >+ author of gic_lpi_syscon driver
> >
> >Hi Rayagonda,
> >
> >Please add the binding for gic_lpi_syscon driver.
> >
> >Thanks,
> >Zhiqiang
> >
> >> -Original Message-
> >> From: Tom Rini
> >> Sent: 2021年8月26日 5:05
> >> To: u-boot@lists.denx.de
> >> Cc: Z.Q. Hou ; Priyanka Jain
> >>
> >> Subject: [PATCH 1/1] Revert "arm64: Layerscape: Survive LPI one-way
> >> reset workaround"
> >>
> >> Ad-hoc bindings that are not part of the upstream device tree /
> >> bindings are not allowed in-tree. Only bindings that are in-progress
> >> with upstream and then re-synced once agreed upon are.
> >>
> >> This reverts commit af288cb291da3abef6be0875527729296f7de7a0.
> >>
> >> Cc: Hou Zhiqiang
> >> Cc: Priyanka Jain
> >> Reported-by: Michael Walle
> >> Signed-off-by: Tom Rini
> >> ---
> >> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 +
> >> arch/arm/dts/fsl-ls1028a.dtsi | 6 --
> >> arch/arm/dts/fsl-ls1088a.dtsi | 6 --
> >> arch/arm/dts/fsl-ls2080a.dtsi | 6 --
> >> arch/arm/dts/fsl-lx2160a.dtsi | 6 --
> >> 5 files changed, 1 insertion(+), 40 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> index 42a096854629..12a64baf 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> @@ -43,22 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef
> >CONFIG_GIC_V3_ITS
> >> int ls_gic_rd_tables_init(void *blob) {
> >> -struct fdt_memory lpi_base;
> >> -fdt_addr_t addr;
> >> -fdt_size_t size;
> >> -int offset, ret;
> >> -
> >> -offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x8000");
> >> -addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset,
> >> "reg",
> >> - 0, , false);
> >> -
> >> -lpi_base.start = addr;
> >> -lpi_base.end = addr + size - 1;
> >> -ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", _base,
> >> NULL, false);
> >> -if (ret) {
> >> -debug("%s: failed to add reserved memory\n", __func__);
> >> -return ret;
> >> -}
> >> +int ret;
> >>
> >> ret = gic_lpi_tables_init();
> >> if (ret)
> >> diff --git a/arch/arm/dts/fsl-ls1028a.dtsi
> >> b/arch/arm/dts/fsl-ls1028a.dtsi index 50f9b527cde1..53b052ed3271
> >> 100644
> >> --- a/arch/arm/dts/fsl-ls1028a.dtsi
> >> +++ b/arch/arm/dts/fsl-ls1028a.dtsi
> >> @@ -44,12 +44,6 @@
> >> IRQ_TYPE_LEVEL_LOW)>;
> >> };
> >>
> >> -gic_lpi_base: syscon@0x8000 {
> >> -compatible = "gic-lpi-base";
> >> -reg = <0x0 0x8000 0x0 0x10>;
> >> -max-gic-redistributors = <2>;
> >> -};
> >> -
> >> timer {
> >> compatible = "arm,armv8-timer";
> >> interrupts = >> a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index
> >> 64caa600ad77..3a5a50fb8313 100644
> >> --- a/arch/arm/dts/fsl-ls1088a.dtsi
> >> +++ b/arch/arm/dts/fsl-ls1088a.dtsi
> >> @@ -27,12 +27,6 @@
> >> interrupts = <1 9 0x4>;
> >> };
> >>
> >> -gic_lpi_base: syscon@0x8000 {
> >> -compatible = "gic-lpi-base";
> >> -reg = <0x0 0x8000 0x0 0x10>;
> >> -max-gic-redistributors = <8>;
> >> -};
> >> -
> >> timer {
> >> compatible = "arm,armv8-timer";
> >> interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low
> >> */ diff
> >> --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
> >> index 7374d580e07e..278daeeb6eea 100644
> >> --- a/arch/arm/dts/fsl-ls2080a.dtsi
> >> +++ b/arch/arm/dts/fsl-ls2080a.dtsi
> >> @@ -27,12 +27,6 @@
> >> interrupts = <1 9 0x4>;
> >> };
> >>
> >> -gic_lpi_base: syscon@0x8000 {
> >> -compatible = "gic-lpi-base";
> >> -reg = <0x0 0x8000 0x0 0x10>;
> >> -max-gic-redistributors = <8>;
> >> -};
> >> -
> >> timer {
> >> compatible = "arm,armv8-timer";
> >> interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low
> >> */ diff
> >> --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
> >> index
> >> a6f0e9bc56be..3b5f0d119e76 100644
> >> --- a/arch/arm/dts/fsl-lx2160a.dtsi
> >> +++ b/arch/arm/dts/fsl-lx2160a.dtsi
> >> @@ -43,12 +43,6 @@
> >> interrupts = <1 9 0x4>;
> >> };
> >>
> >> -gic_lpi_base: syscon@0x8000 {
> >> -compatible = "gic-lpi-base";
> >> -
Re: [PATCH v1] driver: spi: add bcm iproc qspi support.
On Wed, Aug 25, 2021 at 6:55 PM Bharat Kumar Reddy Gooty wrote: > > From: Rayagonda Kokatanur > > IPROC qspi driver supports both BSPI and MSPI modes. > > Signed-off-by: Rayagonda Kokatanur > Signed-off-by: Bharat Gooty > --- > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/iproc_qspi.c | 736 +++ > drivers/spi/iproc_qspi.h | 18 + > 4 files changed, 761 insertions(+) > create mode 100644 drivers/spi/iproc_qspi.c > create mode 100644 drivers/spi/iproc_qspi.h > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index e12699bec7..3253d6badf 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -178,6 +178,12 @@ config ICH_SPI > access the SPI NOR flash on platforms embedding this Intel > ICH IP core. > > +config IPROC_QSPI > + bool "QSPI driver for BCM iProc QSPI Controller" > + help > + This selects the BCM iProc QSPI controller. > + This driver support spi flash single, quad and memory reads. > + > config KIRKWOOD_SPI > bool "Marvell Kirkwood SPI Driver" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index d2f24bccef..8697631870 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -33,6 +33,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o > obj-$(CONFIG_FSL_ESPI) += fsl_espi.o > obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o > obj-$(CONFIG_ICH_SPI) += ich.o > +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o > obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o > obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o > obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o > diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c > new file mode 100644 > index 00..89c6a56858 > --- /dev/null > +++ b/drivers/spi/iproc_qspi.c > @@ -0,0 +1,736 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2020-2021 Broadcom > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "iproc_qspi.h" > + > +/* 175MHz */ > +#define QSPI_AXI_CLK 17500 > +#define QSPI_DEF_SCK_FREQ 5000 > +#define QSPI_WAIT_TIMEOUT_MS 200U > +#define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3)) > + > +/* Chip attributes */ > +#define SPBR_MIN 8U > +#define SPBR_MAX 255U > +#define NUM_CDRAM 16U > + > +#define CDRAM_PCS0 2 > +#define CDRAM_CONT BIT(7) > +#define CDRAM_BITS_EN BIT(6) > +#define CDRAM_QUAD_MODEBIT(8) > +#define CDRAM_RBIT_INPUT BIT(10) > +#define MSPI_SPE BIT(6) > +#define MSPI_CONT_AFTER_CMDBIT(7) > + > +/* Register fields */ > +#define MSPI_SPCR0_MSB_BITS_8 0x0020 > +#define BSPI_RAF_CONTROL_START_MASK0x0001 > +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x0001 > +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK0x0002 > +#define BSPI_BITS_PER_PHASE_ADDR_MARK 0x0001 > +#define BSPI_BITS_PER_CYCLE_DATA_SHIFT 0 > +#define BSPI_BITS_PER_CYCLE_ADDR_SHIFT 16 > +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT3 > +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT1 > +#define BSPI_STRAP_OVERRIDE_SHIFT 0 > + > +/* MSPI registers */ > +#define MSPI_SPCR0_LSB_REG 0x000 > +#define MSPI_SPCR0_MSB_REG 0x004 > +#define MSPI_SPCR1_LSB_REG 0x008 > +#define MSPI_SPCR1_MSB_REG 0x00c > +#define MSPI_NEWQP_REG 0x010 > +#define MSPI_ENDQP_REG 0x014 > +#define MSPI_SPCR2_REG 0x018 > +#define MSPI_STATUS_REG0x020 > +#define MSPI_CPTQP_REG 0x024 > +#define MSPI_TXRAM_REG 0x040 > +#define MSPI_RXRAM_REG 0x0c0 > +#define MSPI_CDRAM_REG 0x140 > +#define MSPI_WRITE_LOCK_REG0x180 > +#define MSPI_DISABLE_FLUSH_GEN_REG 0x184 > + > +/* BSPI registers */ > +#define BSPI_REVISION_ID_REG 0x000 > +#define BSPI_SCRATCH_REG 0x004 > +#define BSPI_MAST_N_BOOT_CTRL_REG 0x008 > +#define BSPI_BUSY_STATUS_REG
Re: [PATCH v1 1/2] pinctrl: single: Parse gpio details from dt
On Tue, Aug 24, 2021 at 3:46 PM Bharat Kumar Reddy Gooty
wrote:
>
> From: Bharat Gooty
>
> Parse different gpio properties from dt as part of probe
> function. This detail is required to enable pinctrl pad
> later when gpio lines are requested.
>
> Signed-off-by: Rayagonda Kokatanur
> Signed-off-by: Bharat Gooty
> ---
> drivers/pinctrl/pinctrl-single.c | 52
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-single.c
> b/drivers/pinctrl/pinctrl-single.c
> index cf9ad3670f..0f96cd5870 100644
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -44,11 +45,27 @@ struct single_func {
> unsigned int *pins;
> };
>
> +/**
> + * struct single_gpiofunc_range - pin ranges with same mux value of gpio fun
> + * @offset: offset base of pins
> + * @npins: number pins with the same mux value of gpio function
> + * @gpiofunc: mux value of gpio function
> + * @node: list node
> + */
> +struct single_gpiofunc_range {
> + u32 offset;
> + u32 npins;
> + u32 gpiofunc;
> + struct list_head node;
> +};
> +
> /**
> * struct single_priv - private data
> * @bits_per_pin: number of bits per pin
> * @npins: number of selectable pins
> * @pin_name: temporary buffer to store the pin name
> + * @functions: list pin functions
> + * @gpiofuncs: list gpio functions
> */
> struct single_priv {
> #if (IS_ENABLED(CONFIG_SANDBOX))
> @@ -58,6 +75,7 @@ struct single_priv {
> unsigned int npins;
> char pin_name[PINNAME_SIZE];
> struct list_head functions;
> + struct list_head gpiofuncs;
> };
>
> /**
> @@ -454,6 +472,36 @@ static int single_get_pins_count(struct udevice *dev)
> return priv->npins;
> }
>
> +static int single_add_gpio_func(struct udevice *dev)
> +{
> + struct single_priv *priv = dev_get_priv(dev);
> + const char *propname = "pinctrl-single,gpio-range";
> + const char *cellname = "#pinctrl-single,gpio-range-cells";
> + struct single_gpiofunc_range *range;
> + struct ofnode_phandle_args gpiospec;
> + int ret, i;
> +
> + for (i = 0; ; i++) {
> + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev),
> propname,
> +cellname, 0, i,
> );
> + /* Do not treat it as error. Only treat it as end condition.
> */
> + if (ret) {
> + ret = 0;
> + break;
> + }
> + range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
> + if (!range) {
> + ret = -ENOMEM;
> + break;
> + }
> + range->offset = gpiospec.args[0];
> + range->npins = gpiospec.args[1];
> + range->gpiofunc = gpiospec.args[2];
> + list_add_tail(>node, >gpiofuncs);
> + }
> + return ret;
> +}
> +
> static int single_probe(struct udevice *dev)
> {
> struct single_pdata *pdata = dev_get_plat(dev);
> @@ -461,6 +509,7 @@ static int single_probe(struct udevice *dev)
> u32 size;
>
> INIT_LIST_HEAD(>functions);
> + INIT_LIST_HEAD(>gpiofuncs);
>
> size = pdata->offset + pdata->width / BITS_PER_BYTE;
> #if (CONFIG_IS_ENABLED(SANDBOX))
> @@ -483,6 +532,9 @@ static int single_probe(struct udevice *dev)
> priv->npins *= (pdata->width / priv->bits_per_pin);
> }
>
> + if (single_add_gpio_func(dev))
> + dev_dbg(dev, "gpio functions are not added\n");
> +
> dev_dbg(dev, "%d pins\n", priv->npins);
> return 0;
> }
> --
> 2.17.1
>
Acked-by: Rayagonda Kokatanur
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v1 2/2] pinctrl: single: Add request() api
On Tue, Aug 24, 2021 at 3:46 PM Bharat Kumar Reddy Gooty
wrote:
>
> From: Bharat Gooty
>
> Add pinctrl_ops->request api to configure pctrl
> pad register in gpio mode.
>
> Signed-off-by: Rayagonda Kokatanur
> Signed-off-by: Bharat Gooty
> ---
> drivers/pinctrl/pinctrl-single.c | 34
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-single.c
> b/drivers/pinctrl/pinctrl-single.c
> index 0f96cd5870..8fc07e3498 100644
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -250,6 +250,39 @@ static int single_get_pin_muxing(struct udevice *dev,
> unsigned int pin,
> return 0;
> }
>
> +static int single_request(struct udevice *dev, int pin, int flags)
> +{
> + struct single_priv *priv = dev_get_priv(dev);
> + struct single_pdata *pdata = dev_get_plat(dev);
> + struct single_gpiofunc_range *frange = NULL;
> + struct list_head *pos, *tmp;
> + phys_addr_t reg;
> + int mux_bytes = 0;
> + u32 data;
> +
> + /* If function mask is null, needn't enable it. */
> + if (!pdata->mask)
> + return -ENOTSUPP;
> +
> + list_for_each_safe(pos, tmp, >gpiofuncs) {
> + frange = list_entry(pos, struct single_gpiofunc_range, node);
> + if ((pin >= frange->offset + frange->npins) ||
> + pin < frange->offset)
> + continue;
> +
> + mux_bytes = pdata->width / BITS_PER_BYTE;
> + reg = pdata->base + pin * mux_bytes;
> +
> + data = single_read(dev, reg);
> + data &= ~pdata->mask;
> + data |= frange->gpiofunc;
> + single_write(dev, data, reg);
> + break;
> + }
> +
> + return 0;
> +}
> +
> static struct single_func *single_allocate_function(struct udevice *dev,
> unsigned int group_pins)
> {
> @@ -587,6 +620,7 @@ const struct pinctrl_ops single_pinctrl_ops = {
> .get_pin_name = single_get_pin_name,
> .set_state = single_set_state,
> .get_pin_muxing = single_get_pin_muxing,
> + .request = single_request,
> };
>
> static const struct udevice_id single_pinctrl_match[] = {
> --
> 2.17.1
>
Acked-by: Rayagonda Kokatanur
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v2 1/1] drivers: mmc: iproc_sdhci: enable HS200 mode
From: Bharat Gooty
Add tuning functionality which is needed for HS200 mode.
For HS200, program the correct needed 1.8 voltage
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
---
Changes from v1:
--Address review comments from Jaehoon Chung,
Add comment for udelay
Move #define to top
Remove udelay
drivers/mmc/iproc_sdhci.c | 92 +++
1 file changed, 83 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c
index 6e4f527e5d..11d86ad658 100644
--- a/drivers/mmc/iproc_sdhci.c
+++ b/drivers/mmc/iproc_sdhci.c
@@ -10,8 +10,11 @@
#include
#include
#include
+#include "mmc_private.h"
#include
+#define MAX_TUNING_LOOP40
+
DECLARE_GLOBAL_DATA_PTR;
struct sdhci_iproc_host {
@@ -140,17 +143,89 @@ static void sdhci_iproc_writeb(struct sdhci_host *host,
u8 val, int reg)
static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
{
- u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 ctrl;
+
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
- /* Reset UHS mode bits */
- ctrl &= ~SDHCI_CTRL_UHS_MASK;
+ sdhci_set_uhs_timing(host);
+ return 0;
+}
- if (host->mmc->ddr_mode)
- ctrl |= UHS_DDR50_BUS_SPEED;
+static void sdhci_start_tuning(struct sdhci_host *host)
+{
+ u32 ctrl;
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
- return 0;
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+}
+
+static void sdhci_end_tuning(struct sdhci_host *host)
+{
+ /* Enable only interrupts served by the SD controller */
+ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+SDHCI_INT_ENABLE);
+ /* Mask all sdhci interrupt sources */
+ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
+}
+
+static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct mmc_cmd cmd;
+ u32 ctrl;
+ u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+ char tuning_loop_counter = MAX_TUNING_LOOP;
+ int ret = 0;
+
+ sdhci_start_tuning(host);
+
+ cmd.cmdidx = opcode;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
+ blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
+
+ sdhci_writew(host, blocksize, SDHCI_BLOCK_SIZE);
+ sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ do {
+ mmc_send_cmd(mmc, , NULL);
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
+ /*
+* For tuning command, do not do busy loop. As tuning
+* is happening (CLK-DATA latching for setup/hold time
+* requirements), give time to complete
+*/
+ udelay(1);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ if (tuning_loop_counter-- == 0)
+ break;
+
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ if (tuning_loop_counter < 0 || (!(ctrl & SDHCI_CTRL_TUNED_CLK))) {
+ ctrl &= ~(SDHCI_CTRL_TUNED_CLK | SDHCI_CTRL_EXEC_TUNING);
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
+ printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode);
+ ret = -EIO;
+ }
+
+ sdhci_end_tuning(host);
+
+ return ret;
}
static struct sdhci_ops sdhci_platform_ops = {
@@ -163,6 +238,7 @@ static struct sdhci_ops sdhci_platform_ops = {
.write_b = sdhci_iproc_writeb,
#endif
.set_ios_post = sdhci_iproc_set_ios_post,
+ .platform_execute_tuning = sdhci_iproc_execute_tuning,
};
struct iproc_sdhci_plat {
@@ -190,9 +266,7 @@ static int iproc_sdhci_probe(struct udevice *dev)
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
- host->voltages = MMC_VDD_165_195 |
-MMC_VDD_32_33 | MMC_VDD_33_34;
- host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B;
+ host->quirks = SDHCI_QUIRK_BROKEN_R1B;
host->host_caps = MMC_MODE_DDR_52MHz;
host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
host->ops = _platform_ops;
--
2.17.1
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v1 1/1] drivers: mmc: iproc_sdhci: enable HS200 mode
On Wed, Feb 10, 2021 at 3:12 AM Jaehoon Chung wrote:
>
> Hi Rayagonda,
>
> On 2/9/21 1:34 PM, Rayagonda Kokatanur wrote:
> > From: Bharat Gooty
> >
> > Add tuning functionality which is needed for HS200 mode.
> > For HS200, program the correct needed 1.8 voltage
>
> I didn't test with this on target. But how did you use HS200 mode?
> In this patch, there is no set to HS200 mode. Is there any other patch.
It can be enabled from a config file (configs/bcm_ns3_defconfig) based
on requirement. Hence not added config file changes.
>
> >
> > Signed-off-by: Bharat Gooty
> > Signed-off-by: Rayagonda Kokatanur
> > ---
> > drivers/mmc/iproc_sdhci.c | 88 +++
> > 1 file changed, 79 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c
> > index f931e4b3c1..360ea01e21 100644
> > --- a/drivers/mmc/iproc_sdhci.c
> > +++ b/drivers/mmc/iproc_sdhci.c
> > @@ -9,6 +9,7 @@
> > #include
> > #include
> > #include
> > +#include "mmc_private.h"
> > #include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> > @@ -139,17 +140,87 @@ static void sdhci_iproc_writeb(struct sdhci_host
> > *host, u8 val, int reg)
> >
> > static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
> > {
> > - u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> > + struct mmc *mmc = (struct mmc *)host->mmc;
> > + u32 ctrl;
> >
> > - /* Reset UHS mode bits */
> > - ctrl &= ~SDHCI_CTRL_UHS_MASK;
> > + if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
> > + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> > + ctrl |= SDHCI_CTRL_VDD_180;
> > + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
> > + }
> >
> > - if (host->mmc->ddr_mode)
> > - ctrl |= UHS_DDR50_BUS_SPEED;
>
> Doesn't need to remove this? If someone want to use DDR mode, doesn't need to
> set this bit?
Supported speeds can come from the capabilities registers
>
> > + sdhci_set_uhs_timing(host);
> > + return 0;
> > +}
> >
> > +static void sdhci_start_tuning(struct sdhci_host *host)
> > +{
> > + u32 ctrl;
> > +
> > + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> > + ctrl |= SDHCI_CTRL_EXEC_TUNING;
> > sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
> >
> > - return 0;
> > + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
> > + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
> > +}
> > +
> > +static void sdhci_end_tuning(struct sdhci_host *host)
> > +{
> > + /* Enable only interrupts served by the SD controller */
> > + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
> > + SDHCI_INT_ENABLE);
> > + /* Mask all sdhci interrupt sources */
> > + sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
> > +}
> > +
> > +static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode)
> > +{
> > +#define MAX_TUNING_LOOP 40
>
> Move to top.
Thank you, will fix it.
>
> > + struct mmc_cmd cmd;
> > + u32 ctrl;
> > + u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
> > + struct sdhci_host *host = dev_get_priv(mmc->dev);
> > + char tuning_loop_counter = MAX_TUNING_LOOP;
> > + int ret = 0;
> > +
> > + sdhci_start_tuning(host);
> > +
> > + cmd.cmdidx = opcode;
> > + cmd.resp_type = MMC_RSP_R1;
> > + cmd.cmdarg = 0;
> > +
> > + if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
>
> According to spec, HS200 can be used with 4/8 bit buswidth.
Iproc SDHCI controller supports HS200 in 8bit mode only.
>
>
> > + blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
> > +
> > + sdhci_writew(host, blocksize, SDHCI_BLOCK_SIZE);
> > + sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
> > + sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
> > +
> > + do {
> > + mmc_send_cmd(mmc, , NULL);
> > + if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
> > + udelay(1);
>
> Add the comment to add udelay(1).
Sure, thank you.
>
> > +
> > + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> > +
> > + if (tuning_loop_counter-- == 0)
> > + break;
> > +
&
[PATCH v1 1/1] drivers: mmc: iproc_sdhci: enable HS200 mode
From: Bharat Gooty
Add tuning functionality which is needed for HS200 mode.
For HS200, program the correct needed 1.8 voltage
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
---
drivers/mmc/iproc_sdhci.c | 88 +++
1 file changed, 79 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c
index f931e4b3c1..360ea01e21 100644
--- a/drivers/mmc/iproc_sdhci.c
+++ b/drivers/mmc/iproc_sdhci.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include "mmc_private.h"
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -139,17 +140,87 @@ static void sdhci_iproc_writeb(struct sdhci_host *host,
u8 val, int reg)
static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
{
- u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 ctrl;
- /* Reset UHS mode bits */
- ctrl &= ~SDHCI_CTRL_UHS_MASK;
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
- if (host->mmc->ddr_mode)
- ctrl |= UHS_DDR50_BUS_SPEED;
+ sdhci_set_uhs_timing(host);
+ return 0;
+}
+static void sdhci_start_tuning(struct sdhci_host *host)
+{
+ u32 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
- return 0;
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+}
+
+static void sdhci_end_tuning(struct sdhci_host *host)
+{
+ /* Enable only interrupts served by the SD controller */
+ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+SDHCI_INT_ENABLE);
+ /* Mask all sdhci interrupt sources */
+ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
+}
+
+static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+#define MAX_TUNING_LOOP40
+ struct mmc_cmd cmd;
+ u32 ctrl;
+ u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+ char tuning_loop_counter = MAX_TUNING_LOOP;
+ int ret = 0;
+
+ sdhci_start_tuning(host);
+
+ cmd.cmdidx = opcode;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
+ blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
+
+ sdhci_writew(host, blocksize, SDHCI_BLOCK_SIZE);
+ sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ do {
+ mmc_send_cmd(mmc, , NULL);
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
+ udelay(1);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ if (tuning_loop_counter-- == 0)
+ break;
+
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ if (tuning_loop_counter < 0 || (!(ctrl & SDHCI_CTRL_TUNED_CLK))) {
+ ctrl &= ~(SDHCI_CTRL_TUNED_CLK | SDHCI_CTRL_EXEC_TUNING);
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
+ printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode);
+ ret = -EIO;
+ }
+
+ udelay(1);
+
+ sdhci_end_tuning(host);
+
+ return ret;
}
static struct sdhci_ops sdhci_platform_ops = {
@@ -162,6 +233,7 @@ static struct sdhci_ops sdhci_platform_ops = {
.write_b = sdhci_iproc_writeb,
#endif
.set_ios_post = sdhci_iproc_set_ios_post,
+ .platform_execute_tuning = sdhci_iproc_execute_tuning,
};
struct iproc_sdhci_plat {
@@ -189,9 +261,7 @@ static int iproc_sdhci_probe(struct udevice *dev)
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
- host->voltages = MMC_VDD_165_195 |
-MMC_VDD_32_33 | MMC_VDD_33_34;
- host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B;
+ host->quirks = SDHCI_QUIRK_BROKEN_R1B;
host->host_caps = MMC_MODE_DDR_52MHz;
host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
host->ops = _platform_ops;
--
2.17.1
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v5 1/1] cmd: gpt: add eMMC and GPT support
From: Corneliu Doban
Add eMMC and GPT support.
- GPT partition list and command to create the GPT added to u-boot
environment
- eMMC boot commands added to u-boot environment
- new gpt commands (enumarate and setenv) that are used by broadcom
update scripts and boot commands
- eMMC specific u-boot configurations with environment saved in eMMC
and GPT support
Signed-off-by: Corneliu Doban
Signed-off-by: Rayagonda Kokatanur
---
Changes from v4:
-Address review comments from Thiru,
Use env_set_hex() instead of env_set_ulong() in two place.
Changes from v3:
-Address review comments from Simon Glass,
Return -ve number instead of 1 upon failure,
Use shorter variable name,
Modified code to avoid buffer overflow,
Use if (!strcmp(...)) instead of if (strcmp(...) == 0)
Changes from v2:
-Address review comments from Simon Glass,
Check for return value of part_driver_get_count(),
Don't check return value of part_driver_get(),
Rewrite part_driver_get() and rename to part_driver_get_first(),
Use env_set_ulong() whereever applicable,
-Address review comments from Michael Nazzareno Trimarchi,
Add new function to set all env vriables,
Changes from v1:
-Address review comments from Simon Glass,
Correct function comments,
Check for return value,
Add helper function in part.h
cmd/gpt.c | 161 +
include/part.h | 29 +
2 files changed, 190 insertions(+)
diff --git a/cmd/gpt.c b/cmd/gpt.c
index df759416c8..56986ad554 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -621,6 +622,152 @@ static int gpt_verify(struct blk_desc *blk_dev_desc,
const char *str_part)
return ret;
}
+/**
+ * gpt_enumerate() - Enumerate partition names into environment variable.
+ *
+ * Enumerate partition names. Partition names are stored in gpt_partition_list
+ * environment variable. Each partition name is delimited by space.
+ *
+ * @desc: block device descriptor
+ *
+ * @Return: '0' on success and -ve error on failure
+ */
+static int gpt_enumerate(struct blk_desc *desc)
+{
+ struct part_driver *first_drv, *part_drv;
+ int str_len = 0, tmp_len;
+ char part_list[2048];
+ int n_drvs;
+ char *ptr;
+
+ part_list[0] = 0;
+ n_drvs = part_driver_get_count();
+ if (!n_drvs) {
+ printf("Failed to get partition driver count\n");
+ return -ENOENT;
+ }
+
+ first_drv = part_driver_get_first();
+ for (part_drv = first_drv; part_drv != first_drv + n_drvs; part_drv++) {
+ struct disk_partition pinfo;
+ int ret;
+ int i;
+
+ for (i = 1; i < part_drv->max_entries; i++) {
+ ret = part_drv->get_info(desc, i, );
+ if (ret) {
+ /* no more entries in table */
+ break;
+ }
+
+ ptr = _list[str_len];
+ tmp_len = strlen((const char *)pinfo.name);
+ str_len += tmp_len;
+ /* +1 for space */
+ str_len++;
+ if (str_len > sizeof(part_list)) {
+ printf("Error insufficient memory\n");
+ return -ENOMEM;
+ }
+ strcpy(ptr, (const char *)pinfo.name);
+ /* One byte for space(" ") delimiter */
+ ptr[tmp_len] = ' ';
+ }
+ }
+ if (*part_list)
+ part_list[strlen(part_list) - 1] = 0;
+ debug("setenv gpt_partition_list %s\n", part_list);
+
+ return env_set("gpt_partition_list", part_list);
+}
+
+/**
+ * gpt_setenv_part_variables() - setup partition environmental variables
+ *
+ * Setup the gpt_partition_name, gpt_partition_entry, gpt_partition_addr
+ * and gpt_partition_size environment variables.
+ *
+ * @pinfo: pointer to disk partition
+ * @i: partition entry
+ *
+ * @Return: '0' on success and -ENOENT on failure
+ */
+static int gpt_setenv_part_variables(struct disk_partition *pinfo, int i)
+{
+ int ret;
+
+ ret = env_set_hex("gpt_partition_addr", pinfo->start);
+ if (ret)
+ goto fail;
+
+ ret = env_set_hex("gpt_partition_size", pinfo->size);
+ if (ret)
+ goto fail;
+
+ ret = env_set_ulong("gpt_partition_entry", i);
+ if (ret)
+ goto fail;
+
+ ret = env_set("gpt_partition_name", (const char *)pinfo->name);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ return -ENOENT;
+}
+
+/**
+ * gpt_setenv() - Dynamically setup environment variables.
+ *
+ * Dynamically
Re: Quick question?
On Fri, Sep 25, 2020 at 9:29 PM jchludzinski wrote: > On 2020-09-25 07:13, Rayagonda Kokatanur wrote: > > On Fri, Sep 25, 2020, 4:32 PM jchludzinski > > wrote: > > > >> On 2020-09-24 17:36, jchludzinski wrote: > >>> I'm trying to bring up an RTOS (vxworks) using u-boot and have had > >>> some "partial" success: > >>> > >>> If I use the 2014 u-boot that comes with Quartus 18.1 (a tarball > >> in > >>> the download), vxworks successfully boots. > >>> > >>> If I clone the github repo > >>> (https://github.com/altera-opensource/u-boot-socfpga.git) and > >> build > >>> u-boot from that (2020), vxworks fails to boot. What appears to be > >>> happening is an (fpga?) watchdog timer goes off and a HW reset is > >>> called. Then of course, u-boot reboots. > >>> > >>> Any thoughts? Why would this occur with the newer u-boot and not > >> with > >>> the older u-boot? > >>> > >>> ---John > >> > >> I don't see the "Watchdog enabled" message in the output from the > >> older > >> u-boot. > > > > watchdog service starts by default in latest uboot and it's set to > > 60s. > > > > If you wait for more than 60s at uboot prompt or you os loading takes > > long time then watchdog resets. > > > > Define CONFIG_WATCHDOG , this will takes care of resting watchdog. > > > > Thanks, > > Rayagonda > > > >> > Thanks for the suggestion but this reset occurs while vxworks is in the > process of booting up. > > Could u-boot set a HW watchdog timer before handing control over to > vxworks and, while vxworks is booting, the timer goes off and calls > reset? > If wdt is not initialized by vxworks then I think uboot wdt will be running and it will reset. Did you try defining CONFIG_WATCHDOG in uboot ? Best regards, Rayagonda smime.p7s Description: S/MIME Cryptographic Signature
Re: Quick question?
On Fri, Sep 25, 2020, 4:32 PM jchludzinski wrote: > On 2020-09-24 17:36, jchludzinski wrote: > > I'm trying to bring up an RTOS (vxworks) using u-boot and have had > > some "partial" success: > > > > If I use the 2014 u-boot that comes with Quartus 18.1 (a tarball in > > the download), vxworks successfully boots. > > > > If I clone the github repo > > (https://github.com/altera-opensource/u-boot-socfpga.git) and build > > u-boot from that (2020), vxworks fails to boot. What appears to be > > happening is an (fpga?) watchdog timer goes off and a HW reset is > > called. Then of course, u-boot reboots. > > > > Any thoughts? Why would this occur with the newer u-boot and not with > > the older u-boot? > > > > ---John > > I don't see the "Watchdog enabled" message in the output from the older > u-boot. > watchdog service starts by default in latest uboot and it's set to 60s. If you wait for more than 60s at uboot prompt or you os loading takes long time then watchdog resets. Define CONFIG_WATCHDOG , this will takes care of resting watchdog. Thanks, Rayagonda > smime.p7s Description: S/MIME Cryptographic Signature
Re: u-boot leaves watchdog enabled by default
On Tue, Sep 15, 2020 at 12:56 PM Michael Walle wrote:
>
> Hi Stefan,
>
> it appears that since commit 06985289d45 ("watchdog: Implement generic
> watchdog_reset() version") - by default - the first watchdog is started
> unconditionally if CONFIG_WDT is set but never stopped before booting
> the operating system.
>
> Shouldn't it also be stopped uncondionally? What's worse is that on one
> board/arch the watchdog is stopped in arch_preboot_os() which is never
> called in the bootefi case. So even if I'd do a workaround and stop it
> manually in my board code, I couldn't do that consistently for
> bootm/bootefi.
>
> Or am I missing something here?
Define CONFIG_WATCHDOG.
This takes care of resetting wdt.
Best regards,
Rayagonda
>
> The SoC on my board has a built-in watchdog and I've noticed this
> behaviour when I was trying to install debian via its stock installer
> which doesn't have any driver support for it.
>
> -michael
Re: [PATCH] arm: gic-v3-its: Add irq UCLASS_DRIVER
Hi Stefan,
On Thu, Sep 10, 2020, 1:16 PM Stefan Roese wrote:
> On 10.09.20 07:58, Rayagonda Kokatanur wrote:
> > Hi Stefan,
> >
> > On Thu, Sep 10, 2020 at 10:53 AM Stefan Roese wrote:
> >>
> >> Hi Rayagonda,
> >>
> >> On 09.09.20 19:15, Rayagonda Kokatanur wrote:
> >>> Hi Stefan,
> >>>
> >>> On Wed, Sep 9, 2020 at 1:57 PM Stefan Roese wrote:
> >>>>
> >>>> On 09.09.20 10:14, Priyanka Jain wrote:
> >>>>> This is required to fix
> >>>>> "Error binding driver 'gic-v3': -96"
> >>>>> on lx2160a platforms.
> >>>>>
> >>>>> Signed-off-by: Priyanka Jain
> >>>>> ---
> >>>>> arch/arm/lib/gic-v3-its.c | 5 +
> >>>>> 1 file changed, 5 insertions(+)
> >>>>>
> >>>>> diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
> >>>>> index a1657e3853..6c6b7c430c 100644
> >>>>> --- a/arch/arm/lib/gic-v3-its.c
> >>>>> +++ b/arch/arm/lib/gic-v3-its.c
> >>>>> @@ -208,3 +208,8 @@ U_BOOT_DRIVER(gic_lpi_syscon) = {
> >>>>> .id = UCLASS_SYSCON,
> >>>>> .of_match = gic_lpi_syscon_ids,
> >>>>> };
> >>>>> +
> >>>>> +UCLASS_DRIVER(irq) = {
> >>>>> + .id = UCLASS_IRQ,
> >>>>> + .name = "irq",
> >>>>> +};
> >>>>
> >>>> I tested this on LX2160 and get this error when booting into Linux:
> >>>>
> >>>> Loading Device Tree to 9fff6000, end 9f3e
> ... OK
> >>>> gic_v3_its_get_gic_lpi_addr: failed to get gic-lpi-base syscon device
> >>>>
> >>>> Starting kernel ...
> >>>>
> >>>> [0.00] Booting Linux on physical CPU 0x00 [0x410fd083]
> >>>>
> >>>> I did not look closely yet. Any idea whats going wrong here?
> >>>
> >>> I added the following patch to use UCLASS_SYSCON to get gic lpi
> details.
> >>>
> >>> commit id - 2ae7adc659f7fca9ea65df4318e5bca2b8274310
> >>>
> >>> because the above commit is failing, hence we need this patch.
> >>> When I tested this I didn't face any issue hence didn't push the above
> change.
> >>> In my case it was failing only in the lower uboot version without this
> patch.
> >>
> >> What's the "lower uboot version"?
> >
> > U-Boot 2020.01 version.
> >
> >>
> >> In any case, it's failing now on the lx2160, since no SYSCON device is
> >> found:
> >>
> >> $ git grep "gic-lpi-base"
> >> arch/arm/lib/gic-v3-its.c: { .compatible = "gic-lpi-base" },
> >> arch/arm/lib/gic-v3-its.c: .name = "gic-lpi-base",
> >>
> >> So no device is providing this compatible in the dts anywhere. Or am I
> >> missing something?
> >
> > If you apply this patch it will work.
>
> This patch is already applied.
>
> > Please let me know if anything more is required or if this patch is
> > the not right way to address the issue.
>
> Again, its not working, as no device is providing "gic-lpi-base" AFICT.
>
Please add dt node which defines "gic-lpi-base" and other details.
@Priyanka Jain - can you please provide dt node
added for your platform lx2160a.
For ex -
gic_lpi_base: syscon@0x8ad7 {
compatible = "gic-lpi-base";
reg = <0x0 0x8ad7 0x0 0x9>;
max-gic-redistributors = <8>;
};
scr {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x6100 0x0500>;
gic: interrupt-controller@2c0 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
reg = <0x02c0 0x01>, /* GICD */
<0x02e0 0x60>; /* GICR */
regmap = <_lpi_base>;
gic_its: gic-its@63c2 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x02c2 0x1>;
};
};
};
Best regards,
Rayagonda
> Thanks,
> Stefan
>
Re: [PATCH] arm: gic-v3-its: Add irq UCLASS_DRIVER
Hi Stefan,
On Thu, Sep 10, 2020 at 10:53 AM Stefan Roese wrote:
>
> Hi Rayagonda,
>
> On 09.09.20 19:15, Rayagonda Kokatanur wrote:
> > Hi Stefan,
> >
> > On Wed, Sep 9, 2020 at 1:57 PM Stefan Roese wrote:
> >>
> >> On 09.09.20 10:14, Priyanka Jain wrote:
> >>> This is required to fix
> >>> "Error binding driver 'gic-v3': -96"
> >>> on lx2160a platforms.
> >>>
> >>> Signed-off-by: Priyanka Jain
> >>> ---
> >>>arch/arm/lib/gic-v3-its.c | 5 +
> >>>1 file changed, 5 insertions(+)
> >>>
> >>> diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
> >>> index a1657e3853..6c6b7c430c 100644
> >>> --- a/arch/arm/lib/gic-v3-its.c
> >>> +++ b/arch/arm/lib/gic-v3-its.c
> >>> @@ -208,3 +208,8 @@ U_BOOT_DRIVER(gic_lpi_syscon) = {
> >>>.id = UCLASS_SYSCON,
> >>>.of_match = gic_lpi_syscon_ids,
> >>>};
> >>> +
> >>> +UCLASS_DRIVER(irq) = {
> >>> + .id = UCLASS_IRQ,
> >>> + .name = "irq",
> >>> +};
> >>
> >> I tested this on LX2160 and get this error when booting into Linux:
> >>
> >> Loading Device Tree to 9fff6000, end 9f3e ... OK
> >> gic_v3_its_get_gic_lpi_addr: failed to get gic-lpi-base syscon device
> >>
> >> Starting kernel ...
> >>
> >> [0.00] Booting Linux on physical CPU 0x00 [0x410fd083]
> >>
> >> I did not look closely yet. Any idea whats going wrong here?
> >
> > I added the following patch to use UCLASS_SYSCON to get gic lpi details.
> >
> > commit id - 2ae7adc659f7fca9ea65df4318e5bca2b8274310
> >
> > because the above commit is failing, hence we need this patch.
> > When I tested this I didn't face any issue hence didn't push the above
> > change.
> > In my case it was failing only in the lower uboot version without this
> > patch.
>
> What's the "lower uboot version"?
U-Boot 2020.01 version.
>
> In any case, it's failing now on the lx2160, since no SYSCON device is
> found:
>
> $ git grep "gic-lpi-base"
> arch/arm/lib/gic-v3-its.c: { .compatible = "gic-lpi-base" },
> arch/arm/lib/gic-v3-its.c: .name = "gic-lpi-base",
>
> So no device is providing this compatible in the dts anywhere. Or am I
> missing something?
If you apply this patch it will work.
Please let me know if anything more is required or if this patch is
the not right way to address the issue.
Thank,
Rayagonda
>
> Thanks,
> Stefan
Re: [PATCH] arm: gic-v3-its: Add irq UCLASS_DRIVER
Hi Stefan,
On Wed, Sep 9, 2020 at 1:57 PM Stefan Roese wrote:
>
> On 09.09.20 10:14, Priyanka Jain wrote:
> > This is required to fix
> > "Error binding driver 'gic-v3': -96"
> > on lx2160a platforms.
> >
> > Signed-off-by: Priyanka Jain
> > ---
> > arch/arm/lib/gic-v3-its.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
> > index a1657e3853..6c6b7c430c 100644
> > --- a/arch/arm/lib/gic-v3-its.c
> > +++ b/arch/arm/lib/gic-v3-its.c
> > @@ -208,3 +208,8 @@ U_BOOT_DRIVER(gic_lpi_syscon) = {
> > .id = UCLASS_SYSCON,
> > .of_match = gic_lpi_syscon_ids,
> > };
> > +
> > +UCLASS_DRIVER(irq) = {
> > + .id = UCLASS_IRQ,
> > + .name = "irq",
> > +};
>
> I tested this on LX2160 and get this error when booting into Linux:
>
> Loading Device Tree to 9fff6000, end 9f3e ... OK
> gic_v3_its_get_gic_lpi_addr: failed to get gic-lpi-base syscon device
>
> Starting kernel ...
>
> [0.00] Booting Linux on physical CPU 0x00 [0x410fd083]
>
> I did not look closely yet. Any idea whats going wrong here?
I added the following patch to use UCLASS_SYSCON to get gic lpi details.
commit id - 2ae7adc659f7fca9ea65df4318e5bca2b8274310
because the above commit is failing, hence we need this patch.
When I tested this I didn't face any issue hence didn't push the above change.
In my case it was failing only in the lower uboot version without this patch.
Best regards,
Rayagonda
>
> Thanks,
> Stefan
Re: [PATCH v4 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
Hi Stefan,
On Thu, Aug 27, 2020 at 5:01 PM Stefan Roese wrote:
>
> Hi Rayagonda,
>
> On 26.07.20 19:07, Rayagonda Kokatanur wrote:
> > Use device tree and UCLASS_IRQ driver to get following
> > Generic Interrupt Controller (GIC) details,
> >
> > -GIC Distributor interface (GICD) base address and
> > -GIC Redistributors (GICR) base address.
> >
> > Signed-off-by: Rayagonda Kokatanur
> > Reviewed-by: Simon Glass
>
> How is this supposed to work on an ARM platform? I'm currently testing
> TOT on an NXP LX2160 platform and it fails with this bootup message:
>
> Error binding driver 'gic-v3': -96
> Some drivers failed to bind
>
> Debugging revealed that UCLASS_IRQ is missing for this platform. The
> driver "irq-uclass.c" is only selectable for X86 & SANDBOX:
>
> config IRQ
> bool "Intel Interrupt controller"
> depends on X86 || SANDBOX
> help
> This enables support for Intel interrupt controllers, including
> ITSS.
> Some devices have extra features, such as Apollo Lake. The
> device has its own uclass since there are several operations
> involved.
>
> This Kconfig help is also not correct any more, as the UCLASS_IRQ
> driver is not Intel specific (any more).
>
> FWICT, it would be best to make CONFIG_IRQ selectable for all platforms
> and select it in the "config GIC_V3_ITS" definition, similar to how it
> done with REGMAP & SYSCON. And change the "config IRQ" help text above.
>
> What do you think?
Sorry I missed your mail.
I am okay with your approach.
Also adding the following code at the end of
"arch/arm/lib/gic-v3-its.c" file, will solve the issue.
I found that this piece of code is not required for the latest uboot
hence I didn't add this as part of my patch.
UCLASS_DRIVER(irq) = {
.id = UCLASS_IRQ,
.name = "irq",
};
Best regards,
Rayagonda
>
> Thanks,
> Stefan
>
> > ---
> > Changes from v3:
> > -Address review comments from Simon,
> >Correct the data type of variables
> >
> > Changes from v1:
> > -Address review comments from Tom Rini,
> >Fix build warning messages.
> >
> > arch/arm/lib/gic-v3-its.c | 73 +++
> > 1 file changed, 66 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
> > index 90f37a123c..5f88643245 100644
> > --- a/arch/arm/lib/gic-v3-its.c
> > +++ b/arch/arm/lib/gic-v3-its.c
> > @@ -3,6 +3,7 @@
> >* Copyright 2019 Broadcom.
> >*/
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -15,6 +16,48 @@ static u32 lpi_id_bits;
> > #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
> > #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
> >
> > +/*
> > + * gic_v3_its_priv - gic details
> > + *
> > + * @gicd_base: gicd base address
> > + * @gicr_base: gicr base address
> > + */
> > +struct gic_v3_its_priv {
> > + ulong gicd_base;
> > + ulong gicr_base;
> > +};
> > +
> > +static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
> > +{
> > + struct udevice *dev;
> > + fdt_addr_t addr;
> > + int ret;
> > +
> > + ret = uclass_get_device_by_driver(UCLASS_IRQ,
> > + DM_GET_DRIVER(arm_gic_v3_its),
> > );
> > + if (ret) {
> > + pr_err("%s: failed to get %s irq device\n", __func__,
> > +DM_GET_DRIVER(arm_gic_v3_its)->name);
> > + return ret;
> > + }
> > +
> > + addr = dev_read_addr_index(dev, 0);
> > + if (addr == FDT_ADDR_T_NONE) {
> > + pr_err("%s: failed to get GICD address\n", __func__);
> > + return -EINVAL;
> > + }
> > + priv->gicd_base = addr;
> > +
> > + addr = dev_read_addr_index(dev, 1);
> > + if (addr == FDT_ADDR_T_NONE) {
> > + pr_err("%s: failed to get GICR address\n", __func__);
> > + return -EINVAL;
> > + }
> > + priv->gicr_base = addr;
> > +
> > + return 0;
> > +}
> > +
> > /*
> >* Program the GIC LPI configuration tables for all
> >* the re-distributors and enable the LPI table
> > @@ -23,15 +66,18 @@ static u32 lpi_id_bits;
> >*/
> > int gic_lpi_tables_init(u64 base, u32 num_redist)
> > {
&g
Re: Change in gic_lpi_tables_init() function
Hi Priyanka,
On Mon, Sep 7, 2020 at 2:26 PM Priyanka Jain wrote:
> Hello Rayagonda,
>
>
>
> With today top of upstream u-boot tree, I am still getting the error in
> booting lx216ardb
>
>
>
> U-Boot 2020.10-rc3-00086-ge5df264e7a (Sep 07 2020 - 14:13:57 +0530)
>
>
>
> “Error binding driver 'gic-v3': -96
>
> Some drivers failed to bind
>
> initcall sequence fbdcf368 failed at call 8201b5e4
> (err=-96)
>
> ### ERROR ### Please RESET the board ###
>
>
>
> But if apply the changes suggested by you, it is booting fine. Can you
> please help to send the pull-request for this soon , so that proper fixes
> are integrated in u-boot code before U-boot v2020.10 release.
>
It was working for me long back without this patch.
Could you please send this patch as you can reproduce it and test it.
Please let me know.
Best regards,
Rayagonda
>
>
> Thanks
>
> Priyanka
>
>
>
> *From:* Rayagonda Kokatanur
> *Sent:* Friday, September 4, 2020 10:50 PM
> *To:* Priyanka Jain
> *Cc:* Z.q. Hou ; Wasim Khan ;
> Bharat Gooty ; Manish Tomar <
> manish.to...@nxp.com>; Xiaobo Xie ; Jiafei Pan <
> jiafei@nxp.com>; Meenakshi Aggarwal
> *Subject:* Re: Change in gic_lpi_tables_init() function
>
>
>
> Hi Priyanka,
>
>
>
> Please add the following code at the end of "arch/arm/lib/gic-v3-its.c"
> file,
> This is not required for the latest uboot hence its not part of the patch.
>
> UCLASS_DRIVER(irq) = {
> .id = UCLASS_IRQ,
> .name = "irq",
> };
>
>
>
> Best regards,
>
> Rayagonda
>
>
>
>
>
> On Fri, Sep 4, 2020 at 9:38 PM Priyanka Jain
> wrote:
>
> Hello Rayagonda,
>
>
>
> I am getting below error with top of tree upstream on lx2160ardb. Any
> pointer here.
>
>
>
> U-Boot 2020.10-rc3-00082-g9bfb567e5f (Sep 04 2020 - 21:27:29 +0530)
>
>
>
> SoC: LX2160ACE Rev2.0 (0x87360020)
>
> Clock Configuration:
>
>CPU0(A72):1900 MHz CPU1(A72):1900 MHz CPU2(A72):1900 MHz
>
>CPU3(A72):1900 MHz CPU4(A72):1900 MHz CPU5(A72):1900 MHz
>
>CPU6(A72):1900 MHz CPU7(A72):1900 MHz CPU8(A72):1900 MHz
>
>CPU9(A72):1900 MHz CPU10(A72):1900 MHz CPU11(A72):1900 MHz
>
>CPU12(A72):1900 MHz CPU13(A72):1900 MHz CPU14(A72):1900 MHz
>
>CPU15(A72):1900 MHz
>
>Bus: 600 MHz DDR: 2600 MT/s
>
> Reset Configuration Word (RCW):
>
>: 4c6b6b30 204c004c
>
>0010: 0c01
>
>0020: 02e001a0 2580 0096
>
>0030:
>
>0040:
>
>0050:
>
>0060: 00027000
>
>0070: 08b30010 00150020
>
> Model: NXP Layerscape LX2160ARDB Board
>
> Board: LX2160ACE Rev2.0-RDB, Board version: B, boot from FlexSPI DEV#1
>
> FPGA: v5.0
>
> SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz
>
> SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
>
> SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
>
> VID: Core voltage after adjustment is at 851 mV
>
> DRAM: 31.9 GiB
>
> DDR31.9 GiB (DDR4, 64-bit, CL=19, ECC on)
>
>DDR Controller Interleaving Mode: 256B
>
>DDR Chip-Select Interleaving Mode: CS0+CS1
>
> Error binding driver 'gic-v3': -96
>
> Some drivers failed to bind
>
> initcall sequence fbdcf368 failed at call 8201b5e4
> (err=-96)
>
> ### ERROR ### Please RESET the board ###
>
>
>
> Regards
>
> Priyanka
>
>
[PATCH v2 1/1] board: ns3: check bnxt chimp handshake status
Chimp is a core in Broadcom netxtream controller (bnxt).
Add support to check bnxt's chimp component status.
Signed-off-by: Rayagonda Kokatanur
---
Changes from V1:
-Address review comments from Simon,
Add comment about chimp failure.
board/broadcom/bcmns3/ns3.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 0357cd0e32..10ae344a06 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/* Default reset-level = 3 and strap-val = 0 */
#define L3_RESET 30
@@ -210,8 +211,24 @@ void reset_cpu(ulong level)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *fdt, struct bd_info *bd)
{
+ u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
+
gic_lpi_tables_init();
+ /*
+* Check for chimp handshake status.
+* Zero timeout value will actually fall to default timeout.
+*
+* System boot is independent of chimp handshake.
+* chimp handshake failure is not a catastrophic error.
+* Hence continue booting if chimp handshake fails.
+*/
+ chimp_handshake_status_optee(0, _hs);
+ if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
+ printf("ChiMP handshake successful\n");
+ else
+ printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
+
return mem_info_parse_fixup(fdt);
}
#endif /* CONFIG_OF_BOARD_SETUP */
--
2.17.1
Re: [PATCH v1 1/1] board: ns3: check bnxt chimp handshake status
Hi Simon,
On Sat, Aug 22, 2020 at 8:39 PM Simon Glass wrote:
>
> Hi Rayagonda,
>
> On Thu, 20 Aug 2020 at 11:42, Rayagonda Kokatanur
> wrote:
> >
> > Chimp is a core in Broadcom netxtream controller (bnxt).
> > Add support to check bnxt's chimp component status.
> >
> > Signed-off-by: Rayagonda Kokatanur
> > ---
> > board/broadcom/bcmns3/ns3.c | 13 +
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
> > index 0357cd0e32..8540c99286 100644
> > --- a/board/broadcom/bcmns3/ns3.c
> > +++ b/board/broadcom/bcmns3/ns3.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > /* Default reset-level = 3 and strap-val = 0 */
> > #define L3_RESET 30
> > @@ -210,8 +211,20 @@ void reset_cpu(ulong level)
> > #ifdef CONFIG_OF_BOARD_SETUP
> > int ft_board_setup(void *fdt, struct bd_info *bd)
> > {
> > + u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
> > +
> > gic_lpi_tables_init();
> >
> > + /*
> > +* Check for chimp handshake status.
> > +* Zero timeout value will actually fall to default timeout.
> > +*/
> > + chimp_handshake_status_optee(0, _hs);
> > + if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
> > + printf("ChiMP handshake successful\n");
> > + else
> > + printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
>
> Where is this error handled? Don't you need to return the error from
> this function?
System boot is independent of chimp hand shake.
Chimp/bnxt handshake failure is not a catastrophic error.
We just want to warn the user that the chimp handshake has failed.
Best regards,
Rayagonda
>
> > +
> > return mem_info_parse_fixup(fdt);
> > }
> > #endif /* CONFIG_OF_BOARD_SETUP */
> > --
> > 2.17.1
> >
>
> Regards,
> Simon
[PATCH v1 1/1] board: ns3: check bnxt chimp handshake status
Chimp is a core in Broadcom netxtream controller (bnxt).
Add support to check bnxt's chimp component status.
Signed-off-by: Rayagonda Kokatanur
---
board/broadcom/bcmns3/ns3.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 0357cd0e32..8540c99286 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/* Default reset-level = 3 and strap-val = 0 */
#define L3_RESET 30
@@ -210,8 +211,20 @@ void reset_cpu(ulong level)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *fdt, struct bd_info *bd)
{
+ u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
+
gic_lpi_tables_init();
+ /*
+* Check for chimp handshake status.
+* Zero timeout value will actually fall to default timeout.
+*/
+ chimp_handshake_status_optee(0, _hs);
+ if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
+ printf("ChiMP handshake successful\n");
+ else
+ printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
+
return mem_info_parse_fixup(fdt);
}
#endif /* CONFIG_OF_BOARD_SETUP */
--
2.17.1
Re: [PATCH v1 1/3] common: ns3: add error logging support
Hi Tom, On Sat, Aug 15, 2020 at 1:22 AM Tom Rini wrote: > > On Sun, May 17, 2020 at 02:02:55PM +0530, Rayagonda Kokatanur wrote: > > > From: Sheetal Tigadoli > > > > Add error logging support in uboot for ns3 platform. > > > > We log the bootup msgs from all bootstages(BL2, BL31, BL33, and Linux) > > on to DDR. When a watchdog is triggered from any of the bootstages, > > CRMU copies these logs to QSPI error logging space. > > > > Later when doing the post-mortem analysis, we parse the QSPI error > > log space. > > > > Signed-off-by: Sheetal Tigadoli > > Signed-off-by: Rayagonda Kokatanur > > This, and the series that starts with "cmd: bcm: add nitro boot command" > seem to conflict. Can you please resubmit any further outstanding > patches? Thanks! Rebased the patch and sent a v2 patch. Thanks, Rayagonda > > -- > Tom
[PATCH v2 5/5] MAINTAINERS: update maintainers file for new files
Update MAINTAINERS file for new files. Signed-off-by: Rayagonda Kokatanur --- MAINTAINERS | 4 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 17ac45587b..2b00674d65 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1005,6 +1005,10 @@ F: arch/arm/dts/ns3-board.dts F: arch/arm/dts/ns3.dtsi F: arch/arm/cpu/armv8/bcmns3 F: arch/arm/include/asm/arch-bcmns3/ +F: cmd/broadcom/Makefile +F: cmd/broadcom/chimp_boot.c +F: cmd/broadcom/nitro_image_load.c +F: cmd/broadcom/chimp_handshake.c TDA19988 HDMI ENCODER M: Liviu Dudau -- 2.17.1
[PATCH v2 3/5] cmd: broadcom: add command for chimp handshake
From: Bharat Kumar Reddy Gooty
Add command for chimp handshake.
Handshake is used to know chimp is loaded and booted successfully.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from V1:
-Address review comments from Simon,
Rearrange header files.
Remove use of typedef.
Command description correction.
cmd/broadcom/Makefile | 1 +
cmd/broadcom/chimp_handshake.c | 33 +
include/broadcom/chimp.h | 6 ++
3 files changed, 40 insertions(+)
create mode 100644 cmd/broadcom/chimp_handshake.c
diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile
index 6cdece1a3a..62268d98d0 100644
--- a/cmd/broadcom/Makefile
+++ b/cmd/broadcom/Makefile
@@ -3,3 +3,4 @@
obj-y += chimp_boot.o
obj-y += nitro_image_load.o
+obj-y += chimp_handshake.o
diff --git a/cmd/broadcom/chimp_handshake.c b/cmd/broadcom/chimp_handshake.c
new file mode 100644
index 00..a90a73a6d7
--- /dev/null
+++ b/cmd/broadcom/chimp_handshake.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom
+ */
+
+#include
+#include
+#include
+
+/* This command should be called after loading the nitro binaries */
+static int do_chimp_hs(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret = CMD_RET_USAGE;
+ u32 hstatus;
+
+ /* Returns 1, if handshake call is success */
+ if (chimp_handshake_status_optee(0, ))
+ ret = CMD_RET_SUCCESS;
+
+ if (hstatus == CHIMP_HANDSHAKE_SUCCESS)
+ printf("ChiMP Handshake successful\n");
+ else
+ printf("ERROR: ChiMP Handshake status 0x%x\n", hstatus);
+
+ return ret;
+}
+
+U_BOOT_CMD
+ (chimp_hs, 1, 1, do_chimp_hs,
+"Verify the Chimp handshake",
+"chimp_hs\n"
+);
diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h
index 73bb1c21e9..738f73eefd 100644
--- a/include/broadcom/chimp.h
+++ b/include/broadcom/chimp.h
@@ -15,6 +15,12 @@
*/
#define BCM_CHIMP_RUNNIG_GOOD 0x8000
+enum {
+ CHIMP_HANDSHAKE_SUCCESS = 0,
+ CHIMP_HANDSHAKE_WAIT_ERROR,
+ CHIMP_HANDSHAKE_WAIT_TIMEOUT,
+};
+
/**
* chimp_fastboot_optee() - api to load bnxt firmware
*
--
2.17.1
[PATCH v2 4/5] board: ns3: kconfig: extend board kconfig with specific commands
From: Vladimir Olovyannikov Extend Kconfig for the board with board-specific commands selection. Signed-off-by: Vladimir Olovyannikov Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- board/broadcom/bcmns3/Kconfig | 7 +++ cmd/Makefile | 2 ++ 2 files changed, 9 insertions(+) diff --git a/board/broadcom/bcmns3/Kconfig b/board/broadcom/bcmns3/Kconfig index 8ce21f980d..cb73f98eae 100644 --- a/board/broadcom/bcmns3/Kconfig +++ b/board/broadcom/bcmns3/Kconfig @@ -12,4 +12,11 @@ config SYS_SOC config SYS_CONFIG_NAME default "bcm_ns3" +config CMD_BCM_EXT_UTILS + bool "Enable Broadcom-specific U-Boot commands" + default y + help + Enable Broadcom specific U-Boot commands such as error log setup + command or any other commands specific to NS3 platform. + endif diff --git a/cmd/Makefile b/cmd/Makefile index 3a9c9747c9..c7a08ed109 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -197,6 +197,8 @@ obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o # core command obj-y += nvedit.o +obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/ + obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/ filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";") -- 2.17.1
[PATCH v2 2/5] cmd: broadcom: add cmd to update bnxt image env variables
From: Vikas Gupta
Add command to update the environmental variables which
are used to read the data from QSPI offsets and load
the binaries to bnxt.
Signed-off-by: Vikas Gupta
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from V1:
-Address review comments from Simon,
Rearrange header files.
Use lower case hex.
Rename struct name from nitro_img_header to img_header.
Drop unnecessary type cast.
Check returun value for env_set_hex().
cmd/broadcom/Makefile | 1 +
cmd/broadcom/nitro_image_load.c | 125
2 files changed, 126 insertions(+)
create mode 100644 cmd/broadcom/nitro_image_load.c
diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile
index 22ccf2f334..6cdece1a3a 100644
--- a/cmd/broadcom/Makefile
+++ b/cmd/broadcom/Makefile
@@ -2,3 +2,4 @@
# Copyright 2020 Broadcom
obj-y += chimp_boot.o
+obj-y += nitro_image_load.o
diff --git a/cmd/broadcom/nitro_image_load.c b/cmd/broadcom/nitro_image_load.c
new file mode 100644
index 00..4a36b300c4
--- /dev/null
+++ b/cmd/broadcom/nitro_image_load.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom
+ */
+
+#include
+#include
+
+#define FW_IMAGE_SIG 0xff123456
+#define CFG_IMAGE_SIG 0xcf54321a
+
+/*
+ * structure for bin file
+ * signature: fw itb file
+ * size: fw itb file
+ * signature: NS3 config file
+ * size: NS3 config file
+ * Data: fw itb file
+ *
+ *
+ * Data: NS3 config file
+ *
+ *
+ */
+
+static struct img_header {
+ u32 bin_sig;
+ u32 bin_size;
+ u32 cfg1_sig;
+ u32 cfg1_size;
+} *img_header;
+
+static int env_set_val(const char *varname, ulong val)
+{
+ int ret;
+
+ ret = env_set_hex(varname, val);
+ if (ret)
+ pr_err("Failed to %s env var\n", varname);
+
+ return ret;
+}
+
+static int do_spi_images_addr(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ uintptr_t images_load_addr;
+ uintptr_t spi_load_addr;
+ u32 len;
+ u32 spi_data_offset = sizeof(struct img_header);
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ /* convert command parameter to fastboot address (base 16), i.e. hex */
+ images_load_addr = simple_strtoul(argv[1], NULL, 16);
+ if (!images_load_addr) {
+ pr_err("Invalid load address\n");
+ return CMD_RET_USAGE;
+ }
+
+ spi_load_addr = simple_strtoul(argv[2], NULL, 16);
+ if (!spi_load_addr) {
+ pr_err("Invalid spi load address\n");
+ return CMD_RET_USAGE;
+ }
+
+ img_header = (struct img_header *)images_load_addr;
+
+ if (img_header->bin_sig != FW_IMAGE_SIG) {
+ pr_err("Invalid Nitro bin file\n");
+ goto error;
+ }
+
+ if (env_set_val("spi_nitro_fw_itb_start_addr", 0))
+ goto error;
+
+ if (env_set_val("spi_nitro_fw_itb_len", 0))
+ goto error;
+
+ if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr", 0))
+ goto error;
+
+ if (env_set_val("spi_nitro_fw_ns3_cfg_len", 0))
+ goto error;
+
+ len = img_header->bin_size;
+
+ if (env_set_val("spi_nitro_fw_itb_start_addr",
+ (spi_load_addr + spi_data_offset)))
+ goto error;
+
+ if (env_set_val("spi_nitro_fw_itb_len", img_header->bin_size))
+ goto error;
+
+ spi_data_offset += len;
+
+ if (img_header->cfg1_sig == CFG_IMAGE_SIG) {
+ len = img_header->cfg1_size;
+
+ if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr",
+ (spi_load_addr + spi_data_offset)))
+ goto error;
+
+ if (env_set_val("spi_nitro_fw_ns3_cfg_len", len))
+ goto error;
+
+ spi_data_offset += len;
+ }
+
+ /* disable secure boot */
+ if (env_set_val("nitro_fastboot_secure", 0))
+ goto error;
+
+ return CMD_RET_SUCCESS;
+
+error:
+ return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD
+ (spi_nitro_images_addr, 3, 1, do_spi_images_addr,
+"Load the bnxt bin header and sets envs ",
+"spi_nitro_images_addr \n"
+);
--
2.17.1
[PATCH v2 1/5] cmd: broadcom: add bnxt boot command
From: Trac Hoang
Chimp is a core in Broadcom netxtream controller (bnxt).
Add command to load binary to chimp and boot bnxt.
Signed-off-by: Trac Hoang
Signed-off-by: Rayagonda Kokatanur
---
Changes from V1:
-Address review comments from Simon,
Update commit message.
Rearrange header files.
Add comments to macros.
cmd/broadcom/Makefile | 4
cmd/broadcom/chimp_boot.c | 37 +
include/broadcom/chimp.h | 6 ++
3 files changed, 47 insertions(+)
create mode 100644 cmd/broadcom/Makefile
create mode 100644 cmd/broadcom/chimp_boot.c
diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile
new file mode 100644
index 00..22ccf2f334
--- /dev/null
+++ b/cmd/broadcom/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2020 Broadcom
+
+obj-y += chimp_boot.o
diff --git a/cmd/broadcom/chimp_boot.c b/cmd/broadcom/chimp_boot.c
new file mode 100644
index 00..16f2b612c4
--- /dev/null
+++ b/cmd/broadcom/chimp_boot.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom
+ */
+
+#include
+#include
+#include
+
+static int do_chimp_fastboot_secure(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u32 health = 0;
+
+ if (chimp_health_status_optee()) {
+ pr_err("Chimp health command fail\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (health == BCM_CHIMP_RUNNIG_GOOD) {
+ printf("skip fastboot...\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ if (chimp_fastboot_optee()) {
+ pr_err("Failed to load secure ChiMP image\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD
+ (chimp_ld_secure, 1, 0, do_chimp_fastboot_secure,
+"Invoke chimp fw load via optee",
+"chimp_ld_secure\n"
+);
diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h
index 7f64152913..73bb1c21e9 100644
--- a/include/broadcom/chimp.h
+++ b/include/broadcom/chimp.h
@@ -9,6 +9,12 @@
#include
+/*
+ * Chimp binary has health status like initialization complete,
+ * crash or running fine
+ */
+#define BCM_CHIMP_RUNNIG_GOOD 0x8000
+
/**
* chimp_fastboot_optee() - api to load bnxt firmware
*
--
2.17.1
[PATCH v2 0/5] add custome commands for broadcom NS3 soc
This patch set adds commands specific to broadcom NS3 soc. Changes from V1: -Address review comments from Simon, Update commit message. Rearrange header files. Add comments to macros. Use lower case hex. Rename struct name from nitro_img_header to img_header. Drop unnecessary type cast. Check returun value for env_set_hex(). Remove use of typedef. Command description correction. Bharat Kumar Reddy Gooty (1): cmd: broadcom: add command for chimp handshake Rayagonda Kokatanur (1): MAINTAINERS: update maintainers file for new files Trac Hoang (1): cmd: broadcom: add bnxt boot command Vikas Gupta (1): cmd: broadcom: add cmd to update bnxt image env variables Vladimir Olovyannikov (1): board: ns3: kconfig: extend board kconfig with specific commands MAINTAINERS | 4 + board/broadcom/bcmns3/Kconfig | 7 ++ cmd/Makefile| 2 + cmd/broadcom/Makefile | 6 ++ cmd/broadcom/chimp_boot.c | 37 ++ cmd/broadcom/chimp_handshake.c | 33 + cmd/broadcom/nitro_image_load.c | 125 include/broadcom/chimp.h| 12 +++ 8 files changed, 226 insertions(+) create mode 100644 cmd/broadcom/Makefile create mode 100644 cmd/broadcom/chimp_boot.c create mode 100644 cmd/broadcom/chimp_handshake.c create mode 100644 cmd/broadcom/nitro_image_load.c -- 2.17.1
Re: [PATCH v3 1/1] phy: add support for stingray PAXB PHY controller
Hi Tom, On Sat, Jun 27, 2020 at 1:31 AM Tom Rini wrote: > > On Thu, Jun 25, 2020 at 10:57:09PM +0530, Rayagonda Kokatanur wrote: > > Hi Tom, > > > > > > On Sun, Apr 12, 2020 at 8:46 PM Rayagonda Kokatanur > > wrote: > > > > > > On Thu, Apr 9, 2020 at 7:11 PM Tom Rini wrote: > > > > > > > > On Thu, Apr 02, 2020 at 04:08:12PM +0530, Rayagonda Kokatanur wrote: > > > > > > > > > From: Srinath Mannam > > > > > > > > > > Add support for stingray PAXB PHY controller driver. > > > > > This driver supports maximum 8 PAXB phys using pipemux data. > > > > > > > > > > Signed-off-by: Srinath Mannam > > > > > Signed-off-by: Rayagonda Kokatanur > > > > > Reviewed-by: Stefan Roese > > > > > --- > > > > > Changes from v2: > > > > > -Address review comments from Stefan Roese, > > > > > Rearrange the include files. > > > > > Remove dm/device.h as its included part of dm.h. > > > > > > > > > > Changes from v1: > > > > > -Address review comments from Stefan Roese, > > > > > Use GENMASK() instead of hard code value. > > > > > Remove unwanted struct declaration. > > > > > Get pr_err() into single line. > > > > > > > > > > drivers/phy/Kconfig | 7 ++ > > > > > drivers/phy/Makefile | 1 + > > > > > drivers/phy/phy-bcm-sr-pcie.c | 177 > > > > > ++ > > > > > > > > The patch itself is fine but I think shows another problem. Can you > > > > please add a patch that lists something relevant in the top-level > > > > MAINTAINERS file and list this and all of the other drivers, etc, that > > > > wouldn't just be listed in the board MAINATINERS file? Thanks! > > > > I have a plan to update the top level MAINTAINER file with all new > > driver and board files in a separate patch. > > Hope this is fine, please let me know. > > OK, thanks. I'll be picking up more patches again soon for -next. Could you please pick this patch. If any further review comments, please let me know. Best regards, Rayagonda > > -- > Tom
[PATCH v4 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
Use device tree and UCLASS_IRQ driver to get following
Generic Interrupt Controller (GIC) details,
-GIC Distributor interface (GICD) base address and
-GIC Redistributors (GICR) base address.
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v3:
-Address review comments from Simon,
Correct the data type of variables
Changes from v1:
-Address review comments from Tom Rini,
Fix build warning messages.
arch/arm/lib/gic-v3-its.c | 73 +++
1 file changed, 66 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 90f37a123c..5f88643245 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -15,6 +16,48 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/*
+ * gic_v3_its_priv - gic details
+ *
+ * @gicd_base: gicd base address
+ * @gicr_base: gicr base address
+ */
+struct gic_v3_its_priv {
+ ulong gicd_base;
+ ulong gicr_base;
+};
+
+static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_IRQ,
+ DM_GET_DRIVER(arm_gic_v3_its), );
+ if (ret) {
+ pr_err("%s: failed to get %s irq device\n", __func__,
+ DM_GET_DRIVER(arm_gic_v3_its)->name);
+ return ret;
+ }
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICD address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicd_base = addr;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICR address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicr_base = addr;
+
+ return 0;
+}
+
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
@@ -23,15 +66,18 @@ static u32 lpi_id_bits;
*/
int gic_lpi_tables_init(u64 base, u32 num_redist)
{
+ struct gic_v3_its_priv priv;
u32 gicd_typer;
u64 val;
u64 tmp;
int i;
u64 redist_lpi_base;
- u64 pend_base = GICR_BASE + GICR_PENDBASER;
+ u64 pend_base;
- gicd_typer = readl(GICD_BASE + GICD_TYPER);
+ if (gic_v3_its_get_gic_addr())
+ return -EINVAL;
+ gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
pr_err("GIC implementation does not support LPI's\n");
@@ -46,7 +92,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
- if ((readl((uintptr_t)(GICR_BASE + offset))) &
+ if ((readl((uintptr_t)(priv.gicr_base + offset))) &
GICR_CTLR_ENABLE_LPIS) {
pr_err("Re-Distributor %d LPI is already enabled\n",
i);
@@ -64,19 +110,21 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
- writeq(val, (GICR_BASE + GICR_PROPBASER));
- tmp = readl(GICR_BASE + GICR_PROPBASER);
+ writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
+ tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_NC;
- writeq(val, (GICR_BASE + GICR_PROPBASER));
+ writeq(val,
+ (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
}
}
redist_lpi_base = base + LPI_PROPBASE_SZ;
+ pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
@@ -94,9 +142,20 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
}
/* Enable LPI for the redistributor */
- writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+ writel(GICR_CTLR_ENABLE_LPIS,
+ (uintptr_t)(
[PATCH v4 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.
Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v3:
-Address review comments from Simon,
Correct the data type of variables
Changes from v2:
-Address review comments from Tom Rini,
Fix build errors messages.
arch/arm/Kconfig| 2 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 +--
arch/arm/include/asm/gic-v3.h | 4 +-
arch/arm/lib/gic-v3-its.c | 63 ++---
4 files changed, 61 insertions(+), 36 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e16fe03887..f88229d092 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,8 @@ endif
config GIC_V3_ITS
bool "ARM GICV3 ITS"
+ select REGMAP
+ select SYSCON
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ad7ea05935..135fe4a462 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -41,37 +41,11 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_GIC_V3_ITS
-#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
-#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
-#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
- PROPTABLE_MAX_SZ, SZ_1M)
-static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
-{
- u32 phandle;
- int err;
- struct fdt_memory gic_rd_tables;
-
- gic_rd_tables.start = base;
- gic_rd_tables.end = base + size - 1;
- err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", _rd_tables,
-);
- if (err < 0)
- debug("%s: failed to add reserved memory: %d\n", __func__, err);
-
- return err;
-}
-
int ls_gic_rd_tables_init(void *blob)
{
- u64 gic_lpi_base;
int ret;
- gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
- ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
- if (ret)
- return ret;
-
- ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+ ret = gic_lpi_tables_init();
if (ret)
debug("%s: failed to init gic-lpi-tables\n", __func__);
diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
index 5131fabec4..35efec78c3 100644
--- a/arch/arm/include/asm/gic-v3.h
+++ b/arch/arm/include/asm/gic-v3.h
@@ -127,9 +127,9 @@
#define GIC_REDISTRIBUTOR_OFFSET 0x2
#ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(u64 base, u32 max_redist);
+int gic_lpi_tables_init(void);
#else
-int gic_lpi_tables_init(u64 base, u32 max_redist)
+int gic_lpi_tables_init(void)
{
return 0;
}
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 5f88643245..a1657e3853 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -4,6 +4,8 @@
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -16,15 +18,22 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/* Number of GIC re-distributors */
+#define MAX_GIC_REDISTRIBUTORS 8
+
/*
* gic_v3_its_priv - gic details
*
* @gicd_base: gicd base address
* @gicr_base: gicr base address
+ * @lpi_base: gic lpi base address
+ * @num_redist: number of gic re-distributors
*/
struct gic_v3_its_priv {
ulong gicd_base;
ulong gicr_base;
+ ulong lpi_base;
+ u32 num_redist;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
@@ -58,13 +67,39 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv
*priv)
return 0;
}
+static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
+{
+ struct regmap *regmap;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+ DM_GET_DRIVER(gic_lpi_syscon), );
+ if (ret) {
+ pr_err("%s: failed to get %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return ret;
+ }
+
+ regmap = syscon_get_regmap(dev);
+ if (!regmap) {
+ pr_err("%s: failed to regmap for %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return -ENODEV;
+ }
+
[PATCH v4 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get gic details like GICD, GICR base address, max number of redistributors and git lpi address. Changes from v3: -Address review comments from Simon, Correct the data type of variables Changes from v2: -Address review comments from Tom Rini, Fix build errors messages. Changes from v1: -Address review comments from Tom Rini, Fix build warning messages. Rayagonda Kokatanur (2): arch: arm: use dt and UCLASS_IRQ to get gic details arch: arm: use dt and UCLASS_SYSCON to get gic lpi details arch/arm/Kconfig| 2 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 + arch/arm/include/asm/gic-v3.h | 4 +- arch/arm/lib/gic-v3-its.c | 136 +--- 4 files changed, 127 insertions(+), 43 deletions(-) -- 2.17.1
[PATCH v4 1/1] cmd: gpt: add eMMC and GPT support
From: Corneliu Doban
Add eMMC and GPT support.
- GPT partition list and command to create the GPT added to u-boot
environment
- eMMC boot commands added to u-boot environment
- new gpt commands (enumarate and setenv) that are used by broadcom
update scripts and boot commands
- eMMC specific u-boot configurations with environment saved in eMMC
and GPT support
Signed-off-by: Corneliu Doban
Signed-off-by: Rayagonda Kokatanur
---
Changes from v3:
-Address review comments from Simon Glass,
Return -ve number instead of 1 upon failure,
Use shorter variable name,
Modified code to avoid buffer overflow,
Use if (!strcmp(...)) instead of if (strcmp(...) == 0)
Changes from v2:
-Address review comments from Simon Glass,
Check for return value of part_driver_get_count(),
Don't check return value of part_driver_get(),
Rewrite part_driver_get() and rename to part_driver_get_first(),
Use env_set_ulong() whereever applicable,
-Address review comments from Michael Nazzareno Trimarchi,
Add new function to set all env vriables,
Changes from v1:
-Address review comments from Simon Glass,
Correct function comments,
Check for return value,
Add helper function in part.h
cmd/gpt.c | 161 +
include/part.h | 29 +
2 files changed, 190 insertions(+)
diff --git a/cmd/gpt.c b/cmd/gpt.c
index df759416c8..2626992e59 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -621,6 +622,152 @@ static int gpt_verify(struct blk_desc *blk_dev_desc,
const char *str_part)
return ret;
}
+/**
+ * gpt_enumerate() - Enumerate partition names into environment variable.
+ *
+ * Enumerate partition names. Partition names are stored in gpt_partition_list
+ * environment variable. Each partition name is delimited by space.
+ *
+ * @desc: block device descriptor
+ *
+ * @Return: '0' on success and -ve error on failure
+ */
+static int gpt_enumerate(struct blk_desc *desc)
+{
+ struct part_driver *first_drv, *part_drv;
+ int str_len = 0, tmp_len;
+ char part_list[2048];
+ int n_drvs;
+ char *ptr;
+
+ part_list[0] = 0;
+ n_drvs = part_driver_get_count();
+ if (!n_drvs) {
+ printf("Failed to get partition driver count\n");
+ return -ENOENT;
+ }
+
+ first_drv = part_driver_get_first();
+ for (part_drv = first_drv; part_drv != first_drv + n_drvs; part_drv++) {
+ struct disk_partition pinfo;
+ int ret;
+ int i;
+
+ for (i = 1; i < part_drv->max_entries; i++) {
+ ret = part_drv->get_info(desc, i, );
+ if (ret) {
+ /* no more entries in table */
+ break;
+ }
+
+ ptr = _list[str_len];
+ tmp_len = strlen((const char *)pinfo.name);
+ str_len += tmp_len;
+ /* +1 for space */
+ str_len++;
+ if (str_len > sizeof(part_list)) {
+ printf("Error insufficient memory\n");
+ return -ENOMEM;
+ }
+ strcpy(ptr, (const char *)pinfo.name);
+ /* One byte for space(" ") delimiter */
+ ptr[tmp_len] = ' ';
+ }
+ }
+ if (*part_list)
+ part_list[strlen(part_list) - 1] = 0;
+ debug("setenv gpt_partition_list %s\n", part_list);
+
+ return env_set("gpt_partition_list", part_list);
+}
+
+/**
+ * gpt_setenv_part_variables() - setup partition environmental variables
+ *
+ * Setup the gpt_partition_name, gpt_partition_entry, gpt_partition_addr
+ * and gpt_partition_size environment variables.
+ *
+ * @pinfo: pointer to disk partition
+ * @i: partition entry
+ *
+ * @Return: '0' on success and -ENOENT on failure
+ */
+static int gpt_setenv_part_variables(struct disk_partition *pinfo, int i)
+{
+ int ret;
+
+ ret = env_set_ulong("gpt_partition_addr", pinfo->start);
+ if (ret)
+ goto fail;
+
+ ret = env_set_ulong("gpt_partition_size", pinfo->size);
+ if (ret)
+ goto fail;
+
+ ret = env_set_ulong("gpt_partition_entry", i);
+ if (ret)
+ goto fail;
+
+ ret = env_set("gpt_partition_name", (const char *)pinfo->name);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ return -ENOENT;
+}
+
+/**
+ * gpt_setenv() - Dynamically setup environment variables.
+ *
+ * Dynamically setup environment variables for name, index, offset and size
+ * for partition in GPT table after running "gp
Re: [PATCH v3 1/1] cmd: gpt: add eMMC and GPT support
Hi Simon,
On Sat, May 16, 2020 at 2:33 AM Simon Glass wrote:
>
> Hi Rayagonda,
>
> On Wed, 13 May 2020 at 09:28, Rayagonda Kokatanur
> wrote:
> >
> > From: Corneliu Doban
> >
> > Add eMMC and GPT support.
> > - GPT partition list and command to create the GPT added to u-boot
> > environment
> > - eMMC boot commands added to u-boot environment
> > - new gpt commands (enumarate and setenv) that are used by broadcom
> > update scripts and boot commands
> > - eMMC specific u-boot configurations with environment saved in eMMC
> > and GPT support
> >
> > Signed-off-by: Corneliu Doban
> > Signed-off-by: Rayagonda Kokatanur
> > ---
> > Changes from v2:
> > -Address review comments from Simon Glass,
> > Check for return value of part_driver_get_count(),
> > Don't check return value of part_driver_get(),
> > Rewrite part_driver_get() and rename to part_driver_get_first(),
> > Use env_set_ulong() whereever applicable,
> >
> > -Address review comments from Michael Nazzareno Trimarchi,
> > Add new function to set all env vriables,
> >
> > Changes from v1:
> > -Address review comments from Simon Glass,
> > Correct function comments,
> > Check for return value,
> > Add helper function in part.h
> >
> > cmd/gpt.c | 160 +
> > include/part.h | 29 +
> > 2 files changed, 189 insertions(+)
>
> This looks good, but can you add a test?
I am finding it a little difficult in adding tests and running existing tests.
I will add a test late for this.
I have fixed all other review comments, requesting you to review patch v4.
Best regards,
Rayagonda
>
> A few nits below
>
> >
> > diff --git a/cmd/gpt.c b/cmd/gpt.c
> > index b8d11c167d..bba79aca64 100644
> > --- a/cmd/gpt.c
> > +++ b/cmd/gpt.c
> > @@ -15,6 +15,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -616,6 +617,151 @@ static int gpt_verify(struct blk_desc *blk_dev_desc,
> > const char *str_part)
> > return ret;
> > }
> >
> > +/**
> > + * gpt_enumerate() - Enumerate partition names into environment variable.
> > + *
> > + * Enumerate partition names. Partition names are stored in
> > gpt_partition_list
> > + * environment variable. Each partition name is delimited by space.
> > + *
> > + * @blk_dev_desc: block device descriptor
> > + *
> > + * @Return: '0' on success and 1 on failure
>
> Should return a -ve error code. You return -ENOMEM for example.
>
> > + */
> > +static int gpt_enumerate(struct blk_desc *blk_dev_desc)
>
> Please use 'desc' for arg as it is shorter
>
> > +{
> > + struct part_driver *first_drv, *part_drv;
> > + int str_len = 0, tmp_len;
> > + char part_list[2048];
> > + int n_drvs;
> > + char *ptr;
> > +
> > + part_list[0] = 0;
> > + n_drvs = part_driver_get_count();
> > + if (!n_drvs) {
> > + printf("Failed to get partition driver count\n");
> > + return 1;
>
> How about -ENOENT?
>
> > + }
> > +
> > + first_drv = part_driver_get_first();
> > + for (part_drv = first_drv; part_drv != first_drv + n_drvs;
> > part_drv++) {
> > + disk_partition_t pinfo;
> > + int ret;
> > + int i;
> > +
> > + for (i = 1; i < part_drv->max_entries; i++) {
> > + ret = part_drv->get_info(blk_dev_desc, i, );
> > + if (ret) {
> > + /* no more entries in table */
> > + break;
> > + }
> > +
> > + ptr = _list[str_len];
> > + tmp_len = strlen((const char *)pinfo.name);
> > + str_len += tmp_len;
>
> +1 for space (below). Otherwise you can overfllow
>
> > + if (str_len > sizeof(part_list)) {
> > + printf("Error insufficient memory\n");
> > + return -ENOMEM;
> > + }
> > + strncpy(ptr, (const char *)pinfo.name, tmp_len);
>
> But you know ptr has enough space, so just use strcpy
>
> > + /* One byte for space(" ") delimite
Re: [PATCH v2 0/2] add broadcom spi driver
Hi Jagan, On Sun, May 17, 2020 at 12:54 PM Rayagonda Kokatanur wrote: > > This patchset, > -adds Broadcom SPI driver for iproc-based platforms and > -extends Micron SPI commands for dual and quad SPI transfers on Micon SPI. > > Changes from v1: > -Address review comments from Jagan Teki, > Remove flash opcode from driver and use include/linux/mtd/spi-nor.h, > Remove CONFIG_BCM_IPROC_USE_BSPI, handle via driver data > > -Address self review comments, > Remove REG_WR, REG_RD, REG_SET, REG_CLR and use writel, readl, > setbits_le32 and clrbits_le32 respectively, > Rename priv data struct variables mspi_hw. bspi_hw, bspi_hw_raf to > mspi, bspi, baspi_raf respectively, > Remove struct bcmspi_platdata. > > Rayagonda Kokatanur (2): > driver: spi: add brcm iproc qspi support. > drivers: spi: add commands for micron SPI > > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/iproc_qspi.c | 808 +++ > drivers/spi/iproc_qspi.h | 18 + > drivers/spi/iproc_spi.c | 71 > include/spi.h| 2 + > 6 files changed, 906 insertions(+) > create mode 100644 drivers/spi/iproc_qspi.c > create mode 100644 drivers/spi/iproc_qspi.h > create mode 100644 drivers/spi/iproc_spi.c Could you please review this patch set. Best regards, Rayagonda > > > -- > 2.17.1 >
[PATCH v3 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
Use device tree and UCLASS_IRQ driver to get following
Generic Interrupt Controller (GIC) details,
-GIC Distributor interface (GICD) base address and
-GIC Redistributors (GICR) base address.
Signed-off-by: Rayagonda Kokatanur
---
Changes from v1:
-Address review comments from Tom Rini,
Fix build warning messages.
arch/arm/lib/gic-v3-its.c | 73 +++
1 file changed, 66 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 90f37a123c..5057cc5421 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -15,6 +16,48 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/*
+ * gic_v3_its_priv - gic details
+ *
+ * @gicd_base: gicd base address
+ * @gicr_base: gicr base address
+ */
+struct gic_v3_its_priv {
+ u32 gicd_base;
+ u32 gicr_base;
+};
+
+static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_IRQ,
+ DM_GET_DRIVER(arm_gic_v3_its), );
+ if (ret) {
+ pr_err("%s: failed to get %s irq device\n", __func__,
+ DM_GET_DRIVER(arm_gic_v3_its)->name);
+ return ret;
+ }
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICD address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicd_base = addr;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICR address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicr_base = addr;
+
+ return 0;
+}
+
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
@@ -23,15 +66,18 @@ static u32 lpi_id_bits;
*/
int gic_lpi_tables_init(u64 base, u32 num_redist)
{
+ struct gic_v3_its_priv priv;
u32 gicd_typer;
u64 val;
u64 tmp;
int i;
u64 redist_lpi_base;
- u64 pend_base = GICR_BASE + GICR_PENDBASER;
+ u64 pend_base;
- gicd_typer = readl(GICD_BASE + GICD_TYPER);
+ if (gic_v3_its_get_gic_addr())
+ return -EINVAL;
+ gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
pr_err("GIC implementation does not support LPI's\n");
@@ -46,7 +92,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
- if ((readl((uintptr_t)(GICR_BASE + offset))) &
+ if ((readl((uintptr_t)(priv.gicr_base + offset))) &
GICR_CTLR_ENABLE_LPIS) {
pr_err("Re-Distributor %d LPI is already enabled\n",
i);
@@ -64,19 +110,21 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
- writeq(val, (GICR_BASE + GICR_PROPBASER));
- tmp = readl(GICR_BASE + GICR_PROPBASER);
+ writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
+ tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_NC;
- writeq(val, (GICR_BASE + GICR_PROPBASER));
+ writeq(val,
+ (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
}
}
redist_lpi_base = base + LPI_PROPBASE_SZ;
+ pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
@@ -94,9 +142,20 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
}
/* Enable LPI for the redistributor */
- writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+ writel(GICR_CTLR_ENABLE_LPIS,
+ (uintptr_t)(priv.gicr_base + offset));
}
return 0;
}
+static const struct udevice_id gic_v3_its_ids[] = {
+ { .c
[PATCH v3 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.
Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.
Signed-off-by: Rayagonda Kokatanur
---
Changes from v2:
-Address review comments from Tom Rini,
Fix build errors messages.
arch/arm/Kconfig| 2 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 +--
arch/arm/include/asm/gic-v3.h | 4 +-
arch/arm/lib/gic-v3-its.c | 63 ++---
4 files changed, 61 insertions(+), 36 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e16fe03887..f88229d092 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,8 @@ endif
config GIC_V3_ITS
bool "ARM GICV3 ITS"
+ select REGMAP
+ select SYSCON
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ad7ea05935..135fe4a462 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -41,37 +41,11 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_GIC_V3_ITS
-#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
-#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
-#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
- PROPTABLE_MAX_SZ, SZ_1M)
-static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
-{
- u32 phandle;
- int err;
- struct fdt_memory gic_rd_tables;
-
- gic_rd_tables.start = base;
- gic_rd_tables.end = base + size - 1;
- err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", _rd_tables,
-);
- if (err < 0)
- debug("%s: failed to add reserved memory: %d\n", __func__, err);
-
- return err;
-}
-
int ls_gic_rd_tables_init(void *blob)
{
- u64 gic_lpi_base;
int ret;
- gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
- ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
- if (ret)
- return ret;
-
- ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+ ret = gic_lpi_tables_init();
if (ret)
debug("%s: failed to init gic-lpi-tables\n", __func__);
diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
index 5131fabec4..35efec78c3 100644
--- a/arch/arm/include/asm/gic-v3.h
+++ b/arch/arm/include/asm/gic-v3.h
@@ -127,9 +127,9 @@
#define GIC_REDISTRIBUTOR_OFFSET 0x2
#ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(u64 base, u32 max_redist);
+int gic_lpi_tables_init(void);
#else
-int gic_lpi_tables_init(u64 base, u32 max_redist)
+int gic_lpi_tables_init(void)
{
return 0;
}
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 5057cc5421..5e82bdf568 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -4,6 +4,8 @@
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -16,15 +18,22 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/* Number of GIC re-distributors */
+#define MAX_GIC_REDISTRIBUTORS 8
+
/*
* gic_v3_its_priv - gic details
*
* @gicd_base: gicd base address
* @gicr_base: gicr base address
+ * @lpi_base: gic lpi base address
+ * @num_redist: number of gic re-distributors
*/
struct gic_v3_its_priv {
u32 gicd_base;
u32 gicr_base;
+ u32 lpi_base;
+ u32 num_redist;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
@@ -58,13 +67,39 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv
*priv)
return 0;
}
+static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
+{
+ struct regmap *regmap;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+ DM_GET_DRIVER(gic_lpi_syscon), );
+ if (ret) {
+ pr_err("%s: failed to get %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return ret;
+ }
+
+ regmap = syscon_get_regmap(dev);
+ if (!regmap) {
+ pr_err("%s: failed to regmap for %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return -ENODEV;
+ }
+ priv->lpi_base = regmap->ranges[0].start;
+
+ priv->num_redist = dev_read_u32_default(dev, "max-gic-r
[PATCH v3 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get gic details like GICD, GICR base address, max number of redistributors and git lpi address. Changes from v2: -Address review comments from Tom Rini, Fix build errors messages. Changes from v1: -Address review comments from Tom Rini, Fix build warning messages. Rayagonda Kokatanur (2): arch: arm: use dt and UCLASS_IRQ to get gic details arch: arm: use dt and UCLASS_SYSCON to get gic lpi details arch/arm/Kconfig| 2 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 + arch/arm/include/asm/gic-v3.h | 4 +- arch/arm/lib/gic-v3-its.c | 136 +--- 4 files changed, 127 insertions(+), 43 deletions(-) -- 2.17.1
Re: [PATCH v2 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Hi Simon, On Sat, Jul 18, 2020 at 8:14 PM Rayagonda Kokatanur wrote: > > Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get > gic details like GICD, GICR base address, max number of redistributors > and git lpi address. > > Changes from v1: > -Address review comments from Tom Rini, > Fix build warning messages. > > Rayagonda Kokatanur (2): > arch: arm: use dt and UCLASS_IRQ to get gic details > arch: arm: use dt and UCLASS_SYSCON to get gic lpi details > > arch/arm/Kconfig | 2 + > arch/arm/include/asm/gic-v3.h | 4 +- > arch/arm/lib/gic-v3-its.c | 136 ++ > 3 files changed, 126 insertions(+), 16 deletions(-) Request you to please review these patches. These are required for other board file patches to build. Best regards, Rayagonda > > > -- > 2.17.1 >
[PATCH v2 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.
Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.
Signed-off-by: Rayagonda Kokatanur
---
arch/arm/Kconfig | 2 ++
arch/arm/include/asm/gic-v3.h | 4 +--
arch/arm/lib/gic-v3-its.c | 63 +++
3 files changed, 60 insertions(+), 9 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f115fcdcc4..2fd20fc648 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,8 @@ endif
config GIC_V3_ITS
bool "ARM GICV3 ITS"
+ select REGMAP
+ select SYSCON
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
index 5131fabec4..35efec78c3 100644
--- a/arch/arm/include/asm/gic-v3.h
+++ b/arch/arm/include/asm/gic-v3.h
@@ -127,9 +127,9 @@
#define GIC_REDISTRIBUTOR_OFFSET 0x2
#ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(u64 base, u32 max_redist);
+int gic_lpi_tables_init(void);
#else
-int gic_lpi_tables_init(u64 base, u32 max_redist)
+int gic_lpi_tables_init(void)
{
return 0;
}
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 5057cc5421..5e82bdf568 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -4,6 +4,8 @@
*/
#include
#include
+#include
+#include
#include
#include
#include
@@ -16,15 +18,22 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/* Number of GIC re-distributors */
+#define MAX_GIC_REDISTRIBUTORS 8
+
/*
* gic_v3_its_priv - gic details
*
* @gicd_base: gicd base address
* @gicr_base: gicr base address
+ * @lpi_base: gic lpi base address
+ * @num_redist: number of gic re-distributors
*/
struct gic_v3_its_priv {
u32 gicd_base;
u32 gicr_base;
+ u32 lpi_base;
+ u32 num_redist;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
@@ -58,13 +67,39 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv
*priv)
return 0;
}
+static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
+{
+ struct regmap *regmap;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+ DM_GET_DRIVER(gic_lpi_syscon), );
+ if (ret) {
+ pr_err("%s: failed to get %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return ret;
+ }
+
+ regmap = syscon_get_regmap(dev);
+ if (!regmap) {
+ pr_err("%s: failed to regmap for %s syscon device\n", __func__,
+ DM_GET_DRIVER(gic_lpi_syscon)->name);
+ return -ENODEV;
+ }
+ priv->lpi_base = regmap->ranges[0].start;
+
+ priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
+ MAX_GIC_REDISTRIBUTORS);
+
+ return 0;
+}
+
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
- * base: Configuration table address
- * num_redist: number of redistributors
*/
-int gic_lpi_tables_init(u64 base, u32 num_redist)
+int gic_lpi_tables_init(void)
{
struct gic_v3_its_priv priv;
u32 gicd_typer;
@@ -77,6 +112,9 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
if (gic_v3_its_get_gic_addr())
return -EINVAL;
+ if (gic_v3_its_get_gic_lpi_addr())
+ return -EINVAL;
+
gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
@@ -89,7 +127,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
* Once the LPI table is enabled, can not program the
* LPI configuration tables again, unless the GIC is reset.
*/
- for (i = 0; i < num_redist; i++) {
+ for (i = 0; i < priv.num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
if ((readl((uintptr_t)(priv.gicr_base + offset))) &
@@ -105,7 +143,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
ITS_MAX_LPI_NRBITS);
/* Set PropBase */
- val = (base |
+ val = (priv.lpi_base |
GICR_PROPBASER_INNERSHAREABLE |
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
@@ -122,10 +160,10 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
[PATCH v2 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
Use device tree and UCLASS_IRQ driver to get following
Generic Interrupt Controller (GIC) details,
-GIC Distributor interface (GICD) base address and
-GIC Redistributors (GICR) base address.
Signed-off-by: Rayagonda Kokatanur
---
Changes from v1:
-Address review comments from Tom Rini,
Fix build warning messages.
arch/arm/lib/gic-v3-its.c | 73 +++
1 file changed, 66 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 90f37a123c..5057cc5421 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -15,6 +16,48 @@ static u32 lpi_id_bits;
#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+/*
+ * gic_v3_its_priv - gic details
+ *
+ * @gicd_base: gicd base address
+ * @gicr_base: gicr base address
+ */
+struct gic_v3_its_priv {
+ u32 gicd_base;
+ u32 gicr_base;
+};
+
+static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_IRQ,
+ DM_GET_DRIVER(arm_gic_v3_its), );
+ if (ret) {
+ pr_err("%s: failed to get %s irq device\n", __func__,
+ DM_GET_DRIVER(arm_gic_v3_its)->name);
+ return ret;
+ }
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICD address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicd_base = addr;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICR address\n", __func__);
+ return -EINVAL;
+ }
+ priv->gicr_base = addr;
+
+ return 0;
+}
+
/*
* Program the GIC LPI configuration tables for all
* the re-distributors and enable the LPI table
@@ -23,15 +66,18 @@ static u32 lpi_id_bits;
*/
int gic_lpi_tables_init(u64 base, u32 num_redist)
{
+ struct gic_v3_its_priv priv;
u32 gicd_typer;
u64 val;
u64 tmp;
int i;
u64 redist_lpi_base;
- u64 pend_base = GICR_BASE + GICR_PENDBASER;
+ u64 pend_base;
- gicd_typer = readl(GICD_BASE + GICD_TYPER);
+ if (gic_v3_its_get_gic_addr())
+ return -EINVAL;
+ gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
/* GIC support for Locality specific peripheral interrupts (LPI's) */
if (!(gicd_typer & GICD_TYPER_LPIS)) {
pr_err("GIC implementation does not support LPI's\n");
@@ -46,7 +92,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
- if ((readl((uintptr_t)(GICR_BASE + offset))) &
+ if ((readl((uintptr_t)(priv.gicr_base + offset))) &
GICR_CTLR_ENABLE_LPIS) {
pr_err("Re-Distributor %d LPI is already enabled\n",
i);
@@ -64,19 +110,21 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
GICR_PROPBASER_RAWAWB |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
- writeq(val, (GICR_BASE + GICR_PROPBASER));
- tmp = readl(GICR_BASE + GICR_PROPBASER);
+ writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
+ tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_NC;
- writeq(val, (GICR_BASE + GICR_PROPBASER));
+ writeq(val,
+ (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
}
}
redist_lpi_base = base + LPI_PROPBASE_SZ;
+ pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < num_redist; i++) {
u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
@@ -94,9 +142,20 @@ int gic_lpi_tables_init(u64 base, u32 num_redist)
}
/* Enable LPI for the redistributor */
- writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+ writel(GICR_CTLR_ENABLE_LPIS,
+ (uintptr_t)(priv.gicr_base + offset));
}
return 0;
}
+static const struct udevice_id gic_v3_its_ids[] = {
+ { .c
[PATCH v2 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get gic details like GICD, GICR base address, max number of redistributors and git lpi address. Changes from v1: -Address review comments from Tom Rini, Fix build warning messages. Rayagonda Kokatanur (2): arch: arm: use dt and UCLASS_IRQ to get gic details arch: arm: use dt and UCLASS_SYSCON to get gic lpi details arch/arm/Kconfig | 2 + arch/arm/include/asm/gic-v3.h | 4 +- arch/arm/lib/gic-v3-its.c | 136 ++ 3 files changed, 126 insertions(+), 16 deletions(-) -- 2.17.1
Re: [PATCH v1 0/2] use dt and UCLASS_IRQ/SYSCON to get gic details
Hi Simon, On Wed, Jul 8, 2020 at 12:45 PM Rayagonda Kokatanur wrote: > > Use device tree and driver class (UCLASS_IRQ and UCLASS_SYSCON) to get > gic details like GICD, GICR base address, max number of redistributors > and git lpi address. > > Rayagonda Kokatanur (2): > arch: arm: use dt and UCLASS_IRQ to get gic details > arch: arm: use dt and UCLASS_SYSCON to get gic lpi details > > arch/arm/Kconfig | 2 + > arch/arm/include/asm/gic-v3.h | 4 +- > arch/arm/lib/gic-v3-its.c | 135 ++ > 3 files changed, 125 insertions(+), 16 deletions(-) > Please review this patch series. These changes are done as per your review comments on other patch sets. Thanks, Rayagonda > -- > 2.17.1 >
[PATCH v5 2/2] configs: ns3: enable tee and optee driver
Enable tee and optee drivers. Signed-off-by: Vikas Gupta Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 0e078f3244..72015c6596 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -4,12 +4,12 @@ CONFIG_TARGET_BCMNS3=y CONFIG_SYS_TEXT_BASE=0xFF00 CONFIG_ENV_SIZE=0x8 CONFIG_NR_DRAM_BANKS=2 -CONFIG_OF_BOARD_SETUP=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_SIGNATURE_MAX_SIZE=0x2000 CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y CONFIG_LOGLEVEL=7 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y @@ -42,6 +42,9 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_TEE=y +CONFIG_OPTEE=y +# CONFIG_OPTEE_TA_AVB is not set CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_FAT_WRITE=y -- 2.17.1
[PATCH v5 0/2] add optee support for broadcom NS3 soc
This is fourth patch set series prepared on top of third
patch set ("add FIT image support for broadcom NS3 soc").
This patch adds optee support.
Changes from v4:
-Address review comments from Simon,
Add blank line before return.
Changes from v3:
-Address review comments from Simon,
Rearrange code and remove while loop,
Add comments for function.
Changes from v2:
-Address review comments from Simon,
Remove own return code and use standard error code.
Take out common lines from different functions and move them
into common static function.
Remove include as its not required.
Move functions with printf from header file into c file.
-Address slef review comments,
Remove optee dt node as this file is no longer in sync with linux.
Changes from v1:
-Address review comments from Thomas Fitzsimmons,
Expand the bnxt full form.
-Address review comments from Simon Glass,
Move c file from board/broadcom/bcmns3/chimp_optee.c to
drivers/tee/broadcom,
Move header file from include/brcm/chimp.h to include/broadcom/chimp.h
Rayagonda Kokatanur (1):
configs: ns3: enable tee and optee driver
Vikas Gupta (1):
drivers: tee: broadcom: add optee based bnxt fw load driver
configs/bcm_ns3_defconfig | 5 +-
drivers/tee/Kconfig| 1 +
drivers/tee/Makefile | 1 +
drivers/tee/broadcom/Kconfig | 7 ++
drivers/tee/broadcom/Makefile | 3 +
drivers/tee/broadcom/chimp_optee.c | 183 +
include/broadcom/chimp.h | 43 +++
7 files changed, 242 insertions(+), 1 deletion(-)
create mode 100644 drivers/tee/broadcom/Kconfig
create mode 100644 drivers/tee/broadcom/Makefile
create mode 100644 drivers/tee/broadcom/chimp_optee.c
create mode 100644 include/broadcom/chimp.h
--
2.17.1
[PATCH v5 1/2] drivers: tee: broadcom: add optee based bnxt fw load driver
From: Vikas Gupta
Add optee based bnxt fw load driver.
bnxt is Broadcom NetXtreme controller Ethernet card.
This driver is used to load bnxt firmware binary using OpTEE.
Signed-off-by: Vikas Gupta
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v4:
-Address review comments from Simon,
Add blank line before return.
Changes from v3:
-Address review comments from Simon,
Rearrange code and remove while loop,
Add comments for function.
Changes from v2:
-Address review comments from Simon,
Remove own return code and use standard error code.
Take out common lines from different functions and move them
into common static function.
Remove include as its not required.
Move functions with printf from header file into c file.
drivers/tee/Kconfig| 1 +
drivers/tee/Makefile | 1 +
drivers/tee/broadcom/Kconfig | 7 ++
drivers/tee/broadcom/Makefile | 3 +
drivers/tee/broadcom/chimp_optee.c | 183 +
include/broadcom/chimp.h | 43 +++
6 files changed, 238 insertions(+)
create mode 100644 drivers/tee/broadcom/Kconfig
create mode 100644 drivers/tee/broadcom/Makefile
create mode 100644 drivers/tee/broadcom/chimp_optee.c
create mode 100644 include/broadcom/chimp.h
diff --git a/drivers/tee/Kconfig b/drivers/tee/Kconfig
index 5c0c89043f..5ca5a0836c 100644
--- a/drivers/tee/Kconfig
+++ b/drivers/tee/Kconfig
@@ -29,6 +29,7 @@ config SANDBOX_TEE
"avb" commands.
source "drivers/tee/optee/Kconfig"
+source "drivers/tee/broadcom/Kconfig"
endmenu
diff --git a/drivers/tee/Makefile b/drivers/tee/Makefile
index f72c68c09f..5c8ffdbce8 100644
--- a/drivers/tee/Makefile
+++ b/drivers/tee/Makefile
@@ -3,3 +3,4 @@
obj-y += tee-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox.o
obj-$(CONFIG_OPTEE) += optee/
+obj-y += broadcom/
diff --git a/drivers/tee/broadcom/Kconfig b/drivers/tee/broadcom/Kconfig
new file mode 100644
index 00..ce95072d4e
--- /dev/null
+++ b/drivers/tee/broadcom/Kconfig
@@ -0,0 +1,7 @@
+config CHIMP_OPTEE
+ bool "Enable secure ChiMP firmware loading"
+ depends on OPTEE
+ default y
+ help
+ This driver is used to load bnxt firmware binary using OpTEE.
+ bnxt is Broadcom NetXtreme controller Ethernet card.
diff --git a/drivers/tee/broadcom/Makefile b/drivers/tee/broadcom/Makefile
new file mode 100644
index 00..cb3cef16df
--- /dev/null
+++ b/drivers/tee/broadcom/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += chimp_optee.o
diff --git a/drivers/tee/broadcom/chimp_optee.c
b/drivers/tee/broadcom/chimp_optee.c
new file mode 100644
index 00..37f9b094f7
--- /dev/null
+++ b/drivers/tee/broadcom/chimp_optee.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright 2020 Broadcom.
+ */
+
+#include
+#include
+#include
+
+#ifdef CONFIG_CHIMP_OPTEE
+
+#define CHMIP_BOOT_UUID { 0x6272636D, 0x2019, 0x0716, \
+ { 0x42, 0x43, 0x4D, 0x5F, 0x53, 0x43, 0x48, 0x49 } }
+
+enum {
+ TEE_CHIMP_FASTBOOT = 0,
+ TEE_CHIMP_HEALTH_STATUS,
+ TEE_CHIMP_HANDSHAKE_STATUS,
+} tee_chmip_cmd;
+
+struct bcm_chimp_data {
+ struct udevice *tee;
+ u32 session;
+} chimp_data;
+
+static int get_open_session(struct bcm_chimp_data *b_data)
+{
+ const struct tee_optee_ta_uuid uuid = CHMIP_BOOT_UUID;
+ struct tee_open_session_arg arg;
+ struct udevice *tee = NULL;
+ int rc;
+
+ tee = tee_find_device(NULL, NULL, NULL, NULL);
+ if (!tee)
+ return -ENODEV;
+
+ memset(, 0, sizeof(arg));
+ tee_optee_ta_uuid_to_octets(arg.uuid, );
+ rc = tee_open_session(tee, , 0, NULL);
+ if (rc < 0)
+ return -ENODEV;
+
+ b_data->tee = tee;
+ b_data->session = arg.session;
+
+ return 0;
+}
+
+static int init_arg(struct tee_invoke_arg *arg, u32 func)
+{
+ if (get_open_session(_data))
+ return -EINVAL;
+
+ memset(arg, 0, sizeof(struct tee_invoke_arg));
+ arg->func = func;
+ arg->session = chimp_data.session;
+
+ return 0;
+}
+
+int chimp_handshake_status_optee(u32 timeout, u32 *hs)
+{
+ struct tee_invoke_arg arg;
+ struct tee_param param[1];
+ int ret;
+
+ ret = init_arg(, TEE_CHIMP_HANDSHAKE_STATUS);
+ if (ret < 0)
+ return ret;
+
+ param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INOUT;
+ param[0].u.value.a = timeout;
+
+ ret = tee_invoke_func(chimp_data.tee, , ARRAY_SIZE(param), param);
+ if (ret < 0) {
+ printf("Handshake status command failed\n");
+ goto out;
+ }
+
+ switch (arg.ret) {
+ case TEE_SUCCESS:
+ *hs = param[0].u.va
[PATCH v4 3/3] board: ns3: add development keys used in FIT
From: Pramod Kumar Add development keys used in FIT. Signed-off-by: Pramod Kumar Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- board/broadcom/bcmns3/fit/keys/dev.crt | 21 +++ board/broadcom/bcmns3/fit/keys/dev.key | 28 ++ 2 files changed, 49 insertions(+) create mode 100644 board/broadcom/bcmns3/fit/keys/dev.crt create mode 100644 board/broadcom/bcmns3/fit/keys/dev.key diff --git a/board/broadcom/bcmns3/fit/keys/dev.crt b/board/broadcom/bcmns3/fit/keys/dev.crt new file mode 100644 index 00..75b75db95c --- /dev/null +++ b/board/broadcom/bcmns3/fit/keys/dev.crt @@ -0,0 +1,21 @@ +-BEGIN CERTIFICATE- +MIIDXTCCAkWgAwIBAgIJAJgq/5aiJttEMA0GCSqGSIb3DQEBCwUAMEUxCzAJBgNV +BAYTAkFVMRMwEQYDVQQIDApTb21lLVN0YXRlMSEwHwYDVQQKDBhJbnRlcm5ldCBX +aWRnaXRzIFB0eSBMdGQwHhcNMTgwOTE5MDkzMzEwWhcNMTgxMDE5MDkzMzEwWjBF +MQswCQYDVQQGEwJBVTETMBEGA1UECAwKU29tZS1TdGF0ZTEhMB8GA1UECgwYSW50 +ZXJuZXQgV2lkZ2l0cyBQdHkgTHRkMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIB +CgKCAQEAzeMQ92YqrejtMCfxjDyHvDW34ATozXSlWsudR+AyCSuJVAIoHEenVh+/ +PuT0+/EMiwsUnLXYBeOsIXDW3k3eHgm88ccb+0g9J6mlHqMaN0tXP+Ua2GFEk2Wv +5Bj5QynorOPoaWL/ecWus2Bvkmyt2pvIpaTjmkUKZ9al3z8WyS6wFlFitXyOWFcK +7Xkl43cOHxYAfbny5loWYDCgpkV+dgYZOoCEmL+Y9HfrQ+uBKGducpzNKeQjX9bn +UT9cleCtHZx0uY4wSGNgfmUMy7oUyVZhFpmjlcfjcfNFcBcoVF6StluoL6v1KRbH +4xJDD/UCn2Uk0S6Zpd7TRc26faOtfwIDAQABo1AwTjAdBgNVHQ4EFgQUZk/KKaWG +p4BtksPdQ8FLzWL/gAIwHwYDVR0jBBgwFoAUZk/KKaWGp4BtksPdQ8FLzWL/gAIw +DAYDVR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAPNveTvOC2bw91cUN1e+B +95qFp2Xd5XGiV35F10dT3VN/Iv2dzHlThq7xaJGkA53lHIXgLUUfnDTHJmoluw+t +UCpG8OWCxM0FbT8ZnXR4SmHK8k4yb7iZa7iu+Ey5B6F3247gJpEl+1iYxus0lqQW +E9dTwMf1YP9Jdf+dRoLKAAI0n5J1PMuseQkGdlRBNUcEg+kXqBSz5hq0xkuPRtey +GiAvpg3G93ft84Q4ov7IjAhJkY7whm6WktisU8mFPru3e9EouxjVtAvu6s9gQThm +pvn6hSL2/3gEOP3v9yBsH6//SOgNdVBGZIdX+HkvD8NZLftbIrDaeL/IfKUm/zXB +zA== +-END CERTIFICATE- diff --git a/board/broadcom/bcmns3/fit/keys/dev.key b/board/broadcom/bcmns3/fit/keys/dev.key new file mode 100644 index 00..55b7033e9f --- /dev/null +++ b/board/broadcom/bcmns3/fit/keys/dev.key @@ -0,0 +1,28 @@ +-BEGIN PRIVATE KEY- +MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQDN4xD3Ziqt6O0w +J/GMPIe8NbfgBOjNdKVay51H4DIJK4lUAigcR6dWH78+5PT78QyLCxSctdgF46wh +cNbeTd4eCbzxxxv7SD0nqaUeoxo3S1c/5RrYYUSTZa/kGPlDKeis4+hpYv95xa6z +YG+SbK3am8ilpOOaRQpn1qXfPxbJLrAWUWK1fI5YVwrteSXjdw4fFgB9ufLmWhZg +MKCmRX52Bhk6gISYv5j0d+tD64EoZ25ynM0p5CNf1udRP1yV4K0dnHS5jjBIY2B+ +ZQzLuhTJVmEWmaOVx+Nx80VwFyhUXpK2W6gvq/UpFsfjEkMP9QKfZSTRLpml3tNF +zbp9o61/AgMBAAECggEBAJ/TZClZk0ob5nyalWVS29/cJ5hs1zgfE/nu1HKmdNEv +jdS8M9z4Nsuhq3msjQ1Da4RInsCkXUT9H3N6QCKkeggBcT6TXYJs6qRuijLFVKWW +A+4i8PsGTxDJQIimZmGgF/KWnaWp5z7lmZ+//fzCBxgMFO+Zl+H7NH+1XmB2fj6/ +bfgnxLbiIqq/2oVJfdjA1Zs2ie3SE5U2hPNiE6TIajFS0PxUOGrojsSQ8z+gfqs3 +hyqo9msAqNQciT79vyXp+3HsxZo9rq5Tk5OtCEfgu0GED/d4/FHbDrZT3TorVYXr +Z3dADxvnnJfBdlQIMetCy/X8z2vKRRXaoWpqg1aiFVECgYEA7Ap5D4nvOie2NXgI +gMPzuYtpH4uF/cZMLGxTKZ3NG4RH6oVUdd4whETXfzBJdnJbIXDTphoHxjUhpGh8 +Ga+U1iqjp9c6Nd8ueVp/c5T1bD8/2RG0QM4iWgPbZDKtj1MqRg7vwAfpJ3kOIc/5 +bKJ4jAopNJMChL6vAZ9+ShPsRqkCgYEA30vbj6K7/giclJnyWkluQTqS8X/XjdAf +F5PkCBHGJnYxkDSzWPq7O5E1wYqTAou1U6nNNoUvZZdpRvo39NSrMCaagQ7GE+xA +j/h7tinD/lPlvoW9N4f4ddqWzsmf7I8OGZtP4IwVi9Pms+zPtrQ7TvuPT4UHTH2E +eE1hlJtic+cCgYEA6oKdNGr+WvEJfqX7DLOiej2f+89LGI7jL1+QYFB/b09FhCNj +fpd57G/ZCmyXEC8di2PlY6mI/8vZ2NZWNc7UONO0NRUIqG1MZxUae2MLUrikXq3Q +QHKMfpJGbo5LEZK29VPxrwAtDSKgf8d5MA1bZwbRWYKVhf1NMnebqU2R+cECgYEA +kOTKXhP85MR1xj928XtAnfcCLs8D8jOgWU5P46SU7ZQ4aRipYA2ivO5m8WWYK0i4 +qsc+MCiQLt3nJHVtJeNyCdai3yfVBEyDQGi+7d+AHGIYbF6f/46tfNwQi7JtobTa +M2eCl3SO7qLbytjZl/avnXrC7Zimuc2gzed4cFO7uPUCgYAo66MLtRWLdHqPDTaa +WhSQZkdKfZxlWNP6XIpBgHnYDIQGZddrjv+zZVFRxLCduh1v8xybbSDKwRkGuXVb +eTQHP2Nc5XsOopCSsDP0v0dUxaOu14C0jJJG2E+EhJsWJ2Eua7o40LEIX2WY7N7f +UqR3bLO5Qh/1OOwJj5WbpzkMwA== +-END PRIVATE KEY- -- 2.17.1
[PATCH v4 1/3] configs: ns3: enable FIT config
Enable FIT config for NS3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index ab26617158..0e078f3244 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -5,6 +5,11 @@ CONFIG_SYS_TEXT_BASE=0xFF00 CONFIG_ENV_SIZE=0x8 CONFIG_NR_DRAM_BANKS=2 CONFIG_OF_BOARD_SETUP=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x2000 +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_LOGLEVEL=7 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y -- 2.17.1
[PATCH v4 2/3] board: ns3: add FIT image its file
From: Pramod Kumar
Add FIT image its file.
Signed-off-by: Pramod Kumar
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
board/broadcom/bcmns3/fit/multi.its | 59 +
1 file changed, 59 insertions(+)
create mode 100644 board/broadcom/bcmns3/fit/multi.its
diff --git a/board/broadcom/bcmns3/fit/multi.its
b/board/broadcom/bcmns3/fit/multi.its
new file mode 100644
index 00..a0ff4bc908
--- /dev/null
+++ b/board/broadcom/bcmns3/fit/multi.its
@@ -0,0 +1,59 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Various kernels, ramdisks and FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Linux kernel Image";
+ data = /incbin/("./Image");
+ type = "kernel";
+ arch = "arm64";
+ os = "linux";
+ compression = "none";
+ load = <0x8008>;
+ entry = <0x8008>;
+ hash-1 {
+ algo = "sha1";
+ };
+ signature {
+ algo = "sha1,rsa2048";
+ key-name-hint = "dev";
+ };
+ };
+
+ fdt-ns3 {
+ description = "FDT Blob";
+ data = /incbin/("./dt-blob.bin");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ hash-1 {
+ algo = "sha1";
+ };
+ signature {
+ algo = "sha1,rsa2048";
+ key-name-hint = "dev";
+ };
+ };
+ };
+
+ configurations {
+ default = "config-ns3";
+ config-ns3 {
+ description = "FIT1 configuration";
+ kernel = "kernel";
+ fdt = "fdt-ns3";
+ signature {
+ algo = "sha1,rsa2048";
+ key-name-hint = "dev";
+ sign-images = "fdt", "kernel";
+ };
+ };
+ };
+};
--
2.17.1
[PATCH v4 0/3] add FIT image support for broadcom NS3 soc
This is third patch set series prepared on top of second
patch set ("add basic driver support for broadcom NS3 soc").
This patch set enables FIT config and add FIT image its
files and keys.
Changes from v3:
- Rebase on top of second patch set.
Changes from v2:
- Rebase on top of second patch set.
Changes from v1:
-Address self review comments,
Rebase on top of latest uboot and updated previous patch series.
Pramod Kumar (2):
board: ns3: add FIT image its file
board: ns3: add development keys used in FIT
Rayagonda Kokatanur (1):
configs: ns3: enable FIT config
board/broadcom/bcmns3/fit/keys/dev.crt | 21 +
board/broadcom/bcmns3/fit/keys/dev.key | 28
board/broadcom/bcmns3/fit/multi.its| 59 ++
configs/bcm_ns3_defconfig | 5 +++
4 files changed, 113 insertions(+)
create mode 100644 board/broadcom/bcmns3/fit/keys/dev.crt
create mode 100644 board/broadcom/bcmns3/fit/keys/dev.key
create mode 100644 board/broadcom/bcmns3/fit/multi.its
--
2.17.1
[PATCH v5 2/7] dt-bindings: pinctrl: add ns3 pads definition
Add NS3 pads definitions. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- .../dt-bindings/pinctrl/brcm,pinctrl-ns3.h| 41 +++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h diff --git a/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h b/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h new file mode 100644 index 00..81ebd58ca5 --- /dev/null +++ b/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + */ + +#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ +#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ + +/* Alternate functions available in MUX controller */ +#define MODE_NITRO 0 +#define MODE_NAND 1 +#define MODE_PNOR 2 +#define MODE_GPIO 3 + +/* Pad configuration attribute */ +#define PAD_SLEW_RATE_ENA BIT(0) +#define PAD_SLEW_RATE_ENA_MASK BIT(0) + +#define PAD_DRIVE_STRENGTH_2_MA(0 << 1) +#define PAD_DRIVE_STRENGTH_4_MABIT(1) +#define PAD_DRIVE_STRENGTH_6_MA(2 << 1) +#define PAD_DRIVE_STRENGTH_8_MA(3 << 1) +#define PAD_DRIVE_STRENGTH_10_MA (4 << 1) +#define PAD_DRIVE_STRENGTH_12_MA (5 << 1) +#define PAD_DRIVE_STRENGTH_14_MA (6 << 1) +#define PAD_DRIVE_STRENGTH_16_MA (7 << 1) +#define PAD_DRIVE_STRENGTH_MASK(7 << 1) + +#define PAD_PULL_UP_ENABIT(4) +#define PAD_PULL_UP_ENA_MASK BIT(4) + +#define PAD_PULL_DOWN_ENA BIT(5) +#define PAD_PULL_DOWN_ENA_MASK BIT(5) + +#define PAD_INPUT_PATH_DIS BIT(6) +#define PAD_INPUT_PATH_DIS_MASKBIT(6) + +#define PAD_HYSTERESIS_ENA BIT(7) +#define PAD_HYSTERESIS_ENA_MASKBIT(7) + +#endif -- 2.17.1
[PATCH v5 4/7] configs: ns3: enable mmc commands
Enable mmc commands for NS3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 432237b56d..a1ee866e54 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -14,6 +14,8 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot> " CONFIG_SYS_XTRACE="n" +CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_SWRITE=y # CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SOURCE is not set CONFIG_OF_CONTROL=y -- 2.17.1
[PATCH v5 7/7] configs: ns3: enable sp805 watchdog driver
Enable sp805 watchdog driver for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 66fbdb20d6..ab26617158 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -37,5 +37,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y CONFIG_FAT_WRITE=y CONFIG_SPL_OF_LIBFDT=y -- 2.17.1
[PATCH v5 5/7] configs: ns3: enable gpt commands
Enable gpt commands for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index a1ee866e54..0f23f30db2 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -14,6 +14,8 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot> " CONFIG_SYS_XTRACE="n" +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_MMC=y CONFIG_CMD_MMC_SWRITE=y # CONFIG_CMD_PINMUX is not set -- 2.17.1
[PATCH v5 3/7] configs: ns3: enable BCM IPROC mmc driver
Enable BCM IPROC mmc driver ns3. Enable DMA for MMC Host to have better reads and writes. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 328b0e2b4e..432237b56d 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -21,6 +21,10 @@ CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_CCF=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_IPROC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y -- 2.17.1
[PATCH v5 6/7] configs: ns3: enable EXT4 and FAT fs support
Enable EXT4 and FAT fs support for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 0f23f30db2..66fbdb20d6 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -20,6 +20,10 @@ CONFIG_CMD_MMC=y CONFIG_CMD_MMC_SWRITE=y # CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SOURCE is not set +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +# CONFIG_DOS_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_DM=y @@ -33,4 +37,5 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_FAT_WRITE=y CONFIG_SPL_OF_LIBFDT=y -- 2.17.1
[PATCH v5 0/7] add basic driver support for broadcom NS3 soc
This is the second patch set series prepared on top of the
first patch set ("add initial support for broadcom NS3 soc").
This patch set will add following,
-defconfig options for basic device like pinctrl,
gpio, mmc, qspi, wdt, i2c and pcie.
-start wdt service
-Enable GPT commands
-Enable EXT4 and FAT fs support
Changes from v4:
-Rebase on top of first patch set.
Changes from v3:
-Rebase on top of first patch set.
Changes from v2:
-Address review comments from Stefan Rose,
Remove patch to stop and start wdt service from board files.
Instead define CONFIG_WATCHDOG defconfig which takes care of
wdt reset for every 1s.
Changes from v1:
-Address review comments from Simon,
-include instead of and
-remove include as its not required
-Use if() instead of #if def
-rearrange code in start_wdt()
-remove #else part of #ifdef CONFIG_DT
-Address review comments from Tom and Simon,
Remove all dt patches as uboot should use the same dt file from Linux.
Rayagonda Kokatanur (7):
configs: ns3: enable pinctrl driver
dt-bindings: pinctrl: add ns3 pads definition
configs: ns3: enable BCM IPROC mmc driver
configs: ns3: enable mmc commands
configs: ns3: enable gpt commands
configs: ns3: enable EXT4 and FAT fs support
configs: ns3: enable sp805 watchdog driver
configs/bcm_ns3_defconfig | 18
.../dt-bindings/pinctrl/brcm,pinctrl-ns3.h| 41 +++
2 files changed, 59 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h
--
2.17.1
[PATCH v5 1/7] configs: ns3: enable pinctrl driver
Enable pinctrl driver for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 9adb44cb51..328b0e2b4e 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -14,12 +14,15 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot> " CONFIG_SYS_XTRACE="n" +# CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SOURCE is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_CCF=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPL_OF_LIBFDT=y -- 2.17.1
[PATCH v5 15/15] MAINTAINERS: update maintainers for broadcom ns3 platform
Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3). Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- MAINTAINERS | 15 +++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2a281a9a0f..f96993b84c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -937,6 +937,21 @@ S: Maintained F: drivers/spmi/ F: include/spmi/ +TARGET_BCMNS3 +M: Bharat Gooty +M: Rayagonda Kokatanur +S: Maintained +F: board/broadcom/bcmns3/ +F: doc/README.bcmns3 +F: configs/bcm_ns3_defconfig +F: include/configs/bcm_ns3.h +F: include/dt-bindings/memory/bcm-ns3-mc.h +F: arch/arm/Kconfig +F: arch/arm/dts/ns3-board.dts +F: arch/arm/dts/ns3.dtsi +F: arch/arm/cpu/armv8/bcmns3 +F: arch/arm/include/asm/arch-bcmns3/ + TDA19988 HDMI ENCODER M: Liviu Dudau S: Maintained -- 2.17.1
[PATCH v5 14/15] doc: add README doc for bcmns3 platform
Add README doc for bcmns3 platform. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- doc/README.bcmns3 | 74 +++ 1 file changed, 74 insertions(+) create mode 100644 doc/README.bcmns3 diff --git a/doc/README.bcmns3 b/doc/README.bcmns3 new file mode 100644 index 00..c51f91471f --- /dev/null +++ b/doc/README.bcmns3 @@ -0,0 +1,74 @@ +BCMNS3 QSPI memory layout += + +BCMNS3 has total 8MB non-volatile SPI flash memory. It is used to store +different images like fip.bin, nitro firmware, DDR shmo value and other backup +images. + +Following is the QSPI flash memory layout. + +/* QSPI layout + * |---|->0x00 + * | | + * | | + * |fip.bin| + * | 2MB | + * | | + * ~ ~ + * ~ ~ + * | | + * | | + * | | + * |---|->0x20 + * | | + * | | + * | | + * | fip.bin (Mirror)| + * |2MB| + * ~ ~ + * ~ ~ + * | | + * | | + * | | + * |---|->0x40 + * | | + * | Nitro NS3 Config | + * | 1.5M | + * | | + * ~ ~ + * ~ ~ + * | | + * |---|->0x58 + * | Nitro NS3 Config | + * | 1.5M | + * |(Mirror) | + * ~ ~ + * ~ ~ + * | | + * |---|->0x70 + * | Nitro NS3 bspd Config | + * |64KB | + * ~ ~ + * ~ ~ + * | | + * |---|->0x71 + * | Nitro NS3 bspd Config | + * |64KB | + * ~ (Mirror)~ + * ~ ~ + * | | + * |---|->0x72 + * |SHMOO | + * |64KB | + * | | + * ~ ~ + * ~ ~ + * |---|->0x73 + * |Meta Data | + * |832KB | + * | | + * ~ ~ + * ~ ~ + * | | + * |---| + */ -- 2.17.1
[PATCH v5 13/15] include/configs: ns3: add support for flashing images
From: Bharat Gooty
Add support for flashing images into QSPI and eMMC.
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
include/configs/bcm_ns3.h | 491 +-
1 file changed, 490 insertions(+), 1 deletion(-)
diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h
index 7aa5cc2dbb..039f4d6759 100644
--- a/include/configs/bcm_ns3.h
+++ b/include/configs/bcm_ns3.h
@@ -290,6 +290,483 @@
"run bootcmd_usb || "\
"run bootcmd_pxe"
+/* Flashing commands */
+#define TFTP_QSPI_PARAM \
+ "fip_qspi_addr=0x0\0"\
+ "fip_qspi_mirror_addr=0x20\0"\
+ "loadaddr=0x9000\0"\
+ "tftpblocksize=1468\0"\
+ "qspi_flash_fip=fip\0"\
+
+/* Flash fit_GPT partition to eMMC */
+#define MMC_FLASH_FIT_GPT \
+ "mmc_flash_gpt="\
+ "if mmc dev ${sd_device_number}; then "\
+ "else "\
+ "echo [mmc_flash_gpt] mmc dev ${sd_device_number} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if gpt write mmc ${sd_device_number} ${fit_partitions}; then "\
+ "else "\
+ "echo [mmc_flash_gpt] gpt write ${fit_partitions} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi \0"
+
+#define MMC_FLASH_IMAGE_RSA \
+ "mmc_flash_image_rsa="\
+ "if mmc dev ${sd_device_number}; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] mmc dev ${sd_device_number} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if gpt setenv mmc ${sd_device_number} ${fit_image}; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] gpt setenv ${fit_image} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if tftp ${loadaddr} ${tftp_dir}${fit_image}; then "\
+ "if test ${fit_image} = Image_rsa.img; then "\
+ "if setenv tftp_fit_image yes; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] "\
+ "setenv tftp_fit_image to yes"\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "fi;"\
+ "else "\
+ "if test ${fit_image} = Image_rsa.img; then "\
+ "echo [mmc_flash_image_rsa] tftp "\
+ "${tftp_dir}${fit_image} ** FAILED **;"\
+ "else "\
+ "if test ${tftp_fit_image} = yes; then "\
+ "if mmc write ${loadaddr} "\
+ "${gpt_partition_addr} "\
+ "${fileblocks}; then "\
+ "else "\
+ "echo "\
+ "[mmc_flash_image_rsa] "\
+ "mmc write "\
+ "${gpt_partition_addr} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "else "\
+ "echo [mmc_flash_image_rsa] tftp "\
+ "${tftp_dir}${fit_image} "\
+ "** FAILED **;"\
+ "fi;"\
+ "fi;"\
+ "exit;"\
+ "fi;"\
+ "if math add filesize filesize 1FF; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] math add command ** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if math div fileblocks filesize 200; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] math div command ** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if mmc write ${loadaddr} ${gpt_partition_addr} ${fileblocks}; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] mmc write ${gpt_partition_addr} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+
[PATCH v5 11/15] board: ns3: limit U-boot relocation within 16MB memory
From: Bharat Kumar Reddy Gooty
By default relocation happens to a higher address of DDR,
i.e, DDR start + DDR size.
U-Boot shall be used to collect the ramdump.
Restrict U-Boot to use only the 16MB memory, so that this
memory can be reserved. Limit relocation to happen within
16MB memory, start 0xFF00_ and end 0x1__
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
board/broadcom/bcmns3/ns3.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 6b7ef04341..a04616b10e 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -144,6 +144,11 @@ static int mem_info_parse_fixup(void *fdt)
int board_init(void)
{
+ /* Setup memory using "memory" node from DTB */
+ if (fdtdec_setup_mem_size_base() != 0)
+ return -EINVAL;
+ fdtdec_setup_memory_banksize();
+
if (bl33_info->version != BL33_INFO_VERSION)
printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
@@ -157,19 +162,30 @@ int board_late_init(void)
int dram_init(void)
{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
+ /*
+* Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_.
+* So that relocation happens with in the last 16MB memory.
+*/
+ gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
+ gd->ram_size = (unsigned long)SZ_16M;
return 0;
}
int dram_init_banksize(void)
{
- fdtdec_setup_memory_banksize();
+ gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
+ gd->bd->bi_dram[0].size = SZ_16M;
return 0;
}
+/* Limit RAM used by U-Boot to the DDR first bank End region */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return BCM_NS3_MEM_END;
+}
+
void reset_cpu(ulong level)
{
u32 reset_level, strap_val;
--
2.17.1
[PATCH v5 09/15] dt-bindings: memory: ns3: add ddr memory definition
Add ddr memory definitions. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- include/dt-bindings/memory/bcm-ns3-mc.h | 31 - 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index fe669e2f87..84795ec27a 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -7,7 +7,8 @@ #define DT_BINDINGS_BCM_NS3_MC_H /* - * Reserved Memory Map : SHMEM & TZDRAM. + * ++--+ 0x8b00 + * | NITRO CRASH DUMP | 32MB * ++--+ 0x8d00 * | SHMEM (NS) | 16 MB * +---+ 0x8e00 @@ -20,6 +21,10 @@ * +---+ 0x8f10 */ +#define BCM_NS3_MEM_NITRO_CRASH_START 0x8ae0 +#define BCM_NS3_MEM_NITRO_CRASH_LEN0x21f +#define BCM_NS3_MEM_NITRO_CRASH_SIZE 0x220 + #define BCM_NS3_MEM_SHARE_START0x8d00 #define BCM_NS3_MEM_SHARE_LEN 0x020f @@ -31,4 +36,28 @@ #define BCM_NS3_MEM_CRMU_PT_START 0x88000 #define BCM_NS3_MEM_CRMU_PT_LEN0x20 +/* default memory starting address and length */ +#define BCM_NS3_MEM_START 0x8000UL +#define BCM_NS3_MEM_LEN0x8000UL +#define BCM_NS3_MEM_END(BCM_NS3_MEM_START + BCM_NS3_MEM_LEN) + +/* memory starting address and length for BANK_1 */ +#define BCM_NS3_BANK_1_MEM_START 0x88000UL +#define BCM_NS3_BANK_1_MEM_LEN 0x18000UL + +/* memory layout information */ +#define BCM_NS3_DDR_INFO_BASE 0x8f22 +#define BCM_NS3_DDR_INFO_RSVD_LEN 0x1000 +#define BCM_NS3_DDR_INFO_LEN 73 +#define BCM_NS3_DDR_INFO_SIG 0x42434d44 +#define BCM_NS3_MAX_NR_BANKS 4 + +#define BCM_NS3_GIC_LPI_BASE 0x8ad7 +#define BCM_NS3_MEM_RSVE_STARTBCM_NS3_GIC_LPI_BASE +#define BCM_NS3_MEM_RSVE_END ((BCM_NS3_MEM_ELOG_START + \ + BCM_NS3_MEM_ELOG_LEN) - \ + BCM_NS3_MEM_RSVE_START) + +#define BCM_NS3_CRMU_PGT_START0x88000UL +#define BCM_NS3_CRMU_PGT_SIZE 0x10 #endif -- 2.17.1
[PATCH v5 08/15] configs: ns3: enable GIC_V3 ITS
Enables the Generic Interrupt Controller (GIC) V3 Interrupt Translation Service (ITS) Locality-specific Peripheral Interrupts (LPI) configuration table and LPI table. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Bharat Kumar Reddy Gooty Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 7e51a926f7..040e753f9f 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_BCMNS3=y CONFIG_SYS_TEXT_BASE=0xFF00 CONFIG_ENV_SIZE=0x8 -- 2.17.1
[PATCH v5 12/15] include/configs: ns3: add env variables for Linux boot
From: Bharat Gooty
Add env variables and commands for booting Linux.
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
include/configs/bcm_ns3.h | 294 ++
1 file changed, 294 insertions(+)
diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h
index 02a736456a..7aa5cc2dbb 100644
--- a/include/configs/bcm_ns3.h
+++ b/include/configs/bcm_ns3.h
@@ -37,4 +37,298 @@
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
+/*
+ * Increase max uncompressed/gunzip size, keeping size same as EMMC linux
+ * partition.
+ */
+#define CONFIG_SYS_BOOTM_LEN 0x0180
+
+/* Env configuration */
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART0
+
+/* Access eMMC Boot_1 and Boot_2 partitions */
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* enable 64-bit PCI resources */
+#define CONFIG_SYS_PCI_64BIT 1
+
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
+#define MAX_CPUS "max_cpus=maxcpus=8\0"
+#define OS_LOG_LEVEL "log_level=loglevel=7\0"
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x68A1 " \
+ "earlyelog=" __stringify(ELOG_AP_UART_LOG_BASE) ",0x1 " \
+ "crashkernel=512M reboot=w\0"
+
+#define PCIE_ARGS "pcie_args=pci=pcie_bus_safe pcie_ports=native
vfio_pci.disable_idle_d3=1\0"
+
+#ifdef CONFIG_BCM_SF2_ETH
+#define ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0"
+#define NET_ARGS "bgmac_platform.ethaddr=${ethaddr} " \
+ "ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off"
+#else
+#define ETH_ADDR
+#define NET_ARGS
+#endif
+
+#define RESERVED_MEM "reserved_mem=memmap=0xff00$0x100\0"
+
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \
+ " ${max_cpus} ${log_level} ${reserved_mem}"
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS " " NET_ARGS "\0"
+
+#define UPDATEME_FLASH_PARAMS "bcm_compat_level=4\0" \
+ "bcm_need_recovery_rootfs=0\0" \
+ "bcm_bl_flash_pending_rfs_imgs=0\0"
+
+#define KERNEL_LOADADDR_CFG \
+ "fit_image_loadaddr=0x9000\0" \
+ "dtb_loadaddr=0x8200\0"
+
+#define INITRD_ARGS "initrd_args=root=/dev/ram rw\0"
+#define INITRD_LOADADDR "initrd_loadaddr=0x9200\0"
+#define INITRD_IMAGE "initrd_image=rootfs-lake-bcm958742t.cpio.gz\0"
+#define MMC_DEV "sd_device_number=0\0"
+#define EXEC_STATE "exec_state=normal\0"
+
+#define EXT4RD_ARGS "ext4rd_args="\
+ "root=/dev/mmcblk${sd_device_number}p${gpt_partition_entry} rw
rootwait\0"
+
+#define WDT_CNTRL "wdt_enable=1\0" \
+ "wdt_timeout_sec=0\0"
+
+#define ELOG_SETUP \
+ "mbox0_addr=0x66424024\0"\
+ "elog_setup="\
+ "if logsetup -s ${mbox0_addr}; then "\
+ "else "\
+ "echo ELOG is not supported by this version of the MCU patch.;"\
+ "exit;"\
+ "fi;"\
+ "if logsetup -c ${mbox0_addr}; then "\
+ "echo ELOG is ready;"\
+ "else "\
+ "echo ELOG is supported, but is not set up.;"\
+ "echo Getting setup file from the server ${serverip}...;"\
+ "if tftp ${tftp_dir}elog_src.txt; then "\
+ "echo Setting up ELOG. Please wait...;"\
+ "if logsetup ${loadaddr} ${mbox0_addr} ${filesize}; "\
+ "then "\
+ "else "\
+ "echo [logsetup] ERROR.;"\
+ "fi;"\
+ "if logsetup -c ${mbox0_addr}; then "\
+ "echo ELOG is READY.;"\
+ "else "\
+ "echo ELOG is NOT SET UP.;"\
+ "fi;"\
+ "else "\
+ "echo ELOG setup file is not available on the server.;"\
+ "fi;"\
+ "fi \0"
+
+/* eMMC partition for FIT images */
+#define FIT_MMC_PARTITION \
+ "fit_partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=env,size=512K,uuid=${uuid_gpt_env};" \
+ "name=Image_rsa.img,size=24MiB,uuid=${uuid_gpt_linux};" \
+ "name=Image1_rsa.img,size=24MiB,uuid=${uuid_gpt_linux1};" \
+ "name
[PATCH v5 10/15] board: ns3: define ddr memory layout
Add both DRAM banks memory information and
the corresponding MMU page table mappings.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
arch/arm/dts/ns3-board.dts | 23
board/broadcom/bcmns3/ns3.c | 106 ++--
configs/bcm_ns3_defconfig | 2 +
3 files changed, 127 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts
index 54e56879a5..4e0966a132 100644
--- a/arch/arm/dts/ns3-board.dts
+++ b/arch/arm/dts/ns3-board.dts
@@ -5,6 +5,29 @@
/dts-v1/;
+#include
+
+/*
+ * Single mem reserve region which includes the following:
+ * Components name Start Addr Size
+ *
+ * GIC LPI tables 0x8ad7_ 0x0009_
+ * Nitro FW0x8ae0_ 0x0020_
+ * Nitro Crash dump0x8b00_ 0x0200_
+ * OPTEE OS0x8d00_ 0x0200_
+ * BL31 services 0x8f00_ 0x0010_
+ * Tmon0x8f10_ 0x_1000
+ * LPM/reserved0x8f10_1000 0x_1000
+ * ATF to Bl33 info0x8f10_2000 0x_1000
+ * ATF error logs 0x8f10_3000 0x0001_
+ * Error log parser0x8f11_3000 0x0010_
+ */
+
+/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END;
+
+/* CRMU page tables */
+/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE;
+
#include "ns3.dtsi"
/ {
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index feb940d9a9..6b7ef04341 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -5,15 +5,41 @@
*/
#include
+#include
#include
#include
#include
#include
#include
+#include
/* Default reset-level = 3 and strap-val = 0 */
#define L3_RESET 30
+#define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
+
+/*
+ * ns3_dram_bank - DDR bank details
+ *
+ * @start: DDR bank start address
+ * @len: DDR bank length
+ */
+struct ns3_dram_bank {
+ u64 start[BCM_NS3_MAX_NR_BANKS];
+ u64 len[BCM_NS3_MAX_NR_BANKS];
+};
+
+/*
+ * ns3_dram_hdr - DDR header info
+ *
+ * @sig: DDR info signature
+ * @bank: DDR bank details
+ */
+struct ns3_dram_hdr {
+ u32 sig;
+ struct ns3_dram_bank bank;
+};
+
static struct mm_region ns3_mem_map[] = {
{
.virt = 0x0UL,
@@ -23,9 +49,15 @@ static struct mm_region ns3_mem_map[] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
- .virt = 0x8000UL,
- .phys = 0x8000UL,
- .size = 0x8000UL,
+ .virt = BCM_NS3_MEM_START,
+ .phys = BCM_NS3_MEM_START,
+ .size = BCM_NS3_MEM_LEN,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = BCM_NS3_BANK_1_MEM_START,
+ .phys = BCM_NS3_BANK_1_MEM_START,
+ .size = BCM_NS3_BANK_1_MEM_LEN,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -44,6 +76,72 @@ DECLARE_GLOBAL_DATA_PTR;
*/
struct bl33_info *bl33_info __section(".data");
+/*
+ * Run modulo 256 checksum calculation and return the calculated checksum
+ */
+static u8 checksum_calc(u8 *p, unsigned int len)
+{
+ unsigned int i;
+ u8 chksum = 0;
+
+ for (i = 0; i < len; i++)
+ chksum += p[i];
+
+ return chksum;
+}
+
+/*
+ * This function parses the memory layout information from a reserved area in
+ * DDR, and then fix up the FDT before passing it to Linux.
+ *
+ * In the case of error, do nothing and the default memory layout in DT will
+ * be used
+ */
+static int mem_info_parse_fixup(void *fdt)
+{
+ struct ns3_dram_hdr hdr;
+ u32 *p32, i, nr_banks;
+ u64 *p64;
+
+ /* validate signature */
+ p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
+ hdr.sig = *p32;
+ if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
+ printf("DDR info signature 0x%x invalid\n", hdr.sig);
+ return -EINVAL;
+ }
+
+ /* run checksum test to validate data */
+ if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
+ printf("Checksum on DDR info failed\n");
+ return -EINVAL;
+ }
+
+ /* parse information for each bank */
+ nr_banks = 0;
+ for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
+ /* skip banks with a length of zero */
+ p64 = (u64 *)BANK_OFFSET(i);
+ if (*(p64 + 1) == 0)
+ continue;
+
+ hdr.bank.start[i] = *p64;
+ hdr.bank.len[i] = *(p64 + 1);
+
+ printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
+
[PATCH v5 04/15] dt-bindings: memory: ns3: add memory definitions
Add NS3 memory definitions. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- Changes from v4: -Address self review comments, Correction u-boot to U-Boot. include/dt-bindings/memory/bcm-ns3-mc.h | 34 + 1 file changed, 34 insertions(+) create mode 100644 include/dt-bindings/memory/bcm-ns3-mc.h diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h new file mode 100644 index 00..fe669e2f87 --- /dev/null +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Broadcom + */ + +#ifndef DT_BINDINGS_BCM_NS3_MC_H +#define DT_BINDINGS_BCM_NS3_MC_H + +/* + * Reserved Memory Map : SHMEM & TZDRAM. + * ++--+ 0x8d00 + * | SHMEM (NS) | 16 MB + * +---+ 0x8e00 + * || TEE_RAM(S)| 4MB + * + TZDRAM +--+ 0x8e40 + * || TA_RAM(S) | 12MB + * ++--+ 0x8f00 + * | BL31 + TMON + LPM | + * | memory | 1MB + * +---+ 0x8f10 + */ + +#define BCM_NS3_MEM_SHARE_START0x8d00 +#define BCM_NS3_MEM_SHARE_LEN 0x020f + +/* ATF/U-boot/Linux error logs */ +#define BCM_NS3_MEM_ELOG_START 0x8f113000 +#define BCM_NS3_MEM_ELOG_LEN 0x0010 + +/* CRMU Page table memroy */ +#define BCM_NS3_MEM_CRMU_PT_START 0x88000 +#define BCM_NS3_MEM_CRMU_PT_LEN0x20 + +#endif -- 2.17.1
[PATCH v5 05/15] board: ns3: add api to save boot parameters passed from BL31
From: Abhishek Shah
Add API to save boot parameters passed from BL31
Use assembly implementation of save_boot_params instead of c function.
Because generally ATF does not set up SP_EL2 on exiting.
Thus, usage of a C function immediately after exiting with no stack
setup done by ATF explicitly, may cause SP_EL2 to be not sane,
which in turn causes a crash if this boot was not lucky to get
an SP_EL2 in valid range. Replace C implementation with assembly one
which does not use stack this early, and let u-boot to set up its stack
later.
Signed-off-by: Abhishek Shah
Signed-off-by: Rajesh Ravi
Signed-off-by: Vladimir Olovyannikov
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v4:
-Address self review comments,
Correction- u-boot to U-Boot.
arch/arm/cpu/armv8/bcmns3/lowlevel.S | 9 +++
arch/arm/include/asm/arch-bcmns3/bl33_info.h | 26
board/broadcom/bcmns3/ns3.c | 10
3 files changed, 45 insertions(+)
create mode 100644 arch/arm/include/asm/arch-bcmns3/bl33_info.h
diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S
b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
index 6709c9a188..bf1a17ab03 100644
--- a/arch/arm/cpu/armv8/bcmns3/lowlevel.S
+++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
@@ -87,3 +87,12 @@ ENTRY(__asm_flush_l3_dcache)
mov lr, x29
ret
ENDPROC(__asm_flush_l3_dcache)
+
+ENTRY(save_boot_params)
+/*
+ * void set_boot_params(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3)
+ */
+ adr x4, bl33_info
+ str x0, [x4]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
diff --git a/arch/arm/include/asm/arch-bcmns3/bl33_info.h
b/arch/arm/include/asm/arch-bcmns3/bl33_info.h
new file mode 100644
index 00..bbc95b0186
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcmns3/bl33_info.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#ifndef BL33_INFO_H
+#define BL33_INFO_H
+#include
+
+/* Increase version number each time this file is modified */
+#define BL33_INFO_VERSION 1
+
+struct chip_info {
+ unsigned int chip_id;
+ unsigned int rev_id;
+};
+
+struct bl33_info {
+ unsigned int version;
+ struct chip_info chip;
+};
+
+extern struct bl33_info *bl33_info;
+
+#endif
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index e38156723c..e51263f85e 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
static struct mm_region ns3_mem_map[] = {
{
@@ -33,8 +34,17 @@ struct mm_region *mem_map = ns3_mem_map;
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Force the bl33_info to the data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+struct bl33_info *bl33_info __section(".data");
+
int board_init(void)
{
+ if (bl33_info->version != BL33_INFO_VERSION)
+ printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
+
return 0;
}
--
2.17.1
[PATCH v5 07/15] board: ns3: program GIC LPI tables
U-boot programs the GIC LPI configuration tables and enables
the LPI table.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
board/broadcom/bcmns3/ns3.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 6a72e28494..feb940d9a9 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
#include
#include
@@ -91,3 +92,12 @@ void reset_cpu(ulong level)
psci_system_reset();
}
}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ gic_lpi_tables_init();
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
--
2.17.1
[PATCH v5 03/15] configs: ns3: enable clock subsystem
Enable clock subsystem for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index a81541e394..7e51a926f7 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -16,5 +16,7 @@ CONFIG_SYS_XTRACE="n" CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_CCF=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y -- 2.17.1
[PATCH v5 06/15] board: ns3: default reset type to L3
Default "reset" from U-Boot to L3 reset.
"reset" command with argument will trigger L1 reset.
Signed-off-by: Rajesh Ravi
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v4:
-Address review comments from Simon,
Move hash defines at top of file and add comment,
Correct spelling mistakes.
board/broadcom/bcmns3/ns3.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index e51263f85e..6a72e28494 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -10,6 +10,9 @@
#include
#include
+/* Default reset-level = 3 and strap-val = 0 */
+#define L3_RESET 30
+
static struct mm_region ns3_mem_map[] = {
{
.virt = 0x0UL,
@@ -68,7 +71,23 @@ int dram_init_banksize(void)
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(ulong level)
{
- psci_system_reset();
+ u32 reset_level, strap_val;
+
+ /* Default reset type is L3 reset */
+ if (!level) {
+ /*
+* Encoding: U-Boot reset command expects decimal argument,
+* Boot strap val: Bits[3:0]
+* reset level: Bits[7:4]
+*/
+ strap_val = L3_RESET % 10;
+ level = L3_RESET / 10;
+ reset_level = level % 10;
+ psci_system_reset2(reset_level, strap_val);
+ } else {
+ /* U-Boot cmd "reset" with any arg will trigger L1 reset */
+ psci_system_reset();
+ }
}
--
2.17.1
[PATCH v5 02/15] arm: cpu: armv8: add L3 memory flush support
Add L3 memory flush support for NS3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/bcmns3/Makefile | 5 ++ arch/arm/cpu/armv8/bcmns3/lowlevel.S | 89 3 files changed, 95 insertions(+) create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 2e48df0eb9..7e33a183d5 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o +obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile new file mode 100644 index 00..a35e29d11a --- /dev/null +++ b/arch/arm/cpu/armv8/bcmns3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 Broadcom. + +obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S new file mode 100644 index 00..6709c9a188 --- /dev/null +++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + * + */ + +#include +#include + +hnf_pstate_poll: + /* x0 has the desired status, return 0 for success, 1 for timeout +* clobber x1, x2, x3, x4, x6, x7 +*/ + mov x1, x0 + mov x7, #0 /* flag for timeout */ + mrs x3, cntpct_el0 /* read timer */ + mov w0, #600 + mov w6, #1000 + mul w0, w0, w6 + add x3, x3, x0 /* timeout after 100 microseconds */ + mov x0, #0x18 + movkx0, #0x6120, lsl #16/* HNF0_PSTATE_STATUS */ + mov w6, #4 /* HN-F node count */ +1: + ldr x2, [x0] + cmp x2, x1 /* check status */ + b.eq2f + mrs x4, cntpct_el0 + cmp x4, x3 + b.ls1b + mov x7, #1 /* timeout */ + b 3f +2: + add x0, x0, #0x1/* move to next node */ + subsw6, w6, #1 + cbnzw6, 1b +3: + mov x0, x7 + ret + +hnf_set_pstate: + /* x0 has the desired state, clobber x1, x2, x6 */ + mov x1, x0 + /* power state to SFONLY */ + mov w6, #4 /* HN-F node count */ + mov x0, #0x10 + movk x0, #0x6120, lsl #16 /* HNF0_PSTATE_REQ */ +1: /* set pstate to sfonly */ + ldr x2, [x0] + and x2, x2, #0xfffc /* & HNFPSTAT_MASK */ + orr x2, x2, x1 + str x2, [x0] + add x0, x0, #0x1/* move to next node */ + subsw6, w6, #1 + cbnzw6, 1b + + ret + +ENTRY(__asm_flush_l3_dcache) + /* +* Return status in x0 +*success 0 +*timeout 1 for setting SFONLY, 2 for FAM, 3 for both +*/ + mov x29, lr + mov x8, #0 + + dsb sy + mov x0, #0x1/* HNFPSTAT_SFONLY */ + bl hnf_set_pstate + + mov x0, #0x4/* SFONLY status */ + bl hnf_pstate_poll + cbz x0, 1f + mov x8, #1 /* timeout */ +1: + dsb sy + mov x0, #0x3/* HNFPSTAT_FAM */ + bl hnf_set_pstate + + mov x0, #0xc/* FAM status */ + bl hnf_pstate_poll + cbz x0, 1f + add x8, x8, #0x2 +1: + mov x0, x8 + mov lr, x29 + ret +ENDPROC(__asm_flush_l3_dcache) -- 2.17.1
[PATCH v5 00/15] add initial support for broadcom NS3 soc
This patch series adds initial support for Broadcom Northstar 3 SoC. NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors targeting a broad range of networking applications. Changes from v4: -Address review comments from Simon, Move hash defines at top of file and add comment, Correct spelling mistakes. -Address self review comments, Correction u-boot to U-Boot. Changes from v3: -Address review comments from Simon, Update commit message ie corrections, expand acronyms etc, Use lower-case hex number, Correct spelling mistakes, Use a struct instead of ad-hoc pointer reading, Use error code and return errro upon failure, Check for return value, Move the documentation to /doc instead of in header file, Update new file doc/README.bcmns3 Use dt and a UCLASS_IRQ to get gic details instead of passing as arguments to function gic_lpi_tables_init(), -Address review comments from Peter Tyser, Fix accidental changes Changes from v2: -Address review comments from Simon, Remove clock dt file inorder to maintain same dt file between uboot and linux. -Address self review comments, Rearrange the headers. Update MAINTAINERS file with dt file change. Changes from v1: -Address review comments from Marek Vasut, Split the series into samller and logical series like core, driver. -Address review comments from Simon Glass, Update MAINTAINERS file. Abhishek Shah (1): board: ns3: add api to save boot parameters passed from BL31 Bharat Gooty (2): include/configs: ns3: add env variables for Linux boot include/configs: ns3: add support for flashing images Bharat Kumar Reddy Gooty (1): board: ns3: limit U-boot relocation within 16MB memory Rayagonda Kokatanur (11): board: ns3: add support for Broadcom Northstar 3 arm: cpu: armv8: add L3 memory flush support configs: ns3: enable clock subsystem dt-bindings: memory: ns3: add memory definitions board: ns3: default reset type to L3 board: ns3: program GIC LPI tables configs: ns3: enable GIC_V3 ITS dt-bindings: memory: ns3: add ddr memory definition board: ns3: define ddr memory layout doc: add README doc for bcmns3 platform MAINTAINERS: update maintainers for broadcom ns3 platform MAINTAINERS | 15 + arch/arm/Kconfig | 10 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/bcmns3/Makefile | 5 + arch/arm/cpu/armv8/bcmns3/lowlevel.S | 98 +++ arch/arm/dts/Makefile| 2 + arch/arm/dts/ns3-board.dts | 47 ++ arch/arm/dts/ns3.dtsi| 34 + arch/arm/include/asm/arch-bcmns3/bl33_info.h | 26 + board/broadcom/bcmns3/Kconfig| 15 + board/broadcom/bcmns3/Makefile | 5 + board/broadcom/bcmns3/ns3.c | 217 + configs/bcm_ns3_defconfig| 25 + doc/README.bcmns3| 74 ++ include/configs/bcm_ns3.h| 823 +++ include/dt-bindings/memory/bcm-ns3-mc.h | 63 ++ 16 files changed, 1460 insertions(+) create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S create mode 100644 arch/arm/dts/ns3-board.dts create mode 100644 arch/arm/dts/ns3.dtsi create mode 100644 arch/arm/include/asm/arch-bcmns3/bl33_info.h create mode 100644 board/broadcom/bcmns3/Kconfig create mode 100644 board/broadcom/bcmns3/Makefile create mode 100644 board/broadcom/bcmns3/ns3.c create mode 100644 configs/bcm_ns3_defconfig create mode 100644 doc/README.bcmns3 create mode 100644 include/configs/bcm_ns3.h create mode 100644 include/dt-bindings/memory/bcm-ns3-mc.h -- 2.17.1
[PATCH v5 01/15] board: ns3: add support for Broadcom Northstar 3
Add support for Broadcom Northstar 3 SoC.
NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors
targeting a broad range of networking applications.
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
arch/arm/Kconfig | 10 ++
arch/arm/dts/Makefile | 2 ++
arch/arm/dts/ns3-board.dts | 24 +
arch/arm/dts/ns3.dtsi | 34 ++
board/broadcom/bcmns3/Kconfig | 15
board/broadcom/bcmns3/Makefile | 5 +++
board/broadcom/bcmns3/ns3.c| 64 ++
configs/bcm_ns3_defconfig | 20 +++
include/configs/bcm_ns3.h | 40 +
9 files changed, 214 insertions(+)
create mode 100644 arch/arm/dts/ns3-board.dts
create mode 100644 arch/arm/dts/ns3.dtsi
create mode 100644 board/broadcom/bcmns3/Kconfig
create mode 100644 board/broadcom/bcmns3/Makefile
create mode 100644 board/broadcom/bcmns3/ns3.c
create mode 100644 configs/bcm_ns3_defconfig
create mode 100644 include/configs/bcm_ns3.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 86238524f7..c61bb1f108 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -732,6 +732,15 @@ config TARGET_BCMNS2
ARMv8 Cortex-A57 processors targeting a broad range of networking
applications.
+config TARGET_BCMNS3
+ bool "Support Broadcom NS3"
+ select ARM64
+ select BOARD_LATE_INIT
+ help
+ Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
+ ARMv8 Cortex-A72 processors targeting a broad range of networking
+ applications.
+
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
@@ -1896,6 +1905,7 @@ source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/broadcom/bcmns2/Kconfig"
+source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/eets/pdu001/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d839cb49b3..66e4e12f6d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -922,6 +922,8 @@ dtb-$(CONFIG_ARCH_BCM68360) += \
dtb-$(CONFIG_ARCH_BCM6858) += \
bcm968580xref.dtb
+dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
+
dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts
new file mode 100644
index 00..54e56879a5
--- /dev/null
+++ b/arch/arm/dts/ns3-board.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+/dts-v1/;
+
+#include "ns3.dtsi"
+
+/ {
+ model = "NS3 model";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/ns3.dtsi b/arch/arm/dts/ns3.dtsi
new file mode 100644
index 00..09098aac3a
--- /dev/null
+++ b/arch/arm/dts/ns3.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+ compatible = "brcm,ns3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000 0x0 0x8000>,
+ <0x8 0x8000 0x1 0x8000>;
+ };
+
+ hsls {
+ compatible = "simple-bus";
+ dma-ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x6890 0x1770>;
+
+ uart1: uart@11 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0011 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <2500>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/board/broadcom/bcmns3/Kconfig b/board/broadcom/bcmns3/Kconfig
new file mode 100644
index 00..8ce21f980d
--- /dev/null
+++ b/board/broadcom/bcmns3/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNS3
+
+config SYS_BOARD
+ default "bcmns3"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_SOC
+ default "bcmns3"
+
+config SYS_CONFIG_NAME
+ default "bcm_ns3"
+
+endif
diff --git a/board/broadcom/bcmns3/Makefile b/board/broadcom/bcmns3/Makefile
new file mode 100644
index 00..3404260148
--- /dev/null
+++ b/board/broadcom/bcmns3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
Re: [PATCH v4 14/15] doc: add README doc for bcmns3 platform
On Wed, Jul 15, 2020 at 6:59 PM Tom Rini wrote: > > On Fri, Jul 10, 2020 at 02:22:19PM +0530, Rayagonda Kokatanur wrote: > > > Add README doc for bcmns3 platform. > > > > Signed-off-by: Rayagonda Kokatanur > > --- > > doc/README.bcmns3 | 74 +++ > > 1 file changed, 74 insertions(+) > > create mode 100644 doc/README.bcmns3 > > Not blocking (as it looks like I should pick this up soon now) but this > really should be under doc/board/ somewhere as rST and linked from > doc/board/index.rst. Thanks Tom. I will take up this change later just to avoid last minute changes. Best regards, Rayagonda > > -- > Tom
[PATCH v4 2/2] configs: ns3: enable tee and optee driver
Enable tee and optee drivers. Signed-off-by: Vikas Gupta Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 0e078f3244..72015c6596 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -4,12 +4,12 @@ CONFIG_TARGET_BCMNS3=y CONFIG_SYS_TEXT_BASE=0xFF00 CONFIG_ENV_SIZE=0x8 CONFIG_NR_DRAM_BANKS=2 -CONFIG_OF_BOARD_SETUP=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_SIGNATURE_MAX_SIZE=0x2000 CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y CONFIG_LOGLEVEL=7 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y @@ -42,6 +42,9 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_TEE=y +CONFIG_OPTEE=y +# CONFIG_OPTEE_TA_AVB is not set CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_FAT_WRITE=y -- 2.17.1
[PATCH v4 1/2] drivers: tee: broadcom: add optee based bnxt fw load driver
From: Vikas Gupta
Add optee based bnxt fw load driver.
bnxt is Broadcom NetXtreme controller Ethernet card.
This driver is used to load bnxt firmware binary using OpTEE.
Signed-off-by: Vikas Gupta
Signed-off-by: Rayagonda Kokatanur
---
Changes from v3:
-Address review comments from Simon,
Rearrange code and remove while loop,
Add comments for function.
Changes from v2:
-Address review comments from Simon,
Remove own return code and use standard error code.
Take out common lines from different functions and move them
into common static function.
Remove include as its not required.
Move functions with printf from header file into c file.
drivers/tee/Kconfig| 1 +
drivers/tee/Makefile | 1 +
drivers/tee/broadcom/Kconfig | 7 ++
drivers/tee/broadcom/Makefile | 3 +
drivers/tee/broadcom/chimp_optee.c | 180 +
include/broadcom/chimp.h | 43 +++
6 files changed, 235 insertions(+)
create mode 100644 drivers/tee/broadcom/Kconfig
create mode 100644 drivers/tee/broadcom/Makefile
create mode 100644 drivers/tee/broadcom/chimp_optee.c
create mode 100644 include/broadcom/chimp.h
diff --git a/drivers/tee/Kconfig b/drivers/tee/Kconfig
index 5c0c89043f..5ca5a0836c 100644
--- a/drivers/tee/Kconfig
+++ b/drivers/tee/Kconfig
@@ -29,6 +29,7 @@ config SANDBOX_TEE
"avb" commands.
source "drivers/tee/optee/Kconfig"
+source "drivers/tee/broadcom/Kconfig"
endmenu
diff --git a/drivers/tee/Makefile b/drivers/tee/Makefile
index f72c68c09f..5c8ffdbce8 100644
--- a/drivers/tee/Makefile
+++ b/drivers/tee/Makefile
@@ -3,3 +3,4 @@
obj-y += tee-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox.o
obj-$(CONFIG_OPTEE) += optee/
+obj-y += broadcom/
diff --git a/drivers/tee/broadcom/Kconfig b/drivers/tee/broadcom/Kconfig
new file mode 100644
index 00..ce95072d4e
--- /dev/null
+++ b/drivers/tee/broadcom/Kconfig
@@ -0,0 +1,7 @@
+config CHIMP_OPTEE
+ bool "Enable secure ChiMP firmware loading"
+ depends on OPTEE
+ default y
+ help
+ This driver is used to load bnxt firmware binary using OpTEE.
+ bnxt is Broadcom NetXtreme controller Ethernet card.
diff --git a/drivers/tee/broadcom/Makefile b/drivers/tee/broadcom/Makefile
new file mode 100644
index 00..cb3cef16df
--- /dev/null
+++ b/drivers/tee/broadcom/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += chimp_optee.o
diff --git a/drivers/tee/broadcom/chimp_optee.c
b/drivers/tee/broadcom/chimp_optee.c
new file mode 100644
index 00..6c39c68f80
--- /dev/null
+++ b/drivers/tee/broadcom/chimp_optee.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright 2020 Broadcom.
+ */
+
+#include
+#include
+#include
+
+#ifdef CONFIG_CHIMP_OPTEE
+
+#define CHMIP_BOOT_UUID { 0x6272636D, 0x2019, 0x0716, \
+ { 0x42, 0x43, 0x4D, 0x5F, 0x53, 0x43, 0x48, 0x49 } }
+
+enum {
+ TEE_CHIMP_FASTBOOT = 0,
+ TEE_CHIMP_HEALTH_STATUS,
+ TEE_CHIMP_HANDSHAKE_STATUS,
+} tee_chmip_cmd;
+
+struct bcm_chimp_data {
+ struct udevice *tee;
+ u32 session;
+} chimp_data;
+
+static int get_open_session(struct bcm_chimp_data *b_data)
+{
+ const struct tee_optee_ta_uuid uuid = CHMIP_BOOT_UUID;
+ struct tee_open_session_arg arg;
+ struct udevice *tee = NULL;
+ int rc;
+
+ tee = tee_find_device(NULL, NULL, NULL, NULL);
+ if (!tee)
+ return -ENODEV;
+
+ memset(, 0, sizeof(arg));
+ tee_optee_ta_uuid_to_octets(arg.uuid, );
+ rc = tee_open_session(tee, , 0, NULL);
+ if (rc < 0)
+ return -ENODEV;
+
+ b_data->tee = tee;
+ b_data->session = arg.session;
+
+ return 0;
+}
+
+static int init_arg(struct tee_invoke_arg *arg, u32 func)
+{
+ if (get_open_session(_data))
+ return -EINVAL;
+
+ memset(arg, 0, sizeof(struct tee_invoke_arg));
+ arg->func = func;
+ arg->session = chimp_data.session;
+
+ return 0;
+}
+
+int chimp_handshake_status_optee(u32 timeout, u32 *hs)
+{
+ struct tee_invoke_arg arg;
+ struct tee_param param[1];
+ int ret;
+
+ ret = init_arg(, TEE_CHIMP_HANDSHAKE_STATUS);
+ if (ret < 0)
+ return ret;
+
+ param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INOUT;
+ param[0].u.value.a = timeout;
+
+ ret = tee_invoke_func(chimp_data.tee, , ARRAY_SIZE(param), param);
+ if (ret < 0) {
+ printf("Handshake status command failed\n");
+ goto out;
+ }
+
+ switch (arg.ret) {
+ case TEE_SUCCESS:
+ *hs = param[0].u.value.a;
+ ret = 0;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+out:
+ tee_close_session(chimp_data.tee, chimp_data.s
[PATCH v4 0/2] add optee support for broadcom NS3 soc
This is fourth patch set series prepared on top of third
patch set ("add FIT image support for broadcom NS3 soc").
This patch adds optee support.
Changes from v3:
-Address review comments from Simon,
Rearrange code and remove while loop,
Add comments for function.
Changes from v2:
-Address review comments from Simon,
Remove own return code and use standard error code.
Take out common lines from different functions and move them
into common static function.
Remove include as its not required.
Move functions with printf from header file into c file.
-Address slef review comments,
Remove optee dt node as this file is no longer in sync with linux.
Changes from v1:
-Address review comments from Thomas Fitzsimmons,
Expand the bnxt full form.
-Address review comments from Simon Glass,
Move c file from board/broadcom/bcmns3/chimp_optee.c to
drivers/tee/broadcom,
Move header file from include/brcm/chimp.h to include/broadcom/chimp.h
Rayagonda Kokatanur (1):
configs: ns3: enable tee and optee driver
Vikas Gupta (1):
drivers: tee: broadcom: add optee based bnxt fw load driver
configs/bcm_ns3_defconfig | 5 +-
drivers/tee/Kconfig| 1 +
drivers/tee/Makefile | 1 +
drivers/tee/broadcom/Kconfig | 7 ++
drivers/tee/broadcom/Makefile | 3 +
drivers/tee/broadcom/chimp_optee.c | 180 +
include/broadcom/chimp.h | 43 +++
7 files changed, 239 insertions(+), 1 deletion(-)
create mode 100644 drivers/tee/broadcom/Kconfig
create mode 100644 drivers/tee/broadcom/Makefile
create mode 100644 drivers/tee/broadcom/chimp_optee.c
create mode 100644 include/broadcom/chimp.h
--
2.17.1
[PATCH v3 2/3] board: ns3: add FIT image its file
From: Pramod Kumar
Add FIT image its file.
Signed-off-by: Pramod Kumar
Signed-off-by: Rayagonda Kokatanur
---
board/broadcom/bcmns3/fit/multi.its | 59 +
1 file changed, 59 insertions(+)
create mode 100644 board/broadcom/bcmns3/fit/multi.its
diff --git a/board/broadcom/bcmns3/fit/multi.its
b/board/broadcom/bcmns3/fit/multi.its
new file mode 100644
index 00..a0ff4bc908
--- /dev/null
+++ b/board/broadcom/bcmns3/fit/multi.its
@@ -0,0 +1,59 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Various kernels, ramdisks and FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Linux kernel Image";
+ data = /incbin/("./Image");
+ type = "kernel";
+ arch = "arm64";
+ os = "linux";
+ compression = "none";
+ load = <0x8008>;
+ entry = <0x8008>;
+ hash-1 {
+ algo = "sha1";
+ };
+ signature {
+ algo = "sha1,rsa2048";
+ key-name-hint = "dev";
+ };
+ };
+
+ fdt-ns3 {
+ description = "FDT Blob";
+ data = /incbin/("./dt-blob.bin");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ hash-1 {
+ algo = "sha1";
+ };
+ signature {
+ algo = "sha1,rsa2048";
+ key-name-hint = "dev";
+ };
+ };
+ };
+
+ configurations {
+ default = "config-ns3";
+ config-ns3 {
+ description = "FIT1 configuration";
+ kernel = "kernel";
+ fdt = "fdt-ns3";
+ signature {
+ algo = "sha1,rsa2048";
+ key-name-hint = "dev";
+ sign-images = "fdt", "kernel";
+ };
+ };
+ };
+};
--
2.17.1
[PATCH v3 3/3] board: ns3: add development keys used in FIT
From: Pramod Kumar Add development keys used in FIT. Signed-off-by: Pramod Kumar Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- board/broadcom/bcmns3/fit/keys/dev.crt | 21 +++ board/broadcom/bcmns3/fit/keys/dev.key | 28 ++ 2 files changed, 49 insertions(+) create mode 100644 board/broadcom/bcmns3/fit/keys/dev.crt create mode 100644 board/broadcom/bcmns3/fit/keys/dev.key diff --git a/board/broadcom/bcmns3/fit/keys/dev.crt b/board/broadcom/bcmns3/fit/keys/dev.crt new file mode 100644 index 00..75b75db95c --- /dev/null +++ b/board/broadcom/bcmns3/fit/keys/dev.crt @@ -0,0 +1,21 @@ +-BEGIN CERTIFICATE- +MIIDXTCCAkWgAwIBAgIJAJgq/5aiJttEMA0GCSqGSIb3DQEBCwUAMEUxCzAJBgNV +BAYTAkFVMRMwEQYDVQQIDApTb21lLVN0YXRlMSEwHwYDVQQKDBhJbnRlcm5ldCBX +aWRnaXRzIFB0eSBMdGQwHhcNMTgwOTE5MDkzMzEwWhcNMTgxMDE5MDkzMzEwWjBF +MQswCQYDVQQGEwJBVTETMBEGA1UECAwKU29tZS1TdGF0ZTEhMB8GA1UECgwYSW50 +ZXJuZXQgV2lkZ2l0cyBQdHkgTHRkMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIB +CgKCAQEAzeMQ92YqrejtMCfxjDyHvDW34ATozXSlWsudR+AyCSuJVAIoHEenVh+/ +PuT0+/EMiwsUnLXYBeOsIXDW3k3eHgm88ccb+0g9J6mlHqMaN0tXP+Ua2GFEk2Wv +5Bj5QynorOPoaWL/ecWus2Bvkmyt2pvIpaTjmkUKZ9al3z8WyS6wFlFitXyOWFcK +7Xkl43cOHxYAfbny5loWYDCgpkV+dgYZOoCEmL+Y9HfrQ+uBKGducpzNKeQjX9bn +UT9cleCtHZx0uY4wSGNgfmUMy7oUyVZhFpmjlcfjcfNFcBcoVF6StluoL6v1KRbH +4xJDD/UCn2Uk0S6Zpd7TRc26faOtfwIDAQABo1AwTjAdBgNVHQ4EFgQUZk/KKaWG +p4BtksPdQ8FLzWL/gAIwHwYDVR0jBBgwFoAUZk/KKaWGp4BtksPdQ8FLzWL/gAIw +DAYDVR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAPNveTvOC2bw91cUN1e+B +95qFp2Xd5XGiV35F10dT3VN/Iv2dzHlThq7xaJGkA53lHIXgLUUfnDTHJmoluw+t +UCpG8OWCxM0FbT8ZnXR4SmHK8k4yb7iZa7iu+Ey5B6F3247gJpEl+1iYxus0lqQW +E9dTwMf1YP9Jdf+dRoLKAAI0n5J1PMuseQkGdlRBNUcEg+kXqBSz5hq0xkuPRtey +GiAvpg3G93ft84Q4ov7IjAhJkY7whm6WktisU8mFPru3e9EouxjVtAvu6s9gQThm +pvn6hSL2/3gEOP3v9yBsH6//SOgNdVBGZIdX+HkvD8NZLftbIrDaeL/IfKUm/zXB +zA== +-END CERTIFICATE- diff --git a/board/broadcom/bcmns3/fit/keys/dev.key b/board/broadcom/bcmns3/fit/keys/dev.key new file mode 100644 index 00..55b7033e9f --- /dev/null +++ b/board/broadcom/bcmns3/fit/keys/dev.key @@ -0,0 +1,28 @@ +-BEGIN PRIVATE KEY- +MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQDN4xD3Ziqt6O0w +J/GMPIe8NbfgBOjNdKVay51H4DIJK4lUAigcR6dWH78+5PT78QyLCxSctdgF46wh +cNbeTd4eCbzxxxv7SD0nqaUeoxo3S1c/5RrYYUSTZa/kGPlDKeis4+hpYv95xa6z +YG+SbK3am8ilpOOaRQpn1qXfPxbJLrAWUWK1fI5YVwrteSXjdw4fFgB9ufLmWhZg +MKCmRX52Bhk6gISYv5j0d+tD64EoZ25ynM0p5CNf1udRP1yV4K0dnHS5jjBIY2B+ +ZQzLuhTJVmEWmaOVx+Nx80VwFyhUXpK2W6gvq/UpFsfjEkMP9QKfZSTRLpml3tNF +zbp9o61/AgMBAAECggEBAJ/TZClZk0ob5nyalWVS29/cJ5hs1zgfE/nu1HKmdNEv +jdS8M9z4Nsuhq3msjQ1Da4RInsCkXUT9H3N6QCKkeggBcT6TXYJs6qRuijLFVKWW +A+4i8PsGTxDJQIimZmGgF/KWnaWp5z7lmZ+//fzCBxgMFO+Zl+H7NH+1XmB2fj6/ +bfgnxLbiIqq/2oVJfdjA1Zs2ie3SE5U2hPNiE6TIajFS0PxUOGrojsSQ8z+gfqs3 +hyqo9msAqNQciT79vyXp+3HsxZo9rq5Tk5OtCEfgu0GED/d4/FHbDrZT3TorVYXr +Z3dADxvnnJfBdlQIMetCy/X8z2vKRRXaoWpqg1aiFVECgYEA7Ap5D4nvOie2NXgI +gMPzuYtpH4uF/cZMLGxTKZ3NG4RH6oVUdd4whETXfzBJdnJbIXDTphoHxjUhpGh8 +Ga+U1iqjp9c6Nd8ueVp/c5T1bD8/2RG0QM4iWgPbZDKtj1MqRg7vwAfpJ3kOIc/5 +bKJ4jAopNJMChL6vAZ9+ShPsRqkCgYEA30vbj6K7/giclJnyWkluQTqS8X/XjdAf +F5PkCBHGJnYxkDSzWPq7O5E1wYqTAou1U6nNNoUvZZdpRvo39NSrMCaagQ7GE+xA +j/h7tinD/lPlvoW9N4f4ddqWzsmf7I8OGZtP4IwVi9Pms+zPtrQ7TvuPT4UHTH2E +eE1hlJtic+cCgYEA6oKdNGr+WvEJfqX7DLOiej2f+89LGI7jL1+QYFB/b09FhCNj +fpd57G/ZCmyXEC8di2PlY6mI/8vZ2NZWNc7UONO0NRUIqG1MZxUae2MLUrikXq3Q +QHKMfpJGbo5LEZK29VPxrwAtDSKgf8d5MA1bZwbRWYKVhf1NMnebqU2R+cECgYEA +kOTKXhP85MR1xj928XtAnfcCLs8D8jOgWU5P46SU7ZQ4aRipYA2ivO5m8WWYK0i4 +qsc+MCiQLt3nJHVtJeNyCdai3yfVBEyDQGi+7d+AHGIYbF6f/46tfNwQi7JtobTa +M2eCl3SO7qLbytjZl/avnXrC7Zimuc2gzed4cFO7uPUCgYAo66MLtRWLdHqPDTaa +WhSQZkdKfZxlWNP6XIpBgHnYDIQGZddrjv+zZVFRxLCduh1v8xybbSDKwRkGuXVb +eTQHP2Nc5XsOopCSsDP0v0dUxaOu14C0jJJG2E+EhJsWJ2Eua7o40LEIX2WY7N7f +UqR3bLO5Qh/1OOwJj5WbpzkMwA== +-END PRIVATE KEY- -- 2.17.1
[PATCH v3 1/3] configs: ns3: enable FIT config
Enable FIT config for NS3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index ab26617158..0e078f3244 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -5,6 +5,11 @@ CONFIG_SYS_TEXT_BASE=0xFF00 CONFIG_ENV_SIZE=0x8 CONFIG_NR_DRAM_BANKS=2 CONFIG_OF_BOARD_SETUP=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x2000 +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_LOGLEVEL=7 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y -- 2.17.1
[PATCH v3 0/3] add FIT image support for broadcom NS3 soc
This is third patch set series prepared on top of second
patch set ("add basic driver support for broadcom NS3 soc").
This patch set enables FIT config and add FIT image its
files and keys.
Changes from v2:
- Rebase on top of second patch set.
Changes from v1:
-Address self review comments,
Rebase on top of latest uboot and updated previous patch series.
Pramod Kumar (2):
board: ns3: add FIT image its file
board: ns3: add development keys used in FIT
Rayagonda Kokatanur (1):
configs: ns3: enable FIT config
board/broadcom/bcmns3/fit/keys/dev.crt | 21 +
board/broadcom/bcmns3/fit/keys/dev.key | 28
board/broadcom/bcmns3/fit/multi.its| 59 ++
configs/bcm_ns3_defconfig | 5 +++
4 files changed, 113 insertions(+)
create mode 100644 board/broadcom/bcmns3/fit/keys/dev.crt
create mode 100644 board/broadcom/bcmns3/fit/keys/dev.key
create mode 100644 board/broadcom/bcmns3/fit/multi.its
--
2.17.1
[PATCH v4 5/7] configs: ns3: enable gpt commands
Enable gpt commands for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index a1ee866e54..0f23f30db2 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -14,6 +14,8 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot> " CONFIG_SYS_XTRACE="n" +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_MMC=y CONFIG_CMD_MMC_SWRITE=y # CONFIG_CMD_PINMUX is not set -- 2.17.1
[PATCH v4 7/7] configs: ns3: enable sp805 watchdog driver
Enable sp805 watchdog driver for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 66fbdb20d6..ab26617158 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -37,5 +37,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y CONFIG_FAT_WRITE=y CONFIG_SPL_OF_LIBFDT=y -- 2.17.1
[PATCH v4 6/7] configs: ns3: enable EXT4 and FAT fs support
Enable EXT4 and FAT fs support for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 0f23f30db2..66fbdb20d6 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -20,6 +20,10 @@ CONFIG_CMD_MMC=y CONFIG_CMD_MMC_SWRITE=y # CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SOURCE is not set +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +# CONFIG_DOS_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_DM=y @@ -33,4 +37,5 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_FAT_WRITE=y CONFIG_SPL_OF_LIBFDT=y -- 2.17.1
[PATCH v4 3/7] configs: ns3: enable BCM IPROC mmc driver
Enable BCM IPROC mmc driver ns3. Enable DMA for MMC Host to have better reads and writes. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 328b0e2b4e..432237b56d 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -21,6 +21,10 @@ CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_CCF=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_IPROC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y -- 2.17.1
[PATCH v4 4/7] configs: ns3: enable mmc commands
Enable mmc commands for NS3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 432237b56d..a1ee866e54 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -14,6 +14,8 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot> " CONFIG_SYS_XTRACE="n" +CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_SWRITE=y # CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SOURCE is not set CONFIG_OF_CONTROL=y -- 2.17.1
[PATCH v4 1/7] configs: ns3: enable pinctrl driver
Enable pinctrl driver for ns3. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- configs/bcm_ns3_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 9adb44cb51..328b0e2b4e 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -14,12 +14,15 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot> " CONFIG_SYS_XTRACE="n" +# CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SOURCE is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_CCF=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPL_OF_LIBFDT=y -- 2.17.1
[PATCH v4 2/7] dt-bindings: pinctrl: add ns3 pads definition
Add NS3 pads definitions. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- .../dt-bindings/pinctrl/brcm,pinctrl-ns3.h| 41 +++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h diff --git a/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h b/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h new file mode 100644 index 00..81ebd58ca5 --- /dev/null +++ b/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + */ + +#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ +#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ + +/* Alternate functions available in MUX controller */ +#define MODE_NITRO 0 +#define MODE_NAND 1 +#define MODE_PNOR 2 +#define MODE_GPIO 3 + +/* Pad configuration attribute */ +#define PAD_SLEW_RATE_ENA BIT(0) +#define PAD_SLEW_RATE_ENA_MASK BIT(0) + +#define PAD_DRIVE_STRENGTH_2_MA(0 << 1) +#define PAD_DRIVE_STRENGTH_4_MABIT(1) +#define PAD_DRIVE_STRENGTH_6_MA(2 << 1) +#define PAD_DRIVE_STRENGTH_8_MA(3 << 1) +#define PAD_DRIVE_STRENGTH_10_MA (4 << 1) +#define PAD_DRIVE_STRENGTH_12_MA (5 << 1) +#define PAD_DRIVE_STRENGTH_14_MA (6 << 1) +#define PAD_DRIVE_STRENGTH_16_MA (7 << 1) +#define PAD_DRIVE_STRENGTH_MASK(7 << 1) + +#define PAD_PULL_UP_ENABIT(4) +#define PAD_PULL_UP_ENA_MASK BIT(4) + +#define PAD_PULL_DOWN_ENA BIT(5) +#define PAD_PULL_DOWN_ENA_MASK BIT(5) + +#define PAD_INPUT_PATH_DIS BIT(6) +#define PAD_INPUT_PATH_DIS_MASKBIT(6) + +#define PAD_HYSTERESIS_ENA BIT(7) +#define PAD_HYSTERESIS_ENA_MASKBIT(7) + +#endif -- 2.17.1
[PATCH v4 0/7] add basic driver support for broadcom NS3 soc
This is the second patch set series prepared on top of the
first patch set ("add initial support for broadcom NS3 soc").
This patch set will add following,
-defconfig options for basic device like pinctrl,
gpio, mmc, qspi, wdt, i2c and pcie.
-start wdt service
-Enable GPT commands
-Enable EXT4 and FAT fs support
Changes from v3:
-Rebase on top of first patch set.
Changes from v2:
-Address review comments from Stefan Rose,
Remove patch to stop and start wdt service from board files.
Instead define CONFIG_WATCHDOG defconfig which takes care of
wdt reset for every 1s.
Changes from v1:
-Address review comments from Simon,
-include instead of and
-remove include as its not required
-Use if() instead of #if def
-rearrange code in start_wdt()
-remove #else part of #ifdef CONFIG_DT
-Address review comments from Tom and Simon,
Remove all dt patches as uboot should use the same dt file from Linux.
Rayagonda Kokatanur (7):
configs: ns3: enable pinctrl driver
dt-bindings: pinctrl: add ns3 pads definition
configs: ns3: enable BCM IPROC mmc driver
configs: ns3: enable mmc commands
configs: ns3: enable gpt commands
configs: ns3: enable EXT4 and FAT fs support
configs: ns3: enable sp805 watchdog driver
configs/bcm_ns3_defconfig | 18
.../dt-bindings/pinctrl/brcm,pinctrl-ns3.h| 41 +++
2 files changed, 59 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h
--
2.17.1
[PATCH v4 15/15] MAINTAINERS: update maintainers for broadcom ns3 platform
Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3). Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- Changes from v3: -Address review comments from Simon, Update new file doc/README.bcmns3 -Address review comments from Peter Tyser, Fix accidental changes MAINTAINERS | 15 +++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2a281a9a0f..f96993b84c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -937,6 +937,21 @@ S: Maintained F: drivers/spmi/ F: include/spmi/ +TARGET_BCMNS3 +M: Bharat Gooty +M: Rayagonda Kokatanur +S: Maintained +F: board/broadcom/bcmns3/ +F: doc/README.bcmns3 +F: configs/bcm_ns3_defconfig +F: include/configs/bcm_ns3.h +F: include/dt-bindings/memory/bcm-ns3-mc.h +F: arch/arm/Kconfig +F: arch/arm/dts/ns3-board.dts +F: arch/arm/dts/ns3.dtsi +F: arch/arm/cpu/armv8/bcmns3 +F: arch/arm/include/asm/arch-bcmns3/ + TDA19988 HDMI ENCODER M: Liviu Dudau S: Maintained -- 2.17.1
[PATCH v4 14/15] doc: add README doc for bcmns3 platform
Add README doc for bcmns3 platform. Signed-off-by: Rayagonda Kokatanur --- doc/README.bcmns3 | 74 +++ 1 file changed, 74 insertions(+) create mode 100644 doc/README.bcmns3 diff --git a/doc/README.bcmns3 b/doc/README.bcmns3 new file mode 100644 index 00..c51f91471f --- /dev/null +++ b/doc/README.bcmns3 @@ -0,0 +1,74 @@ +BCMNS3 QSPI memory layout += + +BCMNS3 has total 8MB non-volatile SPI flash memory. It is used to store +different images like fip.bin, nitro firmware, DDR shmo value and other backup +images. + +Following is the QSPI flash memory layout. + +/* QSPI layout + * |---|->0x00 + * | | + * | | + * |fip.bin| + * | 2MB | + * | | + * ~ ~ + * ~ ~ + * | | + * | | + * | | + * |---|->0x20 + * | | + * | | + * | | + * | fip.bin (Mirror)| + * |2MB| + * ~ ~ + * ~ ~ + * | | + * | | + * | | + * |---|->0x40 + * | | + * | Nitro NS3 Config | + * | 1.5M | + * | | + * ~ ~ + * ~ ~ + * | | + * |---|->0x58 + * | Nitro NS3 Config | + * | 1.5M | + * |(Mirror) | + * ~ ~ + * ~ ~ + * | | + * |---|->0x70 + * | Nitro NS3 bspd Config | + * |64KB | + * ~ ~ + * ~ ~ + * | | + * |---|->0x71 + * | Nitro NS3 bspd Config | + * |64KB | + * ~ (Mirror)~ + * ~ ~ + * | | + * |---|->0x72 + * |SHMOO | + * |64KB | + * | | + * ~ ~ + * ~ ~ + * |---|->0x73 + * |Meta Data | + * |832KB | + * | | + * ~ ~ + * ~ ~ + * | | + * |---| + */ -- 2.17.1
[PATCH v4 12/15] include/configs: ns3: add env variables for Linux boot
From: Bharat Gooty
Add env variables and commands for booting Linux.
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v3:
-Address review comments from Simon,
Move the documentation to /doc instead of in header file.
include/configs/bcm_ns3.h | 294 ++
1 file changed, 294 insertions(+)
diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h
index 02a736456a..7aa5cc2dbb 100644
--- a/include/configs/bcm_ns3.h
+++ b/include/configs/bcm_ns3.h
@@ -37,4 +37,298 @@
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
+/*
+ * Increase max uncompressed/gunzip size, keeping size same as EMMC linux
+ * partition.
+ */
+#define CONFIG_SYS_BOOTM_LEN 0x0180
+
+/* Env configuration */
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART0
+
+/* Access eMMC Boot_1 and Boot_2 partitions */
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* enable 64-bit PCI resources */
+#define CONFIG_SYS_PCI_64BIT 1
+
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
+#define MAX_CPUS "max_cpus=maxcpus=8\0"
+#define OS_LOG_LEVEL "log_level=loglevel=7\0"
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x68A1 " \
+ "earlyelog=" __stringify(ELOG_AP_UART_LOG_BASE) ",0x1 " \
+ "crashkernel=512M reboot=w\0"
+
+#define PCIE_ARGS "pcie_args=pci=pcie_bus_safe pcie_ports=native
vfio_pci.disable_idle_d3=1\0"
+
+#ifdef CONFIG_BCM_SF2_ETH
+#define ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0"
+#define NET_ARGS "bgmac_platform.ethaddr=${ethaddr} " \
+ "ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off"
+#else
+#define ETH_ADDR
+#define NET_ARGS
+#endif
+
+#define RESERVED_MEM "reserved_mem=memmap=0xff00$0x100\0"
+
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \
+ " ${max_cpus} ${log_level} ${reserved_mem}"
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS " " NET_ARGS "\0"
+
+#define UPDATEME_FLASH_PARAMS "bcm_compat_level=4\0" \
+ "bcm_need_recovery_rootfs=0\0" \
+ "bcm_bl_flash_pending_rfs_imgs=0\0"
+
+#define KERNEL_LOADADDR_CFG \
+ "fit_image_loadaddr=0x9000\0" \
+ "dtb_loadaddr=0x8200\0"
+
+#define INITRD_ARGS "initrd_args=root=/dev/ram rw\0"
+#define INITRD_LOADADDR "initrd_loadaddr=0x9200\0"
+#define INITRD_IMAGE "initrd_image=rootfs-lake-bcm958742t.cpio.gz\0"
+#define MMC_DEV "sd_device_number=0\0"
+#define EXEC_STATE "exec_state=normal\0"
+
+#define EXT4RD_ARGS "ext4rd_args="\
+ "root=/dev/mmcblk${sd_device_number}p${gpt_partition_entry} rw
rootwait\0"
+
+#define WDT_CNTRL "wdt_enable=1\0" \
+ "wdt_timeout_sec=0\0"
+
+#define ELOG_SETUP \
+ "mbox0_addr=0x66424024\0"\
+ "elog_setup="\
+ "if logsetup -s ${mbox0_addr}; then "\
+ "else "\
+ "echo ELOG is not supported by this version of the MCU patch.;"\
+ "exit;"\
+ "fi;"\
+ "if logsetup -c ${mbox0_addr}; then "\
+ "echo ELOG is ready;"\
+ "else "\
+ "echo ELOG is supported, but is not set up.;"\
+ "echo Getting setup file from the server ${serverip}...;"\
+ "if tftp ${tftp_dir}elog_src.txt; then "\
+ "echo Setting up ELOG. Please wait...;"\
+ "if logsetup ${loadaddr} ${mbox0_addr} ${filesize}; "\
+ "then "\
+ "else "\
+ "echo [logsetup] ERROR.;"\
+ "fi;"\
+ "if logsetup -c ${mbox0_addr}; then "\
+ "echo ELOG is READY.;"\
+ "else "\
+ "echo ELOG is NOT SET UP.;"\
+ "fi;"\
+ "else "\
+ "echo ELOG setup file is not available on the server.;"\
+ "fi;"\
+ "fi \0"
+
+/* eMMC partition for FIT images */
+#define FIT_MMC_PARTITION \
+ "fit_partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=env,size=512K,uuid=${uuid_gpt_env};" \
+ "name=Image_rsa.img,size=24MiB,uuid=${uuid_
[PATCH v4 13/15] include/configs: ns3: add support for flashing images
From: Bharat Gooty
Add support for flashing images into QSPI and eMMC.
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
include/configs/bcm_ns3.h | 491 +-
1 file changed, 490 insertions(+), 1 deletion(-)
diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h
index 7aa5cc2dbb..039f4d6759 100644
--- a/include/configs/bcm_ns3.h
+++ b/include/configs/bcm_ns3.h
@@ -290,6 +290,483 @@
"run bootcmd_usb || "\
"run bootcmd_pxe"
+/* Flashing commands */
+#define TFTP_QSPI_PARAM \
+ "fip_qspi_addr=0x0\0"\
+ "fip_qspi_mirror_addr=0x20\0"\
+ "loadaddr=0x9000\0"\
+ "tftpblocksize=1468\0"\
+ "qspi_flash_fip=fip\0"\
+
+/* Flash fit_GPT partition to eMMC */
+#define MMC_FLASH_FIT_GPT \
+ "mmc_flash_gpt="\
+ "if mmc dev ${sd_device_number}; then "\
+ "else "\
+ "echo [mmc_flash_gpt] mmc dev ${sd_device_number} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if gpt write mmc ${sd_device_number} ${fit_partitions}; then "\
+ "else "\
+ "echo [mmc_flash_gpt] gpt write ${fit_partitions} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi \0"
+
+#define MMC_FLASH_IMAGE_RSA \
+ "mmc_flash_image_rsa="\
+ "if mmc dev ${sd_device_number}; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] mmc dev ${sd_device_number} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if gpt setenv mmc ${sd_device_number} ${fit_image}; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] gpt setenv ${fit_image} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if tftp ${loadaddr} ${tftp_dir}${fit_image}; then "\
+ "if test ${fit_image} = Image_rsa.img; then "\
+ "if setenv tftp_fit_image yes; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] "\
+ "setenv tftp_fit_image to yes"\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "fi;"\
+ "else "\
+ "if test ${fit_image} = Image_rsa.img; then "\
+ "echo [mmc_flash_image_rsa] tftp "\
+ "${tftp_dir}${fit_image} ** FAILED **;"\
+ "else "\
+ "if test ${tftp_fit_image} = yes; then "\
+ "if mmc write ${loadaddr} "\
+ "${gpt_partition_addr} "\
+ "${fileblocks}; then "\
+ "else "\
+ "echo "\
+ "[mmc_flash_image_rsa] "\
+ "mmc write "\
+ "${gpt_partition_addr} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "else "\
+ "echo [mmc_flash_image_rsa] tftp "\
+ "${tftp_dir}${fit_image} "\
+ "** FAILED **;"\
+ "fi;"\
+ "fi;"\
+ "exit;"\
+ "fi;"\
+ "if math add filesize filesize 1FF; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] math add command ** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if math div fileblocks filesize 200; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] math div command ** FAILED **;"\
+ "exit;"\
+ "fi;"\
+ "if mmc write ${loadaddr} ${gpt_partition_addr} ${fileblocks}; then "\
+ "else "\
+ "echo [mmc_flash_image_rsa] mmc write ${gpt_partition_addr} "\
+ "** FAILED **;"\
+ "exit;"\
+ "fi;"\
+
[PATCH v4 07/15] board: ns3: program GIC LPI tables
U-boot programs the GIC LPI configuration tables and enables
the LPI table.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
---
Changes from v3:
-Address review comments from Simon,
Use dt and a UCLASS_IRQ to get gic details instead of passing
as arguments to function gic_lpi_tables_init().
board/broadcom/bcmns3/ns3.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 1221f26ddc..e7896f8e11 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
#include
#include
@@ -88,3 +89,12 @@ void reset_cpu(ulong level)
psci_system_reset();
}
}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ gic_lpi_tables_init();
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
--
2.17.1
[PATCH v4 08/15] configs: ns3: enable GIC_V3 ITS
Enables the Generic Interrupt Controller (GIC) V3 Interrupt Translation Service (ITS) Locality-specific Peripheral Interrupts (LPI) configuration table and LPI table. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Bharat Kumar Reddy Gooty Reviewed-by: Simon Glass --- Changes from v3: -Address review comments from Simon, Update the commit message ie expand the acronyms configs/bcm_ns3_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 7e51a926f7..040e753f9f 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_BCMNS3=y CONFIG_SYS_TEXT_BASE=0xFF00 CONFIG_ENV_SIZE=0x8 -- 2.17.1
[PATCH v4 10/15] board: ns3: define ddr memory layout
Add both DRAM banks memory information and
the corresponding MMU page table mappings.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v3:
-Address review comments from Simon,
Correct spelling mistakes,
Use a struct instead of ad-hoc pointer reading,
Use error code and return errro upon failure,
Check for return value.
arch/arm/dts/ns3-board.dts | 23
board/broadcom/bcmns3/ns3.c | 106 ++--
configs/bcm_ns3_defconfig | 2 +
3 files changed, 127 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts
index 54e56879a5..4e0966a132 100644
--- a/arch/arm/dts/ns3-board.dts
+++ b/arch/arm/dts/ns3-board.dts
@@ -5,6 +5,29 @@
/dts-v1/;
+#include
+
+/*
+ * Single mem reserve region which includes the following:
+ * Components name Start Addr Size
+ *
+ * GIC LPI tables 0x8ad7_ 0x0009_
+ * Nitro FW0x8ae0_ 0x0020_
+ * Nitro Crash dump0x8b00_ 0x0200_
+ * OPTEE OS0x8d00_ 0x0200_
+ * BL31 services 0x8f00_ 0x0010_
+ * Tmon0x8f10_ 0x_1000
+ * LPM/reserved0x8f10_1000 0x_1000
+ * ATF to Bl33 info0x8f10_2000 0x_1000
+ * ATF error logs 0x8f10_3000 0x0001_
+ * Error log parser0x8f11_3000 0x0010_
+ */
+
+/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END;
+
+/* CRMU page tables */
+/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE;
+
#include "ns3.dtsi"
/ {
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index e7896f8e11..418db67875 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -5,11 +5,37 @@
*/
#include
+#include
#include
#include
#include
#include
#include
+#include
+
+#define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
+
+/*
+ * ns3_dram_bank - DDR bank details
+ *
+ * @start: DDR bank start address
+ * @len: DDR bank length
+ */
+struct ns3_dram_bank {
+ u64 start[BCM_NS3_MAX_NR_BANKS];
+ u64 len[BCM_NS3_MAX_NR_BANKS];
+};
+
+/*
+ * ns3_dram_hdr - DDR header info
+ *
+ * @sig: DDR info signature
+ * @bank: DDR bank details
+ */
+struct ns3_dram_hdr {
+ u32 sig;
+ struct ns3_dram_bank bank;
+};
static struct mm_region ns3_mem_map[] = {
{
@@ -20,9 +46,15 @@ static struct mm_region ns3_mem_map[] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
- .virt = 0x8000UL,
- .phys = 0x8000UL,
- .size = 0x8000UL,
+ .virt = BCM_NS3_MEM_START,
+ .phys = BCM_NS3_MEM_START,
+ .size = BCM_NS3_MEM_LEN,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = BCM_NS3_BANK_1_MEM_START,
+ .phys = BCM_NS3_BANK_1_MEM_START,
+ .size = BCM_NS3_BANK_1_MEM_LEN,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -41,6 +73,72 @@ DECLARE_GLOBAL_DATA_PTR;
*/
struct bl33_info *bl33_info __section(".data");
+/*
+ * Run modulo 256 checksum calculation and return the calculated checksum
+ */
+static u8 checksum_calc(u8 *p, unsigned int len)
+{
+ unsigned int i;
+ u8 chksum = 0;
+
+ for (i = 0; i < len; i++)
+ chksum += p[i];
+
+ return chksum;
+}
+
+/*
+ * This function parses the memory layout information from a reserved area in
+ * DDR, and then fix up the FDT before passing it to Linux.
+ *
+ * In the case of error, do nothing and the default memory layout in DT will
+ * be used
+ */
+static int mem_info_parse_fixup(void *fdt)
+{
+ struct ns3_dram_hdr hdr;
+ u32 *p32, i, nr_banks;
+ u64 *p64;
+
+ /* validate signature */
+ p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
+ hdr.sig = *p32;
+ if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
+ printf("DDR info signature 0x%x invalid\n", hdr.sig);
+ return -EINVAL;
+ }
+
+ /* run checksum test to validate data */
+ if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
+ printf("Checksum on DDR info failed\n");
+ return -EINVAL;
+ }
+
+ /* parse information for each bank */
+ nr_banks = 0;
+ for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
+ /* skip banks with a length of zero */
+ p64 = (u64 *)BANK_OFFSET(i);
+ if (*(p64 + 1) == 0)
+ continue;
+
+ hdr.bank.start[i] = *p64;
+ hdr.bank.len[i] = *(p64
[PATCH v4 09/15] dt-bindings: memory: ns3: add ddr memory definition
Add ddr memory definitions. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- Changes from v3: -Address review comments from Simon, Use lower-case hex numbers. include/dt-bindings/memory/bcm-ns3-mc.h | 31 - 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index fe669e2f87..84795ec27a 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -7,7 +7,8 @@ #define DT_BINDINGS_BCM_NS3_MC_H /* - * Reserved Memory Map : SHMEM & TZDRAM. + * ++--+ 0x8b00 + * | NITRO CRASH DUMP | 32MB * ++--+ 0x8d00 * | SHMEM (NS) | 16 MB * +---+ 0x8e00 @@ -20,6 +21,10 @@ * +---+ 0x8f10 */ +#define BCM_NS3_MEM_NITRO_CRASH_START 0x8ae0 +#define BCM_NS3_MEM_NITRO_CRASH_LEN0x21f +#define BCM_NS3_MEM_NITRO_CRASH_SIZE 0x220 + #define BCM_NS3_MEM_SHARE_START0x8d00 #define BCM_NS3_MEM_SHARE_LEN 0x020f @@ -31,4 +36,28 @@ #define BCM_NS3_MEM_CRMU_PT_START 0x88000 #define BCM_NS3_MEM_CRMU_PT_LEN0x20 +/* default memory starting address and length */ +#define BCM_NS3_MEM_START 0x8000UL +#define BCM_NS3_MEM_LEN0x8000UL +#define BCM_NS3_MEM_END(BCM_NS3_MEM_START + BCM_NS3_MEM_LEN) + +/* memory starting address and length for BANK_1 */ +#define BCM_NS3_BANK_1_MEM_START 0x88000UL +#define BCM_NS3_BANK_1_MEM_LEN 0x18000UL + +/* memory layout information */ +#define BCM_NS3_DDR_INFO_BASE 0x8f22 +#define BCM_NS3_DDR_INFO_RSVD_LEN 0x1000 +#define BCM_NS3_DDR_INFO_LEN 73 +#define BCM_NS3_DDR_INFO_SIG 0x42434d44 +#define BCM_NS3_MAX_NR_BANKS 4 + +#define BCM_NS3_GIC_LPI_BASE 0x8ad7 +#define BCM_NS3_MEM_RSVE_STARTBCM_NS3_GIC_LPI_BASE +#define BCM_NS3_MEM_RSVE_END ((BCM_NS3_MEM_ELOG_START + \ + BCM_NS3_MEM_ELOG_LEN) - \ + BCM_NS3_MEM_RSVE_START) + +#define BCM_NS3_CRMU_PGT_START0x88000UL +#define BCM_NS3_CRMU_PGT_SIZE 0x10 #endif -- 2.17.1
[PATCH v4 11/15] board: ns3: limit U-boot relocation within 16MB memory
From: Bharat Kumar Reddy Gooty
By default relocation happens to a higher address of DDR,
i.e, DDR start + DDR size.
U-Boot shall be used to collect the ramdump.
Restrict U-Boot to use only the 16MB memory, so that this
memory can be reserved. Limit relocation to happen within
16MB memory, start 0xFF00_ and end 0x1__
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Simon Glass
---
Changes from v3:
-Address review comments from Simon,
Update the commit message.
board/broadcom/bcmns3/ns3.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 418db67875..33e25376f2 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -141,6 +141,11 @@ static int mem_info_parse_fixup(void *fdt)
int board_init(void)
{
+ /* Setup memory using "memory" node from DTB */
+ if (fdtdec_setup_mem_size_base() != 0)
+ return -EINVAL;
+ fdtdec_setup_memory_banksize();
+
if (bl33_info->version != BL33_INFO_VERSION)
printf("*** warning: ATF BL31 and u-boot not in sync! ***\n");
@@ -154,19 +159,30 @@ int board_late_init(void)
int dram_init(void)
{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
+ /*
+* Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_.
+* So that relocation happens with in the last 16MB memory.
+*/
+ gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
+ gd->ram_size = (unsigned long)SZ_16M;
return 0;
}
int dram_init_banksize(void)
{
- fdtdec_setup_memory_banksize();
+ gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
+ gd->bd->bi_dram[0].size = SZ_16M;
return 0;
}
+/* Limit RAM used by U-Boot to the DDR first bank End region */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return BCM_NS3_MEM_END;
+}
+
void reset_cpu(ulong level)
{
#define L3_RESET 30
--
2.17.1
[PATCH v4 06/15] board: ns3: default reset type to L3
Default "reset" from U-Boot to L3 reset.
"reset" command with argument will trigger L1 reset.
Signed-off-by: Rajesh Ravi
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
---
Changes from v3:
-Address review comments from Simon,
Update commit message ie change u-boot to U-Boot
board/broadcom/bcmns3/ns3.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 5e644bd466..1221f26ddc 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -68,7 +68,23 @@ int dram_init_banksize(void)
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(ulong level)
{
- psci_system_reset();
+#define L3_RESET 30
+ u32 reset_level, strap_val;
+
+ /* Default reset type is L3 reset */
+ if (!level) {
+ /*
+* Encoding: u-boot reset command expects decimal argument
+* strap val = 1st decimal digit;reset level = 2nd decimal digit
+*/
+ strap_val = L3_RESET % 10;
+ level = L3_RESET / 10;
+ reset_level = level % 10;
+ psci_system_reset2(reset_level, strap_val);
+ } else {
+ /* U-boot cmd "reset" with any arg will trigger L1 reset */
+ psci_system_reset();
+ }
}
--
2.17.1
[PATCH v4 04/15] dt-bindings: memory: ns3: add memory definitions
Add NS3 memory definitions. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- Changes from v3: -Address review comments from Simon, Use lower-case hex number include/dt-bindings/memory/bcm-ns3-mc.h | 34 + 1 file changed, 34 insertions(+) create mode 100644 include/dt-bindings/memory/bcm-ns3-mc.h diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h new file mode 100644 index 00..fe669e2f87 --- /dev/null +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Broadcom + */ + +#ifndef DT_BINDINGS_BCM_NS3_MC_H +#define DT_BINDINGS_BCM_NS3_MC_H + +/* + * Reserved Memory Map : SHMEM & TZDRAM. + * ++--+ 0x8d00 + * | SHMEM (NS) | 16 MB + * +---+ 0x8e00 + * || TEE_RAM(S)| 4MB + * + TZDRAM +--+ 0x8e40 + * || TA_RAM(S) | 12MB + * ++--+ 0x8f00 + * | BL31 + TMON + LPM | + * | memory | 1MB + * +---+ 0x8f10 + */ + +#define BCM_NS3_MEM_SHARE_START0x8d00 +#define BCM_NS3_MEM_SHARE_LEN 0x020f + +/* ATF/U-boot/Linux error logs */ +#define BCM_NS3_MEM_ELOG_START 0x8f113000 +#define BCM_NS3_MEM_ELOG_LEN 0x0010 + +/* CRMU Page table memroy */ +#define BCM_NS3_MEM_CRMU_PT_START 0x88000 +#define BCM_NS3_MEM_CRMU_PT_LEN0x20 + +#endif -- 2.17.1
