from:"Stefan Mavrodiev"

[U-Boot] [PATCH 1/1] net: sun8i_emac: Remove debug message

2019-11-04 Thread Stefan Mavrodiev

When booting with sun8i_emac driver, the user get output like this:

  ...
  Net:   phy interface7
  eth0: ethernet@1c3
  ...

The first line doesn't provide any useful information except for the
developers. I guess this is some leftover debugging message. This
patch change it to such. The new output is:

  ...
  Net:   eth0: ethernet@1c3
  ...

Signed-off-by: Stefan Mavrodiev 
---
 drivers/net/sun8i_emac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 0629b16e57..e6cb074bc4 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -968,7 +968,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice 
*dev)
 
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
-   printf("phy interface%d\n", pdata->phy_interface);
+   debug("phy interface%d\n", pdata->phy_interface);
 
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
-- 
2.17.1

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Re: [U-Boot] [PATCH 1/1] sunxi: Fix pll1 clock calculation

2019-08-26 Thread Stefan Mavrodiev


Can someone review this patch?

Best regards,
Stefan

On 7/31/19 4:15 PM, Stefan Mavrodiev wrote:

clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families.
PLL1 clock sets the default system clock, defined as:
   sun6i: 100800
   sun8i: 100800
   sun50i: 81600

With the current calculation, m = 2 and k = 3. Solving for n,
this results 28. Solving back:
   (24MHz * 28 * 3) / 2 = 1008MHz

However if the requested clock is 816, n is 22.66 rounded
to 22, which results:
   (24MHz * 28 * 3) / 2 = 792MHz

Changing k to 4 satisfies both system clocks:
   (24E6 * 21 * 4) / 2 = 1008MHz
   (24E6 * 17 * 4) / 2 = 816MHz

Signed-off-by: Stefan Mavrodiev 
---
  arch/arm/mach-sunxi/clock_sun6i.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index 1628f3a7b6..6ca38f73d9 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk)
if (clk > 115200) {
k = 2;
} else if (clk > 76800) {
-   k = 3;
+   k = 4;
m = 2;
}
  

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[U-Boot] [PATCH 1/1] sunxi: Fix pll1 clock calculation

2019-07-31 Thread Stefan Mavrodiev

clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families.
PLL1 clock sets the default system clock, defined as:
  sun6i: 100800
  sun8i: 100800
  sun50i: 81600

With the current calculation, m = 2 and k = 3. Solving for n,
this results 28. Solving back:
  (24MHz * 28 * 3) / 2 = 1008MHz

However if the requested clock is 816, n is 22.66 rounded
to 22, which results:
  (24MHz * 28 * 3) / 2 = 792MHz

Changing k to 4 satisfies both system clocks:
  (24E6 * 21 * 4) / 2 = 1008MHz
  (24E6 * 17 * 4) / 2 = 816MHz

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/mach-sunxi/clock_sun6i.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index 1628f3a7b6..6ca38f73d9 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk)
if (clk > 115200) {
k = 2;
} else if (clk > 76800) {
-   k = 3;
+   k = 4;
m = 2;
}
 
-- 
2.17.1

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Re: [U-Boot] [PATCH] video: backlight: fix pwm invertation

2019-07-02 Thread Stefan Mavrodiev



On 7/2/19 12:05 PM, Stefan Mavrodiev wrote:

Hi,

On 7/2/19 11:42 AM, Nicolas Chauvet wrote:
Le mar. 2 juil. 2019 à 09:41, Stefan Mavrodiev  a 
écrit :

Hi,

On 6/27/19 9:56 PM, marvi...@posteo.de wrote:

Am Freitag, 21. Juni 2019, 22:01:35 CEST schrieb Marc Dietrich:

Fixes: 57e7775413 ("video: backlight: Parse PWM polarity cell")

set_pwm will always fail if pwm_set_invert is not implemented, 
leaving the
backlight dark. Fix this by calling pwm_set_invert only if pwm is 
inverted.

I'm not sure if this is true. pwm_set_invert() checks for .set_invert.
Which pwm driver you're using?

This is drivers/pwm/pwm_tegra.c
Here .set_invert is not implemented.

Thx for the review.

You're right. Some drivers has #pwm-cells = <2> and in this case 
polarity is 0.


However your approach is wrong. You will break other drivers with 
#pwm-cells = <3>.

I think your patch should look something like this:

ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
if (ret == -ENOSYS)
    ret = 0;

return log_ret(ret);



You should ask the custodians to review this.



This will not return error if set_inverted is not implemented.



Stefan


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Re: [U-Boot] [PATCH] video: backlight: fix pwm invertation

2019-07-02 Thread Stefan Mavrodiev


Hi,

On 7/2/19 11:42 AM, Nicolas Chauvet wrote:

Le mar. 2 juil. 2019 à 09:41, Stefan Mavrodiev  a écrit :

Hi,

On 6/27/19 9:56 PM, marvi...@posteo.de wrote:

Am Freitag, 21. Juni 2019, 22:01:35 CEST schrieb Marc Dietrich:

Fixes: 57e7775413 ("video: backlight: Parse PWM polarity cell")

set_pwm will always fail if pwm_set_invert is not implemented, leaving the
backlight dark. Fix this by calling pwm_set_invert only if pwm is inverted.

I'm not sure if this is true. pwm_set_invert() checks for .set_invert.
Which pwm driver you're using?

This is drivers/pwm/pwm_tegra.c
Here .set_invert is not implemented.

Thx for the review.

You're right. Some drivers has #pwm-cells = <2> and in this case 
polarity is 0.


However your approach is wrong. You will break other drivers with 
#pwm-cells = <3>.

I think your patch should look something like this:

ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
if (ret == -ENOSYS)
    ret = 0;

return log_ret(ret);

This will not return error if set_inverted is not implemented.


Stefan

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Re: [U-Boot] [PATCH] video: backlight: fix pwm invertation

2019-07-02 Thread Stefan Mavrodiev


Hi,

On 6/27/19 9:56 PM, marvi...@posteo.de wrote:

Am Freitag, 21. Juni 2019, 22:01:35 CEST schrieb Marc Dietrich:

Fixes: 57e7775413 ("video: backlight: Parse PWM polarity cell")

set_pwm will always fail if pwm_set_invert is not implemented, leaving the
backlight dark. Fix this by calling pwm_set_invert only if pwm is inverted.

I'm not sure if this is true. pwm_set_invert() checks for .set_invert.
Which pwm driver you're using?




Signed-off-by: Marc Dietrich 

ping?



---
  drivers/video/pwm_backlight.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index a587977c22..26bcbeb42b 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -61,12 +61,13 @@ static int set_pwm(struct pwm_backlight_priv *priv)

duty_cycle = priv->period_ns * (priv->cur_level - priv->min_level) /
(priv->max_level - priv->min_level + 1);
+
ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
 duty_cycle);
-   if (ret)
-   return log_ret(ret);

-   ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
+   if (!ret && priv->polarity)
+   ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
This shouldn't be a problem. Rather the driver doesn't handle polarity 
correctly.

+
return log_ret(ret);
  }

--
2.17.1


P.S.

You should cc to all maintainers. You can use ./scripts/get_maintainer.pl.


Best regards,
Stefan Mavrodiev

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[U-Boot] [PATCH v2 1/1] common: fdt_support: Check mtdparts cell size

2019-04-23 Thread Stefan Mavrodiev

When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8 bytes (2 cells) [1].

This patch read #size-cells and uses either fdt32_t or
fdt64_t cell size. The default is fdt32_t.

[1] Documentation/devicetree/bindings/mtd/partition.txt

Signed-off-by: Stefan Mavrodiev 
---
Changes for v2:
- Use fdt_setprop_u64() and ..._u32() instead of fdt_setprop()
- Add size value using fdt_appendprop_u64() and ..._u32()

 common/fdt_support.c | 31 ++-
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42583e3ed8..1c1a954829 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -724,11 +724,6 @@ int fdt_increase_size(void *fdt, int add_len)
 #include 
 #include 
 
-struct reg_cell {
-   unsigned int r0;
-   unsigned int r1;
-};
-
 static int fdt_del_subnodes(const void *blob, int parent_offset)
 {
int off, ndepth;
@@ -787,15 +782,22 @@ int fdt_node_set_part_info(void *blob, int parent_offset,
 {
struct list_head *pentry;
struct part_info *part;
-   struct reg_cell cell;
int off, ndepth = 0;
int part_num, ret;
+   int sizecell;
char buf[64];
 
ret = fdt_del_partitions(blob, parent_offset);
if (ret < 0)
return ret;
 
+   /*
+* Check if size/address is 1 or 2 cells.
+* We assume #address-cells and #size-cells have same value.
+*/
+   sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+   0, "#size-cells", 1);
+
/*
 * Check if it is nand {}; subnode, adjust
 * the offset in this case
@@ -844,10 +846,21 @@ add_ro:
goto err_prop;
}
 
-   cell.r0 = cpu_to_fdt32(part->offset);
-   cell.r1 = cpu_to_fdt32(part->size);
 add_reg:
-   ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+   if (sizecell == 2) {
+   ret = fdt_setprop_u64(blob, newoff,
+ "reg", part->offset);
+   if (!ret)
+   ret = fdt_appendprop_u64(blob, newoff,
+"reg", part->size);
+   } else {
+   ret = fdt_setprop_u32(blob, newoff,
+ "reg", part->offset);
+   if (!ret)
+   ret = fdt_appendprop_u32(blob, newoff,
+"reg", part->size);
+   }
+
if (ret == -FDT_ERR_NOSPACE) {
ret = fdt_increase_size(blob, 512);
if (!ret)
-- 
2.17.1

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Re: [U-Boot] [PATCH 1/1] common: fdt_support: Check mtdparts cell size

2019-04-22 Thread Stefan Mavrodiev



On 4/21/19 10:33 PM, Simon Glass wrote:

Hi Stefan,

On Fri, 12 Apr 2019 at 02:46, Stefan Mavrodiev  wrote:

When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8 bytes (2 cells) [1].

This patch read #size-cells and uses either fdt32_t or
fdt64_t cell size. The default is fdt32_t.

[1] Documentation/devicetree/bindings/mtd/partition.txt

Signed-off-by: Stefan Mavrodiev 
---
  common/fdt_support.c | 33 -
  1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42583e3ed8..b0501e12e6 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -724,11 +724,6 @@ int fdt_increase_size(void *fdt, int add_len)
  #include 
  #include 

-struct reg_cell {
-   unsigned int r0;
-   unsigned int r1;
-};
-
  static int fdt_del_subnodes(const void *blob, int parent_offset)
  {
 int off, ndepth;
@@ -787,15 +782,22 @@ int fdt_node_set_part_info(void *blob, int parent_offset,
  {
 struct list_head *pentry;
 struct part_info *part;
-   struct reg_cell cell;
 int off, ndepth = 0;
 int part_num, ret;
+   int sizecell;
 char buf[64];

 ret = fdt_del_partitions(blob, parent_offset);
 if (ret < 0)
 return ret;

+   /*
+* Check if size/address is 1 or 2 cells.
+* We assume #address-cells and #size-cells have same value.
+*/
+   sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+   0, "#size-cells", 1);
+
 /*
  * Check if it is nand {}; subnode, adjust
  * the offset in this case
@@ -844,10 +846,23 @@ add_ro:
 goto err_prop;
 }

-   cell.r0 = cpu_to_fdt32(part->offset);
-   cell.r1 = cpu_to_fdt32(part->size);
  add_reg:
-   ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+   if (sizecell == 2) {
+   fdt64_t cell[2];
+
+   cell[0] = cpu_to_fdt64(part->offset);
+   cell[1] = cpu_to_fdt64(part->size);
+   ret = fdt_setprop(blob, newoff,
+ "reg", cell, sizeof(cell));

Can you use fdt_setprop_u64() and ..._u32() instead?

Sure.



+   } else {
+   fdt32_t cell[2];
+
+   cell[0] = cpu_to_fdt32(part->offset);
+   cell[1] = cpu_to_fdt32(part->size);
+   ret = fdt_setprop(blob, newoff,
+ "reg", cell, sizeof(cell));
+   }
+
 if (ret == -FDT_ERR_NOSPACE) {
 ret = fdt_increase_size(blob, 512);
     if (!ret)
--
2.17.1


Regards,
SImon

Best regards,
Stefan Mavrodiev
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[U-Boot] [PATCH 1/1] common: fdt_support: Check mtdparts cell size

2019-04-12 Thread Stefan Mavrodiev

When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8 bytes (2 cells) [1].

This patch read #size-cells and uses either fdt32_t or
fdt64_t cell size. The default is fdt32_t.

[1] Documentation/devicetree/bindings/mtd/partition.txt

Signed-off-by: Stefan Mavrodiev 
---
 common/fdt_support.c | 33 -
 1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42583e3ed8..b0501e12e6 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -724,11 +724,6 @@ int fdt_increase_size(void *fdt, int add_len)
 #include 
 #include 
 
-struct reg_cell {
-   unsigned int r0;
-   unsigned int r1;
-};
-
 static int fdt_del_subnodes(const void *blob, int parent_offset)
 {
int off, ndepth;
@@ -787,15 +782,22 @@ int fdt_node_set_part_info(void *blob, int parent_offset,
 {
struct list_head *pentry;
struct part_info *part;
-   struct reg_cell cell;
int off, ndepth = 0;
int part_num, ret;
+   int sizecell;
char buf[64];
 
ret = fdt_del_partitions(blob, parent_offset);
if (ret < 0)
return ret;
 
+   /*
+* Check if size/address is 1 or 2 cells.
+* We assume #address-cells and #size-cells have same value.
+*/
+   sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+   0, "#size-cells", 1);
+
/*
 * Check if it is nand {}; subnode, adjust
 * the offset in this case
@@ -844,10 +846,23 @@ add_ro:
goto err_prop;
}
 
-   cell.r0 = cpu_to_fdt32(part->offset);
-   cell.r1 = cpu_to_fdt32(part->size);
 add_reg:
-   ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+   if (sizecell == 2) {
+   fdt64_t cell[2];
+
+   cell[0] = cpu_to_fdt64(part->offset);
+   cell[1] = cpu_to_fdt64(part->size);
+   ret = fdt_setprop(blob, newoff,
+ "reg", cell, sizeof(cell));
+   } else {
+   fdt32_t cell[2];
+
+   cell[0] = cpu_to_fdt32(part->offset);
+   cell[1] = cpu_to_fdt32(part->size);
+   ret = fdt_setprop(blob, newoff,
+ "reg", cell, sizeof(cell));
+   }
+
if (ret == -FDT_ERR_NOSPACE) {
ret = fdt_increase_size(blob, 512);
if (!ret)
-- 
2.17.1

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[U-Boot] [PATCH v2 1/1] video: backlight: Parse PWM polarity cell

2019-04-11 Thread Stefan Mavrodiev

This patch enables the reading of the polarity cell from a PWM
phandle and calls pwm_set_invert().

Not all platforms have polarity cell, so skip if it's not pressent.

Signed-off-by: Stefan Mavrodiev 
---
Changes for v2:
- Check if phandle has polarity cell
- Add missing signed-off-by

 drivers/video/pwm_backlight.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index bd733f5f1c..a587977c22 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -39,6 +39,12 @@ struct pwm_backlight_priv {
struct udevice *pwm;
uint channel;
uint period_ns;
+   /*
+* the polarity of one PWM
+* 0: normal polarity
+* 1: inverted polarity
+*/
+   bool polarity;
u32 *levels;
int num_levels;
uint default_level;
@@ -57,7 +63,10 @@ static int set_pwm(struct pwm_backlight_priv *priv)
(priv->max_level - priv->min_level + 1);
ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
 duty_cycle);
+   if (ret)
+   return log_ret(ret);
 
+   ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
return log_ret(ret);
 }
 
@@ -202,6 +211,8 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice 
*dev)
return log_msg_ret("Not enough arguments to pwm\n", -EINVAL);
priv->channel = args.args[0];
priv->period_ns = args.args[1];
+   if (args.args_count > 2)
+   priv->polarity = args.args[2];
 
index = dev_read_u32_default(dev, "default-brightness-level", 255);
cell = dev_read_prop(dev, "brightness-levels", &len);
-- 
2.17.1

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[U-Boot] [PATCH 1/1] video: backlight: Parse PWM polarity cell

2019-03-25 Thread Stefan Mavrodiev

This patch enables the reading of the polarity cell from a PWM
phandle and calls pwm_set_invert().
---
 drivers/video/pwm_backlight.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index bd733f5f1c..0a08a76af1 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -39,6 +39,12 @@ struct pwm_backlight_priv {
struct udevice *pwm;
uint channel;
uint period_ns;
+   /*
+* the polarity of one PWM
+* 0: normal polarity
+* 1: inverted polarity
+*/
+   bool polarity;
u32 *levels;
int num_levels;
uint default_level;
@@ -57,7 +63,10 @@ static int set_pwm(struct pwm_backlight_priv *priv)
(priv->max_level - priv->min_level + 1);
ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
 duty_cycle);
+   if (ret)
+   return log_ret(ret);
 
+   ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
return log_ret(ret);
 }
 
@@ -202,6 +211,7 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice 
*dev)
return log_msg_ret("Not enough arguments to pwm\n", -EINVAL);
priv->channel = args.args[0];
priv->period_ns = args.args[1];
+   priv->polarity = args.args[2];
 
index = dev_read_u32_default(dev, "default-brightness-level", 255);
cell = dev_read_prop(dev, "brightness-levels", &len);
-- 
2.17.1

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Re: [U-Boot] [PATCH v2 4/8] spi: sun4i: Access registers and bits via enum offsets

2019-02-18 Thread Stefan Mavrodiev



On 2/18/19 12:38 PM, Jagan Teki wrote:

Hi Stefan,

On Fri, Feb 15, 2019 at 12:12 PM Stefan Mavrodiev  wrote:



[snip]


+static const unsigned long sun4i_spi_bits[] = {

Same here, make it uint32_t, since it describes register masks in 32 bit
registers.


+[SPI_GCR_TP]= BIT(18),
+[SPI_TCR_CPHA]  = BIT(2),
+[SPI_TCR_CPOL]  = BIT(3),
+[SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
+[SPI_TCR_XCH]   = BIT(10),
+[SPI_TCR_CS_SEL]= 12,
+[SPI_TCR_CS_MASK]   = 0x3000,
+[SPI_TCR_CS_MANUAL] = BIT(16),
+[SPI_TCR_CS_LEVEL]  = BIT(17),
+[SPI_FCR_TF_RST]= BIT(8),
+[SPI_FCR_RF_RST]= BIT(9),
+[SPI_FSR_RF_CNT_MASK]   = GENMASK(6, 0),
+};
+
+static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
+.regs   = sun4i_spi_regs,
+.bits   = sun4i_spi_bits,
+};
+
   static const struct udevice_id sun4i_spi_ids[] = {
-{ .compatible = "allwinner,sun4i-a10-spi"  },
+{
+  .compatible = "allwinner,sun4i-a10-spi",
+  .data = (ulong)&sun4i_a10_spi_variant,
+},
  { }
   };



I checked the rest as good as my brain allows me at 11pm, but it's still
quite a change with a lot of bits here and there :-(

Stefan, can you please test that this still works for you on the A20? If
I find some time I can try to hook up some SPI chip to my BananaPi, but
I guess it's easier for you to test.

Here are some test results:

=> sf probe 0:0
SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total
16 MiB

=> sf test 0 10
SPI flash test:
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.312 Mbps
3 read: 815 ticks, 1256 KiB/s 10.048 Mbps
Test passed
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.312 Mbps
3 read: 815 ticks, 1256 KiB/s 10.048 Mbps

The original tests can be seen here [1].

Apparently the patch works and it can be seen some
speed improvement.

Thanks for testing this.

Can I add your Tested-by credit?

Sure.
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Re: [U-Boot] [PATCH v2 4/8] spi: sun4i: Access registers and bits via enum offsets

2019-02-14 Thread Stefan Mavrodiev

[SPI_TCR]   = SUN4I_CTL_REG,
+   [SPI_FCR]   = SUN4I_CTL_REG,
+   [SPI_FSR]   = SUN4I_FIFO_STA_REG,
+   [SPI_CCR]   = SUN4I_CLK_CTL_REG,
+   [SPI_BC]= SUN4I_BURST_CNT_REG,
+   [SPI_TC]= SUN4I_XMIT_CNT_REG,
+   [SPI_TXD]   = SUN4I_TXDATA_REG,
+   [SPI_RXD]   = SUN4I_RXDATA_REG,
+};
+
+static const unsigned long sun4i_spi_bits[] = {

Same here, make it uint32_t, since it describes register masks in 32 bit
registers.


+   [SPI_GCR_TP]= BIT(18),
+   [SPI_TCR_CPHA]  = BIT(2),
+   [SPI_TCR_CPOL]  = BIT(3),
+   [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
+   [SPI_TCR_XCH]   = BIT(10),
+   [SPI_TCR_CS_SEL]= 12,
+   [SPI_TCR_CS_MASK]   = 0x3000,
+   [SPI_TCR_CS_MANUAL] = BIT(16),
+   [SPI_TCR_CS_LEVEL]  = BIT(17),
+   [SPI_FCR_TF_RST]= BIT(8),
+   [SPI_FCR_RF_RST]= BIT(9),
+   [SPI_FSR_RF_CNT_MASK]   = GENMASK(6, 0),
+};
+
+static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
+   .regs   = sun4i_spi_regs,
+   .bits   = sun4i_spi_bits,
+};
+
  static const struct udevice_id sun4i_spi_ids[] = {
-   { .compatible = "allwinner,sun4i-a10-spi"  },
+   {
+ .compatible = "allwinner,sun4i-a10-spi",
+ .data = (ulong)&sun4i_a10_spi_variant,
+   },
{ }
  };
  


I checked the rest as good as my brain allows me at 11pm, but it's still
quite a change with a lot of bits here and there :-(

Stefan, can you please test that this still works for you on the A20? If
I find some time I can try to hook up some SPI chip to my BananaPi, but
I guess it's easier for you to test.


Here are some test results:

=> sf probe 0:0
SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 
16 MiB


=> sf test 0 10
SPI flash test:
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.312 Mbps
3 read: 815 ticks, 1256 KiB/s 10.048 Mbps
Test passed
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.312 Mbps
3 read: 815 ticks, 1256 KiB/s 10.048 Mbps

The original tests can be seen here [1].

Apparently the patch works and it can be seen some
speed improvement.

The test is done on A20-SOM204 board. I can run it on other boards as
well, but since the routing is the same, I don't this there is a need.


Best regards,
Stefan Mavrodiev

[1] https://patchwork.ozlabs.org/patch/869763/



Cheers,
Andre.

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[U-Boot] [PATCH 1/1] sunxi: board: Add i2c initialization for sun50i

2019-01-08 Thread Stefan Mavrodiev

To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.

This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.

Tested with A64-SOM204 board.

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/include/asm/arch-sunxi/gpio.h |  3 +++
 board/sunxi/board.c| 12 
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 2daf23f6f5..40a3f845d0 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -176,6 +176,7 @@ enum sunxi_gpio_number {
 
 #define SUN5I_GPE_SDC2 3
 #define SUN8I_GPE_TWI2 3
+#define SUN50I_GPE_TWI23
 
 #define SUNXI_GPF_SDC0 2
 #define SUNXI_GPF_UART04
@@ -193,8 +194,10 @@ enum sunxi_gpio_number {
 #define SUN4I_GPH_SDC1 5
 #define SUN6I_GPH_TWI0 2
 #define SUN8I_GPH_TWI0 2
+#define SUN50I_GPH_TWI02
 #define SUN6I_GPH_TWI1 2
 #define SUN8I_GPH_TWI1 2
+#define SUN50I_GPH_TWI12
 #define SUN6I_GPH_TWI2 2
 #define SUN6I_GPH_UART02
 #define SUN9I_GPH_UART02
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f022f365e9..ad14837291 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -98,6 +98,10 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN50I)
+   sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
+   sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
+   clock_twi_onoff(0, 1);
 #endif
 #endif
 
@@ -120,6 +124,10 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN50I)
+   sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
+   sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
+   clock_twi_onoff(1, 1);
 #endif
 #endif
 
@@ -142,6 +150,10 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN50I)
+   sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
+   sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
+   clock_twi_onoff(2, 1);
 #endif
 #endif
 
-- 
2.17.1

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Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-20 Thread Stefan Mavrodiev



On 12/20/18 2:44 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 6:12 PM Stefan Mavrodiev  wrote:


On 12/20/18 2:38 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 5:38 PM Stefan Mavrodiev  wrote:

On 12/20/18 1:54 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 4:49 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:56 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 4:18 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:45 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:14 PM, Jagan Teki wrote:

On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki  wrote:

On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev  wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
   drivers/spi/sun4i_spi.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)

  while (len--) {
  byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;

Acked-by: Jagan Teki 

But, have you tested how much data in the fifo before drained? It's
better we can get the available data before reading via fifo_sta

I don't understand what's the point of doing this?

Didn't get? don't you understand what I'm saying or it not require
from point of you?

Maybe I don't understand correctly what you're saying.

You comment now and previous mail doesn't match. better be specific.

For draining fifo.
We can find how much data available before reading from fifo and
assign to local rx.

static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
{
   u32 reg, cnt
   u8 byte;

/* See how much data is available */
reg = readl(&priv->regs->fifo_sta);
reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;

if (len > cnt)
len = cnt;

while (len--) {
byte = readb(&priv->regs->rxdata);
*priv->rx_buf++ = byte;
}
}

This can be perfect drain fifo, and this is what I'm trying to test
you with existing code and after your patch and verify whether all the
data perfectly drain or not before and after.

Hope you understand, this time.

Hope I understood this time...


I've made some modification to sun4i_spi_xfer:

static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
  const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
struct sun4i_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);

u32 len = bitlen / 8;
u32 reg, cnt;
u8 nbytes;
int ret;

priv->tx_buf = dout;
priv->rx_buf = din;

if (bitlen % 8) {
debug("%s: non byte-aligned SPI transfer.\n", __func__);
return -ENAVAIL;
}

if (flags & SPI_XFER_BEGIN)
sun4i_spi_set_cs(bus, slave_plat->cs, true);

reg = readl(&priv->regs->ctl);

/* Reset FIFOs */
writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);

while (len) {
/* Setup the transfer now... */
nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));

if (!priv->rx_buf)
printf("%s: Sending %d bytes, ", __func__, nbytes);

/* Setup the counters */
writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);

/* Fill the TX FIFO */
sun4i_spi_fill_fifo(priv, nbytes);

/* Start the transfer */
reg = readl(&priv->regs->ctl);
writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);

/* Wait transfer to complete */
ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
false, SUN4I_SPI_TIMEOUT_US, false);
if (ret) {
printf("ERROR: sun4i_spi: Timeout transferring data\n");
sun4i_spi_set_cs(bus, slave_plat->cs, false);
return ret;
}

/* Drain the RX FIFO */
if (!priv->rx_buf) {
reg = readl(&priv-&g

Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-20 Thread Stefan Mavrodiev



On 12/20/18 2:38 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 5:38 PM Stefan Mavrodiev  wrote:


On 12/20/18 1:54 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 4:49 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:56 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 4:18 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:45 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:14 PM, Jagan Teki wrote:

On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki  wrote:

On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev  wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
  drivers/spi/sun4i_spi.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)

 while (len--) {
 byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;

Acked-by: Jagan Teki 

But, have you tested how much data in the fifo before drained? It's
better we can get the available data before reading via fifo_sta

I don't understand what's the point of doing this?

Didn't get? don't you understand what I'm saying or it not require
from point of you?

Maybe I don't understand correctly what you're saying.

You comment now and previous mail doesn't match. better be specific.

For draining fifo.
We can find how much data available before reading from fifo and
assign to local rx.

static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
{
  u32 reg, cnt
  u8 byte;

   /* See how much data is available */
   reg = readl(&priv->regs->fifo_sta);
   reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
   cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;

   if (len > cnt)
   len = cnt;

   while (len--) {
   byte = readb(&priv->regs->rxdata);
   *priv->rx_buf++ = byte;
   }
}

This can be perfect drain fifo, and this is what I'm trying to test
you with existing code and after your patch and verify whether all the
data perfectly drain or not before and after.

Hope you understand, this time.

Hope I understood this time...


I've made some modification to sun4i_spi_xfer:

static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 const void *dout, void *din, unsigned long flags)
{
   struct udevice *bus = dev->parent;
   struct sun4i_spi_priv *priv = dev_get_priv(bus);
   struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);

   u32 len = bitlen / 8;
   u32 reg, cnt;
   u8 nbytes;
   int ret;

   priv->tx_buf = dout;
   priv->rx_buf = din;

   if (bitlen % 8) {
   debug("%s: non byte-aligned SPI transfer.\n", __func__);
   return -ENAVAIL;
   }

   if (flags & SPI_XFER_BEGIN)
   sun4i_spi_set_cs(bus, slave_plat->cs, true);

   reg = readl(&priv->regs->ctl);

   /* Reset FIFOs */
   writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);

   while (len) {
   /* Setup the transfer now... */
   nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));

   if (!priv->rx_buf)
   printf("%s: Sending %d bytes, ", __func__, nbytes);

   /* Setup the counters */
   writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
   writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);

   /* Fill the TX FIFO */
   sun4i_spi_fill_fifo(priv, nbytes);

   /* Start the transfer */
   reg = readl(&priv->regs->ctl);
   writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);

   /* Wait transfer to complete */
   ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
   false, SUN4I_SPI_TIMEOUT_US, false);
   if (ret) {
   printf("ERROR: sun4i_spi: Timeout transferring data\n");
   sun4i_spi_set_cs(bus, slave_plat->cs, false);
   return ret;
   }

   /* Drain the RX FIFO */
   if (!priv->rx_buf) {
   reg = readl(&priv->regs->fifo_sta);
   reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
   cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
   pr

Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-20 Thread Stefan Mavrodiev



On 12/20/18 1:54 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 4:49 PM Stefan Mavrodiev  wrote:


On 12/20/18 12:56 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 4:18 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:45 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:14 PM, Jagan Teki wrote:

On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki  wrote:

On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev  wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
 drivers/spi/sun4i_spi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)

while (len--) {
byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;

Acked-by: Jagan Teki 

But, have you tested how much data in the fifo before drained? It's
better we can get the available data before reading via fifo_sta

I don't understand what's the point of doing this?

Didn't get? don't you understand what I'm saying or it not require
from point of you?

Maybe I don't understand correctly what you're saying.

You comment now and previous mail doesn't match. better be specific.

For draining fifo.
We can find how much data available before reading from fifo and
assign to local rx.

static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
{
 u32 reg, cnt
 u8 byte;

  /* See how much data is available */
  reg = readl(&priv->regs->fifo_sta);
  reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
  cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;

  if (len > cnt)
  len = cnt;

  while (len--) {
  byte = readb(&priv->regs->rxdata);
  *priv->rx_buf++ = byte;
  }
}

This can be perfect drain fifo, and this is what I'm trying to test
you with existing code and after your patch and verify whether all the
data perfectly drain or not before and after.

Hope you understand, this time.


Hope I understood this time...


I've made some modification to sun4i_spi_xfer:

static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
  struct udevice *bus = dev->parent;
  struct sun4i_spi_priv *priv = dev_get_priv(bus);
  struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);

  u32 len = bitlen / 8;
  u32 reg, cnt;
  u8 nbytes;
  int ret;

  priv->tx_buf = dout;
  priv->rx_buf = din;

  if (bitlen % 8) {
  debug("%s: non byte-aligned SPI transfer.\n", __func__);
  return -ENAVAIL;
  }

  if (flags & SPI_XFER_BEGIN)
  sun4i_spi_set_cs(bus, slave_plat->cs, true);

  reg = readl(&priv->regs->ctl);

  /* Reset FIFOs */
  writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);

  while (len) {
  /* Setup the transfer now... */
  nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));

  if (!priv->rx_buf)
  printf("%s: Sending %d bytes, ", __func__, nbytes);

  /* Setup the counters */
  writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
  writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);

  /* Fill the TX FIFO */
  sun4i_spi_fill_fifo(priv, nbytes);

  /* Start the transfer */
  reg = readl(&priv->regs->ctl);
  writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);

  /* Wait transfer to complete */
  ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
  false, SUN4I_SPI_TIMEOUT_US, false);
  if (ret) {
  printf("ERROR: sun4i_spi: Timeout transferring data\n");
  sun4i_spi_set_cs(bus, slave_plat->cs, false);
  return ret;
  }

  /* Drain the RX FIFO */
  if (!priv->rx_buf) {
  reg = readl(&priv->regs->fifo_sta);
  reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
  cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
  printf("rx fifo: before: %d, ", cnt);
  }

  sun4i_spi_drain_fifo(priv, nbytes);

So it's draining fifo without need to checking the

Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-20 Thread Stefan Mavrodiev



On 12/20/18 12:56 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 4:18 PM Stefan Mavrodiev  wrote:


On 12/20/18 12:45 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev  wrote:

On 12/20/18 12:14 PM, Jagan Teki wrote:

On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki  wrote:

On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev  wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
drivers/spi/sun4i_spi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)

   while (len--) {
   byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;

Acked-by: Jagan Teki 

But, have you tested how much data in the fifo before drained? It's
better we can get the available data before reading via fifo_sta

I don't understand what's the point of doing this?

Didn't get? don't you understand what I'm saying or it not require
from point of you?

Maybe I don't understand correctly what you're saying.

You comment now and previous mail doesn't match. better be specific.

For draining fifo.
We can find how much data available before reading from fifo and
assign to local rx.

static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
{
u32 reg, cnt
u8 byte;

 /* See how much data is available */
 reg = readl(&priv->regs->fifo_sta);
 reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
 cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;

 if (len > cnt)
 len = cnt;

 while (len--) {
 byte = readb(&priv->regs->rxdata);
 *priv->rx_buf++ = byte;
 }
}

This can be perfect drain fifo, and this is what I'm trying to test
you with existing code and after your patch and verify whether all the
data perfectly drain or not before and after.

Hope you understand, this time.



Hope I understood this time...


I've made some modification to sun4i_spi_xfer:

static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
              const void *dout, void *din, unsigned long flags)
{
    struct udevice *bus = dev->parent;
    struct sun4i_spi_priv *priv = dev_get_priv(bus);
    struct dm_spi_slave_platdata *slave_plat = 
dev_get_parent_platdata(dev);


    u32 len = bitlen / 8;
    u32 reg, cnt;
    u8 nbytes;
    int ret;

    priv->tx_buf = dout;
    priv->rx_buf = din;

    if (bitlen % 8) {
        debug("%s: non byte-aligned SPI transfer.\n", __func__);
        return -ENAVAIL;
    }

    if (flags & SPI_XFER_BEGIN)
        sun4i_spi_set_cs(bus, slave_plat->cs, true);

    reg = readl(&priv->regs->ctl);

    /* Reset FIFOs */
    writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);

    while (len) {
        /* Setup the transfer now... */
        nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));

        if (!priv->rx_buf)
            printf("%s: Sending %d bytes, ", __func__, nbytes);

        /* Setup the counters */
        writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
        writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);

        /* Fill the TX FIFO */
        sun4i_spi_fill_fifo(priv, nbytes);

        /* Start the transfer */
        reg = readl(&priv->regs->ctl);
        writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);

        /* Wait transfer to complete */
        ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
                    false, SUN4I_SPI_TIMEOUT_US, false);
        if (ret) {
            printf("ERROR: sun4i_spi: Timeout transferring data\n");
            sun4i_spi_set_cs(bus, slave_plat->cs, false);
            return ret;
        }

        /* Drain the RX FIFO */
        if (!priv->rx_buf) {
            reg = readl(&priv->regs->fifo_sta);
            reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
            cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
            printf("rx fifo: before: %d, ", cnt);
        }

        sun4i_spi_drain_fifo(priv, nbytes);

        if (!priv->rx_buf) {
            reg = readl(&priv->regs->fifo_sta);
            reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
            cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
            printf("after: %d\n", cnt);

Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-20 Thread Stefan Mavrodiev



On 12/20/18 12:45 PM, Jagan Teki wrote:

On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev  wrote:


On 12/20/18 12:14 PM, Jagan Teki wrote:

On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki  wrote:

On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev  wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
   drivers/spi/sun4i_spi.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)

  while (len--) {
  byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;

Acked-by: Jagan Teki 

But, have you tested how much data in the fifo before drained? It's
better we can get the available data before reading via fifo_sta

I don't understand what's the point of doing this?

Didn't get? don't you understand what I'm saying or it not require
from point of you?

Maybe I don't understand correctly what you're saying.
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Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-20 Thread Stefan Mavrodiev



On 12/20/18 12:14 PM, Jagan Teki wrote:

On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki  wrote:

On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev  wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
  drivers/spi/sun4i_spi.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)

 while (len--) {
 byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;

Acked-by: Jagan Teki 

But, have you tested how much data in the fifo before drained? It's
better we can get the available data before reading via fifo_sta

I don't understand what's the point of doing this?

Didn't find any response on this? Indeed I'm waiting for it.

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Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-19 Thread Stefan Mavrodiev



On 12/17/18 8:37 AM, Stefan Mavrodiev wrote:


On 12/14/18 5:55 PM, Maxime Ripard wrote:

On Fri, Dec 14, 2018 at 04:14:31PM +0200, Stefan Mavrodiev wrote:

On 12/14/18 11:25 AM, Maxime Ripard wrote:

On Thu, Dec 13, 2018 at 09:12:57AM +0200, Stefan Mavrodiev wrote:

On 12/6/18 8:41 AM, Stefan Mavrodiev wrote:

On 12/5/18 5:46 PM, Maxime Ripard wrote:

On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
    drivers/spi/sun4i_spi.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void
sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
      while (len--) {
    byte = readb(&priv->regs->rxdata);
-    *priv->rx_buf++ = byte;
+    if (priv->rx_buf)
+    *priv->rx_buf++ = byte;

It seems pretty inefficient to test the pointer at each access, it
would be better to check it once before starting the transfer.

I'm not sure if that can even happen?

I've tried to check that before draining the receive fifo, but
then the controller doesn't work. I'm thinking that the fifo must
be drained in any case.

Any further comments?

I was expecting you to comment on whether the FIFO needed to be
drained or not :)

Sorry. I didn't understand that.

Anyway. After some code checking, I found that the FIFO needs to be 
drained

because TP_EN (Transmit Pause Enable) bit is set during bus claim.

"

In master mode, it is used to control transmit state machine to
stop smart burst sending when RX FIFO is full.

..."

Perhaps this bit should be enabled only when we want to read back data?

It's been a while since I last looked at the spi driver. What is linux
doing?


In the kernel version there is the same check, like the one in the patch:

drivers/spi/spi-sun4i.c:
static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
..

while (len--) {
    byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
    if (sspi->rx_buf)
        *sspi->rx_buf++ = byte;
}
.

Guess I've missed this check when I was adopting the driver for u-boot.




Maxime



Any comments?
I think with all said, the patch can be merged as it is.

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Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-16 Thread Stefan Mavrodiev



On 12/14/18 5:55 PM, Maxime Ripard wrote:

On Fri, Dec 14, 2018 at 04:14:31PM +0200, Stefan Mavrodiev wrote:

On 12/14/18 11:25 AM, Maxime Ripard wrote:

On Thu, Dec 13, 2018 at 09:12:57AM +0200, Stefan Mavrodiev wrote:

On 12/6/18 8:41 AM, Stefan Mavrodiev wrote:

On 12/5/18 5:46 PM, Maxime Ripard wrote:

On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
    drivers/spi/sun4i_spi.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void
sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
      while (len--) {
    byte = readb(&priv->regs->rxdata);
-    *priv->rx_buf++ = byte;
+    if (priv->rx_buf)
+    *priv->rx_buf++ = byte;

It seems pretty inefficient to test the pointer at each access, it
would be better to check it once before starting the transfer.

I'm not sure if that can even happen?

I've tried to check that before draining the receive fifo, but
then the controller doesn't work. I'm thinking that the fifo must
be drained in any case.

Any further comments?

I was expecting you to comment on whether the FIFO needed to be
drained or not :)

Sorry. I didn't understand that.

Anyway. After some code checking, I found that the FIFO needs to be drained
because TP_EN (Transmit Pause Enable) bit is set during bus claim.

"

In master mode, it is used to control transmit state machine to
stop smart burst sending when RX FIFO is full.

..."

Perhaps this bit should be enabled only when we want to read back data?

It's been a while since I last looked at the spi driver. What is linux
doing?


In the kernel version there is the same check, like the one in the patch:

drivers/spi/spi-sun4i.c:
static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
..

while (len--) {
    byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
    if (sspi->rx_buf)
        *sspi->rx_buf++ = byte;
}
.

Guess I've missed this check when I was adopting the driver for u-boot.




Maxime


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Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-14 Thread Stefan Mavrodiev



On 12/14/18 11:25 AM, Maxime Ripard wrote:

On Thu, Dec 13, 2018 at 09:12:57AM +0200, Stefan Mavrodiev wrote:

On 12/6/18 8:41 AM, Stefan Mavrodiev wrote:

On 12/5/18 5:46 PM, Maxime Ripard wrote:

On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
   drivers/spi/sun4i_spi.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void
sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
     while (len--) {
   byte = readb(&priv->regs->rxdata);
-    *priv->rx_buf++ = byte;
+    if (priv->rx_buf)
+    *priv->rx_buf++ = byte;

It seems pretty inefficient to test the pointer at each access, it
would be better to check it once before starting the transfer.

I'm not sure if that can even happen?

I've tried to check that before draining the receive fifo, but
then the controller doesn't work. I'm thinking that the fifo must
be drained in any case.

Any further comments?

I was expecting you to comment on whether the FIFO needed to be
drained or not :)


Sorry. I didn't understand that.

Anyway. After some code checking, I found that the FIFO needs to be drained
because TP_EN (Transmit Pause Enable) bit is set during bus claim.

"

In master mode, it is used to control transmit state machine to
stop smart burst sending when RX FIFO is full.

..."

Perhaps this bit should be enabled only when we want to read back data?



Maxime


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Re: [U-Boot] [PATCH 1/1] usb: musb-new: sunxi: Fix null pointer access

2018-12-12 Thread Stefan Mavrodiev



On 12/5/18 3:16 PM, Marek Vasut wrote:

On 12/05/2018 02:06 PM, Stefan Mavrodiev wrote:

On 12/5/18 2:57 PM, Marek Vasut wrote:

On 12/05/2018 01:49 PM, Stefan Mavrodiev wrote:

When the device is in peripheral mode

Can you have two devices, one in peripheral mode and one in host mode,
on the same system ?

Not 100% sure, but I'm thinking there is only one OTG port for
all sunxi boards. The operation is decided in the Kconfig.

I'm rather sure I saw sunxi boards with more than one USB port.


there is no
struct usb_bus_priv allocated pointer, as the uclass driver
("usb_dev_generic") doesn't call per_device_auto_alloc_size.

This results in writing to the internal SDRAM at
 priv->desc_before_addr = true;

Signed-off-by: Stefan Mavrodiev 
---
   drivers/usb/musb-new/sunxi.c | 8 ++--
   1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 6cf9826cda..f3deb9bc66 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -435,11 +435,14 @@ static int musb_usb_probe(struct udevice *dev)
   {
   struct sunxi_glue *glue = dev_get_priv(dev);
   struct musb_host_data *host = &glue->mdata;
-    struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
   struct musb_hdrc_platform_data pdata;
   void *base = dev_read_addr_ptr(dev);
   int ret;
   +#ifdef CONFIG_USB_MUSB_HOST
+    struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+#endif
+
   if (!base)
   return -EINVAL;
   @@ -459,7 +462,6 @@ static int musb_usb_probe(struct udevice *dev)
   return ret;
   }
   -    priv->desc_before_addr = true;

See my question at the beginning, and if that can be the case, the fix
is to check if priv is not null here, eg.
if (priv)
   priv->...

Still, why is the priv data not allocated for device ?

Depending on configuration, the device is registered ether as
UCLASS_USB_DEV_GENERIC or UCLASS_USB. There is no

    .per_device_auto_alloc_size = sizeof(struct usb_bus_priv),

for the second. (As seen in drivers/usb/host/usb-uclass.c)

I see the code is rather horrible. I'd expect all that configuration to
come from DT otg-mode property instead of being hard-wired into the
code. Sigh.

Jagan, A-B ? I'd like to pick this .


   memset(&pdata, 0, sizeof(pdata));
   pdata.power = 250;
@@ -467,6 +469,8 @@ static int musb_usb_probe(struct udevice *dev)
   pdata.config = glue->cfg->config;
     #ifdef CONFIG_USB_MUSB_HOST
+    priv->desc_before_addr = true;
+
   pdata.mode = MUSB_HOST;
   host->host = musb_init_controller(&pdata, &glue->dev, base);
   if (!host->host)




Any further comments?

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Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-12 Thread Stefan Mavrodiev



On 12/6/18 8:41 AM, Stefan Mavrodiev wrote:


On 12/5/18 5:46 PM, Maxime Ripard wrote:

On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
  drivers/spi/sun4i_spi.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)

    while (len--) {
  byte = readb(&priv->regs->rxdata);
-    *priv->rx_buf++ = byte;
+    if (priv->rx_buf)
+    *priv->rx_buf++ = byte;

It seems pretty inefficient to test the pointer at each access, it
would be better to check it once before starting the transfer.

I'm not sure if that can even happen?


I've tried to check that before draining the receive fifo, but then 
the controller doesn't

work. I'm thinking that the fifo must be drained in any case.



Maxime


Any further comments?


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Re: [U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-06 Thread Stefan Mavrodiev



On 12/5/18 5:46 PM, Maxime Ripard wrote:

On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
  drivers/spi/sun4i_spi.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)
  
  	while (len--) {

byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;

It seems pretty inefficient to test the pointer at each access, it
would be better to check it once before starting the transfer.

I'm not sure if that can even happen?


I've tried to check that before draining the receive fifo, but then the 
controller doesn't

work. I'm thinking that the fifo must be drained in any case.



Maxime


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Re: [U-Boot] [PATCH 1/1] usb: musb-new: sunxi: Fix null pointer access

2018-12-05 Thread Stefan Mavrodiev



On 12/5/18 2:57 PM, Marek Vasut wrote:

On 12/05/2018 01:49 PM, Stefan Mavrodiev wrote:

When the device is in peripheral mode

Can you have two devices, one in peripheral mode and one in host mode,
on the same system ?


Not 100% sure, but I'm thinking there is only one OTG port for
all sunxi boards. The operation is decided in the Kconfig.




there is no
struct usb_bus_priv allocated pointer, as the uclass driver
("usb_dev_generic") doesn't call per_device_auto_alloc_size.

This results in writing to the internal SDRAM at
priv->desc_before_addr = true;

Signed-off-by: Stefan Mavrodiev 
---
  drivers/usb/musb-new/sunxi.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 6cf9826cda..f3deb9bc66 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -435,11 +435,14 @@ static int musb_usb_probe(struct udevice *dev)
  {
struct sunxi_glue *glue = dev_get_priv(dev);
struct musb_host_data *host = &glue->mdata;
-   struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct musb_hdrc_platform_data pdata;
void *base = dev_read_addr_ptr(dev);
int ret;
  
+#ifdef CONFIG_USB_MUSB_HOST

+   struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+#endif
+
if (!base)
return -EINVAL;
  
@@ -459,7 +462,6 @@ static int musb_usb_probe(struct udevice *dev)

return ret;
}
  
-	priv->desc_before_addr = true;

See my question at the beginning, and if that can be the case, the fix
is to check if priv is not null here, eg.
if (priv)
  priv->...

Still, why is the priv data not allocated for device ?


Depending on configuration, the device is registered ether as
UCLASS_USB_DEV_GENERIC or UCLASS_USB. There is no

   .per_device_auto_alloc_size = sizeof(struct usb_bus_priv),

for the second. (As seen in drivers/usb/host/usb-uclass.c)




memset(&pdata, 0, sizeof(pdata));
pdata.power = 250;
@@ -467,6 +469,8 @@ static int musb_usb_probe(struct udevice *dev)
pdata.config = glue->cfg->config;
  
  #ifdef CONFIG_USB_MUSB_HOST

+   priv->desc_before_addr = true;
+
pdata.mode = MUSB_HOST;
host->host = musb_init_controller(&pdata, &glue->dev, base);
if (!host->host)




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[U-Boot] [PATCH 1/1] usb: musb-new: sunxi: Fix null pointer access

2018-12-05 Thread Stefan Mavrodiev

When the device is in peripheral mode there is no
struct usb_bus_priv allocated pointer, as the uclass driver
("usb_dev_generic") doesn't call per_device_auto_alloc_size.

This results in writing to the internal SDRAM at
priv->desc_before_addr = true;

Signed-off-by: Stefan Mavrodiev 
---
 drivers/usb/musb-new/sunxi.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 6cf9826cda..f3deb9bc66 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -435,11 +435,14 @@ static int musb_usb_probe(struct udevice *dev)
 {
struct sunxi_glue *glue = dev_get_priv(dev);
struct musb_host_data *host = &glue->mdata;
-   struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct musb_hdrc_platform_data pdata;
void *base = dev_read_addr_ptr(dev);
int ret;
 
+#ifdef CONFIG_USB_MUSB_HOST
+   struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+#endif
+
if (!base)
return -EINVAL;
 
@@ -459,7 +462,6 @@ static int musb_usb_probe(struct udevice *dev)
return ret;
}
 
-   priv->desc_before_addr = true;
 
memset(&pdata, 0, sizeof(pdata));
pdata.power = 250;
@@ -467,6 +469,8 @@ static int musb_usb_probe(struct udevice *dev)
pdata.config = glue->cfg->config;
 
 #ifdef CONFIG_USB_MUSB_HOST
+   priv->desc_before_addr = true;
+
pdata.mode = MUSB_HOST;
host->host = musb_init_controller(&pdata, &glue->dev, base);
if (!host->host)
-- 
2.17.1

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[U-Boot] [PATCH 1/1] arm: sunxi: Add NULL pointer check

2018-12-05 Thread Stefan Mavrodiev

Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev 
---
 drivers/spi/sun4i_spi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct 
sun4i_spi_priv *priv, int len)
 
while (len--) {
byte = readb(&priv->regs->rxdata);
-   *priv->rx_buf++ = byte;
+   if (priv->rx_buf)
+   *priv->rx_buf++ = byte;
}
 }
 
-- 
2.17.1

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[U-Boot] [PATCH 1/1] sunxi: mmc: Fix phase delays

2018-03-27 Thread Stefan Mavrodiev

U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where
PLL5 is used, with clock rates respectively 600MHz and 768MHz.
Thus there are different phase degree steps - 24 for the kernel and
30 for u-boot.

In the kernel driver the phase is set 90 deg for output and 120 for
sample. Dividing by 30 will result values 3 and 4. Those are the
values set in the u-boot driver.

However, the condition defining delays is wrong. MMC core driver
requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but
phase is set 30 deg for output and 120 deg for sample.

Apparently this works for most cards.
On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains
about it. Maybe there is other boards with similar problem?
So the fix is to match delays for both u-boot and kernel.

Signed-off-by: Stefan Mavrodiev 
---
 drivers/mmc/sunxi_mmc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4edb4be..be55dc4 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -146,19 +146,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, 
unsigned int hz)
oclk_dly = 0;
sclk_dly = 5;
 #ifdef CONFIG_MACH_SUN9I
-   } else if (hz <= 5000) {
+   } else if (hz <= 5200) {
oclk_dly = 5;
sclk_dly = 4;
} else {
-   /* hz > 5000 */
+   /* hz > 5200 */
oclk_dly = 2;
sclk_dly = 4;
 #else
-   } else if (hz <= 5000) {
+   } else if (hz <= 5200) {
oclk_dly = 3;
sclk_dly = 4;
} else {
-   /* hz > 5000 */
+   /* hz > 5200 */
oclk_dly = 1;
sclk_dly = 4;
 #endif
-- 
2.7.4

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[U-Boot] [PATCH 1/1] i2c: mvtwsi.c: Fix set speed

2018-02-12 Thread Stefan Mavrodiev

Previous patch for this driver breaks i2c initialization.

commit 8bcf12ccce89 ("i2c: mvtwsi.c: Avoid NULL dereference")

If actual_speed is passed as NULL in this function:
static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
int slaveadd, uint *actual_speed)
than __twsi_i2c_set_bus_speed never get called. This causes i2c clock
to run on default speed - 2MHz (measured with oscilloscope). This is issue
on some boards, sunxi for example, since on I2C0 bus PMU is connected.

The bootlogs with and without the patch are as follows:

Wihtout the patch:
U-Boot SPL 2018.03-rc2 (Feb 13 2018 - 09:23:17 +0200)
DRAM: 1024 MiB
Failed to set core voltage! Can't set CPU frequency
Trying to boot from FEL

U-Boot 2018.03-rc2 (Feb 13 2018 - 09:23:17 +0200) Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
Model: Olimex A20-OLinuXino-LIME2
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0

With the patch:
U-Boot SPL 2018.03-rc2-1-g838ff85 (Feb 13 2018 - 09:24:34 +0200)
DRAM: 1024 MiB
CPU: 91200Hz, AXI/AHB/APB: 3/2/2
Trying to boot from FEL

U-Boot 2018.03-rc2-1-g838ff85 (Feb 13 2018 - 09:24:34 +0200) Allwinner 
Technology

CPU:   Allwinner A20 (SUN7I)
Model: Olimex A20-OLinuXino-LIME2
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0

Signed-off-by: Stefan Mavrodiev 
---
 drivers/i2c/mvtwsi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 30bee0d..38bca89 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -487,11 +487,14 @@ static uint __twsi_i2c_set_bus_speed(struct 
mvtwsi_registers *twsi,
 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
int slaveadd, uint *actual_speed)
 {
+   uint tmp_speed;
+
/* Reset controller */
twsi_reset(twsi);
/* Set speed */
+   tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed);
if (actual_speed)
-   *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed);
+   *actual_speed = tmp_speed;
/* Set slave address; even though we don't use it */
writel(slaveadd, &twsi->slave_address);
writel(0, &twsi->xtnd_slave_addr);
-- 
2.7.4

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Re: [U-Boot] [PATCH v4 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-08 Thread Stefan Mavrodiev


On 02/08/2018 09:03 AM, Jagan Teki wrote:

On Thu, Feb 8, 2018 at 11:54 AM, Stefan Mavrodiev
 wrote:

On 02/07/2018 07:19 PM, Maxime Ripard wrote:

On Wed, Feb 07, 2018 at 12:55:54PM +0530, Jagan Teki wrote:

+&spi0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&spi0_pins_b>, <&spi0_cs0_pins_b>;
+   status = "okay";
+
+   flash: w25q128@0 {

Was it sync from Linux?

No, this isn't in the linux dts.

But we have to, please send it to Linux first.

We've already commented this issue. In the v2 [1], I've explained that
this
won't go mainline, since it's optional feature. Rather it will be
managed
with overlays.

Thought this was already in ML, and ready to merge. So this never go
to Linux tree since it's optional? then add u-boot.dtsi for this
atleast since we always sync dts from Linux.

This is an optional feature on that board. We should be making it as
easy as possible to enable it, but a defconfig is a *default*
configuration, and if the board doesn't have it by default, it
shouldn't be enabled in the defconfig.

Maxime


Sorry, but I'm really confused. In the first patch Jagan said to make
separate patch
"just to test" the driver. Then I've made patch "just to test", and it's
turn out it wasn't not OK,
because it should be compatible with linux, u-boot and etc. What's the point
since it's just for testing...?

Sorry again, but can someone explain to me, that to do?
I'm not trying to pick on you guys. Just want to do the right thing.

I think we're in out-of-sync for some reason.

Here is my suggestion:
Since it is "optional feature however similar boards of this type
could not have it"?

How about separate defconfig file?
A20-OLinuXino-Lime2-spinor_defconfig and have same dts file with

/* Disable SPI NOR by default: it optional on A20-OLinuXino-Lime2 boards */
status = "disabled";

But the dts should accept by Linux as well.


Already tried this [1] and got rejected.

[1] https://patchwork.kernel.org/patch/10076721/

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Re: [U-Boot] [PATCH v4 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-08 Thread Stefan Mavrodiev


On 02/07/2018 07:19 PM, Maxime Ripard wrote:

On Wed, Feb 07, 2018 at 12:55:54PM +0530, Jagan Teki wrote:

+&spi0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&spi0_pins_b>, <&spi0_cs0_pins_b>;
+   status = "okay";
+
+   flash: w25q128@0 {

Was it sync from Linux?

No, this isn't in the linux dts.

But we have to, please send it to Linux first.

We've already commented this issue. In the v2 [1], I've explained that this
won't go mainline, since it's optional feature. Rather it will be managed
with overlays.

Thought this was already in ML, and ready to merge. So this never go
to Linux tree since it's optional? then add u-boot.dtsi for this
atleast since we always sync dts from Linux.

This is an optional feature on that board. We should be making it as
easy as possible to enable it, but a defconfig is a *default*
configuration, and if the board doesn't have it by default, it
shouldn't be enabled in the defconfig.

Maxime

Sorry, but I'm really confused. In the first patch Jagan said to make 
separate patch
"just to test" the driver. Then I've made patch "just to test", and it's 
turn out it wasn't not OK,
because it should be compatible with linux, u-boot and etc. What's the 
point since it's just for testing...?


Sorry again, but can someone explain to me, that to do?
I'm not trying to pick on you guys. Just want to do the right thing.

Best regards,
Stefan Mavrodiev

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Re: [U-Boot] [PATCH v4 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-07 Thread Stefan Mavrodiev


On 02/07/2018 09:25 AM, Jagan Teki wrote:

On Wed, Feb 7, 2018 at 12:35 PM, Stefan Mavrodiev
 wrote:

On 02/07/2018 08:39 AM, Jagan Teki wrote:

On Wed, Feb 7, 2018 at 12:00 PM, Stefan Mavrodiev
 wrote:

On 02/06/2018 06:48 PM, Jagan Teki wrote:

On Tue, Feb 6, 2018 at 6:44 PM, Stefan Mavrodiev 
wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
 - Exposing spi0 alternative pins in the dts file
 - Add alias node, enabling driver probing
 - Add flash sub-node of spi
 - Enable spi flash related options in the defconfig file

The testing log is:

 U-Boot SPL 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07
+0200)
 DRAM: 1024 MiB
 CPU: 91200Hz, AXI/AHB/APB: 3/2/2
 Trying to boot from FEL

Why FEL? can't it boot from SPI-FLASH?

Because I previously erased the flash during testing. Here is same,
booting
from SPI:

U-Boot SPL 2018.03-rc1-00075-g61ce225 (Feb 07 2018 - 08:21:07 +0200)
DRAM: 1024 MiB
CPU: 91200Hz, AXI/AHB/APB: 3/2/2
Trying to boot from sunxi SPI


U-Boot 2018.03-rc1-00075-g61ce225 (Feb 07 2018 - 08:21:07 +0200)
Allwinner
Technology


CPU:   Allwinner A20 (SUN7I)
Model: Olimex A20-OLinuXino-LIME2
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
Loading Environment from SPI Flash... SF: Detected w25q128bv with page
size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
In:serial
Out:   serial
Err:   serial
Allwinner mUSB OTG (Peripheral)
SCSI:  SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   No ethernet found.
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
USB2:   USB EHCI 1.00
USB3:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
   scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot:



 U-Boot 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07
+0200)
Allwinner Technology

 CPU:   Allwinner A20 (SUN7I)
 Model: Olimex A20-OLinuXino-LIME2
 I2C:   ready
 DRAM:  1 GiB
 MMC:   SUNXI SD/MMC: 0
 Loading Environment from SPI Flash... SF: Detected w25q128bv with
page
size 256 Bytes, erase size 4 KiB, total 16 MiB
 OK
 In:serial
 Out:   serial
 Err:   serial
 Allwinner mUSB OTG (Peripheral)
 SCSI:  SATA link 0 timeout.
 AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
 flags: ncq stag pm led clo only pmp pio slum part ccc apst
 Net:   No ethernet found.
 starting USB...
 USB0:   USB EHCI 1.00
 USB1:   USB OHCI 1.0
 USB2:   USB EHCI 1.00
 USB3:   USB OHCI 1.0
 scanning bus 0 for devices... 1 USB Device(s) found
 scanning bus 2 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s)
found
 Hit any key to stop autoboot:  0

 # Probe device
 => sf probe
 SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB,
total 16 MiB

How did this resolved w/o sspi?

I enabled both CONFIG_SPI_FLASH and CONFIG_DM_SPI_FLASH. The driver-model
search for
"spi-flash" compatible string, probe it and bind it to the spi driver.



 # Erase
 => sf erase 0x1000 0x100
 SF: 256 bytes @ 0x1000 Erased: ERROR
 => sf erase 0x1000 0x1000
 SF: 4096 bytes @ 0x1000 Erased: OK

 # Test
 => sf test 0 10
 SPI flash test:
 0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
 1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
 2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
 3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
 Test passed
 0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
 1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
 2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
 3 read: 8872 ticks, 115 KiB/s 0.920 Mbps

 # Try write/read
 => sf erase 0x1000 0x1000
 SF: 4096 bytes @ 0x1000 Erased: OK

 => md.b 0x5000 0x100
 5000: a9 4d b7 68 d2 48 69 c3 09 78 fa d3 33 66 e9 53
.M.h.Hi..x..3f.S
 5010: b0 53 af 79 ad 33 79 b1 f1 e3 1d 09 2e ba dd dc
.S.y.3y.
 5020: 8c eb eb 53 f4 ef 66 89 b5 e9 f6 fb af 73 7f cb
...S..f..s..
 5030: b6 4b bf de c3 fd de bb 9a 53 ad 7d ef 38 6f bf
.K...S.}.8o.
 5040: fd fb e7 5e e9 db fc 0c fc f7 be 76 ad b9 fd eb
...^...v
 5050: f3 ed 5f b5 bb bd ba 8f ff df 1f bf f3 ff fb d7
.._.
 5060: b7 6e 9e 5f af 7a 62 ed 7f 66 1b 6d fd fb 47 f7
.n._.zb..f.m..G.
 5070: b7 fa f4 db d5 b6 d5 ff 81 e6 f5 d9 8f ef ff db

 5080: b7 dd bd fb f3 1d 9d 2f f6 db c8 7f fb cf b9 f3
.../
 5090: 3c ee da 2f b7 5e 6f bc f1 2f 2b cf 3f f2 fb ee
<../.^o../+.?...
 50a0: 6f 5e 99 c3 3b 51 bd d4 be 40 4e db ab ed f9 77
o^..;Q.

Re: [U-Boot] [PATCH v4 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-07 Thread Stefan Mavrodiev


On 02/07/2018 08:39 AM, Jagan Teki wrote:

On Wed, Feb 7, 2018 at 12:00 PM, Stefan Mavrodiev
 wrote:

On 02/06/2018 06:48 PM, Jagan Teki wrote:

On Tue, Feb 6, 2018 at 6:44 PM, Stefan Mavrodiev 
wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
- Exposing spi0 alternative pins in the dts file
- Add alias node, enabling driver probing
- Add flash sub-node of spi
- Enable spi flash related options in the defconfig file

The testing log is:

U-Boot SPL 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07
+0200)
DRAM: 1024 MiB
CPU: 91200Hz, AXI/AHB/APB: 3/2/2
Trying to boot from FEL

Why FEL? can't it boot from SPI-FLASH?

Because I previously erased the flash during testing. Here is same, booting
from SPI:

   U-Boot SPL 2018.03-rc1-00075-g61ce225 (Feb 07 2018 - 08:21:07 +0200)
   DRAM: 1024 MiB
   CPU: 91200Hz, AXI/AHB/APB: 3/2/2
   Trying to boot from sunxi SPI


   U-Boot 2018.03-rc1-00075-g61ce225 (Feb 07 2018 - 08:21:07 +0200) Allwinner
Technology


   CPU:   Allwinner A20 (SUN7I)
   Model: Olimex A20-OLinuXino-LIME2
   I2C:   ready
   DRAM:  1 GiB
   MMC:   SUNXI SD/MMC: 0
   Loading Environment from SPI Flash... SF: Detected w25q128bv with page
size 256 Bytes, erase size 4 KiB, total 16 MiB
   OK
   In:serial
   Out:   serial
   Err:   serial
   Allwinner mUSB OTG (Peripheral)
   SCSI:  SATA link 0 timeout.
   AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
   flags: ncq stag pm led clo only pmp pio slum part ccc apst
   Net:   No ethernet found.
   starting USB...
   USB0:   USB EHCI 1.00
   USB1:   USB OHCI 1.0
   USB2:   USB EHCI 1.00
   USB3:   USB OHCI 1.0
   scanning bus 0 for devices... 1 USB Device(s) found
   scanning bus 2 for devices... 1 USB Device(s) found
  scanning usb for storage devices... 0 Storage Device(s) found
   Hit any key to stop autoboot:



U-Boot 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07 +0200)
Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
Model: Olimex A20-OLinuXino-LIME2
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
Loading Environment from SPI Flash... SF: Detected w25q128bv with page
size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
In:serial
Out:   serial
Err:   serial
Allwinner mUSB OTG (Peripheral)
SCSI:  SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   No ethernet found.
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
USB2:   USB EHCI 1.00
USB3:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
   scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot:  0

# Probe device
=> sf probe
SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB,
total 16 MiB

How did this resolved w/o sspi?

I enabled both CONFIG_SPI_FLASH and CONFIG_DM_SPI_FLASH. The driver-model
search for
"spi-flash" compatible string, probe it and bind it to the spi driver.



# Erase
=> sf erase 0x1000 0x100
SF: 256 bytes @ 0x1000 Erased: ERROR
=> sf erase 0x1000 0x1000
SF: 4096 bytes @ 0x1000 Erased: OK

# Test
=> sf test 0 10
SPI flash test:
0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
Test passed
0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
3 read: 8872 ticks, 115 KiB/s 0.920 Mbps

# Try write/read
=> sf erase 0x1000 0x1000
SF: 4096 bytes @ 0x1000 Erased: OK

=> md.b 0x5000 0x100
5000: a9 4d b7 68 d2 48 69 c3 09 78 fa d3 33 66 e9 53
.M.h.Hi..x..3f.S
5010: b0 53 af 79 ad 33 79 b1 f1 e3 1d 09 2e ba dd dc
.S.y.3y.
5020: 8c eb eb 53 f4 ef 66 89 b5 e9 f6 fb af 73 7f cb
...S..f..s..
5030: b6 4b bf de c3 fd de bb 9a 53 ad 7d ef 38 6f bf
.K...S.}.8o.
5040: fd fb e7 5e e9 db fc 0c fc f7 be 76 ad b9 fd eb
...^...v
5050: f3 ed 5f b5 bb bd ba 8f ff df 1f bf f3 ff fb d7
.._.
5060: b7 6e 9e 5f af 7a 62 ed 7f 66 1b 6d fd fb 47 f7
.n._.zb..f.m..G.
5070: b7 fa f4 db d5 b6 d5 ff 81 e6 f5 d9 8f ef ff db

5080: b7 dd bd fb f3 1d 9d 2f f6 db c8 7f fb cf b9 f3
.../
5090: 3c ee da 2f b7 5e 6f bc f1 2f 2b cf 3f f2 fb ee
<../.^o../+.?...
50a0: 6f 5e 99 c3 3b 51 bd d4 be 40 4e db ab ed f9 77
o^..;Q...@Nw
50b0: 9f f6 7d ed 54 4a 68 f8 7d ee 53 9b ff ae ef e4
..}.TJh.}.S.
50c0: 73 ff 3c c7 f7 df f6 be bf 0f 97 96 3d 9b 9e 9f
s.<.=...
50d0: e4 49 ca ff

Re: [U-Boot] [PATCH v4 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-07 Thread Stefan Mavrodiev


On 02/06/2018 06:48 PM, Jagan Teki wrote:

On Tue, Feb 6, 2018 at 6:44 PM, Stefan Mavrodiev  wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
   - Exposing spi0 alternative pins in the dts file
   - Add alias node, enabling driver probing
   - Add flash sub-node of spi
   - Enable spi flash related options in the defconfig file

The testing log is:

   U-Boot SPL 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07 +0200)
   DRAM: 1024 MiB
   CPU: 91200Hz, AXI/AHB/APB: 3/2/2
   Trying to boot from FEL

Why FEL? can't it boot from SPI-FLASH?
Because I previously erased the flash during testing. Here is same, 
booting from SPI:


  U-Boot SPL 2018.03-rc1-00075-g61ce225 (Feb 07 2018 - 08:21:07 +0200)
  DRAM: 1024 MiB
  CPU: 91200Hz, AXI/AHB/APB: 3/2/2
  Trying to boot from sunxi SPI


  U-Boot 2018.03-rc1-00075-g61ce225 (Feb 07 2018 - 08:21:07 +0200) 
Allwinner Technology


  CPU:   Allwinner A20 (SUN7I)
  Model: Olimex A20-OLinuXino-LIME2
  I2C:   ready
  DRAM:  1 GiB
  MMC:   SUNXI SD/MMC: 0
  Loading Environment from SPI Flash... SF: Detected w25q128bv with 
page size 256 Bytes, erase size 4 KiB, total 16 MiB

  OK
  In:    serial
  Out:   serial
  Err:   serial
  Allwinner mUSB OTG (Peripheral)
  SCSI:  SATA link 0 timeout.
  AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
  flags: ncq stag pm led clo only pmp pio slum part ccc apst
  Net:   No ethernet found.
  starting USB...
  USB0:   USB EHCI 1.00
  USB1:   USB OHCI 1.0
  USB2:   USB EHCI 1.00
  USB3:   USB OHCI 1.0
  scanning bus 0 for devices... 1 USB Device(s) found
  scanning bus 2 for devices... 1 USB Device(s) found
         scanning usb for storage devices... 0 Storage Device(s) found
  Hit any key to stop autoboot:



   U-Boot 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07 +0200) 
Allwinner Technology

   CPU:   Allwinner A20 (SUN7I)
   Model: Olimex A20-OLinuXino-LIME2
   I2C:   ready
   DRAM:  1 GiB
   MMC:   SUNXI SD/MMC: 0
   Loading Environment from SPI Flash... SF: Detected w25q128bv with page size 
256 Bytes, erase size 4 KiB, total 16 MiB
   OK
   In:serial
   Out:   serial
   Err:   serial
   Allwinner mUSB OTG (Peripheral)
   SCSI:  SATA link 0 timeout.
   AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
   flags: ncq stag pm led clo only pmp pio slum part ccc apst
   Net:   No ethernet found.
   starting USB...
   USB0:   USB EHCI 1.00
   USB1:   USB OHCI 1.0
   USB2:   USB EHCI 1.00
   USB3:   USB OHCI 1.0
   scanning bus 0 for devices... 1 USB Device(s) found
   scanning bus 2 for devices... 1 USB Device(s) found
  scanning usb for storage devices... 0 Storage Device(s) found
   Hit any key to stop autoboot:  0

   # Probe device
   => sf probe
   SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 
MiB

How did this resolved w/o sspi?
I enabled both CONFIG_SPI_FLASH and CONFIG_DM_SPI_FLASH. The 
driver-model search for

"spi-flash" compatible string, probe it and bind it to the spi driver.



   # Erase
   => sf erase 0x1000 0x100
   SF: 256 bytes @ 0x1000 Erased: ERROR
   => sf erase 0x1000 0x1000
   SF: 4096 bytes @ 0x1000 Erased: OK

   # Test
   => sf test 0 10
   SPI flash test:
   0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
   1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
   2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
   3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
   Test passed
   0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
   1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
   2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
   3 read: 8872 ticks, 115 KiB/s 0.920 Mbps

   # Try write/read
   => sf erase 0x1000 0x1000
   SF: 4096 bytes @ 0x1000 Erased: OK

   => md.b 0x5000 0x100
   5000: a9 4d b7 68 d2 48 69 c3 09 78 fa d3 33 66 e9 53.M.h.Hi..x..3f.S
   5010: b0 53 af 79 ad 33 79 b1 f1 e3 1d 09 2e ba dd dc.S.y.3y.
   5020: 8c eb eb 53 f4 ef 66 89 b5 e9 f6 fb af 73 7f cb...S..f..s..
   5030: b6 4b bf de c3 fd de bb 9a 53 ad 7d ef 38 6f bf.K...S.}.8o.
   5040: fd fb e7 5e e9 db fc 0c fc f7 be 76 ad b9 fd eb...^...v
   5050: f3 ed 5f b5 bb bd ba 8f ff df 1f bf f3 ff fb d7.._.
   5060: b7 6e 9e 5f af 7a 62 ed 7f 66 1b 6d fd fb 47 f7.n._.zb..f.m..G.
   5070: b7 fa f4 db d5 b6 d5 ff 81 e6 f5 d9 8f ef ff db
   5080: b7 dd bd fb f3 1d 9d 2f f6 db c8 7f fb cf b9 f3.../
   5090: 3c ee da 2f b7 5e 6f bc f1 2f 2b cf 3f f2 fb ee<../.^o../+.?...
   50a0: 6f 5e 99 c3 3b 51 bd d4 be 40 4e db ab ed f9 77o^..;Q...@Nw
   50b0: 9f f6 7d ed 54 4a 68 f8 7d ee 53 9b ff ae ef e4..}.TJh.}.S.
   50c0: 73 ff 3c c7 f7 df f6 be bf 0f 97 96 3d 9b 9e 9fs.<.=...
   50d0: e4 49 ca ff be fa ff df f7 7a cf ab 7f 7a 7b cf.I...z...z{.
   50e0: bb c7 9f 3f c1 99 f2 f2 bf ee cf fb d5 b9 e2 e8...?
   50f0: ec e8

[U-Boot] [PATCH v4 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-06 Thread Stefan Mavrodiev

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
  - Exposing spi0 alternative pins in the dts file
  - Add alias node, enabling driver probing
  - Add flash sub-node of spi
  - Enable spi flash related options in the defconfig file

The testing log is:

  U-Boot SPL 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07 +0200)
  DRAM: 1024 MiB
  CPU: 91200Hz, AXI/AHB/APB: 3/2/2
  Trying to boot from FEL

  U-Boot 2018.03-rc1-00075-g35a689a-dirty (Feb 06 2018 - 14:40:07 +0200) 
Allwinner Technology

  CPU:   Allwinner A20 (SUN7I)
  Model: Olimex A20-OLinuXino-LIME2
  I2C:   ready
  DRAM:  1 GiB
  MMC:   SUNXI SD/MMC: 0
  Loading Environment from SPI Flash... SF: Detected w25q128bv with page size 
256 Bytes, erase size 4 KiB, total 16 MiB
  OK
  In:serial
  Out:   serial
  Err:   serial
  Allwinner mUSB OTG (Peripheral)
  SCSI:  SATA link 0 timeout.
  AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
  flags: ncq stag pm led clo only pmp pio slum part ccc apst
  Net:   No ethernet found.
  starting USB...
  USB0:   USB EHCI 1.00
  USB1:   USB OHCI 1.0
  USB2:   USB EHCI 1.00
  USB3:   USB OHCI 1.0
  scanning bus 0 for devices... 1 USB Device(s) found
  scanning bus 2 for devices... 1 USB Device(s) found
 scanning usb for storage devices... 0 Storage Device(s) found
  Hit any key to stop autoboot:  0

  # Probe device
  => sf probe
  SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 
MiB

  # Erase
  => sf erase 0x1000 0x100
  SF: 256 bytes @ 0x1000 Erased: ERROR
  => sf erase 0x1000 0x1000
  SF: 4096 bytes @ 0x1000 Erased: OK

  # Test
  => sf test 0 10
  SPI flash test:
  0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
  1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
  2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
  3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
  Test passed
  0 erase: 12104 ticks, 84 KiB/s 0.672 Mbps
  1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
  2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
  3 read: 8872 ticks, 115 KiB/s 0.920 Mbps

  # Try write/read
  => sf erase 0x1000 0x1000
  SF: 4096 bytes @ 0x1000 Erased: OK

  => md.b 0x5000 0x100
  5000: a9 4d b7 68 d2 48 69 c3 09 78 fa d3 33 66 e9 53.M.h.Hi..x..3f.S
  5010: b0 53 af 79 ad 33 79 b1 f1 e3 1d 09 2e ba dd dc.S.y.3y.
  5020: 8c eb eb 53 f4 ef 66 89 b5 e9 f6 fb af 73 7f cb...S..f..s..
  5030: b6 4b bf de c3 fd de bb 9a 53 ad 7d ef 38 6f bf.K...S.}.8o.
  5040: fd fb e7 5e e9 db fc 0c fc f7 be 76 ad b9 fd eb...^...v
  5050: f3 ed 5f b5 bb bd ba 8f ff df 1f bf f3 ff fb d7.._.
  5060: b7 6e 9e 5f af 7a 62 ed 7f 66 1b 6d fd fb 47 f7.n._.zb..f.m..G.
  5070: b7 fa f4 db d5 b6 d5 ff 81 e6 f5 d9 8f ef ff db
  5080: b7 dd bd fb f3 1d 9d 2f f6 db c8 7f fb cf b9 f3.../
  5090: 3c ee da 2f b7 5e 6f bc f1 2f 2b cf 3f f2 fb ee<../.^o../+.?...
  50a0: 6f 5e 99 c3 3b 51 bd d4 be 40 4e db ab ed f9 77o^..;Q...@Nw
  50b0: 9f f6 7d ed 54 4a 68 f8 7d ee 53 9b ff ae ef e4..}.TJh.}.S.
  50c0: 73 ff 3c c7 f7 df f6 be bf 0f 97 96 3d 9b 9e 9fs.<.=...
  50d0: e4 49 ca ff be fa ff df f7 7a cf ab 7f 7a 7b cf.I...z...z{.
  50e0: bb c7 9f 3f c1 99 f2 f2 bf ee cf fb d5 b9 e2 e8...?
  50f0: ec e8 b2 bd 21 1f 5a ef 7a 7d 9d ad 31 89 3f 6f!.Z.z}..1.?o

  => sf write 0x5000 0x1000 0x100
  device 0 offset 0x1000, size 0x100
  SF: 256 bytes @ 0x1000 Written: OK
  => sf read 0x5100 0x1000 0x100
  device 0 offset 0x1000, size 0x100
  SF: 256 bytes @ 0x1000 Read: OK

  => cmp.b 0x5000 0x5100 0x100
  Total of 256 byte(s) were the same

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 30 ++
 configs/A20-OLinuXino-Lime2_defconfig  | 11 +++
 drivers/mtd/spi/Makefile   |  4 +++-
 include/configs/sunxi-common.h |  2 ++
 4 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index d5c796c..a6ee87c 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -54,6 +54,7 @@
 
aliases {
serial0 = &uart0;
+   spi0 = &spi0;
};
 
chosen {
@@ -215,6 +216,20 @@
allwinner,pull = ;
};
 
+   spi0_pins_b: spi0@1 {
+   allwinner,pins = "PC0", "PC1", "PC2";
+   allwinner,function = "spi0";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
+   spi0_cs0_pins_b: spi0_cs0@1 {
+   allwinner,pins = "PC23";
+   allwinner,function = "spi0";
+   allwinner,drive = ;
+   allwinn

[U-Boot] [PATCH v4 1/2] arm: sunxi: Allwinner A10 SPI driver

2018-02-06 Thread Stefan Mavrodiev

Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.

Signed-off-by: Stefan Mavrodiev 
---
 Changes for v4:
- Sync patch with u-boot-sunxi (80719938c9f901cc6b90b85d8065d084a03c06ae)
- Change wait_for_bits() to wait_for_bits_le32()
- Change CCTL register modification
- Some coding style changes
- Add flash subnode in the DT
- Disable spl build of sf_probe
- Enable CONFIG_DM_SPI_FLASH
- Set enviroment in spi flash

 Changes for v3:
- Add required changes in dts and defeconfig file for testing

 Changes for v2:
- Updated copyright including original owners
- Remove write/read register function. They are replaced with direct opts
- Some coding style changes

 drivers/spi/Kconfig |   5 +
 drivers/spi/Makefile|   1 +
 drivers/spi/sun4i_spi.c | 456 
 3 files changed, 462 insertions(+)
 create mode 100644 drivers/spi/sun4i_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1e95dc4..bb9f800 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -148,6 +148,11 @@ config STM32_QSPI
  used to access the SPI NOR flash chips on platforms embedding
  this ST IP core.
 
+config SUN4I_SPI
+   bool "Allwinner A10 SoCs SPI controller"
+   help
+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
+
 config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4b6000f..794e70c 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
new file mode 100644
index 000..b86b5a0
--- /dev/null
+++ b/drivers/spi/sun4i_spi.c
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik 
+ * M.B.W. Wajer 
+ *
+ * (C) Copyright 2017 Olimex Ltd..
+ * Stefan Mavrodiev 
+ *
+ * Based on linux spi driver. Original copyright follows:
+ * linux/drivers/spi/spi-sun4i.c
+ *
+ * Copyright (C) 2012 - 2014 Allwinner Tech
+ * Pan Nan 
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#define SUN4I_FIFO_DEPTH   64
+
+#define SUN4I_RXDATA_REG   0x00
+
+#define SUN4I_TXDATA_REG   0x04
+
+#define SUN4I_CTL_REG  0x08
+#define SUN4I_CTL_ENABLE   BIT(0)
+#define SUN4I_CTL_MASTER   BIT(1)
+#define SUN4I_CTL_CPHA BIT(2)
+#define SUN4I_CTL_CPOL BIT(3)
+#define SUN4I_CTL_CS_ACTIVE_LOWBIT(4)
+#define SUN4I_CTL_LMTF BIT(6)
+#define SUN4I_CTL_TF_RST   BIT(8)
+#define SUN4I_CTL_RF_RST   BIT(9)
+#define SUN4I_CTL_XCH_MASK 0x0400
+#define SUN4I_CTL_XCH  BIT(10)
+#define SUN4I_CTL_CS_MASK  0x3000
+#define SUN4I_CTL_CS(cs)   (((cs) << 12) & SUN4I_CTL_CS_MASK)
+#define SUN4I_CTL_DHB  BIT(15)
+#define SUN4I_CTL_CS_MANUALBIT(16)
+#define SUN4I_CTL_CS_LEVEL BIT(17)
+#define SUN4I_CTL_TP   BIT(18)
+
+#define SUN4I_INT_CTL_REG  0x0c
+#define SUN4I_INT_CTL_RF_F34   BIT(4)
+#define SUN4I_INT_CTL_TF_E34   BIT(12)
+#define SUN4I_INT_CTL_TC   BIT(16)
+
+#define SUN4I_INT_STA_REG  0x10
+
+#define SUN4I_DMA_CTL_REG  0x14
+
+#define SUN4I_WAIT_REG 0x18
+
+#define SUN4I_CLK_CTL_REG  0x1c
+#define SUN4I_CLK_CTL_CDR2_MASK0xff
+#define SUN4I_CLK_CTL_CDR2(div)((div) & 
SUN4I_CLK_CTL_CDR2_MASK)
+#define SUN4I_CLK_CTL_CDR1_MASK0xf
+#define SUN4I_CLK_CTL_CDR1(div)(((div) & 
SUN4I_CLK_CTL_CDR1_MASK) << 8)
+#define SUN4I_CLK_CTL_DRS  BIT(12)
+
+#define SUN4I_MAX_XFER_SIZE0xff
+
+#define SUN4I_BURST_CNT_REG0x20
+#define SUN4I_BURST_CNT(cnt)   ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_XMIT_CNT_REG 0x24
+#define SUN4I_XMIT_CNT(cnt)((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_FIFO_STA_REG 0x28
+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_TF_CNT_BITS 16
+
+#define SUN4I_SPI_MAX_RATE 2400
+#define SUN4I_SPI_MIN_RATE 3000
+#define SUN4I_SPI_DEFAULT_RATE 100
+#define SUN4I_SPI_TIMEOUT_

Re: [U-Boot] [PATCH v3 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-06 Thread Stefan Mavrodiev


On 02/01/2018 04:45 PM, Jagan Teki wrote:

On Thu, Feb 1, 2018 at 8:08 PM, Stefan Mavrodiev
 wrote:

On 01/30/2018 09:15 AM, Stefan Mavrodiev wrote:

On 01/22/2018 10:36 AM, Jagan Teki wrote:

On Tue, Jan 2, 2018 at 4:31 PM, Stefan Mavrodiev
 wrote:

On 12/26/2017 11:47 AM, Jagan Teki wrote:

On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev 
wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
 - Exposing spi0 alternative pins in the dts file
 - Add alias node, enabling driver probing
 - Enable spi flash related options in the defconfig file

The testing log is:
 U-Boot SPL 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 -
11:39:48)
 DRAM: 1024 MiB
 CPU: 91200Hz, AXI/AHB/APB: 3/2/2
 Trying to boot from sunxi SPI


 U-Boot 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48
+0200)
Allwinner Technology

 CPU:   Allwinner A20 (SUN7I)
 Model: Olimex A20-OLinuXino-LIME2

Lime2 doen't have in-built spi-nor is it?

We have some prototypes with this option.

I've Rev.6 does it have spi-nor?

I assume Rev.6 is actually Rev.F. The first prototype with SPI flash is
Rev.I (Rev.9).



 I2C:   ready
 DRAM:  1 GiB
 MMC:   SUNXI SD/MMC: 0
 MMC: no card present
 mmc_init: -123, time 1
 *** Warning - MMC init failed, using default environment

you lost the env? since it's spi-nor better to use flash env.

What's the point since this is only test case?

this can be an issue if we boot the system from spi-nor, where we can
get saved env.


 In:serial
 Out:   serial
 Err:   serial
 Allwinner mUSB OTG (Peripheral)
 SCSI:  SATA link 0 timeout.
 AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
 flags: ncq stag pm led clo only pmp pio slum part ccc apst
 Net:   No ethernet found.
 starting USB...
 USB0:   USB EHCI 1.00
 USB1:   USB OHCI 1.0
 USB2:   USB EHCI 1.00
 USB3:   USB OHCI 1.0
 scanning bus 0 for devices... 1 USB Device(s) found
 scanning bus 2 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s)
found
 Hit any key to stop autoboot:  0
 => sspi

 => sf probe
 SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB,
total 16 MiB

try to use erase/write and read commands to verify

# Erase one sector
=> sf erase 0x1000 0x100
SF: 256 bytes @ 0x1000 Erased: ERROR
=> sf erase 0x1000 0x1000
SF: 4096 bytes @ 0x1000 Erased: OK

# Get some random data
=> md.b 0x5000 0x100
5000: d6 4d d0 7e 93 d8 0f 48 1b ef 7f 7e be 4e a8 5d
.M.~...H...~.N.]
5010: fd 9f e5 7f 2f 7b 5b 19 ed de d8 58 99 7a 24 da
/{[X.z$.
5020: ef dd 9c 45 d7 97 ab 4f e7 fb ee 61 bc de 6a 1a
...E...O...a..j.
5030: 9a 9f f4 3a be 4b 2f f3 ce 77 87 7e 07 23 af ff
...:.K/..w.~.#..
5040: e5 e5 c0 fa 65 e2 78 9b 16 38 42 52 e5 6c 52 0d
e.x..8BR.lR.
5050: f5 ff da 94 7f 98 96 d7 f0 9d 66 ae 9b b9 a2 cd
..f.
5060: 0b dd f1 c9 1d 3b fe 5b cf ef d6 ce 8b c5 fd 56
.;.[...V
5070: e2 52 eb 78 d4 f1 bf 57 56 6a 57 58 52 f1 0e 9d
.R.x...WVjWXR...
5080: df be f8 19 bf cf d7 ac 4b 3e 86 21 3f c3 fe 3e
K>.!?..>
5090: ea 27 52 ca 1f 79 bd 7b ef bf 96 c9 9d f6 81 d3
.'R..y.{
50a0: cc 2e 8b c8 34 7f c5 2f 29 19 a8 dc 54 7a 07 1d
4../)...Tz..
50b0: f4 e6 db ed 38 03 59 bb 31 ee b3 dd 5c e6 be 58
8.Y.1...\..X
50c0: a6 7c 87 61 84 47 e0 b1 a1 fc 6e d3 d5 93 bf 8a
.|.a.Gn.
50d0: 5d a3 be 4b cf 07 1d 92 ff 36 f9 46 fb 5a cb 8f
]..K.6.F.Z..
50e0: f9 27 7a b8 7b 07 2e 22 a1 ee 56 bc a7 de 57 6a
.'z.{.."..V...Wj
50f0: da d4 7d 7f ee db 7a e2 bc 5c 44 64 b7 fc ea 3e
..}...z..\Dd...

# Write one page to spi-nor
=> sf write 0x5000 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Written: OK

# Readback data
=> sf read 0x5100 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Read: OK

# Compare data
=> cmp.b 0x5000 0x5100 0x100
Total of 256 byte(s) were the same


 => sf test 0 10
 SPI flash test:
 0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
 1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
 2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
 3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
 Test passed
 0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
 1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
 2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
     3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
 =>

Signed-off-by: Stefan Mavrodiev 
---
arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 21
+
configs/A20-OLinuXino-Lime2_defconfig  |  8 
2 files changed, 29 insertions(+)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index d5c796c..3c708da 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-li

[U-Boot] [PATCH v2 1/3] Move CONFIG_PHY_ADDR to Kconfig

2018-02-02 Thread Stefan Mavrodiev

CONFIG_PHY_ADDR is used for old-style configuration. This makes
impossible changing the PHY address, if multiple boards share a same
config header file (for example include/configs/sunxi-common.h).

Moving this to Kconfig helps overcoming this issue. It's defined
as entry inside PHYLIB section.

After the implemention, moveconfig was run. The issues are:
- edb9315a  - CONFIG_PHYLIB is not enabled. Entry is
  deleted.

- ds414 - CONFIG_PHYLIB is in incompatible format:
  { 0x1, 0x0 }. This entry is also deleted.

- devkit3250- The PHY_ADDR is in hex format (0x1F).
  Manually CONFIG_PHY_ADDR=31 is added in
  the defconfig.

After the changes the suspicious defconfigs passes building.

Signed-off-by: Stefan Mavrodiev 
Acked-by: Maxime Ripard 
---
 Changes for v2:
   - Replaced CONFIG_SUNXI_PHY_ADDR with a common one
 CONFIG_PHY_ADDR, using moveconfig.

 README | 4 
 configs/devkit3250_defconfig   | 1 +
 configs/khadas-vim_defconfig   | 1 +
 configs/libretech-cc_defconfig | 1 +
 configs/p212_defconfig | 1 +
 drivers/net/phy/Kconfig| 7 +++
 include/configs/am335x_shc.h   | 1 -
 include/configs/baltos.h   | 1 -
 include/configs/devkit3250.h   | 1 -
 include/configs/ds414.h| 1 -
 include/configs/edb93xx.h  | 1 -
 include/configs/khadas-vim.h   | 2 --
 include/configs/libretech-cc.h | 2 --
 include/configs/p212.h | 2 --
 include/configs/pepper.h   | 1 -
 include/configs/sunxi-common.h | 2 --
 include/configs/work_92105.h   | 1 -
 include/configs/x600.h | 1 -
 scripts/config_whitelist.txt   | 1 -
 19 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/README b/README
index b53ea7d..499184d 100644
--- a/README
+++ b/README
@@ -1436,10 +1436,6 @@ The following options need to be configured:
be at least 4MB.
 
 - MII/PHY support:
-   CONFIG_PHY_ADDR
-
-   The address of PHY on MII bus.
-
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 
The clock frequency of the MII bus
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 2ad08ae..930b631 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -36,6 +36,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_NAND=y
 CONFIG_SPL_NAND_SIMPLE=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR=31
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 4ceab90..e9a96d3 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
 CONFIG_PHY_MESON_GXL=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index 3bccff1..86852b1 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
 CONFIG_PHY_MESON_GXL=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index cb9be4a..9466238 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
 CONFIG_PHY_MESON_GXL=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 95b7534..c934aed 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -12,6 +12,13 @@ menuconfig PHYLIB
 
 if PHYLIB
 
+config PHY_ADDR
+   int "PHY address"
+   default 1 if ARCH_SUNXI
+   default 0
+   help
+ The address of PHY on MII bus. Usually in range of 0 to 31.
+
 config B53_SWITCH
bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
help
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index e2d329a..2b705fc 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -264,7 +264,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_ADDR0
 #define CONFIG_PHY_SMSC
 
 /* I2C configuration */
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 75dd0c5..31ae20c 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -285,7 +285,6 @@
 #endif
 
 /* Network. */
-#define CONFIG_PHY_ADDR0
 #define CONFIG_PHY_SMSC
 #define CONFIG_MII
 #define CONFIG_PHY_ATHEROS
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 526a81a..b66b90e 100644
--- a/include/configs/devkit3250.h
+++ b/include/conf

Re: [U-Boot] [PATCH 3/3] sunxi: Add A20-SOM204-EVB-eMMC board

2018-02-02 Thread Stefan Mavrodiev


On 02/02/2018 02:54 PM, Maxime Ripard wrote:

On Fri, Feb 02, 2018 at 11:37:03AM +0200, Stefan Mavrodiev wrote:

A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.

Signed-off-by: Stefan Mavrodiev 

Acked-by: Maxime Ripard 

Thanks!
Maxime

Should I send "Patch v2" with the changes mentioned by Jagan (Wrong 
--subject-prefix and updated MAINTAINERS) ?


Regards,
Stefan Mavrodiev

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[U-Boot] [PATCH v2 3/3] sunxi: Add A20-SOM204-EVB-eMMC board

2018-02-02 Thread Stefan Mavrodiev

A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.

Signed-off-by: Stefan Mavrodiev 
Acked-by: Maxime Ripard 
---
 Changes for v2:
- Add missing MAINTAINERS entry
- Reworked defconfig file

 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts | 36 +++
 board/sunxi/MAINTAINERS   |  1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  | 34 +
 4 files changed, 72 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
 create mode 100644 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 97e8790..f9764a4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -304,6 +304,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
sun7i-a20-olimex-som204-evb.dtb \
+   sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts 
b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
new file mode 100644
index 000..c56620a
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev 
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som204-evb.dts"
+
+/ {
+   model = "Olimex A20-SOM204-EVB-eMMC";
+   compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
+
+   mmc2_pwrseq: mmc2_pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&mmc2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc2_pins_a>;
+   vmmc-supply = <®_vcc3v3>;
+   mmc-pwrseq = <&mmc2_pwrseq>;
+   bus-width = <4>;
+   non-removable;
+   status = "okay";
+
+   emmc: emmc@0 {
+   reg = <0>;
+   compatible = "mmc-card";
+   broken-hpi;
+   };
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 2298853..5aadb98 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -315,6 +315,7 @@ OLIMEX A20-SOM204 BOARD
 M: Stefan Mavrodiev 
 S: Maintained
 F: configs/A20-Olimex-SOM204-EVB_defconfig
+F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
 
 ORANGEPI WIN/WIN PLUS BOARD
 M: Jagan Teki 
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig 
b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
new file mode 100644
index 000..11fe6bd
--- /dev/null
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_I2C1_ENABLE=y
+CONFIG_SATAPWR="PC3"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_ADDR=3
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-- 
2.7.4

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[U-Boot] [PATCH v2 2/3] sunxi: Add A20-SOM204-EVB board

2018-02-02 Thread Stefan Mavrodiev

This is new System-On-Module platform with universal dimm socket for
easy insertation. The EVB board is designed to be universal with
future modules.

Base features of A20-SOM204 board includes:
* 1GB DDR3 RAM
* AXP209 PMU
* KSZ9031 Gigabit PHY
* AT24C16 EEPROM
* Status LED
* LCD connector
* GPIO connector

There will be variants with the following options:
* Second LAN8710A Megabit PHY
* 16MB SPI Flash memory
* eMMC card
* ATECC508 crypto device

The EVB board has:
* Debug UART
* MicroSD card connector
* USB-OTG connector
* Two USB host
* RTL8723BS WiFi/BT combo
* IrDA transceiver/receiver
* HDMI connector
* VGA connector
* Megabit ethernet transceiver
* Gigabit ethernet transceiver
* SATA connector
* CAN driver
* CSI camera
* MIC and HP connectors
* PCIe x4 connector
* USB3 connector
* Two UEXT connectors
* Two user LEDs

Some of the features are multiplexed and cannot be used the same time:
CAN and Megabit PHY. Others are not usable with A20 SoC: PCIe and USB3.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.

Signed-off-by: Stefan Mavrodiev 
Acked-by: Maxime Ripard 
---
 Changes for v2:
- Add missing MAINTAINERS entry
- Reworked defconfig file
 
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 296 +++
 board/sunxi/MAINTAINERS  |   5 +
 configs/A20-Olimex-SOM204-EVB_defconfig  |  33 +++
 4 files changed, 335 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
 create mode 100644 configs/A20-Olimex-SOM204-EVB_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ebbc0ca..97e8790 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -303,6 +303,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+   sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts 
b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
new file mode 100644
index 000..c183920
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev 
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Olimex A20-SOM204-EVB";
+   compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
+
+   aliases {
+   serial0 = &uart0;
+   serial1 = &uart4;
+   serial2 = &uart7;
+   spi0 = &spi1;
+   spi1 = &spi2;
+   ethernet1 = &rtl8723bs;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   stat {
+   label = "a20-som204-evb:green:stat";
+   gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   led1 {
+   label = "a20-som204-evb:green:led1";
+   gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   led2 {
+   label = "a20-som204-evb:yellow:led2";
+   gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+   };
+
+   rtl_pwrseq: rtl_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&ahci {
+   target-supply = <®_ahci_5v>;
+   status = "okay";
+};
+
+&codec {
+   status = "okay";
+};
+
+&cpu0 {
+   cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+   status = "okay";
+};
+
+&ehci1 {
+   status = "okay";
+};
+
+&gmac {
+   pinctrl-names = "default";
+   pinctrl-0 = <&gmac_pins_rgmii_a>;
+   phy = <&phy3>;
+   phy-mode = "rgmii";
+   phy-supply = <®_vcc3v3>;
+
+   snps,re

[U-Boot] [PATCH 1/3] Move CONFIG_PHY_ADDR to Kconfig

2018-02-02 Thread Stefan Mavrodiev

CONFIG_PHY_ADDR is used for old-style configuration. This makes
impossible changing the PHY address, if multiple boards share a same
config header file (for example include/configs/sunxi-common.h).

Moving this to Kconfig helps overcoming this issue. It's defined
as entry inside PHYLIB section.

After the implemention, moveconfig was run. The issues are:
- edb9315a  - CONFIG_PHYLIB is not enabled. Entry is
  deleted.

- ds414 - CONFIG_PHYLIB is in incompatible format:
  { 0x1, 0x0 }. This entry is also deleted.

- devkit3250- The PHY_ADDR is in hex format (0x1F).
  Manually CONFIG_PHY_ADDR=31 is added in
  the defconfig.

After the changes the suspicious defconfigs passes building.

Signed-off-by: Stefan Mavrodiev 
---
 README | 4 
 configs/devkit3250_defconfig   | 1 +
 configs/khadas-vim_defconfig   | 1 +
 configs/libretech-cc_defconfig | 1 +
 configs/p212_defconfig | 1 +
 drivers/net/phy/Kconfig| 7 +++
 include/configs/am335x_shc.h   | 1 -
 include/configs/baltos.h   | 1 -
 include/configs/devkit3250.h   | 1 -
 include/configs/ds414.h| 1 -
 include/configs/edb93xx.h  | 1 -
 include/configs/khadas-vim.h   | 2 --
 include/configs/libretech-cc.h | 2 --
 include/configs/p212.h | 2 --
 include/configs/pepper.h   | 1 -
 include/configs/sunxi-common.h | 2 --
 include/configs/work_92105.h   | 1 -
 include/configs/x600.h | 1 -
 scripts/config_whitelist.txt   | 1 -
 19 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/README b/README
index b53ea7d..499184d 100644
--- a/README
+++ b/README
@@ -1436,10 +1436,6 @@ The following options need to be configured:
be at least 4MB.
 
 - MII/PHY support:
-   CONFIG_PHY_ADDR
-
-   The address of PHY on MII bus.
-
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 
The clock frequency of the MII bus
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 2ad08ae..930b631 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -36,6 +36,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_NAND=y
 CONFIG_SPL_NAND_SIMPLE=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR=31
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 4ceab90..e9a96d3 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
 CONFIG_PHY_MESON_GXL=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index 3bccff1..86852b1 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
 CONFIG_PHY_MESON_GXL=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index cb9be4a..9466238 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
 CONFIG_PHY_MESON_GXL=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 95b7534..c934aed 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -12,6 +12,13 @@ menuconfig PHYLIB
 
 if PHYLIB
 
+config PHY_ADDR
+   int "PHY address"
+   default 1 if ARCH_SUNXI
+   default 0
+   help
+ The address of PHY on MII bus. Usually in range of 0 to 31.
+
 config B53_SWITCH
bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
help
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index e2d329a..2b705fc 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -264,7 +264,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_ADDR0
 #define CONFIG_PHY_SMSC
 
 /* I2C configuration */
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 75dd0c5..31ae20c 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -285,7 +285,6 @@
 #endif
 
 /* Network. */
-#define CONFIG_PHY_ADDR0
 #define CONFIG_PHY_SMSC
 #define CONFIG_MII
 #define CONFIG_PHY_ATHEROS
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 526a81a..b66b90e 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -73,7 +73,6 @@
 #define CONFIG_RMII
 #define CONFIG_PHY_SMSC
 #define CONFIG_LPC32XX_ETH
-#define CONFIG_PHY_ADDR

[U-Boot] [PATCH 3/3] sunxi: Add A20-SOM204-EVB-eMMC board

2018-02-02 Thread Stefan Mavrodiev

A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts | 36 +++
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  | 34 +
 3 files changed, 71 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
 create mode 100644 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 97e8790..f9764a4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -304,6 +304,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
sun7i-a20-olimex-som204-evb.dtb \
+   sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts 
b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
new file mode 100644
index 000..c56620a
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev 
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som204-evb.dts"
+
+/ {
+   model = "Olimex A20-SOM204-EVB-eMMC";
+   compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
+
+   mmc2_pwrseq: mmc2_pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&mmc2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc2_pins_a>;
+   vmmc-supply = <®_vcc3v3>;
+   mmc-pwrseq = <&mmc2_pwrseq>;
+   bus-width = <4>;
+   non-removable;
+   status = "okay";
+
+   emmc: emmc@0 {
+   reg = <0>;
+   compatible = "mmc-card";
+   broken-hpi;
+   };
+};
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig 
b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
new file mode 100644
index 000..11fe6bd
--- /dev/null
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_I2C1_ENABLE=y
+CONFIG_SATAPWR="PC3"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_ADDR=3
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-- 
2.7.4

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[U-Boot] [PATCH 2/3] sunxi: Add A20-SOM204-EVB board

2018-02-02 Thread Stefan Mavrodiev

This is new System-On-Module platform with universal dimm socket for
easy insertation. The EVB board is designed to be universal with
future modules. Product page is located here [1].

Base features of A20-SOM204 board includes:
* 1GB DDR3 RAM
* AXP209 PMU
* KSZ9031 Gigabit PHY
* AT24C16 EEPROM
* Status LED
* LCD connector
* GPIO connector

There will be variants with the following options:
* Second LAN8710A Megabit PHY
* 16MB SPI Flash memory
* eMMC card
* ATECC508 crypto device

The EVB board has:
* Debug UART
* MicroSD card connector
* USB-OTG connector
* Two USB host
* RTL8723BS WiFi/BT combo
* IrDA transceiver/receiver
* HDMI connector
* VGA connector
* Megabit ethernet transceiver
* Gigabit ethernet transceiver
* SATA connector
* CAN driver
* CSI camera
* MIC and HP connectors
* PCIe x4 connector
* USB3 connector
* Two UEXT connectors
* Two user LEDs

Some of the features are multiplexed and cannot be used the same time:
CAN and Megabit PHY. Others are not usable with A20 SoC: PCIe and USB3.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.

[1] https://www.olimex.com/Products/SOM204/

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 296 +++
 configs/A20-Olimex-SOM204-EVB_defconfig  |  33 +++
 3 files changed, 330 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
 create mode 100644 configs/A20-Olimex-SOM204-EVB_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ebbc0ca..97e8790 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -303,6 +303,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+   sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts 
b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
new file mode 100644
index 000..c183920
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev 
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Olimex A20-SOM204-EVB";
+   compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
+
+   aliases {
+   serial0 = &uart0;
+   serial1 = &uart4;
+   serial2 = &uart7;
+   spi0 = &spi1;
+   spi1 = &spi2;
+   ethernet1 = &rtl8723bs;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   stat {
+   label = "a20-som204-evb:green:stat";
+   gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   led1 {
+   label = "a20-som204-evb:green:led1";
+   gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   led2 {
+   label = "a20-som204-evb:yellow:led2";
+   gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+   };
+
+   rtl_pwrseq: rtl_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&ahci {
+   target-supply = <®_ahci_5v>;
+   status = "okay";
+};
+
+&codec {
+   status = "okay";
+};
+
+&cpu0 {
+   cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+   status = "okay";
+};
+
+&ehci1 {
+   status = "okay";
+};
+
+&gmac {
+   pinctrl-names = "default";
+   pinctrl-0 = <&gmac_pins_rgmii_a>;
+   phy = <&phy3>;
+   phy-mode = "rgmii";
+   phy-supply = <®_vcc3v3>;
+
+   snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+   snps,reset-active-low;
+   snp

Re: [U-Boot] [PATCH v3 2/2] Enable test case with A20-OLinuXino-Lime2

2018-02-01 Thread Stefan Mavrodiev


On 01/30/2018 09:15 AM, Stefan Mavrodiev wrote:

On 01/22/2018 10:36 AM, Jagan Teki wrote:

On Tue, Jan 2, 2018 at 4:31 PM, Stefan Mavrodiev
 wrote:

On 12/26/2017 11:47 AM, Jagan Teki wrote:

On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev 
wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
    - Exposing spi0 alternative pins in the dts file
    - Add alias node, enabling driver probing
    - Enable spi flash related options in the defconfig file

The testing log is:
    U-Boot SPL 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 
11:39:48)

    DRAM: 1024 MiB
    CPU: 91200Hz, AXI/AHB/APB: 3/2/2
    Trying to boot from sunxi SPI


    U-Boot 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 
11:39:48 +0200)

Allwinner Technology

    CPU:   Allwinner A20 (SUN7I)
    Model: Olimex A20-OLinuXino-LIME2

Lime2 doen't have in-built spi-nor is it?

We have some prototypes with this option.

I've Rev.6 does it have spi-nor?
I assume Rev.6 is actually Rev.F. The first prototype with SPI flash 
is Rev.I (Rev.9).





    I2C:   ready
    DRAM:  1 GiB
    MMC:   SUNXI SD/MMC: 0
    MMC: no card present
    mmc_init: -123, time 1
    *** Warning - MMC init failed, using default environment

you lost the env? since it's spi-nor better to use flash env.

What's the point since this is only test case?

this can be an issue if we boot the system from spi-nor, where we can
get saved env.




    In:    serial
    Out:   serial
    Err:   serial
    Allwinner mUSB OTG (Peripheral)
    SCSI:  SATA link 0 timeout.
    AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
    flags: ncq stag pm led clo only pmp pio slum part ccc apst
    Net:   No ethernet found.
    starting USB...
    USB0:   USB EHCI 1.00
    USB1:   USB OHCI 1.0
    USB2:   USB EHCI 1.00
    USB3:   USB OHCI 1.0
    scanning bus 0 for devices... 1 USB Device(s) found
    scanning bus 2 for devices... 1 USB Device(s) found
   scanning usb for storage devices... 0 Storage Device(s) 
found

    Hit any key to stop autoboot:  0
    => sspi

    => sf probe
    SF: Detected w25q128bv with page size 256 Bytes, erase size 4 
KiB,

total 16 MiB

try to use erase/write and read commands to verify

# Erase one sector
=> sf erase 0x1000 0x100
SF: 256 bytes @ 0x1000 Erased: ERROR
=> sf erase 0x1000 0x1000
SF: 4096 bytes @ 0x1000 Erased: OK

# Get some random data
=> md.b 0x5000 0x100
5000: d6 4d d0 7e 93 d8 0f 48 1b ef 7f 7e be 4e a8 5d 
.M.~...H...~.N.]
5010: fd 9f e5 7f 2f 7b 5b 19 ed de d8 58 99 7a 24 da 
/{[X.z$.
5020: ef dd 9c 45 d7 97 ab 4f e7 fb ee 61 bc de 6a 1a 
...E...O...a..j.
5030: 9a 9f f4 3a be 4b 2f f3 ce 77 87 7e 07 23 af ff 
...:.K/..w.~.#..
5040: e5 e5 c0 fa 65 e2 78 9b 16 38 42 52 e5 6c 52 0d 
e.x..8BR.lR.
5050: f5 ff da 94 7f 98 96 d7 f0 9d 66 ae 9b b9 a2 cd 
..f.
5060: 0b dd f1 c9 1d 3b fe 5b cf ef d6 ce 8b c5 fd 56 
.;.[...V
5070: e2 52 eb 78 d4 f1 bf 57 56 6a 57 58 52 f1 0e 9d 
.R.x...WVjWXR...
5080: df be f8 19 bf cf d7 ac 4b 3e 86 21 3f c3 fe 3e 
K>.!?..>
5090: ea 27 52 ca 1f 79 bd 7b ef bf 96 c9 9d f6 81 d3 
.'R..y.{
50a0: cc 2e 8b c8 34 7f c5 2f 29 19 a8 dc 54 7a 07 1d 
4../)...Tz..
50b0: f4 e6 db ed 38 03 59 bb 31 ee b3 dd 5c e6 be 58 
8.Y.1...\..X
50c0: a6 7c 87 61 84 47 e0 b1 a1 fc 6e d3 d5 93 bf 8a 
.|.a.Gn.
50d0: 5d a3 be 4b cf 07 1d 92 ff 36 f9 46 fb 5a cb 8f 
]..K.6.F.Z..
50e0: f9 27 7a b8 7b 07 2e 22 a1 ee 56 bc a7 de 57 6a 
.'z.{.."..V...Wj
50f0: da d4 7d 7f ee db 7a e2 bc 5c 44 64 b7 fc ea 3e 
..}...z..\Dd...


# Write one page to spi-nor
=> sf write 0x5000 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Written: OK

# Readback data
=> sf read 0x5100 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Read: OK

# Compare data
=> cmp.b 0x5000 0x5100 0x100
Total of 256 byte(s) were the same


    => sf test 0 10
    SPI flash test:
    0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
    1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
    2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
    3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
    Test passed
    0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
    1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
    2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
    3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
    =>

Signed-off-by: Stefan Mavrodiev 
---
   arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 21 
+

   configs/A20-OLinuXino-Lime2_defconfig  |  8 
   2 files changed, 29 insertions(+)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index d5c796c..3c708da 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -54,6 +54,7 @@

  aliases {
  serial0

[U-Boot] [PATCH 3/3] sunxi: Add A20-SOM204-EVB-eMMC board

2018-02-01 Thread Stefan Mavrodiev

A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts | 36 +++
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  | 36 +++
 3 files changed, 73 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
 create mode 100644 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a358d19..c85979c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -286,6 +286,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
sun7i-a20-olimex-som204-evb.dtb \
+   sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts 
b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
new file mode 100644
index 000..c56620a
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev 
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som204-evb.dts"
+
+/ {
+   model = "Olimex A20-SOM204-EVB-eMMC";
+   compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
+
+   mmc2_pwrseq: mmc2_pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&mmc2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc2_pins_a>;
+   vmmc-supply = <®_vcc3v3>;
+   mmc-pwrseq = <&mmc2_pwrseq>;
+   bus-width = <4>;
+   non-removable;
+   status = "okay";
+
+   emmc: emmc@0 {
+   reg = <0>;
+   compatible = "mmc-card";
+   broken-hpi;
+   };
+};
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig 
b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
new file mode 100644
index 000..4becfe0
--- /dev/null
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_I2C1_ENABLE=y
+CONFIG_SATAPWR="PC3"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_DFU_RAM=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_SUNXI_PHY_ADDR=3
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-- 
2.7.4

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[U-Boot] [PATCH 2/3] sunxi: Add A20-SOM204-EVB board

2018-02-01 Thread Stefan Mavrodiev

This is new System-On-Module platform with universal dimm socket for
easy insertation. The EVB board is designed to be universal with
future modules. Product page is located here [1].

Base features of A20-SOM204 board includes:
* 1GB DDR3 RAM
* AXP209 PMU
* KSZ9031 Gigabit PHY
* AT24C16 EEPROM
* Status LED
* LCD connector
* GPIO connector

There will be variants with the following options:
* Second LAN8710A Megabit PHY
* 16MB SPI Flash memory
* eMMC card
* ATECC508 crypto device

The EVB board has:
* Debug UART
* MicroSD card connector
* USB-OTG connector
* Two USB host
* RTL8723BS WiFi/BT combo
* IrDA transceiver/receiver
* HDMI connector
* VGA connector
* Megabit ethernet transceiver
* Gigabit ethernet transceiver
* SATA connector
* CAN driver
* CSI camera
* MIC and HP connectors
* PCIe x4 connector
* USB3 connector
* Two UEXT connectors
* Two user LEDs

Some of the features are multiplexed and cannot be used the same time:
CAN and Megabit PHY. Others are not usable with A20 SoC: PCIe and USB3.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.

[1] https://www.olimex.com/Products/SOM204/

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 296 +++
 configs/A20-Olimex-SOM204-EVB_defconfig  |  35 
 3 files changed, 332 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
 create mode 100644 configs/A20-Olimex-SOM204-EVB_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fe156fe..a358d19 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -285,6 +285,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+   sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts 
b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
new file mode 100644
index 000..c183920
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev 
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Olimex A20-SOM204-EVB";
+   compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
+
+   aliases {
+   serial0 = &uart0;
+   serial1 = &uart4;
+   serial2 = &uart7;
+   spi0 = &spi1;
+   spi1 = &spi2;
+   ethernet1 = &rtl8723bs;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   stat {
+   label = "a20-som204-evb:green:stat";
+   gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   led1 {
+   label = "a20-som204-evb:green:led1";
+   gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   led2 {
+   label = "a20-som204-evb:yellow:led2";
+   gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+   };
+
+   rtl_pwrseq: rtl_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&ahci {
+   target-supply = <®_ahci_5v>;
+   status = "okay";
+};
+
+&codec {
+   status = "okay";
+};
+
+&cpu0 {
+   cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+   status = "okay";
+};
+
+&ehci1 {
+   status = "okay";
+};
+
+&gmac {
+   pinctrl-names = "default";
+   pinctrl-0 = <&gmac_pins_rgmii_a>;
+   phy = <&phy3>;
+   phy-mode = "rgmii";
+   phy-supply = <®_vcc3v3>;
+
+   snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+   snps,reset-active-low;
+   snp

[U-Boot] [PATCH 1/3] sunxi: Add selective PHY address

2018-02-01 Thread Stefan Mavrodiev

By default PHY address used for sunxi boards is 1. Some new boards
(A20-SOM204-EVB) uses different address.

The code enables selective PHY address via menuconfig inside ARM
submenu. The option has default value of 1.

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/mach-sunxi/Kconfig| 9 +
 include/configs/sunxi-common.h | 4 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1fededd..034c2fd 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -838,6 +838,15 @@ config GMAC_TX_DELAY
---help---
Set the GMAC Transmit Clock Delay Chain value.
 
+config SUNXI_PHY_ADDR
+   int "PHY address"
+   default 1
+   depends on SUN7I_GMAC
+   ---help---
+   The default PHY address for SUNXI is 1. Change this if your PHY
+   is configured with different address.
+
+
 config SPL_STACK_R_ADDR
default 0x4fe0 if MACH_SUN4I
default 0x4fe0 if MACH_SUN5I
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ee1cb39..fd68d2b 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -288,12 +288,12 @@ extern int soft_i2c_gpio_scl;
 
 /* Ethernet support */
 #ifdef CONFIG_SUN4I_EMAC
-#define CONFIG_PHY_ADDR1
+#define CONFIG_PHY_ADDRCONFIG_SUNXI_PHY_ADDR
 #define CONFIG_MII /* MII PHY management   */
 #endif
 
 #ifdef CONFIG_SUN7I_GMAC
-#define CONFIG_PHY_ADDR1
+#define CONFIG_PHY_ADDRCONFIG_SUNXI_PHY_ADDR
 #define CONFIG_MII /* MII PHY management   */
 #define CONFIG_PHY_REALTEK
 #endif
-- 
2.7.4

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Re: [U-Boot] [PATCH v3 2/2] Enable test case with A20-OLinuXino-Lime2

2018-01-30 Thread Stefan Mavrodiev


On 01/22/2018 10:36 AM, Jagan Teki wrote:

On Tue, Jan 2, 2018 at 4:31 PM, Stefan Mavrodiev
 wrote:

On 12/26/2017 11:47 AM, Jagan Teki wrote:

On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev 
wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
- Exposing spi0 alternative pins in the dts file
- Add alias node, enabling driver probing
- Enable spi flash related options in the defconfig file

The testing log is:
U-Boot SPL 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48)
DRAM: 1024 MiB
CPU: 91200Hz, AXI/AHB/APB: 3/2/2
Trying to boot from sunxi SPI


U-Boot 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48 +0200)
Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
Model: Olimex A20-OLinuXino-LIME2

Lime2 doen't have in-built spi-nor is it?

We have some prototypes with this option.

I've Rev.6 does it have spi-nor?
I assume Rev.6 is actually Rev.F. The first prototype with SPI flash is 
Rev.I (Rev.9).





I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
MMC: no card present
mmc_init: -123, time 1
*** Warning - MMC init failed, using default environment

you lost the env? since it's spi-nor better to use flash env.

What's the point since this is only test case?

this can be an issue if we boot the system from spi-nor, where we can
get saved env.




In:serial
Out:   serial
Err:   serial
Allwinner mUSB OTG (Peripheral)
SCSI:  SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   No ethernet found.
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
USB2:   USB EHCI 1.00
USB3:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
   scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot:  0
=> sspi

=> sf probe
SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB,
total 16 MiB

try to use erase/write and read commands to verify

# Erase one sector
=> sf erase 0x1000 0x100
SF: 256 bytes @ 0x1000 Erased: ERROR
=> sf erase 0x1000 0x1000
SF: 4096 bytes @ 0x1000 Erased: OK

# Get some random data
=> md.b 0x5000 0x100
5000: d6 4d d0 7e 93 d8 0f 48 1b ef 7f 7e be 4e a8 5d .M.~...H...~.N.]
5010: fd 9f e5 7f 2f 7b 5b 19 ed de d8 58 99 7a 24 da /{[X.z$.
5020: ef dd 9c 45 d7 97 ab 4f e7 fb ee 61 bc de 6a 1a ...E...O...a..j.
5030: 9a 9f f4 3a be 4b 2f f3 ce 77 87 7e 07 23 af ff ...:.K/..w.~.#..
5040: e5 e5 c0 fa 65 e2 78 9b 16 38 42 52 e5 6c 52 0d e.x..8BR.lR.
5050: f5 ff da 94 7f 98 96 d7 f0 9d 66 ae 9b b9 a2 cd ..f.
5060: 0b dd f1 c9 1d 3b fe 5b cf ef d6 ce 8b c5 fd 56 .;.[...V
5070: e2 52 eb 78 d4 f1 bf 57 56 6a 57 58 52 f1 0e 9d .R.x...WVjWXR...
5080: df be f8 19 bf cf d7 ac 4b 3e 86 21 3f c3 fe 3e K>.!?..>
5090: ea 27 52 ca 1f 79 bd 7b ef bf 96 c9 9d f6 81 d3 .'R..y.{
50a0: cc 2e 8b c8 34 7f c5 2f 29 19 a8 dc 54 7a 07 1d 4../)...Tz..
50b0: f4 e6 db ed 38 03 59 bb 31 ee b3 dd 5c e6 be 58 8.Y.1...\..X
50c0: a6 7c 87 61 84 47 e0 b1 a1 fc 6e d3 d5 93 bf 8a .|.a.Gn.
50d0: 5d a3 be 4b cf 07 1d 92 ff 36 f9 46 fb 5a cb 8f ]..K.6.F.Z..
50e0: f9 27 7a b8 7b 07 2e 22 a1 ee 56 bc a7 de 57 6a .'z.{.."..V...Wj
50f0: da d4 7d 7f ee db 7a e2 bc 5c 44 64 b7 fc ea 3e ..}...z..\Dd...

# Write one page to spi-nor
=> sf write 0x5000 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Written: OK

# Readback data
=> sf read 0x5100 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Read: OK

# Compare data
=> cmp.b 0x5000 0x5100 0x100
Total of 256 byte(s) were the same


=> sf test 0 10
SPI flash test:
0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
Test passed
0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
=>

Signed-off-by: Stefan Mavrodiev 
---
   arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 21 +
   configs/A20-OLinuXino-Lime2_defconfig  |  8 
   2 files changed, 29 insertions(+)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index d5c796c..3c708da 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -54,6 +54,7 @@

  aliases {
  serial0 = &uart0;
+   spi0 = &spi0;

Re: [U-Boot] [PATCH v3 2/2] Enable test case with A20-OLinuXino-Lime2

2018-01-10 Thread Stefan Mavrodiev


On 01/02/2018 01:01 PM, Stefan Mavrodiev wrote:

On 12/26/2017 11:47 AM, Jagan Teki wrote:
On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev  
wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
   - Exposing spi0 alternative pins in the dts file
   - Add alias node, enabling driver probing
   - Enable spi flash related options in the defconfig file

The testing log is:
   U-Boot SPL 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48)
   DRAM: 1024 MiB
   CPU: 91200Hz, AXI/AHB/APB: 3/2/2
   Trying to boot from sunxi SPI


   U-Boot 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48 
+0200) Allwinner Technology


   CPU:   Allwinner A20 (SUN7I)
   Model: Olimex A20-OLinuXino-LIME2

Lime2 doen't have in-built spi-nor is it?

We have some prototypes with this option.



   I2C:   ready
   DRAM:  1 GiB
   MMC:   SUNXI SD/MMC: 0
   MMC: no card present
   mmc_init: -123, time 1
   *** Warning - MMC init failed, using default environment

you lost the env? since it's spi-nor better to use flash env.

What's the point since this is only test case?



   In:    serial
   Out:   serial
   Err:   serial
   Allwinner mUSB OTG (Peripheral)
   SCSI:  SATA link 0 timeout.
   AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
   flags: ncq stag pm led clo only pmp pio slum part ccc apst
   Net:   No ethernet found.
   starting USB...
   USB0:   USB EHCI 1.00
   USB1:   USB OHCI 1.0
   USB2:   USB EHCI 1.00
   USB3:   USB OHCI 1.0
   scanning bus 0 for devices... 1 USB Device(s) found
   scanning bus 2 for devices... 1 USB Device(s) found
  scanning usb for storage devices... 0 Storage Device(s) found
   Hit any key to stop autoboot:  0
   => sspi

   => sf probe
   SF: Detected w25q128bv with page size 256 Bytes, erase size 4 
KiB, total 16 MiB

try to use erase/write and read commands to verify

# Erase one sector
=> sf erase 0x1000 0x100
SF: 256 bytes @ 0x1000 Erased: ERROR
=> sf erase 0x1000 0x1000
SF: 4096 bytes @ 0x1000 Erased: OK

# Get some random data
=> md.b 0x5000 0x100
5000: d6 4d d0 7e 93 d8 0f 48 1b ef 7f 7e be 4e a8 5d 
.M.~...H...~.N.]
5010: fd 9f e5 7f 2f 7b 5b 19 ed de d8 58 99 7a 24 da 
/{[X.z$.
5020: ef dd 9c 45 d7 97 ab 4f e7 fb ee 61 bc de 6a 1a 
...E...O...a..j.
5030: 9a 9f f4 3a be 4b 2f f3 ce 77 87 7e 07 23 af ff 
...:.K/..w.~.#..
5040: e5 e5 c0 fa 65 e2 78 9b 16 38 42 52 e5 6c 52 0d 
e.x..8BR.lR.
5050: f5 ff da 94 7f 98 96 d7 f0 9d 66 ae 9b b9 a2 cd 
..f.
5060: 0b dd f1 c9 1d 3b fe 5b cf ef d6 ce 8b c5 fd 56 
.;.[...V
5070: e2 52 eb 78 d4 f1 bf 57 56 6a 57 58 52 f1 0e 9d 
.R.x...WVjWXR...
5080: df be f8 19 bf cf d7 ac 4b 3e 86 21 3f c3 fe 3e 
K>.!?..>
5090: ea 27 52 ca 1f 79 bd 7b ef bf 96 c9 9d f6 81 d3 
.'R..y.{
50a0: cc 2e 8b c8 34 7f c5 2f 29 19 a8 dc 54 7a 07 1d 
4../)...Tz..
50b0: f4 e6 db ed 38 03 59 bb 31 ee b3 dd 5c e6 be 58 
8.Y.1...\..X
50c0: a6 7c 87 61 84 47 e0 b1 a1 fc 6e d3 d5 93 bf 8a 
.|.a.Gn.
50d0: 5d a3 be 4b cf 07 1d 92 ff 36 f9 46 fb 5a cb 8f 
]..K.6.F.Z..
50e0: f9 27 7a b8 7b 07 2e 22 a1 ee 56 bc a7 de 57 6a 
.'z.{.."..V...Wj

50f0: da d4 7d 7f ee db 7a e2 bc 5c 44 64 b7 fc ea 3e ..}...z..\Dd...

# Write one page to spi-nor
=> sf write 0x5000 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Written: OK

# Readback data
=> sf read 0x5100 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Read: OK

# Compare data
=> cmp.b 0x5000 0x5100 0x100
Total of 256 byte(s) were the same



   => sf test 0 10
   SPI flash test:
   0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
   1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
   2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
   3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
   Test passed
   0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
   1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
   2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
   3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
   =>

Signed-off-by: Stefan Mavrodiev 
---
  arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 21 +
  configs/A20-OLinuXino-Lime2_defconfig  |  8 
  2 files changed, 29 insertions(+)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts

index d5c796c..3c708da 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -54,6 +54,7 @@

 aliases {
 serial0 = &uart0;
+   spi0 = &spi0;
 };

 chosen {
@@ -215,6 +216,20 @@
 allwinner,pull = ;
 };

+   spi0_pins_b: spi0@1 {
+   allwinner,pins = "PC0", "PC1", "PC2";
+   allwinner,function = "spi0";
+   allwinner,drive = ;
+

Re: [U-Boot] [PATCH v3 2/2] Enable test case with A20-OLinuXino-Lime2

2018-01-02 Thread Stefan Mavrodiev


On 12/26/2017 11:47 AM, Jagan Teki wrote:

On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev  wrote:

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
   - Exposing spi0 alternative pins in the dts file
   - Add alias node, enabling driver probing
   - Enable spi flash related options in the defconfig file

The testing log is:
   U-Boot SPL 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48)
   DRAM: 1024 MiB
   CPU: 91200Hz, AXI/AHB/APB: 3/2/2
   Trying to boot from sunxi SPI


   U-Boot 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48 +0200) 
Allwinner Technology

   CPU:   Allwinner A20 (SUN7I)
   Model: Olimex A20-OLinuXino-LIME2

Lime2 doen't have in-built spi-nor is it?

We have some prototypes with this option.



   I2C:   ready
   DRAM:  1 GiB
   MMC:   SUNXI SD/MMC: 0
   MMC: no card present
   mmc_init: -123, time 1
   *** Warning - MMC init failed, using default environment

you lost the env? since it's spi-nor better to use flash env.

What's the point since this is only test case?



   In:serial
   Out:   serial
   Err:   serial
   Allwinner mUSB OTG (Peripheral)
   SCSI:  SATA link 0 timeout.
   AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
   flags: ncq stag pm led clo only pmp pio slum part ccc apst
   Net:   No ethernet found.
   starting USB...
   USB0:   USB EHCI 1.00
   USB1:   USB OHCI 1.0
   USB2:   USB EHCI 1.00
   USB3:   USB OHCI 1.0
   scanning bus 0 for devices... 1 USB Device(s) found
   scanning bus 2 for devices... 1 USB Device(s) found
  scanning usb for storage devices... 0 Storage Device(s) found
   Hit any key to stop autoboot:  0
   => sspi

   => sf probe
   SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 
MiB

try to use erase/write and read commands to verify

# Erase one sector
=> sf erase 0x1000 0x100
SF: 256 bytes @ 0x1000 Erased: ERROR
=> sf erase 0x1000 0x1000
SF: 4096 bytes @ 0x1000 Erased: OK

# Get some random data
=> md.b 0x5000 0x100
5000: d6 4d d0 7e 93 d8 0f 48 1b ef 7f 7e be 4e a8 5d .M.~...H...~.N.]
5010: fd 9f e5 7f 2f 7b 5b 19 ed de d8 58 99 7a 24 da /{[X.z$.
5020: ef dd 9c 45 d7 97 ab 4f e7 fb ee 61 bc de 6a 1a ...E...O...a..j.
5030: 9a 9f f4 3a be 4b 2f f3 ce 77 87 7e 07 23 af ff ...:.K/..w.~.#..
5040: e5 e5 c0 fa 65 e2 78 9b 16 38 42 52 e5 6c 52 0d e.x..8BR.lR.
5050: f5 ff da 94 7f 98 96 d7 f0 9d 66 ae 9b b9 a2 cd ..f.
5060: 0b dd f1 c9 1d 3b fe 5b cf ef d6 ce 8b c5 fd 56 .;.[...V
5070: e2 52 eb 78 d4 f1 bf 57 56 6a 57 58 52 f1 0e 9d .R.x...WVjWXR...
5080: df be f8 19 bf cf d7 ac 4b 3e 86 21 3f c3 fe 3e K>.!?..>
5090: ea 27 52 ca 1f 79 bd 7b ef bf 96 c9 9d f6 81 d3 .'R..y.{
50a0: cc 2e 8b c8 34 7f c5 2f 29 19 a8 dc 54 7a 07 1d 4../)...Tz..
50b0: f4 e6 db ed 38 03 59 bb 31 ee b3 dd 5c e6 be 58 8.Y.1...\..X
50c0: a6 7c 87 61 84 47 e0 b1 a1 fc 6e d3 d5 93 bf 8a .|.a.Gn.
50d0: 5d a3 be 4b cf 07 1d 92 ff 36 f9 46 fb 5a cb 8f ]..K.6.F.Z..
50e0: f9 27 7a b8 7b 07 2e 22 a1 ee 56 bc a7 de 57 6a .'z.{.."..V...Wj
50f0: da d4 7d 7f ee db 7a e2 bc 5c 44 64 b7 fc ea 3e ..}...z..\Dd...

# Write one page to spi-nor
=> sf write 0x5000 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Written: OK

# Readback data
=> sf read 0x5100 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Read: OK

# Compare data
=> cmp.b 0x5000 0x5100 0x100
Total of 256 byte(s) were the same



   => sf test 0 10
   SPI flash test:
   0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
   1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
   2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
   3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
   Test passed
   0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
   1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
   2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
   3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
   =>

Signed-off-by: Stefan Mavrodiev 
---
  arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 21 +
  configs/A20-OLinuXino-Lime2_defconfig  |  8 
  2 files changed, 29 insertions(+)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index d5c796c..3c708da 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -54,6 +54,7 @@

 aliases {
 serial0 = &uart0;
+   spi0 = &spi0;
 };

 chosen {
@@ -215,6 +216,20 @@
 allwinner,pull = ;
 };

+   spi0_pins_b: spi0@1 {
+   allwinner,pins = "PC0", "PC1", "PC2";
+   allwinner,function = "spi0";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
+   spi0_cs0_pins_b: spi0_cs0@1 {
+

[U-Boot] [PATCH v3 2/2] Enable test case with A20-OLinuXino-Lime2

2017-12-22 Thread Stefan Mavrodiev

Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
  - Exposing spi0 alternative pins in the dts file
  - Add alias node, enabling driver probing
  - Enable spi flash related options in the defconfig file

The testing log is:
  U-Boot SPL 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48)
  DRAM: 1024 MiB
  CPU: 91200Hz, AXI/AHB/APB: 3/2/2
  Trying to boot from sunxi SPI
  
  
  U-Boot 2018.01-rc2-00023-gfa13cb3-dirty (Dec 22 2017 - 11:39:48 +0200) 
Allwinner Technology
  
  CPU:   Allwinner A20 (SUN7I)
  Model: Olimex A20-OLinuXino-LIME2
  I2C:   ready
  DRAM:  1 GiB
  MMC:   SUNXI SD/MMC: 0
  MMC: no card present
  mmc_init: -123, time 1
  *** Warning - MMC init failed, using default environment
  
  In:serial
  Out:   serial
  Err:   serial
  Allwinner mUSB OTG (Peripheral)
  SCSI:  SATA link 0 timeout.
  AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
  flags: ncq stag pm led clo only pmp pio slum part ccc apst 
  Net:   No ethernet found.
  starting USB...
  USB0:   USB EHCI 1.00
  USB1:   USB OHCI 1.0
  USB2:   USB EHCI 1.00
  USB3:   USB OHCI 1.0
  scanning bus 0 for devices... 1 USB Device(s) found
  scanning bus 2 for devices... 1 USB Device(s) found
 scanning usb for storage devices... 0 Storage Device(s) found
  Hit any key to stop autoboot:  0 
  => sspi
  
  => sf probe
  SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 
MiB
  => sf test 0 10
  SPI flash test:
  0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
  1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
  2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
  3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
  Test passed
  0 erase: 11407 ticks, 89 KiB/s 0.712 Mbps
  1 check: 8881 ticks, 115 KiB/s 0.920 Mbps
  2 write: 10824 ticks, 94 KiB/s 0.752 Mbps
  3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
  =>

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 21 +
 configs/A20-OLinuXino-Lime2_defconfig  |  8 
 2 files changed, 29 insertions(+)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index d5c796c..3c708da 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -54,6 +54,7 @@
 
aliases {
serial0 = &uart0;
+   spi0 = &spi0;
};
 
chosen {
@@ -215,6 +216,20 @@
allwinner,pull = ;
};
 
+   spi0_pins_b: spi0@1 {
+   allwinner,pins = "PC0", "PC1", "PC2";
+   allwinner,function = "spi0";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
+   spi0_cs0_pins_b: spi0_cs0@1 {
+   allwinner,pins = "PC23";
+   allwinner,function = "spi0";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
@@ -257,6 +272,12 @@
status = "okay";
 };
 
+&spi0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&spi0_pins_b>, <&spi0_cs0_pins_b>;
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/configs/A20-OLinuXino-Lime2_defconfig 
b/configs/A20-OLinuXino-Lime2_defconfig
index 1edc844..c499e3d 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -30,3 +30,11 @@ CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_DM_SPI=y
+CONFIG_SUN4I_SPI=y
-- 
2.7.4

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[U-Boot] [PATCH v3 1/2] arm: sunxi: Allwinner A10 SPI driver

2017-12-22 Thread Stefan Mavrodiev

Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.

Signed-off-by: Stefan Mavrodiev 
---
 Changes for v3:
- Add required changes in dts and defeconfig file for testing

 Changes for v2:
- Updated copyright including original owners
- Remove write/read register function. They are replaced with direct opts
- Some coding style changes

 drivers/spi/Kconfig |   5 +
 drivers/spi/Makefile|   1 +
 drivers/spi/sun4i_spi.c | 456 
 3 files changed, 462 insertions(+)
 create mode 100644 drivers/spi/sun4i_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 494639f..9001182 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -132,6 +132,11 @@ config STM32_QSPI
  used to access the SPI NOR flash chips on platforms embedding
  this ST IP core.
 
+config SUN4I_SPI
+   bool "Allwinner A10 SoCs SPI controller"
+   help
+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
+
 config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e3184db..aa7645a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
new file mode 100644
index 000..4f4cca6
--- /dev/null
+++ b/drivers/spi/sun4i_spi.c
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik 
+ * M.B.W. Wajer 
+ *
+ * (C) Copyright 2017 Olimex Ltd..
+ * Stefan Mavrodiev 
+ *
+ *
+ * Based on linux spi driver. Original copyright follows:
+ * linux/drivers/spi/spi-sun4i.c
+ *
+ * Copyright (C) 2012 - 2014 Allwinner Tech
+ * Pan Nan 
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard 
+ *
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#define SUN4I_FIFO_DEPTH   64
+
+#define SUN4I_RXDATA_REG   0x00
+
+#define SUN4I_TXDATA_REG   0x04
+
+#define SUN4I_CTL_REG  0x08
+#define SUN4I_CTL_ENABLE   BIT(0)
+#define SUN4I_CTL_MASTER   BIT(1)
+#define SUN4I_CTL_CPHA BIT(2)
+#define SUN4I_CTL_CPOL BIT(3)
+#define SUN4I_CTL_CS_ACTIVE_LOWBIT(4)
+#define SUN4I_CTL_LMTF BIT(6)
+#define SUN4I_CTL_TF_RST   BIT(8)
+#define SUN4I_CTL_RF_RST   BIT(9)
+#define SUN4I_CTL_XCH_MASK 0x0400
+#define SUN4I_CTL_XCH  BIT(10)
+#define SUN4I_CTL_CS_MASK  0x3000
+#define SUN4I_CTL_CS(cs)   (((cs) << 12) & SUN4I_CTL_CS_MASK)
+#define SUN4I_CTL_DHB  BIT(15)
+#define SUN4I_CTL_CS_MANUALBIT(16)
+#define SUN4I_CTL_CS_LEVEL BIT(17)
+#define SUN4I_CTL_TP   BIT(18)
+
+#define SUN4I_INT_CTL_REG  0x0c
+#define SUN4I_INT_CTL_RF_F34   BIT(4)
+#define SUN4I_INT_CTL_TF_E34   BIT(12)
+#define SUN4I_INT_CTL_TC   BIT(16)
+
+#define SUN4I_INT_STA_REG  0x10
+
+#define SUN4I_DMA_CTL_REG  0x14
+
+#define SUN4I_WAIT_REG 0x18
+
+#define SUN4I_CLK_CTL_REG  0x1c
+#define SUN4I_CLK_CTL_CDR2_MASK0xff
+#define SUN4I_CLK_CTL_CDR2(div)((div) & 
SUN4I_CLK_CTL_CDR2_MASK)
+#define SUN4I_CLK_CTL_CDR1_MASK0xf
+#define SUN4I_CLK_CTL_CDR1(div)(((div) & 
SUN4I_CLK_CTL_CDR1_MASK) << 8)
+#define SUN4I_CLK_CTL_DRS  BIT(12)
+
+#define SUN4I_MAX_XFER_SIZE0xff
+
+#define SUN4I_BURST_CNT_REG0x20
+#define SUN4I_BURST_CNT(cnt)   ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_XMIT_CNT_REG 0x24
+#define SUN4I_XMIT_CNT(cnt)((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_FIFO_STA_REG 0x28
+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_TF_CNT_BITS 16
+
+#define SUN4I_SPI_MAX_RATE 2400
+#define SUN4I_SPI_MIN_RATE 3000
+#define SUN4I_SPI_DEFAULT_RATE 100
+#define SUN4I_SPI_TIMEOUT_US   100
+
+/* sun4i spi register set */
+struct sun4i_spi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctl;
+   u32 intctl;
+   u32 st;
+   u32 dmactl;
+   u32 wait;
+   u32 cctl;
+   u32 bc;
+   u32 tc;
+   u32 fifo_sta;
+};
+
+struct sun4i_spi_platdata {
+   u32 base_addr;
+   u32 m

Re: [U-Boot] [PATCH v2 1/1] arm: sunxi: Allwinner A10 SPI driver

2017-12-20 Thread Stefan Mavrodiev


On 12/13/2017 08:27 AM, Jagan Teki wrote:

On Wed, Dec 13, 2017 at 11:43 AM, Stefan Mavrodiev  wrote:

On 12/13/2017 07:19 AM, Jagan Teki wrote:

On Fri, Dec 8, 2017 at 5:08 PM, Jagan Teki 
wrote:

On Fri, Dec 8, 2017 at 2:05 PM, Stefan Mavrodiev 
wrote:

Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel (currently 4.15.0-rc1).

Signed-off-by: Stefan Mavrodiev 
---

Reviewed-by: Jagan Teki 

Are you planning to send dts and configs changes for this? I'm enough
confident to apply only when it tested.

thanks!


I'm not sure I understand you.

I've made the test with Lime2, but the spi flash is optional in production.
Thus I'm not sure if changes in the dts and config should be made.
I've tried pushing spi node to mainline kernel dts, but the patch wasn't
accepted. https://patchwork.kernel.org/patch/10076721/

Yes I've seen.


I can update sun4i, sun5i and sun7i dtsi files to add spi0_pins_b, if this
is the point of your question.

But it should accept Linux first for dts updates.

thanks!


I guess there won't be any changes in the device tree files as described 
here:

https://patchwork.kernel.org/patch/10109445/

Best regards,
Stefan Mavrodiev

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Re: [U-Boot] [PATCH v2 1/1] arm: sunxi: Allwinner A10 SPI driver

2017-12-12 Thread Stefan Mavrodiev


On 12/13/2017 07:19 AM, Jagan Teki wrote:

On Fri, Dec 8, 2017 at 5:08 PM, Jagan Teki  wrote:

On Fri, Dec 8, 2017 at 2:05 PM, Stefan Mavrodiev  wrote:

Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel (currently 4.15.0-rc1).

Signed-off-by: Stefan Mavrodiev 
---

Reviewed-by: Jagan Teki 

Are you planning to send dts and configs changes for this? I'm enough
confident to apply only when it tested.

thanks!


I'm not sure I understand you.

I've made the test with Lime2, but the spi flash is optional in 
production. Thus I'm not sure if changes in the dts and config should be 
made.
I've tried pushing spi node to mainline kernel dts, but the patch wasn't 
accepted. https://patchwork.kernel.org/patch/10076721/


I can update sun4i, sun5i and sun7i dtsi files to add spi0_pins_b, if 
this is the point of your question.


Regards,
Stefan Mavrodiev

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[U-Boot] [PATCH v2 1/1] arm: sunxi: Allwinner A10 SPI driver

2017-12-08 Thread Stefan Mavrodiev

Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel (currently 4.15.0-rc1).

Signed-off-by: Stefan Mavrodiev 
---
 Changes for v2:
- Updated copyright including original owners
- Remove write/read register function. They are replaced with direct opts
- Some coding style changes

 Tested with A20-OLinuXino-Lime2 with W25Q128 chip. The output is:
 => sspi 

 => sf probe
 SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 MiB
 => sf test 0 10
 SPI flash test:
 0 erase: 11373 ticks, 90 KiB/s 0.720 Mbps
 1 check: 8883 ticks, 115 KiB/s 0.920 Mbps
 2 write: 10769 ticks, 95 KiB/s 0.760 Mbps
 3 read: 8871 ticks, 115 KiB/s 0.920 Mbps
 Test passed
 0 erase: 11373 ticks, 90 KiB/s 0.720 Mbps
 1 check: 8883 ticks, 115 KiB/s 0.920 Mbps
 2 write: 10769 ticks, 95 KiB/s 0.760 Mbps
 3 read: 8871 ticks, 115 KiB/s 0.920 Mbps
 =>
 
 drivers/spi/Kconfig |   5 +
 drivers/spi/Makefile|   1 +
 drivers/spi/sun4i_spi.c | 456 
 3 files changed, 462 insertions(+)
 create mode 100644 drivers/spi/sun4i_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 88da9a4..d78253a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -132,6 +132,11 @@ config STM32_QSPI
  used to access the SPI NOR flash chips on platforms embedding
  this ST IP core.
 
+config SUN4I_SPI
+   bool "Allwinner A10 SoCs SPI controller"
+   help
+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
+
 config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ad56203..04ba305 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
new file mode 100644
index 000..4f4cca6
--- /dev/null
+++ b/drivers/spi/sun4i_spi.c
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik 
+ * M.B.W. Wajer 
+ *
+ * (C) Copyright 2017 Olimex Ltd..
+ * Stefan Mavrodiev 
+ *
+ *
+ * Based on linux spi driver. Original copyright follows:
+ * linux/drivers/spi/spi-sun4i.c
+ *
+ * Copyright (C) 2012 - 2014 Allwinner Tech
+ * Pan Nan 
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard 
+ *
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#define SUN4I_FIFO_DEPTH   64
+
+#define SUN4I_RXDATA_REG   0x00
+
+#define SUN4I_TXDATA_REG   0x04
+
+#define SUN4I_CTL_REG  0x08
+#define SUN4I_CTL_ENABLE   BIT(0)
+#define SUN4I_CTL_MASTER   BIT(1)
+#define SUN4I_CTL_CPHA BIT(2)
+#define SUN4I_CTL_CPOL BIT(3)
+#define SUN4I_CTL_CS_ACTIVE_LOWBIT(4)
+#define SUN4I_CTL_LMTF BIT(6)
+#define SUN4I_CTL_TF_RST   BIT(8)
+#define SUN4I_CTL_RF_RST   BIT(9)
+#define SUN4I_CTL_XCH_MASK 0x0400
+#define SUN4I_CTL_XCH  BIT(10)
+#define SUN4I_CTL_CS_MASK  0x3000
+#define SUN4I_CTL_CS(cs)   (((cs) << 12) & SUN4I_CTL_CS_MASK)
+#define SUN4I_CTL_DHB  BIT(15)
+#define SUN4I_CTL_CS_MANUALBIT(16)
+#define SUN4I_CTL_CS_LEVEL BIT(17)
+#define SUN4I_CTL_TP   BIT(18)
+
+#define SUN4I_INT_CTL_REG  0x0c
+#define SUN4I_INT_CTL_RF_F34   BIT(4)
+#define SUN4I_INT_CTL_TF_E34   BIT(12)
+#define SUN4I_INT_CTL_TC   BIT(16)
+
+#define SUN4I_INT_STA_REG  0x10
+
+#define SUN4I_DMA_CTL_REG  0x14
+
+#define SUN4I_WAIT_REG 0x18
+
+#define SUN4I_CLK_CTL_REG  0x1c
+#define SUN4I_CLK_CTL_CDR2_MASK0xff
+#define SUN4I_CLK_CTL_CDR2(div)((div) & 
SUN4I_CLK_CTL_CDR2_MASK)
+#define SUN4I_CLK_CTL_CDR1_MASK0xf
+#define SUN4I_CLK_CTL_CDR1(div)(((div) & 
SUN4I_CLK_CTL_CDR1_MASK) << 8)
+#define SUN4I_CLK_CTL_DRS  BIT(12)
+
+#define SUN4I_MAX_XFER_SIZE0xff
+
+#define SUN4I_BURST_CNT_REG0x20
+#define SUN4I_BURST_CNT(cnt)   ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_XMIT_CNT_REG 0x24
+#define SUN4I_XMIT_CNT(cnt)((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_FIFO_STA_REG 0x28
+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
+#define SUN4I_FIFO_S

[U-Boot] [PATCH 1/1] arm: sunxi: Allwinner A10 SPI driver

2017-12-01 Thread Stefan Mavrodiev

Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel (currently 4.15.0-rc1).

Signed-off-by: Stefan Mavrodiev 
---
 Tested with A20-OLinuXino-Lime2 with W25Q128 chip. The output is:
 => sspi

 => sf probe
 SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 Mib

 => sf test 0 100
 SPI flash test:
 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps
 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps
 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps
 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps
 Test passed
 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps
 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps
 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps
 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps

 drivers/spi/Kconfig |   5 +
 drivers/spi/Makefile|   1 +
 drivers/spi/sun4i_spi.c | 423 
 3 files changed, 429 insertions(+)
 create mode 100644 drivers/spi/sun4i_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 88da9a4..d78253a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -132,6 +132,11 @@ config STM32_QSPI
  used to access the SPI NOR flash chips on platforms embedding
  this ST IP core.
 
+config SUN4I_SPI
+   bool "Allwinner A10 SoCs SPI controller"
+   help
+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
+
 config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ad56203..04ba305 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
new file mode 100644
index 000..3ef1c68
--- /dev/null
+++ b/drivers/spi/sun4i_spi.c
@@ -0,0 +1,423 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik 
+ * M.B.W. Wajer 
+ *
+ * (C) Copyright 2017 Olimex Ltd..
+ * Stefan Mavrodiev 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#define SUN4I_FIFO_DEPTH   64
+
+#define SUN4I_RXDATA_REG   0x00
+
+#define SUN4I_TXDATA_REG   0x04
+
+#define SUN4I_CTL_REG  0x08
+#define SUN4I_CTL_ENABLE   BIT(0)
+#define SUN4I_CTL_MASTER   BIT(1)
+#define SUN4I_CTL_CPHA BIT(2)
+#define SUN4I_CTL_CPOL BIT(3)
+#define SUN4I_CTL_CS_ACTIVE_LOWBIT(4)
+#define SUN4I_CTL_LMTF BIT(6)
+#define SUN4I_CTL_TF_RST   BIT(8)
+#define SUN4I_CTL_RF_RST   BIT(9)
+#define SUN4I_CTL_XCH  BIT(10)
+#define SUN4I_CTL_CS_MASK  0x3000
+#define SUN4I_CTL_CS(cs)   (((cs) << 12) & SUN4I_CTL_CS_MASK)
+#define SUN4I_CTL_DHB  BIT(15)
+#define SUN4I_CTL_CS_MANUALBIT(16)
+#define SUN4I_CTL_CS_LEVEL BIT(17)
+#define SUN4I_CTL_TP   BIT(18)
+
+#define SUN4I_INT_CTL_REG  0x0c
+#define SUN4I_INT_CTL_RF_F34   BIT(4)
+#define SUN4I_INT_CTL_TF_E34   BIT(12)
+#define SUN4I_INT_CTL_TC   BIT(16)
+
+#define SUN4I_INT_STA_REG  0x10
+
+#define SUN4I_DMA_CTL_REG  0x14
+
+#define SUN4I_WAIT_REG 0x18
+
+#define SUN4I_CLK_CTL_REG  0x1c
+#define SUN4I_CLK_CTL_CDR2_MASK0xff
+#define SUN4I_CLK_CTL_CDR2(div)((div) & 
SUN4I_CLK_CTL_CDR2_MASK)
+#define SUN4I_CLK_CTL_CDR1_MASK0xf
+#define SUN4I_CLK_CTL_CDR1(div)(((div) & 
SUN4I_CLK_CTL_CDR1_MASK) << 8)
+#define SUN4I_CLK_CTL_DRS  BIT(12)
+
+#define SUN4I_MAX_XFER_SIZE0xff
+
+#define SUN4I_BURST_CNT_REG0x20
+#define SUN4I_BURST_CNT(cnt)   ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_XMIT_CNT_REG 0x24
+#define SUN4I_XMIT_CNT(cnt)((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_FIFO_STA_REG 0x28
+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_TF_CNT_BITS 16
+
+#define SUN4I_SPI_MAX_RATE 2400
+#define SUN4I_SPI_MIN_RATE 3000
+#define SUN4I_SPI_DEFAULT_RATE 100
+#define SUN4I_SPI_TIMEOUT_US   100
+
+struct sun4i_spi_platdata {
+   u32 base_addr;
+   u32 freq;
+};
+
+struct sun4i_spi_priv {
+   u32 base_addr;
+   u32 freq;
+   u32 mode;
+
+   const u8*tx_buf;
+   u8

Re: [U-Boot] [PATCH v2 1/1] sunxi: Fix A20-OLinuXino-MICRO LAN8710 support

2017-11-03 Thread Stefan Mavrodiev


On 11/03/2017 01:07 PM, Karsten Merker wrote:

On Fri, Nov 03, 2017 at 08:56:51AM +0200, Stefan Mavrodiev wrote:


 From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.

Signed-off-by: Stefan Mavrodiev 
---
Changes for v2:
- The pin mux is done with Kconfig option
- Same option is enable by default for
A20-OLinuXino-MICRO boards
  board/sunxi/gmac.c | 4 
  configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
  configs/A20-OLinuXino_MICRO_defconfig  | 1 +
  drivers/net/Kconfig| 8 
  4 files changed, 14 insertions(+)

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 69eb8ff..826650c 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -33,7 +33,11 @@ void eth_init_board(void)
  
  #ifndef CONFIG_MACH_SUN6I

/* Configure pin mux settings for GMAC */
+#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
+   for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
+#else
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#endif
  #ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig 
b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index 2ff2723..43bcea9 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPL_I2C_SUPPORT=y
  # CONFIG_SPL_EFI_PARTITION is not set
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
  CONFIG_AXP_ALDO3_VOLT=2800
  CONFIG_AXP_ALDO4_VOLT=2800
  CONFIG_SCSI=y
diff --git a/configs/A20-OLinuXino_MICRO_defconfig 
b/configs/A20-OLinuXino_MICRO_defconfig
index 1a0ad5a..22eacb3 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -20,6 +20,7 @@ CONFIG_SPL_I2C_SUPPORT=y
  # CONFIG_SPL_EFI_PARTITION is not set
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
  CONFIG_AXP_ALDO3_VOLT=2800
  CONFIG_AXP_ALDO4_VOLT=2800
  CONFIG_SCSI=y

Hello,

wouldn't this break networking on pre-revision-J A20-OLinuXino_MICRO
boards?  AIUI, the A20-OLinuXino_MICRO before Revision J uses PA17 to
control the (low-active) RESETB# line of the RTL8201CP used on the
older board revisions, so with this change the PHY on pre-revision-J
boards would be held in permanent reset state.  AIUI, it would be
necessary to have two different defconfigs - the existing defconfig
for pre-revision-J boards (without CONFIG_SUN7I_GMAC_FORCE_TXERR)
and an additional new one for revision-J-and-newer boards which
sets CONFIG_SUN7I_GMAC_FORCE_TXERR=y.


Yes, the boards before rev.J uses this signal as EPHY-RST#, but only as
an option. It's disconnected by N/A resistor. So setting this as output-low
will not have any unwanted effect. You can see this in this schematic:
https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A10-OLinuXino-MICRO/A20-OLINUXINO-MICRO_4GB_Rev_G1.pdf


diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index c1ce54e..f9f04e4 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -244,6 +244,14 @@ config SUN7I_GMAC
help
  Enable the support for Sun7i GMAC Ethernet controller
  
+config SUN7I_GMAC_FORCE_TXERR

+   bool "Force PA17 as gmac function"
+   depends on SUN7I_GMAC
+   help
+ Some ethernet phys needs TXERR control. Since the GMAC
+ doesn't have such signal, setting PA17 as GMAC function
+ makes the pin output low, which enables data transmission.
+
  config SUN4I_EMAC
bool "Allwinner Sun4i Ethernet MAC support"
depends on DM_ETH
Regards,
Karsten


Regards,
Stefan Mavrodiev

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[U-Boot] [PATCH v2 1/1] sunxi: Fix A20-OLinuXino-MICRO LAN8710 support

2017-11-03 Thread Stefan Mavrodiev

From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.

Signed-off-by: Stefan Mavrodiev 
---
Changes for v2:
- The pin mux is done with Kconfig option
- Same option is enable by default for
A20-OLinuXino-MICRO boards
 board/sunxi/gmac.c | 4 
 configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
 configs/A20-OLinuXino_MICRO_defconfig  | 1 +
 drivers/net/Kconfig| 8 
 4 files changed, 14 insertions(+)

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 69eb8ff..826650c 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -33,7 +33,11 @@ void eth_init_board(void)
 
 #ifndef CONFIG_MACH_SUN6I
/* Configure pin mux settings for GMAC */
+#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
+   for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
+#else
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#endif
 #ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig 
b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index 2ff2723..43bcea9 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
diff --git a/configs/A20-OLinuXino_MICRO_defconfig 
b/configs/A20-OLinuXino_MICRO_defconfig
index 1a0ad5a..22eacb3 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -20,6 +20,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index c1ce54e..f9f04e4 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -244,6 +244,14 @@ config SUN7I_GMAC
help
  Enable the support for Sun7i GMAC Ethernet controller
 
+config SUN7I_GMAC_FORCE_TXERR
+   bool "Force PA17 as gmac function"
+   depends on SUN7I_GMAC
+   help
+ Some ethernet phys needs TXERR control. Since the GMAC
+ doesn't have such signal, setting PA17 as GMAC function
+ makes the pin output low, which enables data transmission.
+
 config SUN4I_EMAC
bool "Allwinner Sun4i Ethernet MAC support"
depends on DM_ETH
-- 
2.7.4

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[U-Boot] [PATCH 1/1] sunxi: Fix A20-OLinuXino-MICRO dts for LAN8710

2017-09-27 Thread Stefan Mavrodiev

From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
index 7e3006f..0bc5ea9 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
@@ -95,7 +95,7 @@
 
 &gmac {
pinctrl-names = "default";
-   pinctrl-0 = <&gmac_pins_mii_a>;
+   pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
@@ -226,6 +226,13 @@
 };
 
 &pio {
+   gmac_txerr: gmac_txerr@0 {
+   allwinner,pins = "PA17";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
allwinner,pins = "PH11";
allwinner,function = "gpio_in";
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/1] sunxi: Fix A20-OLinuXino-MICRO dts for LAN8710

2017-09-27 Thread Stefan Mavrodiev


On 09/27/2017 04:19 PM, Maxime Ripard wrote:

Hi Stefan,

You should also put Jagan Teki as recipients.

On Wed, Sep 27, 2017 at 07:19:10AM +, Stefan Mavrodiev wrote:

 From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.

Signed-off-by: Stefan Mavrodiev 
---
  arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 9 -
  1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
index 7e3006f..0bc5ea9 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
@@ -95,7 +95,7 @@
  
  &gmac {

pinctrl-names = "default";
-   pinctrl-0 = <&gmac_pins_mii_a>;
+   pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
@@ -226,6 +226,13 @@
  };
  
  &pio {

+   gmac_txerr: gmac_txerr@0 {
+   allwinner,pins = "PA17";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+

There's two issues with that patch:
   - In general we try to sync the DT with Linux when we can, and the
 patch that ended up in Linux wasn't this one.

I'm little confused. If I sync the DT with the one from mainline linux,
doesn't this counts as dangerous? I mean it will be the only one that is 
synced.

This could corrupt building if sun7i-a20.dtsi is not synced for example.

   - And we don't have any pinctrl support in U-Boot, that patch will
 basically do nothing

The code that changes the muxing is here:
http://git.denx.de/?p=u-boot.git;a=blob;f=board/sunxi/gmac.c#l34

Again, since this is common for all boards, doesn't it counts as dangerous?
This is feature only on our board.


Maxime



Best regards,
Stefan Mavrodiev



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[U-Boot] [PATCH v2 1/1] sunxi: Add support for A20-OLinuXino-MICRO-eMMC

2017-09-21 Thread Stefan Mavrodiev

From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.

The dts file is the same from mainline kernel.

Signed-off-by: Stefan Mavrodiev 
---
Changes for v2:
 - Synced with latest u-boot
 - Removed MMC3 CD pin configuration

 arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts | 70 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig  | 27 ++
 2 files changed, 97 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
 create mode 100644 configs/A20-OLinuXino_MICRO-eMMC_defconfig

diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
new file mode 100644
index 000..d99e7b1
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
@@ -0,0 +1,70 @@
+ /*
+ * Copyright 2017 Olimex Ltd.
+ * Stefan Mavrodiev 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun7i-a20-olinuxino-micro.dts"
+
+/ {
+   model = "Olimex A20-OLinuXino-MICRO-eMMC";
+   compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20";
+
+   mmc2_pwrseq: pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&mmc2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc2_pins_a>;
+   vmmc-supply = <®_vcc3v3>;
+   bus-width = <4>;
+   non-removable;
+   mmc-pwrseq = <&mmc2_pwrseq>;
+   status = "okay";
+
+   emmc: emmc@0 {
+   reg = <0>;
+   compatible = "mmc-card";
+   broken-hpi;
+   };
+};
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig 
b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
new file mode 100644
index 000..3e07d00
--- /dev/null
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_I2C1_ENABLE=y
+CONFIG_VIDEO_VGA=y
+CONFIG_SATAPWR="PB8"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/1] sunxi: Add support for A20-OLinuXino-MICRO-eMMC

2017-09-13 Thread Stefan Mavrodiev


On 09/13/2017 03:24 PM, Jagan Teki wrote:

On Mon, Sep 4, 2017 at 11:25 AM, Stefan Mavrodiev  wrote:

 From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.

The dts file is the same from mainline kernel.

Signed-off-by: Stefan Mavrodiev 
---
  arch/arm/dts/Makefile   |  1 +
  arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts | 70 +

Please send this dts to Linux.

thanks!


The dts is already acknowledged in mainline linux by Maxime Ripard,
and will be available in version 4.15.
https://patchwork.kernel.org/patch/9924197/

Best regards,
Stefan Mavrodiev  


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Re: [U-Boot] [PATCH 1/1] sunxi: Add support for A20-OLinuXino-MICRO-eMMC

2017-09-13 Thread Stefan Mavrodiev


On 09/04/2017 08:55 AM, Stefan Mavrodiev wrote:

 From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.

The dts file is the same from mainline kernel.

Signed-off-by: Stefan Mavrodiev 
---
  arch/arm/dts/Makefile   |  1 +
  arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts | 70 +
  board/sunxi/MAINTAINERS |  5 ++
  configs/A20-OLinuXino_MICRO-eMMC_defconfig  | 28 ++
  4 files changed, 104 insertions(+)
  create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
  create mode 100644 configs/A20-OLinuXino_MICRO-eMMC_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 762429c..a6f2cba 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -282,6 +282,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
sun7i-a20-olinuxino-micro.dtb \
+   sun7i-a20-olinuxino-micro-emmc.dtb \
sun7i-a20-orangepi.dtb \
sun7i-a20-orangepi-mini.dtb \
sun7i-a20-pcduino3.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
new file mode 100644
index 000..d99e7b1
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
@@ -0,0 +1,70 @@
+ /*
+ * Copyright 2017 Olimex Ltd.
+ * Stefan Mavrodiev 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun7i-a20-olinuxino-micro.dts"
+
+/ {
+   model = "Olimex A20-OLinuXino-MICRO-eMMC";
+   compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20";
+
+   mmc2_pwrseq: pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&mmc2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc2_pins_a>;
+   vmmc-supply = <®_vcc3v3>;
+   bus-width = <4>;
+   non-removable;
+   mmc-pwrseq = <&mmc2_pwrseq>;
+   status = "okay";
+
+   emmc: emmc@0 {
+   reg = <0>;
+   compatible = "mmc-card";
+   broken-hpi;
+   };
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index ff6eea2..eddf38f 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -83,6 +83,11 @@ M:   FUKAUMI Naoki 
  S:Maintained
  F:configs/A20-OLinuXino-Lime_defconfig
  
+A20-OLINUXINO-MICRO-EMMC BOARD

+M: Stefan Mavrodiev 
+S: Maintained
+F: configs/A20-OLinuXino_MICRO-eMMC_defconfig
+
  A20-OLINUXINO-LIME2 BOARD
  M:Iain Paton 
  S:Maintained
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig 
b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
new file mode 100644
index 000..cfcb770
--- /dev/null
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUN

[U-Boot] [PATCH 1/1] sunxi: Add support for A20-OLinuXino-MICRO-eMMC

2017-09-04 Thread Stefan Mavrodiev

From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.

The dts file is the same from mainline kernel.

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts | 70 +
 board/sunxi/MAINTAINERS |  5 ++
 configs/A20-OLinuXino_MICRO-eMMC_defconfig  | 28 ++
 4 files changed, 104 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
 create mode 100644 configs/A20-OLinuXino_MICRO-eMMC_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 762429c..a6f2cba 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -282,6 +282,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
sun7i-a20-olinuxino-micro.dtb \
+   sun7i-a20-olinuxino-micro-emmc.dtb \
sun7i-a20-orangepi.dtb \
sun7i-a20-orangepi-mini.dtb \
sun7i-a20-pcduino3.dtb \
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts 
b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
new file mode 100644
index 000..d99e7b1
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
@@ -0,0 +1,70 @@
+ /*
+ * Copyright 2017 Olimex Ltd.
+ * Stefan Mavrodiev 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun7i-a20-olinuxino-micro.dts"
+
+/ {
+   model = "Olimex A20-OLinuXino-MICRO-eMMC";
+   compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20";
+
+   mmc2_pwrseq: pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&mmc2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc2_pins_a>;
+   vmmc-supply = <®_vcc3v3>;
+   bus-width = <4>;
+   non-removable;
+   mmc-pwrseq = <&mmc2_pwrseq>;
+   status = "okay";
+
+   emmc: emmc@0 {
+   reg = <0>;
+   compatible = "mmc-card";
+   broken-hpi;
+   };
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index ff6eea2..eddf38f 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -83,6 +83,11 @@ M:   FUKAUMI Naoki 
 S: Maintained
 F: configs/A20-OLinuXino-Lime_defconfig
 
+A20-OLINUXINO-MICRO-EMMC BOARD
+M: Stefan Mavrodiev 
+S: Maintained
+F: configs/A20-OLinuXino_MICRO-eMMC_defconfig
+
 A20-OLINUXINO-LIME2 BOARD
 M: Iain Paton 
 S: Maintained
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig 
b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
new file mode 100644
index 000..cfcb770
--- /dev/null
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN=&qu

Re: [U-Boot] [PATCH v1 1/1] ARM:SUNXI: Update DRAM clock for Olimex A20 boards

2016-10-27 Thread Stefan Mavrodiev


Hi,

I've notice that you've reduced DRAM clock for Lime2 and Lime, but not 
for A20-SOM.


Is there any specific reason for this?


Regards,

Stefan Mavrodiev

Olimex LDT


On 10/11/2016 12:38 PM, Hans de Goede wrote:

Hi,

On 10/11/2016 10:44 AM, Stefan Mavrodiev wrote:

Originally dram clock was set to 480MHz, but this behaves
unstable. To improve stability the clock is reduced to 384MHz

Signed-off-by: Stefan Mavrodiev 


The exact same change is already in u-boot-sunxi/next, and I've already
send out a pullreq to get this merged.

Regards,

Hans


---
 configs/A20-OLinuXino-Lime2_defconfig | 2 +-
 configs/A20-OLinuXino-Lime_defconfig  | 2 +-
 configs/A20-Olimex-SOM-EVB_defconfig  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/configs/A20-OLinuXino-Lime2_defconfig 
b/configs/A20-OLinuXino-Lime2_defconfig

index 5688622..4751fe0 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/A20-OLinuXino-Lime_defconfig 
b/configs/A20-OLinuXino-Lime_defconfig

index c4f6e1a..024dc2d 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig 
b/configs/A20-Olimex-SOM-EVB_defconfig

index 7a14a7b..3f4e90d 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"



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[U-Boot] [PATCH v1 1/1] ARM:SUNXI: Update DRAM clock for Olimex A20 boards

2016-10-11 Thread Stefan Mavrodiev

Originally dram clock was set to 480MHz, but this behaves
unstable. To improve stability the clock is reduced to 384MHz

Signed-off-by: Stefan Mavrodiev 
---
 configs/A20-OLinuXino-Lime2_defconfig | 2 +-
 configs/A20-OLinuXino-Lime_defconfig  | 2 +-
 configs/A20-Olimex-SOM-EVB_defconfig  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/configs/A20-OLinuXino-Lime2_defconfig 
b/configs/A20-OLinuXino-Lime2_defconfig
index 5688622..4751fe0 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/A20-OLinuXino-Lime_defconfig 
b/configs/A20-OLinuXino-Lime_defconfig
index c4f6e1a..024dc2d 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig 
b/configs/A20-Olimex-SOM-EVB_defconfig
index 7a14a7b..3f4e90d 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"
-- 
2.9.3

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[U-Boot] [PATCH v2] sunxi: Add support for A33-OLinuXino board

2016-09-02 Thread Stefan Mavrodiev

A33-OLinuXino is A33 development board designed by Olimex LTD.

It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
headphone and mic jacks, connector for LiPo battery and optional
4GB NAND Flash.

It has two 40-pin headers. One for LCD panel, and one for
additional modules. Also there is CSI/DSI connector.

The dts files are identical to the ones submitted to the upstream kernel.

Signed-off-by: Stefan Mavrodiev 
---
Changes for v2:
- Reworked defconfig
- Synced dts with upstream kernel
- Added maintainer

 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/sun8i-a33-olinuxino.dts | 226 +++
 board/sunxi/MAINTAINERS  |   5 +
 configs/A33-OLinuXino_defconfig  |  43 +++
 4 files changed, 275 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-a33-olinuxino.dts
 create mode 100644 configs/A33-OLinuXino_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7d1944f..f2de09a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -243,6 +243,7 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-q8-tablet.dtb
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-ga10h-v1.1.dtb \
+sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-r16-parrot.dtb
diff --git a/arch/arm/dts/sun8i-a33-olinuxino.dts 
b/arch/arm/dts/sun8i-a33-olinuxino.dts
new file mode 100644
index 000..9ea637e
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-olinuxino.dts
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2016 - Stefan Mavrodiev 
+ *  Olimex LTD. 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+
+/ {
+   model = "Olimex A33-OLinuXino";
+   compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&led_pin_olinuxino>;
+
+   green {
+   label = "a33-olinuxino:green:usr";
+   gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
+   };
+   };
+};
+
+&ehci0 {
+   status = "okay";
+};
+
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
+   vmmc-supply = <®_dcdc1>;
+   bus-width = <4>;
+   cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+   cd-inverted;
+   status = "okay";
+};
+
+&ohci0 {
+   status = "okay";
+};
+
+&pio {
+   led_pin_olinuxino: led_pins@0 {
+   allwinner,pins = "PB7";
+

[U-Boot] [PATCH 1/1] sunxi: Add support for A33-OLinuXino board

2016-06-18 Thread stefan . mavrodiev

From: Stefan Mavrodiev 

---
 arch/arm/dts/Makefile|   3 +-
 arch/arm/dts/sun8i-a33-olinuxino.dts | 223 +++
 configs/A33_OLinuXino_defconfig  |  29 +
 3 files changed, 254 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun8i-a33-olinuxino.dts
 create mode 100644 configs/A33_OLinuXino_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a827613..dbda275 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -221,7 +221,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-q8-tablet.dtb \
-   sun8i-a33-sinlinx-sina33.dtb
+   sun8i-a33-sinlinx-sina33.dtb \
+   sun8i-a33-olinuxino.dtb
 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
diff --git a/arch/arm/dts/sun8i-a33-olinuxino.dts 
b/arch/arm/dts/sun8i-a33-olinuxino.dts
new file mode 100644
index 000..2eaeb55
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-olinuxino.dts
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2016 - Stefan Mavrodiev 
+ *  Olimex LTD. 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "A33-OLinuXino";
+   compatible = "allwinner,sun8i-a33";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&led_pin_olinuxino>;
+
+   green {
+   label = "olinuxino:green:usr";
+   gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* LED2 */
+   linux,default-trigger = "heartbeat";
+   };
+   };
+};
+
+&ehci0 {
+   status = "okay";
+};
+
+&ohci0 {
+   status = "okay";
+};
+
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
+   vmmc-supply = <®_dcdc1>;
+   bus-width = <4>;
+   cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+   cd-inverted;
+   status = "okay";
+};
+
+&pio {
+   mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
+   allwinner,pins = "PB4";
+   allwinner,function = "gpio_in";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
+   led_pin_olinuxino: led_pins@0 {
+   allwinner,pins = "PB7";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+};
+
+&r_rsb

[U-Boot] [PATCH] sunxi: Olimex A20 boards: Enable LDO3 and LDO4 regulators

2016-05-23 Thread Stefan Mavrodiev

Sets LDO3 and LDO4 regulators at 2.8V. In the current config
these are off. This causes kernel to hang during
axp209 initialization.

Signed-off-by: Stefan Mavrodiev 
---
 configs/A20-OLinuXino_MICRO_defconfig | 2 ++
 configs/A20-Olimex-SOM-EVB_defconfig  | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/A20-OLinuXino_MICRO_defconfig 
b/configs/A20-OLinuXino_MICRO_defconfig
index e952562..0dfa989 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -26,3 +26,5 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig 
b/configs/A20-Olimex-SOM-EVB_defconfig
index cecf4c2..ed9bbb1 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -29,3 +29,5 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
-- 
2.8.1

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