[PATCH] video: Fix line padding calculation for 16 and 24 BPP bitmaps

[Sylwester Nawrocki]

Each row in the pixel array in the bitmap file is padded
if necessary so the row size is always a multiple of 4 bytes.
In current code the complement of row size to a multiple of
4 bytes is further unnecessarily multiplied by the pixel size.
This results in incorrect displaying of bitmaps having row size
that is not a multiple of 4 bytes. Fix this by removing
the unnecessary multiplication.

Tested with 24BPP bitmap and XRGB32 display.

Signed-off-by: Sylwester Nawrocki 
---
 drivers/video/video_bmp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index 5a4d12c68d..5537378781 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -328,7 +328,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
for (j = 0; j < width; j++)
fb_put_word(, );
 
-   bmap += (padded_width - width) * 2;
+   bmap += (padded_width - width);
fb -= width * 2 + priv->line_length;
}
break;
@@ -352,7 +352,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
}
}
fb -= priv->line_length + width * (bpix / 8);
-   bmap += (padded_width - width) * 3;
+   bmap += (padded_width - width);
}
break;
 #endif /* CONFIG_BMP_24BPP */
-- 
2.17.1

Re: USB patch for rpi4

[Sylwester Nawrocki]

Hi,

(Cc: Nicolas and Jim)

On 11.06.2020 11:18, Peter Robinson wrote:
 I am trying to test v4 of your patch series for USB support on rpi4:

 I am building u-boot 64-bit.  Testing on a rpi4 B 1.2 board.  But, USB is
 not working for me and wanted to see if you had any ideas.  Are there
 other dependencies other than just applying your patch series?

 I've pasted the u-boot console output below.

 From what I can tell this board does not need the VL805 firmware
>>>
>>> 1.2 rev boards do need the firmware loading patch series, not sure
>>> about any other patches.
>>
>> Are you sure?  A colleague of mine said that it was in 1.4 that the flash
>> chip for the VL805 was removed.  I can physically see that the flash
>> chip is on my board.
> 
> Yes, I am sure, the 1.2 is for the 2/4Gb model with the changes that
> need the firmware loading, the 1.4 according to their rev docs is
> limited to the 8Gb model ATM.
> 
> https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md

I'm also using rev. 1.2 board and it has the flash chip mounted and doesn't
need the VL805 firmware loading patch series.

>> In any case, I did figure out one thing that was going on.  I was using
>> the rpi4 DTB as it came shipped with my board.  I found that on the
>> PCIe node there was a typo in the compatible string.  I fixed that:
>> bus-range = <0x0 0x1>;
>> -   compatible = "brcm,bcm7211-pcie",
>> "brcm,bcm7445-pcie", "brcm,pci-plat-dev";
>> +   compatible = "brcm,bcm2711-pcie",
>> "brcm,bcm7445-pcie", "brcm,pci-plat-dev";
>> max-link-speed = <0x2>;
>>
>> ...and USB now starts up and works.

I'm glad you figured it out. Sorry, I just read your e-mails now, 
after 4 days holiday. 

In my patch set I used compatible as in mainline Linux kernel
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-brcmstb.c#n1025

AFAICS there exist BCM7211 and BCM2711 SoCs and instead of modifying 
devicetree we could also add another compatible string in the driver, 
as shown  below.
 
There will likely be follow up patches adding proper support for other
Broadcom STB SoCs to the pcie_brcmstb driver, taking care of any possible
differences in the PCIe controller. 

--8<-
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
index dade79e..ceae56a 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -608,6 +608,7 @@ static const struct dm_pci_ops brcm_pcie_ops = {
 };
 
 static const struct udevice_id brcm_pcie_ids[] = {
+   { .compatible = "brcm,bcm7211-pcie" },
{ .compatible = "brcm,bcm2711-pcie" },
{ }
 };
-->8-

-- 
Regards,
Sylwester

Re: [PATCH v4 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq

[Sylwester Nawrocki]

Hi,

On 26.05.2020 09:49, Marek Szyprowski wrote:
> On 25.05.2020 23:40, Simon Glass wrote:
>> On Mon, 25 May 2020 at 11:42, Sylwester Nawrocki  
>> wrote:
>>> On 25.05.2020 19:04, Simon Glass wrote:
>>>> On Mon, 25 May 2020 at 10:57, Sylwester Nawrocki  
>>>> wrote:
>>>>> On 25.05.2020 16:57, Simon Glass wrote:
>>>>>> On Mon, 25 May 2020 at 05:40, Sylwester Nawrocki 
>>>>>>  wrote:
>>>>>>> There might be hardware configurations where 64-bit data accesses
>>>>>>> to XHCI registers are not supported properly.  This patch removes
>>>>>>> the readq/writeq so always two 32-bit accesses are used to read/write
>>>>>>> 64-bit XHCI registers, similarly as it is done in Linux kernel.
>>>>>>>
>>>>>>> This patch fixes operation of the XHCI controller on RPI4 Broadcom
>>>>>>> BCM2711 SoC based board, where the VL805 USB XHCI controller is
>>>>>>> connected to the PCIe Root Complex, which is attached to the system
>>>>>>> through the SCB bridge.
>>>>>>>
>>>>>>> Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
>>>>>>> the 64-bit wide register accesses initiated by the CPU are not properly
>>>>>>> translated to a sequence of 32-bit PCIe accesses.
>>>>>>> xhci_readq(), for example, always returns same value in upper and lower
>>>>>>> 32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234.
>>>>>> Then I think this should be done with a quirk flag, enabled for this
>>>>>> particular device via the compatible string. It should not be an #if,
>>>>>> but an if().
>>>>> Thanks for your comments. I will check and see how this could be done.
>>>>> It might not be so straightforward since the XHCI controller is a PCI
>>>>> device matched by the pci_device_id so we would need to be looking
>>>>> at the compatible string of the PCI controller to set the quirk in
>>>>> the xhci layer. It's the PCI bridge that introduces the limitation,
>>>>> not the VL805 XHCI controller chip.
>>>> OK then it should be modelled as such.
>>>>
>>>> How is this done in Linux?
>>> In Linux simply always two 32-bit accesses are used for 64-bit registers
>>> read/write.

>> Well the USB maintainer (Marek) might be OK with that, not sure.
> 
> 32bit access is always safe according to the XHCI specification and such 
> one is always used by the Linux kernel. 64bit access might give a few 
> CPU cycles of performance improvement, but in case of typical u-boot use 
> case this is simply negligible. Do we really need to make the code 
> over-engineered for no good reason?

I didn't have a chance to measure it but I believe in practice there would be 
no any significant performance improvement. There are only few xhci_readq, 
xhci_writeq calls in the code and most of them are in a one off initialization
procedure. The only one that would matter is in xhci_acknowledge_event(),
but if we add a new (ctrl) argument to xhci_{readq,writeq} and testing of the
quirk it will likely be not much different as if we just used two 32-bit 
reads/writes unconditionally, as far as performance is concerned.

>>> And the quirks in the generic PCI XHCI driver are based on the PCI vendor
>>> and the PCI device ID, so it's not helpful. I couldn't find any reference
>>> to the parent PCI bridge there.

>> In xhci_pci_probe() you can look at the PCI vendor/device  with something 
>> like:
>>
>> struct pci_child_platdata *plat = dev_get_parent_platdata(dev);   //
>> see comments for that struct in pci.h

We need to test the PCI bridge so we could use dev->parent rather than dev
here. I'm not sure if the 64-bit data access issue is inherent to the PCI
controller itself or rather to its integration logic within the SoC 
(the SCB bridge). In other words, if in other Broadcom SoC same PCI vendor/
device controller might not need the quirk. I guess such approach would be
good enough. 

The question is whether we want to introduce the quirks mechanism now for
the readq/writeq issue. My feeling is that it's better to align with what
Linux does and the quirks could be useful for other purposes.

>> int quirks = 0;
>> if (plat->vendor == xxx && plat->device == xxx)
>> quirks |= SOMETHING
>> xhci_register(, quirks);  // add a new param
>>
>> in xhci_register() you can store the quirk in ctrl.
>>>> You can add a quirk in the PCI controller and then XHCI can check its
>>>> parent's platdata to see the flag, perhaps, since the parent will
>>>> always be UCLASS_PCI.
>>> OK, I imagined something like that.
>>>
>>>> You can always add the device to the devicetree if needed, and then
>>>> you get a compatible string.
>>> Will have a look, I wasn't aware we could add a node just for such purpose
>>> without negative side effects.
>> So long as you get the 'reg' property correct (i.e. same bus, device,
>> function) then you are OK. See pci-info.rst for docs

--
Regards, 
Sylwester

Re: [PATCH v4 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq

[Sylwester Nawrocki]

Hi Simon,

On 25.05.2020 19:04, Simon Glass wrote:
> On Mon, 25 May 2020 at 10:57, Sylwester Nawrocki  
> wrote:
>> On 25.05.2020 16:57, Simon Glass wrote:
>>> On Mon, 25 May 2020 at 05:40, Sylwester Nawrocki  
>>> wrote:
>>>>
>>>> There might be hardware configurations where 64-bit data accesses
>>>> to XHCI registers are not supported properly.  This patch removes
>>>> the readq/writeq so always two 32-bit accesses are used to read/write
>>>> 64-bit XHCI registers, similarly as it is done in Linux kernel.
>>>>
>>>> This patch fixes operation of the XHCI controller on RPI4 Broadcom
>>>> BCM2711 SoC based board, where the VL805 USB XHCI controller is
>>>> connected to the PCIe Root Complex, which is attached to the system
>>>> through the SCB bridge.
>>>>
>>>> Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
>>>> the 64-bit wide register accesses initiated by the CPU are not properly
>>>> translated to a sequence of 32-bit PCIe accesses.
>>>> xhci_readq(), for example, always returns same value in upper and lower
>>>> 32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234.
>>
>>> Then I think this should be done with a quirk flag, enabled for this
>>> particular device via the compatible string. It should not be an #if,
>>> but an if().
>>
>> Thanks for your comments. I will check and see how this could be done.
>> It might not be so straightforward since the XHCI controller is a PCI
>> device matched by the pci_device_id so we would need to be looking
>> at the compatible string of the PCI controller to set the quirk in
>> the xhci layer. It's the PCI bridge that introduces the limitation,
>> not the VL805 XHCI controller chip.
> 
> OK then it should be modelled as such.
> 
> How is this done in Linux?

In Linux simply always two 32-bit accesses are used for 64-bit registers
read/write.

And the quirks in the generic PCI XHCI driver are based on the PCI vendor
and the PCI device ID, so it's not helpful. I couldn't find any reference 
to the parent PCI bridge there.

> You can add a quirk in the PCI controller and then XHCI can check its
> parent's platdata to see the flag, perhaps, since the parent will
> always be UCLASS_PCI.

OK, I imagined something like that.

> You can always add the device to the devicetree if needed, and then
> you get a compatible string.

Will have a look, I wasn't aware we could add a node just for such purpose
without negative side effects.

-- 
Regards,
Sylwester

Re: [PATCH v4 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq

[Sylwester Nawrocki]

Hi Simon,

On 25.05.2020 16:57, Simon Glass wrote:
> On Mon, 25 May 2020 at 05:40, Sylwester Nawrocki  
> wrote:
>>
>> There might be hardware configurations where 64-bit data accesses
>> to XHCI registers are not supported properly.  This patch removes
>> the readq/writeq so always two 32-bit accesses are used to read/write
>> 64-bit XHCI registers, similarly as it is done in Linux kernel.
>>
>> This patch fixes operation of the XHCI controller on RPI4 Broadcom
>> BCM2711 SoC based board, where the VL805 USB XHCI controller is
>> connected to the PCIe Root Complex, which is attached to the system
>> through the SCB bridge.
>>
>> Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
>> the 64-bit wide register accesses initiated by the CPU are not properly
>> translated to a sequence of 32-bit PCIe accesses.
>> xhci_readq(), for example, always returns same value in upper and lower
>> 32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234.

> Then I think this should be done with a quirk flag, enabled for this
> particular device via the compatible string. It should not be an #if,
> but an if().

Thanks for your comments. I will check and see how this could be done.
It might not be so straightforward since the XHCI controller is a PCI 
device matched by the pci_device_id so we would need to be looking 
at the compatible string of the PCI controller to set the quirk in 
the xhci layer. It's the PCI bridge that introduces the limitation, 
not the VL805 XHCI controller chip.

-- 
Regards,
Sylwester

[PATCH v4 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian

[Sylwester Nawrocki]

From: Nicolas Saenz Julienne 

Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
 e7d4a95da86e0 "bitfield: fix *_encode_bits()",
 37a3862e12382 "bitfield: add u8 helpers".

Signed-off-by: Nicolas Saenz Julienne 
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki 
---
Changes since v3:
 - none.
Changes since v2:
 - added some more missing whitespaces as pointed out by checkpatch.pl.
Changes since v1:
 - added empty lines between functions and macros.
Changes since RFC:
 - new patch.
---
 include/linux/bitfield.h | 52 
 1 file changed, 52 insertions(+)

diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..7ad8b08 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,56 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
 
+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+
+static __always_inline u64 field_multiplier(u64 field)
+{
+   if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+   __bad_mask();
+   return field & -field;
+}
+
+static __always_inline u64 field_mask(u64 field)
+{
+   return field / field_multiplier(field);
+}
+
+#define MAKE_OP(type, base, to, from)  \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{  \
+   if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
+   __field_overflow(); \
+   return to((v & field_mask(field)) * field_multiplier(field));   \
+}  \
+static __always_inline __##type type##_replace_bits(__##type old,  \
+   base val, base field)   \
+{  \
+   return (old & ~to(field)) | type##_encode_bits(val, field); \
+}  \
+static __always_inline void type##p_replace_bits(__##type * p, \
+   base val, base field)   \
+{  \
+   *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
+}  \
+static __always_inline base type##_get_bits(__##type v, base field)\
+{  \
+   return (from(v) & field) / field_multiplier(field); \
+}
+
+#define __MAKE_OP(size)
\
+   MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
+   MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
+   MAKE_OP(u##size, u##size, ,)
+
+MAKE_OP(u8, u8, ,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+
+#undef __MAKE_OP
+#undef MAKE_OP
+
 #endif
-- 
2.7.4

[PATCH v4 8/9] pci: Add driver for Broadcom BCM2711 SoC PCIe controller

[Sylwester Nawrocki]

This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is used.

The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.

Signed-off-by: Nicolas Saenz Julienne 
Signed-off-by: Sylwester Nawrocki 
---
Changes since v3:
 - none.
Changes since v2 (mostly addressing Simon's review comments):
 - removed MDO_RD_DONE, MDIO_WT_DONE macro definitions,
 - updated the Kconfig entry help text,
 - reordered #include entries to match the coding style,
 - s/udev/dev,
 - s/ENODEV/EINVAL in brcm_pcie_probe() and brcm_pcie_config_address()
   functions,
 - Simplified brcm_pcie_mdio_{read, write} functions (readl_poll_timeout),
 - shortened register bit fields macro definitions,
 - dropped brcm_pcie_perst_set() and brcm_pcie_bridge_sw_init_set()
   function in favour of direct clrbits_le32/setbits_le32 calls,
 - use setbits_le32/clrbits_le32/clrsetbits_le32 instead of
   readl(), u32p_replace_bits(), writel() sequence
 - simplified brcm_pcie_config_address(), brcm_pcie_set_gen() functions,
 - changed reset pulse delay to 100 us,
 - Replaced FIELD_GET() with open coded bitwise operations,
 - brcm_cpie_cfg_index() function merged into brcm_pcie_config_address(),
 - use standard PCI PCI_EXP_LNKSTA_CLS_* link speed defines
 - added kernel-doc function comments.

Changes since v1:
 - fixed argument in brcm_pcie_set_ssc() function call,
 - changed rc_bar2_size assignment to value 0xC000, as in upstream
   devicetree.
Changes since RFC:
 - reworked to align with current Linux mainline version and u-boot
   driver by Nicolas Saenz Julienne.
---
 drivers/pci/Kconfig|   9 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_brcmstb.c | 623 +
 3 files changed, 633 insertions(+)
 create mode 100644 drivers/pci/pcie_brcmstb.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 437cd9a..543bd46 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -197,4 +197,13 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable Gen2 PCIe controller,
  which could be found on MT7623 SoC family.
 
+config PCI_BRCMSTB
+   bool "Broadcom STB PCIe controller"
+   depends on DM_PCI
+   depends on ARCH_BCM283X
+   help
+ Say Y here if you want to enable support for PCIe controller
+ on Broadcom set-top-box (STB) SoCs.
+ This driver currently supports only BCM2711 SoC and RC mode
+ of the controller.
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc..3e53b1f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
new file mode 100644
index 000..dade79e
--- /dev/null
+++ b/drivers/pci/pcie_brcmstb.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB PCIe controller driver
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ *
+ * Based on upstream Linux kernel driver:
+ * drivers/pci/controller/pcie-brcmstb.c
+ * Copyright (C) 2009 - 2017 Broadcom
+ *
+ * Based driver by Nicolas Saenz Julienne
+ * Copyright (C) 2020 Nicolas Saenz Julienne 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Offset of the mandatory PCIe capability config registers */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+/* The PCIe controller register offsets */
+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1   0x0188
+#define  VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK0xc
+#define  VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN0x0
+
+#define PCIE_RC_CFG_PRIV1_ID_VAL3  0x043c
+#define  CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xff
+
+#define PCIE_RC_DL_MDIO_ADDR   0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA0x1108
+
+#define PCIE_MISC_MISC_CTRL0x4008
+#define  MISC_CTRL_SCB_ACCESS_EN_MASK  0x1000
+#define  MISC_CTRL_CFG_READ_UR_MODE_MASK   0x2000
+#define  MISC_CTRL_MAX_BURST_SIZE_MASK 0x30
+#define  MISC_CTRL_MAX_BURST_SIZE_128  0x0
+#define  MISC_CTRL_SCB0_SIZE_MASK  0xf800
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO   0x400c
+#define PCIE_MEM_WIN0_LO(win)  \
+   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + 

[PATCH v4 5/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v3:
 - none.
Changes since v2:
 -  fixed typo MAX_MAP_MAX_ENTRIES -> MEM_MAP_MAX_ENTRIES
Changes since v1:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 4295356..9f5bca3 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,10 +11,15 @@
 #include 
 #include 
 
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS   0x6UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE   0x80UL
+
 #ifdef CONFIG_ARM64
 #include 
 
-static struct mm_region bcm283x_mem_map[] = {
+#define MEM_MAP_MAX_ENTRIES (4)
+
+static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
 };
 
-static struct mm_region bcm2711_mem_map[] = {
+static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
 PTE_BLOCK_NON_SHARE |
 PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
+   .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+   }, {
/* List terminator */
0,
}
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
 {
int i;
 
-   for (i = 0; i < 2; i++) {
+   for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;
-- 
2.7.4

[PATCH v4 9/9] configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
---
Changes since v3:
 - added missing rpi_4_defconfig changes
Changes since v2:
 - rpi_4_32b_defconfig, rpi_4_defconfig changes moved to separate
   patch
Changes since v1:
 - removed unneeded CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY entry.
Changes since RFC:
 - none.
---
 configs/rpi_4_defconfig | 9 +
 configs/rpi_arm64_defconfig | 8 +++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 6d148da..3f1a1b5 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index fea86be..f12d1e3 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="usb start"
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
-- 
2.7.4

[PATCH v4 7/9] pci: Add some PCI Express capability register offset definitions

[Sylwester Nawrocki]

Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v3:
 - none.
Changes since v2:
 - added Current Link Speed defines.
Changes since v1:
 - none.
Changes since RFC:
 - ensure the entries are added in order, sorted by ascending
   address values.
---
 include/pci.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/include/pci.h b/include/pci.h
index dfdbb32..ff5f620 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -479,11 +479,20 @@
 #define PCI_EXP_DEVCTL 8   /* Device Control */
 #define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
 #define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
 #define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_CLS0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
+#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
+#define  PCI_EXP_LNKSTA_NLW0x03f0  /* Negotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
 #define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
+#define PCI_EXP_LNKCTL248  /* Link Control 2 */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v4 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq

[Sylwester Nawrocki]

There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly.  This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.

This patch fixes operation of the XHCI controller on RPI4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.

Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
xhci_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234.

Cc: Sergey Temerkhanov 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
Changes since RFC:
 - dropped Kconfig option, switched to not using readq/writeq
   unconditionally.
---
 include/usb/xhci.h | 8 
 1 file changed, 8 deletions(-)

diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 6017504..c16106a 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -,28 +,20 @@ static inline void xhci_writel(uint32_t volatile *regs, 
const unsigned int val)
  */
 static inline u64 xhci_readq(__le64 volatile *regs)
 {
-#if BITS_PER_LONG == 64
-   return readq(regs);
-#else
__u32 *ptr = (__u32 *)regs;
u64 val_lo = readl(ptr);
u64 val_hi = readl(ptr + 1);
return val_lo + (val_hi << 32);
-#endif
 }
 
 static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
 {
-#if BITS_PER_LONG == 64
-   writeq(val, regs);
-#else
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
/* FIXME */
u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
-#endif
 }
 
 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
-- 
2.7.4

[PATCH v4 4/9] rpi4: shorten a mapping for the DRAM

[Sylwester Nawrocki]

From: Marek Szyprowski 

Remove the overlap between DRAM and device's IO area.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9966d6c..4295356 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
{
.virt = 0xUL,
.phys = 0xUL,
-   .size = 0xfe00UL,
+   .size = 0xfc00UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 PTE_BLOCK_INNER_SHARE
}, {
-- 
2.7.4

[PATCH v4 0/9] USB host support for Raspberry Pi 4 board (64-bit)

[Sylwester Nawrocki]

Hi all,

This patch series adds USB host support for Raspberry Pi 4 board. 
It includes the Broadcom STB PCIe controller driver ported from Linux 
kernel, a memory mapping update for the xHCI controller on PCIe bus
for 64-bit builds and some related fixes and updates in the usb/xhci 
and the pci driver core code.

The 32-bit ARM part has be excluded from the series and will be posted
separately.

The difference comparing to previous version is only in the config update
patch "configs: Enable support for the XHCI controller on RPI4 board (ARM
 64-bit)".

The patch series is based on v2020.07-rc1 tree.

Thanks,
Sylwester

Marek Szyprowski (3):
  rpi4: shorten a mapping for the DRAM
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
64bit)
  configs: Enable support for the XHCI controller on RPI4 board (ARM
64-bit)

Nicolas Saenz Julienne (1):
  linux/bitfield.h: Add primitives for manipulating bitfields both in
host- and fixed-endian

Sylwester Nawrocki (5):
  usb: xhci: Add missing cache flush in the scratchpad array
initialization
  usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
  pci: Move some PCIe register offset definitions to a common header
  pci: Add some PCI Express capability register offset definitions
  pci: Add driver for Broadcom BCM2711 SoC PCIe controller

 arch/arm/mach-bcm283x/init.c  |  20 +-
 configs/rpi_4_defconfig   |   9 +
 configs/rpi_arm64_defconfig   |   8 +-
 drivers/pci/Kconfig   |   9 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pci-rcar-gen3.c   |   8 -
 drivers/pci/pcie_brcmstb.c| 623 ++
 drivers/pci/pcie_intel_fpga.c |   3 -
 drivers/usb/host/xhci-mem.c   |   3 +
 include/linux/bitfield.h  |  52 
 include/pci.h |  22 +-
 include/usb/xhci.h|   8 -
 12 files changed, 740 insertions(+), 26 deletions(-)
 create mode 100644 drivers/pci/pcie_brcmstb.c

-- 
2.7.4

[PATCH v4 3/9] pci: Move some PCIe register offset definitions to a common header

[Sylwester Nawrocki]

Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
Changes since RFC:
 - whitespace clean up.
---
 drivers/pci/pci-rcar-gen3.c   |  8 
 drivers/pci/pcie_intel_fpga.c |  3 ---
 include/pci.h | 13 +++--
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 30eff67..393f1c9 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
 #define RCAR_PCI_MAX_RESOURCES 4
 #define MAX_NR_INBOUND_MAPS6
 
-#define PCI_EXP_FLAGS  2   /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE 0x00f0  /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
-#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x0010  /* Data Link Layer Link Active 
Reporting Capable */
-#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN 0xfff8  /* Physical Slot Number */
-
 enum {
RCAR_PCI_ACCESS_READ,
RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 6a9f29c..69363a0 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -65,9 +65,6 @@
 #define IS_ROOT_PORT(pcie, bdf)\
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
 
-#define PCI_EXP_LNKSTA 18  /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
-
 /**
  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  * @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index aff56b2..dfdbb32 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
 #define  PCI_EA_FIELD_MASK 0xfffc  /* For Base & Max Offset */
 
 /* PCI Express capabilities */
+#define PCI_EXP_FLAGS  2   /* Capabilities register */
+#define  PCI_EXP_FLAGS_TYPE0x00f0  /* Device/Port type */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
 #define PCI_EXP_DEVCAP 4   /* Device capabilities */
-#define  PCI_EXP_DEVCAP_FLR 0x1000 /* Function Level Reset */
+#define  PCI_EXP_DEVCAP_FLR0x1000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL 8   /* Device Control */
-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
+#define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
+#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
+#define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v4 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization

[Sylwester Nawrocki]

In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails and there is a timeout while waiting for the command completion
event. After adding the missing cache flush everything seems to be working
as expected.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
---
 drivers/usb/host/xhci-mem.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 93450ee..729bdc3 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
scratchpad->sp_array[i] = cpu_to_le64(ptr);
}
 
+   xhci_flush_cache((uintptr_t)scratchpad->sp_array,
+sizeof(u64) * num_sp);
+
return 0;
 
 fail_sp3:
-- 
2.7.4

Re: [PATCH v3 9/9] configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit)

[Sylwester Nawrocki]

Hi Matthias,

On 24.05.2020 20:30, Matthias Brugger wrote:
> On 13/05/2020 11:21, Sylwester Nawrocki wrote:
>> On 12.05.2020 20:47, Sylwester Nawrocki wrote:
>>> This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
>>> and USB commands. To get it working one has to call the following commands:
>>> "pci enum; usb start;", thus such commands have been added to the default
>>> "preboot" environment variable. One has to update their environment if it
>>> is already configured to get this feature working out of the box.
>>>
>>> Signed-off-by: Marek Szyprowski 
>>> Signed-off-by: Sylwester Nawrocki 
>>> ---
>>> Changes since v2:
>>>  - rpi_4_32b_defconfig, rpi_4_defconfig changes moved to separate
>>>patch
>>
>> rpi_4_defconfig changes should also be part of $subject patch,
>> I will fix it in next version.
> 
> Do you plan to send a new version the next days?
> I'd like to get this into v2020.07 but we are already late in the development 
> cycle.

Sure, I will submit new version today.

-- 
Regards,
Sylwester

Re: [PATCH v3 9/9] configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit)

[Sylwester Nawrocki]

On 12.05.2020 20:47, Sylwester Nawrocki wrote:
> This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
> and USB commands. To get it working one has to call the following commands:
> "pci enum; usb start;", thus such commands have been added to the default
> "preboot" environment variable. One has to update their environment if it
> is already configured to get this feature working out of the box.
> 
> Signed-off-by: Marek Szyprowski 
> Signed-off-by: Sylwester Nawrocki 
> ---
> Changes since v2:
>  - rpi_4_32b_defconfig, rpi_4_defconfig changes moved to separate
>patch

rpi_4_defconfig changes should also be part of $subject patch,
I will fix it in next version.

[RESEND PATCH v3 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian

[Sylwester Nawrocki]

From: Nicolas Saenz Julienne 

Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
 e7d4a95da86e0 "bitfield: fix *_encode_bits()",
 37a3862e12382 "bitfield: add u8 helpers".

Signed-off-by: Nicolas Saenz Julienne 
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki 
---
Resending as I sent wrong version of [PATCH v3 6/9] by mistake.

Changes since v2:
 - added some more missing whitespaces as pointed out by checkpatch.pl.

Changes since v1:
 - added empty lines between functions and macros.

Changes since RFC:
 - new patch.
---
 include/linux/bitfield.h | 52 
 1 file changed, 52 insertions(+)

diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..7ad8b08 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,56 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})

+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+
+static __always_inline u64 field_multiplier(u64 field)
+{
+   if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+   __bad_mask();
+   return field & -field;
+}
+
+static __always_inline u64 field_mask(u64 field)
+{
+   return field / field_multiplier(field);
+}
+
+#define MAKE_OP(type, base, to, from)  \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{  \
+   if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
+   __field_overflow(); \
+   return to((v & field_mask(field)) * field_multiplier(field));   \
+}  \
+static __always_inline __##type type##_replace_bits(__##type old,  \
+   base val, base field)   \
+{  \
+   return (old & ~to(field)) | type##_encode_bits(val, field); \
+}  \
+static __always_inline void type##p_replace_bits(__##type * p, \
+   base val, base field)   \
+{  \
+   *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
+}  \
+static __always_inline base type##_get_bits(__##type v, base field)\
+{  \
+   return (from(v) & field) / field_multiplier(field); \
+}
+
+#define __MAKE_OP(size)
\
+   MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
+   MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
+   MAKE_OP(u##size, u##size, ,)
+
+MAKE_OP(u8, u8, ,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+
+#undef __MAKE_OP
+#undef MAKE_OP
+
 #endif
--
2.7.4

[PATCH v3 8/9] pci: Add driver for Broadcom BCM2711 SoC PCIe controller

[Sylwester Nawrocki]

This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is used.

The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.

Signed-off-by: Nicolas Saenz Julienne 
Signed-off-by: Sylwester Nawrocki 
---
Changes since v2:
 - removed MDO_RD_DONE, MDIO_WT_DONE macro definitions,
 - updated the Kconfig entry help text,
 - reordered #include entries to match the coding style,
 - s/udev/dev,
 - s/ENODEV/EINVAL in brcm_pcie_probe() and brcm_pcie_config_address()
   functions,
 - Simplified brcm_pcie_mdio_{read, write} functions (readl_poll_timeout),
 - shortened register bit fields macro definitions,
 - dropped brcm_pcie_perst_set() and brcm_pcie_bridge_sw_init_set()
   function in favour of direct clrbits_le32/setbits_le32 calls,
 - use setbits_le32/clrbits_le32/clrsetbits_le32 instead of
   readl(), u32p_replace_bits(), writel() sequence
 - simplified brcm_pcie_config_address(), brcm_pcie_set_gen() functions,
 - changed reset pulse delay to 100 us,
 - Replaced FIELD_GET() with open coded bitwise operations,
 - brcm_cpie_cfg_index() function merged into brcm_pcie_config_address(),
 - use standard PCI PCI_EXP_LNKSTA_CLS_* link speed defines
 - added kernel-doc function comments.

Changes since v1:
 - fixed argument in brcm_pcie_set_ssc() function call,
 - changed rc_bar2_size assignment to value 0xC000, as in upstream
   devicetree.
Changes since RFC:
 - reworked to align with current Linux mainline version and u-boot
   driver by Nicolas Saenz Julienne.
---
 drivers/pci/Kconfig|   9 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_brcmstb.c | 623 +
 3 files changed, 633 insertions(+)
 create mode 100644 drivers/pci/pcie_brcmstb.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 437cd9a..543bd46 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -197,4 +197,13 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable Gen2 PCIe controller,
  which could be found on MT7623 SoC family.
 
+config PCI_BRCMSTB
+   bool "Broadcom STB PCIe controller"
+   depends on DM_PCI
+   depends on ARCH_BCM283X
+   help
+ Say Y here if you want to enable support for PCIe controller
+ on Broadcom set-top-box (STB) SoCs.
+ This driver currently supports only BCM2711 SoC and RC mode
+ of the controller.
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc..3e53b1f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
new file mode 100644
index 000..dade79e
--- /dev/null
+++ b/drivers/pci/pcie_brcmstb.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB PCIe controller driver
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ *
+ * Based on upstream Linux kernel driver:
+ * drivers/pci/controller/pcie-brcmstb.c
+ * Copyright (C) 2009 - 2017 Broadcom
+ *
+ * Based driver by Nicolas Saenz Julienne
+ * Copyright (C) 2020 Nicolas Saenz Julienne 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Offset of the mandatory PCIe capability config registers */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+/* The PCIe controller register offsets */
+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1   0x0188
+#define  VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK0xc
+#define  VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN0x0
+
+#define PCIE_RC_CFG_PRIV1_ID_VAL3  0x043c
+#define  CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xff
+
+#define PCIE_RC_DL_MDIO_ADDR   0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA0x1108
+
+#define PCIE_MISC_MISC_CTRL0x4008
+#define  MISC_CTRL_SCB_ACCESS_EN_MASK  0x1000
+#define  MISC_CTRL_CFG_READ_UR_MODE_MASK   0x2000
+#define  MISC_CTRL_MAX_BURST_SIZE_MASK 0x30
+#define  MISC_CTRL_MAX_BURST_SIZE_128  0x0
+#define  MISC_CTRL_SCB0_SIZE_MASK  0xf800
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO   0x400c
+#define PCIE_MEM_WIN0_LO(win)  \
+   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI   0x401

[PATCH v3 9/9] configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit)

[Sylwester Nawrocki]

This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
---
Changes since v2:
 - rpi_4_32b_defconfig, rpi_4_defconfig changes moved to separate
   patch
Changes since v1:
 - removed unneeded CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY entry.

Changes since RFC:
 - none.
---
 configs/rpi_arm64_defconfig | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index fea86be..f12d1e3 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="usb start"
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
-- 
2.7.4

[PATCH v3 7/9] pci: Add some PCI Express capability register offset definitions

[Sylwester Nawrocki]

Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v2:
 - added Current Link Speed defines.
Changes since v1:
 - none.
Changes since RFC:
 - ensure the entries are added in order, sorted by ascending
   address values.
---
 include/pci.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/include/pci.h b/include/pci.h
index dfdbb32..ff5f620 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -479,11 +479,20 @@
 #define PCI_EXP_DEVCTL 8   /* Device Control */
 #define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
 #define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
 #define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_CLS0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
+#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
+#define  PCI_EXP_LNKSTA_NLW0x03f0  /* Negotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
 #define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
+#define PCI_EXP_LNKCTL248  /* Link Control 2 */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v3 5/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v2:
 -  fixed typo MAX_MAP_MAX_ENTRIES -> MEM_MAP_MAX_ENTRIES
Changes since v1:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 4295356..9f5bca3 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,10 +11,15 @@
 #include 
 #include 
 
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS   0x6UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE   0x80UL
+
 #ifdef CONFIG_ARM64
 #include 
 
-static struct mm_region bcm283x_mem_map[] = {
+#define MEM_MAP_MAX_ENTRIES (4)
+
+static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
 };
 
-static struct mm_region bcm2711_mem_map[] = {
+static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
 PTE_BLOCK_NON_SHARE |
 PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
+   .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+   }, {
/* List terminator */
0,
}
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
 {
int i;
 
-   for (i = 0; i < 2; i++) {
+   for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;
-- 
2.7.4

[PATCH v3 3/9] pci: Move some PCIe register offset definitions to a common header

[Sylwester Nawrocki]

Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
Changes since RFC:
 - whitespace clean up.
---
 drivers/pci/pci-rcar-gen3.c   |  8 
 drivers/pci/pcie_intel_fpga.c |  3 ---
 include/pci.h | 13 +++--
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 30eff67..393f1c9 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
 #define RCAR_PCI_MAX_RESOURCES 4
 #define MAX_NR_INBOUND_MAPS6
 
-#define PCI_EXP_FLAGS  2   /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE 0x00f0  /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
-#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x0010  /* Data Link Layer Link Active 
Reporting Capable */
-#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN 0xfff8  /* Physical Slot Number */
-
 enum {
RCAR_PCI_ACCESS_READ,
RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 6a9f29c..69363a0 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -65,9 +65,6 @@
 #define IS_ROOT_PORT(pcie, bdf)\
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
 
-#define PCI_EXP_LNKSTA 18  /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
-
 /**
  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  * @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index aff56b2..dfdbb32 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
 #define  PCI_EA_FIELD_MASK 0xfffc  /* For Base & Max Offset */
 
 /* PCI Express capabilities */
+#define PCI_EXP_FLAGS  2   /* Capabilities register */
+#define  PCI_EXP_FLAGS_TYPE0x00f0  /* Device/Port type */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
 #define PCI_EXP_DEVCAP 4   /* Device capabilities */
-#define  PCI_EXP_DEVCAP_FLR 0x1000 /* Function Level Reset */
+#define  PCI_EXP_DEVCAP_FLR0x1000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL 8   /* Device Control */
-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
+#define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
+#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
+#define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v3 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian

[Sylwester Nawrocki]

From: Nicolas Saenz Julienne 

Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
 e7d4a95da86e0 "bitfield: fix *_encode_bits()",
 37a3862e12382 "bitfield: add u8 helpers".

Signed-off-by: Nicolas Saenz Julienne 
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki 
---
Changes since v1:
 - added empty lines between functions and macros.

Changes since RFC:
 - new patch.
---
 include/linux/bitfield.h | 50 
 1 file changed, 50 insertions(+)

diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..7acba4c 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,54 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
 
+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+static __always_inline u64 field_multiplier(u64 field)
+{
+   if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+   __bad_mask();
+   return field & -field;
+}
+static __always_inline u64 field_mask(u64 field)
+{
+   return field / field_multiplier(field);
+}
+
+#define MAKE_OP(type,base,to,from) \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{  \
+   if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
+   __field_overflow(); \
+   return to((v & field_mask(field)) * field_multiplier(field));   \
+}  \
+static __always_inline __##type type##_replace_bits(__##type old,  \
+   base val, base field)   \
+{  \
+   return (old & ~to(field)) | type##_encode_bits(val, field); \
+}  \
+static __always_inline void type##p_replace_bits(__##type *p,  \
+   base val, base field)   \
+{  \
+   *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
+}  \
+static __always_inline base type##_get_bits(__##type v, base field)\
+{  \
+   return (from(v) & field)/field_multiplier(field);   \
+}
+
+#define __MAKE_OP(size)
\
+   MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
+   MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
+   MAKE_OP(u##size,u##size,,)
+
+MAKE_OP(u8,u8,,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+
+#undef __MAKE_OP
+#undef MAKE_OP
+
 #endif
-- 
2.7.4

[PATCH v3 4/9] rpi4: shorten a mapping for the DRAM

[Sylwester Nawrocki]

From: Marek Szyprowski 

Remove the overlap between DRAM and device's IO area.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9966d6c..4295356 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
{
.virt = 0xUL,
.phys = 0xUL,
-   .size = 0xfe00UL,
+   .size = 0xfc00UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 PTE_BLOCK_INNER_SHARE
}, {
-- 
2.7.4

[PATCH v3 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization

[Sylwester Nawrocki]

In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails and there is a timeout while waiting for the command completion
event. After adding the missing cache flush everything seems to be working
as expected.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
---
 drivers/usb/host/xhci-mem.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 93450ee..729bdc3 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
scratchpad->sp_array[i] = cpu_to_le64(ptr);
}
 
+   xhci_flush_cache((uintptr_t)scratchpad->sp_array,
+sizeof(u64) * num_sp);
+
return 0;
 
 fail_sp3:
-- 
2.7.4

[PATCH v3 0/9] USB host support for Raspberry Pi 4 board (64-bit)

[Sylwester Nawrocki]

Hi all,

This patch series adds USB host support for Raspberry Pi 4 board. 
It includes the Broadcom STB PCIe controller driver ported from Linux 
kernel, a memory mapping update for the xHCI controller on PCIe bus
for 64-bit builds and some related fixes and updates in the usb/xhci 
and the pci driver core code.

The 32-bit ARM part has be excluded from the series and will be posted
separately.

This iteration includes mostly correction in the PCIe controller driver
patch addressing Simon's review comments. Hopefully I have addressed 
all comments. I didn't decide to use struct for the control registers
as the registers offsets used are sparse and I don't have detailed 
documentation of the hardware to be able to define the struct accurately.

The patch series is based on v2020.07-rc1 tree.

Thanks,
Sylwester

Marek Szyprowski (2):
  rpi4: shorten a mapping for the DRAM
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
64bit)

Nicolas Saenz Julienne (1):
  linux/bitfield.h: Add primitives for manipulating bitfields both in
host- and fixed-endian

Sylwester Nawrocki (6):
  usb: xhci: Add missing cache flush in the scratchpad array
initialization
  usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
  pci: Move some PCIe register offset definitions to a common header
  pci: Add some PCI Express capability register offset definitions
  pci: Add driver for Broadcom BCM2711 SoC PCIe controller
  configs: Enable support for the XHCI controller on RPI4 board (ARM
64-bit)

 arch/arm/mach-bcm283x/init.c  |  20 +-
 configs/rpi_arm64_defconfig   |   8 +-
 drivers/pci/Kconfig   |   9 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pci-rcar-gen3.c   |   8 -
 drivers/pci/pcie_brcmstb.c| 623 ++
 drivers/pci/pcie_intel_fpga.c |   3 -
 drivers/usb/host/xhci-mem.c   |   3 +
 include/linux/bitfield.h  |  50 
 include/pci.h |  22 +-
 include/usb/xhci.h|   8 -
 11 files changed, 729 insertions(+), 26 deletions(-)
 create mode 100644 drivers/pci/pcie_brcmstb.c

-- 
2.7.4

[PATCH v3 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq

[Sylwester Nawrocki]

There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly.  This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.

This patch fixes operation of the XHCI controller on RPI4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.

Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
xhci_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234.

Cc: Sergey Temerkhanov 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
Changes since RFC:
 - dropped Kconfig option, switched to not using readq/writeq
   unconditionally.
---
 include/usb/xhci.h | 8 
 1 file changed, 8 deletions(-)

diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 6017504..c16106a 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -,28 +,20 @@ static inline void xhci_writel(uint32_t volatile *regs, 
const unsigned int val)
  */
 static inline u64 xhci_readq(__le64 volatile *regs)
 {
-#if BITS_PER_LONG == 64
-   return readq(regs);
-#else
__u32 *ptr = (__u32 *)regs;
u64 val_lo = readl(ptr);
u64 val_hi = readl(ptr + 1);
return val_lo + (val_hi << 32);
-#endif
 }
 
 static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
 {
-#if BITS_PER_LONG == 64
-   writeq(val, regs);
-#else
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
/* FIXME */
u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
-#endif
 }
 
 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
-- 
2.7.4

Re: [PATCH v2 09/10] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

Hi Jim,

On 08.05.2020 16:25, Jim Quinlan wrote:
 static int brcm_pcie_probe(struct udevice *dev)
 +{
 +   struct udevice *ctlr = pci_get_controller(dev);
 +   struct pci_controller *hose = dev_get_uclass_priv(ctlr);
 +   struct brcm_pcie *pcie = dev_get_priv(dev);
 +   void __iomem *base = pcie->base;
 +   bool ssc_good = false;
 +   int num_out_wins = 0;
 +   u64 rc_bar2_offset, rc_bar2_size;
 +   unsigned int scb_size_val;
 +   int i, ret;
 +   u16 nlw, cls, lnksta;
 +   u32 tmp;
 +
 +   /* Reset the bridge */
 +   brcm_pcie_bridge_sw_init_set(pcie, 1);
 +
 +   udelay(150);
>>> Please add a comment as to how you chose the value, and below.
>> This was picked from Jim Quinlan's original code submission:
>> https://protect2.fireeye.com/url?k=9d9c41ed-c002ef77-9d9dcaa2-0cc47a336fae-205e162c16256602=1=https%3A%2F%2Flkml.org%2Flkml%2F2018%2F9%2F19%2F642
>>
>> Sadly there isn't any comment there.

> The bridge is being reset and then un-reset.  The delay is a safety
> precaution to preclude the reset signal from looking like a glitch.

If you don't mind I will add that sentence as a comment for the reset
delay.

-- 
Regards,
Sylwester

Re: [RFC PATCH 1/2] arm: provide a function for boards init code to modify MMU virtual-physical map

[Sylwester Nawrocki]

On 12.05.2020 15:17, Marek Szyprowski wrote:
> -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
> -  enum dcache_option option);
> +static inline void mmu_set_region_dcache_behaviour(phys_addr_t start,
> + size_t size, enum dcache_option option)

aarch64 build fails with an error:

arch/arm/cpu/armv8/cache_v8.c:555:6: error: redefinition of 
‘mmu_set_region_dcache_behaviour’
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  ^~~
In file included from ./arch/arm/include/asm/cache.h:11:0,
 from include/net.h:15,
 from include/common.h:41,
 from arch/arm/cpu/armv8/cache_v8.c:10:
./arch/arm/include/asm/system.h:593:20: note: previous definition of 
‘mmu_set_region_dcache_behaviour’ was here
 static inline void mmu_set_region_dcache_behaviour(phys_addr_t start,
^~~
  CC  common/exports.o
scripts/Makefile.build:265: recipe for target 'arch/arm/cpu/armv8/cache_v8.o' 
failed
make[1]: *** [arch/arm/cpu/armv8/cache_v8.o] Error 1
Makefile:1790: recipe for target 'arch/arm/cpu/armv8' failed
make: *** [arch/arm/cpu/armv8] Error 2

-- 
Thanks,
Sylwester

Re: [PATCH v2 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

[Sylwester Nawrocki]

On 11.05.2020 21:47, Matthias Brugger wrote:
 static void rpi4_create_pcie_xhci_mapping(void)
 +{
 +  unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT;
 +  phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS;
 +  unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE;
 +
 +  while (size) {
 +  set_section_phys(sect, phys_addr, DCACHE_OFF);
 +  sect++;
 +  phys_addr += MMU_SECTION_SIZE;
 +  size -= MMU_SECTION_SIZE;
 +  }
 +}
>>> I wonder if we can't do all this in the pcie driver probe function. Maybe 
>>> we can
>>> create a new function like mmu_set_region_dcache_behaviour_phys which 
>>> allows us
>>> to update a mapping that's not 1:1.
>>>
>>> Tom what do you think?
>> I think a harder look at how PowerPC handled this situation is in order,
>> and then following / extending that path is in order.
>>
> Thanks Tom for the feedback.
> Sylwester, I propose to split the series in two. One for adding the driver to
> 64-bit U-Boot and another one to add support for rpi_4_32b_defconfig. This way
> we could get the driver merged for 2020.07 for sure, while 32-bit parts could
> take more cycles to be ready. What do you think?

Sounds good to me, I will split the series and will post the 64-bits part
first, while we work on the 32-bit part according to your suggestions.

-- 
Thanks,
Sylwester

Re: [PATCH] config: Enable USB Keyboard support on RPi4

[Sylwester Nawrocki]

Hi Matthias,

On 08.05.2020 17:55, Matthias Brugger wrote:
> It seems we are missing
> CONFIG_SYS_STDIO_DEREGISTER=y
> at least for me without this, U-Boot does not build.

Isn't it selected by USB_KEYBOARD? I also had related build issues
which disappeared after running "make clean".

-- 
Regards,
Sylwester

Re: [PATCH v2 09/10] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

Hi Simon,

On 06.05.2020 16:47, Simon Glass wrote:
> On Mon, 4 May 2020 at 06:45, Sylwester Nawrocki  
> wrote:

>> ---
>>  drivers/pci/Kconfig|   6 +
>>  drivers/pci/Makefile   |   1 +
>>  drivers/pci/pcie_brcmstb.c | 594 
>> +
>>  3 files changed, 601 insertions(+)
>>  create mode 100644 drivers/pci/pcie_brcmstb.c
> 
> A few small comments.

Thank you for time and a valuable review.

>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig

>> +config PCI_BRCMSTB
>> +   bool "Broadcom STB PCIe controller"
>> +   depends on DM_PCI
>> +   depends on ARCH_BCM283X
>> +   help
>> + Say Y here if you want to enable Broadcom STB PCIe controller 
>> support.
> 
> What is STB? What features does this support? You should get a warning
> here to write at least three lines.

I'm going to change that help text to something along the lines of:

  Say Y here if you want to enable support for PCIe controller
  on Broadcom set-top-box (STB) SoCs.
  This driver currently supports only BCM2711 SoC and RC mode
  of the controller.

>> diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
>> new file mode 100644
>> index 000..c6ddf92
>> --- /dev/null
>> +++ b/drivers/pci/pcie_brcmstb.c
>> @@ -0,0 +1,594 @@

>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
> 
> Check ordering of include files:
> 
> https://protect2.fireeye.com/url?k=c3a0292d-9e737093-c3a1a262-0cc47a31ba82-690f9f10b3970f9d=1=https%3A%2F%2Fwww.denx.de%2Fwiki%2FU-Boot%2FCodingStyle

Thanks for the hint, it felt there was something wrong with the ordering.

>> +#define PCIE_MISC_MISC_CTRL0x4008
>> +#define  PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK0x1000
>> +#define  PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
>> +#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK   0x30
>> +#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_1280x0
>> +#define  PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK0xf800
> 
> If you have a _MASK, don't you need a _SHIFT to allow you to read from
> the field?

I had shift definitions originally but these got removed when we started to
use the FIELD_GET macro and similar. Shifts are retrieved there from a mask 
by ffs() call (find first bit set in a word). If that's not preferred in 
u-boot I will switch back to using explicit shift definitions.

> Can you drop the PCIE_MISC prefix? These are very long and local to this file.

Yes, will do. It seems many of these bit field macro definitions could have 
shorter names. I revisited them all again and shortened most of them.
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO   0x400c
>> +#define PCIE_MEM_WIN0_LO(win)  \
>> +   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)

>> +/* MDIO registers */

>> +#define MDIO_RD_DONE(x)(((x) & MDIO_DATA_DONE_MASK) 
>> ? 1 : 0)
>> +#define MDIO_WT_DONE(x)(((x) & MDIO_DATA_DONE_MASK) 
>> ? 0 : 1)
> 
> Are these two worth it? You can do this in your code> if (readl(xxx) & 
> MDIO_DATA_DONE_MASK)

I will drop these macros, have copied them from the Linux driver without
much thought. They are not really necessary, especially when we use
readl_poll_timout().
 
> If you must use these, then I think true/false are better than 1/0.

>> +struct brcm_pcie {
> 
> struct comment

Ok.
>> +   void __iomem*base;
>> +
>> +   int gen;
>> +   boolssc;
>> +};
>> +
>> +#define msleep(a) udelay((a) * 1000)
> 
> This is already defined in U-Boot.

Indeed, I should have grepped for mdelay rather than msleep. 

>> +/*
>> + * This is to convert the size of the inbound "BAR" region to the
>> + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> 
> Please use a proper function comments with args and return value.

Will improve that.

>> + */
>> +static int brcm_pcie_encode_ibar_size(u64 size)
>> +{
>> +   int log2_in = ilog2(size);
>> +
>> +   if (log2_in >= 12 && log2_in <= 15)
>> +   /* Covers 4KB to 32KB (inclusive) */
>> +   return (log2_in - 12) + 0x1c;
>> +   else if (log2_in >= 16 && log2_in <= 37)
>> +   /* Covers 64KB to 32GB, (inclusive) */
>> +   return log2_in - 15;
>> +   /* Something is awry so disable */
> 
&

Re: [PATCH v2 09/10] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

Hi Nicolas, 

On 05.05.2020 17:45, Nicolas Saenz Julienne wrote:
> If it's OK with you, as I'm already familiar with the driver from maintaining
> it on the Linux kernel, I wouldn't mind doing it here too.
> 
> Sylwester, if you're also interested I can send a patch adding both of us.

Of course, I'm fine with having you as the maintainer of the driver.
You can add me as well, I'm just not sure if a formal separate MAINTAINERS
entry is needed. It looks like it would be first one with two persons for 
one driver.

-- 
Regards,
Sylwester

Re: [PATCH v2 09/10] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

On 05.05.2020 16:13, Nicolas Saenz Julienne wrote:
> On Mon, 2020-05-04 at 14:45 +0200, Sylwester Nawrocki wrote:
>> This patch adds basic driver for the Broadcom STB PCIe host controller.
>> The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
>> handling removed. The inbound access memory region is not currently
>> parsed from dma-ranges DT property and a fixed 4GB region is used.
 ^^
  (I will change that to 3GB in next version)
>> The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
>> USB Host Controller.
>>
>> Signed-off-by: Nicolas Saenz Julienne 
>> Signed-off-by: Sylwester Nawrocki 

> I don't know if it's a little redundant already having a Signed-off-by tag, 
> but if relevant you can add my:
> 
> Reviewed-by: Nicolas Saenz Julienne 

Thanks for your review, I think it doesn't hurt to add the tag,
it would indicate your review of final version.

-- 
Regards,
Sylwester

Re: [PATCH] config: Enable USB Keyboard support on RPi4

[Sylwester Nawrocki]

On 05.05.2020 16:51, Nicolas Saenz Julienne wrote:
> Supporting USB keyboards out of the box is both handy for development
> and production. Notably if u-boot is used to boot into GRUB.
> 
> Signed-off-by: Nicolas Saenz Julienne 

Reviewed-by: Sylwester Nawrocki 

> --- 
> Note that rpi_arm64_defconfig already supports USB keyboard. This is to
> be applied on top of Sylwester Nawrocki's PCIe/xHCI on RPi4 series.
Thanks for the patch, USB keyboard worked well for me on rpi4. I actually
used that feature to verify my PCIe/xHCI patch series.

-- 
Regards,
Sylwester

[PATCH v2 10/10] config: Enable support for the XHCI controller on RPI4 board

[Sylwester Nawrocki]

From: Marek Szyprowski 

This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
---
Changes since v1:
 - removed unneeded CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY entry.

Changes since RFC:
 - none.
---
 configs/rpi_4_32b_defconfig | 9 +
 configs/rpi_4_defconfig | 9 +
 configs/rpi_arm64_defconfig | 8 +++-
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 72cda5d..0dd763f 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 6d148da..3f1a1b5 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index fea86be..f12d1e3 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="usb start"
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
-- 
2.7.4

[PATCH v2 09/10] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

This patch adds basic driver for the Broadcom STB PCIe host controller.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 4GB region is used.

The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.

Signed-off-by: Nicolas Saenz Julienne 
Signed-off-by: Sylwester Nawrocki 
---
Changes since v1:
 - fixed argument in brcm_pcie_set_ssc() function call
 - changed rc_bar2_size assignment to value 0xC000, as in upstream
   devicetre
Changes since RFC:
 - reworked to align with current Linux mainline version and u-boot
   driver by Nicolas Saenz Julienne

brcmstb pcie
---
 drivers/pci/Kconfig|   6 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_brcmstb.c | 594 +
 3 files changed, 601 insertions(+)
 create mode 100644 drivers/pci/pcie_brcmstb.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 437cd9a..056a021 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -197,4 +197,10 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable Gen2 PCIe controller,
  which could be found on MT7623 SoC family.
 
+config PCI_BRCMSTB
+   bool "Broadcom STB PCIe controller"
+   depends on DM_PCI
+   depends on ARCH_BCM283X
+   help
+ Say Y here if you want to enable Broadcom STB PCIe controller support.
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc..3e53b1f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
new file mode 100644
index 000..c6ddf92
--- /dev/null
+++ b/drivers/pci/pcie_brcmstb.c
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB PCIe controller driver
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ *
+ * Based on upstream Linux kernel driver:
+ * drivers/pci/controller/pcie-brcmstb.c
+ * Copyright (C) 2009 - 2017 Broadcom
+ *
+ * Based driver by Nicolas Saenz Julienne
+ * Copyright (C) 2020 Nicolas Saenz Julienne 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+/* Broadcom STB PCIe Register Offsets */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1
0x0188
+#define  PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define  PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
+
+#define PCIE_RC_CFG_PRIV1_ID_VAL3  0x043c
+#define  PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xff
+
+#define PCIE_RC_DL_MDIO_ADDR   0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA0x1108
+
+#define PCIE_MISC_MISC_CTRL0x4008
+#define  PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK0x1000
+#define  PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK   0x30
+#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_1280x0
+#define  PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK0xf800
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO   0x400c
+#define PCIE_MEM_WIN0_LO(win)  \
+   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI   0x4010
+#define PCIE_MEM_WIN0_HI(win)  \
+   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+
+#define PCIE_MISC_RC_BAR1_CONFIG_LO0x402c
+#define  PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_RC_BAR2_CONFIG_LO0x4034
+#define  PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_HI0x4038
+
+#define PCIE_MISC_RC_BAR3_CONFIG_LO0x403c
+#define  PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_PCIE_STATUS  0x4068
+#define  PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK  0x80
+#define  PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
+#define  PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
+#define  PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK   0x40
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT0x4070
+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK0xfff0
+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff

[PATCH v2 07/10] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian

[Sylwester Nawrocki]

From: Nicolas Saenz Julienne 

Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
 e7d4a95da86e0 "bitfield: fix *_encode_bits()",
 37a3862e12382 "bitfield: add u8 helpers".

Signed-off-by: Nicolas Saenz Julienne 
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki 
---
Changes since v1:
 - added empty lines between functions and macros.

Changes since RFC:
 - new patch.
---
 include/linux/bitfield.h | 50 
 1 file changed, 50 insertions(+)

diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..7acba4c 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,54 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
 
+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+static __always_inline u64 field_multiplier(u64 field)
+{
+   if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+   __bad_mask();
+   return field & -field;
+}
+static __always_inline u64 field_mask(u64 field)
+{
+   return field / field_multiplier(field);
+}
+
+#define MAKE_OP(type,base,to,from) \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{  \
+   if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
+   __field_overflow(); \
+   return to((v & field_mask(field)) * field_multiplier(field));   \
+}  \
+static __always_inline __##type type##_replace_bits(__##type old,  \
+   base val, base field)   \
+{  \
+   return (old & ~to(field)) | type##_encode_bits(val, field); \
+}  \
+static __always_inline void type##p_replace_bits(__##type *p,  \
+   base val, base field)   \
+{  \
+   *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
+}  \
+static __always_inline base type##_get_bits(__##type v, base field)\
+{  \
+   return (from(v) & field)/field_multiplier(field);   \
+}
+
+#define __MAKE_OP(size)
\
+   MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
+   MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
+   MAKE_OP(u##size,u##size,,)
+
+MAKE_OP(u8,u8,,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+
+#undef __MAKE_OP
+#undef MAKE_OP
+
 #endif
-- 
2.7.4

[PATCH v2 04/10] rpi4: shorten a mapping for the DRAM

[Sylwester Nawrocki]

From: Marek Szyprowski 

Remove the overlap between DRAM and device's IO area.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9966d6c..4295356 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
{
.virt = 0xUL,
.phys = 0xUL,
-   .size = 0xfe00UL,
+   .size = 0xfc00UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 PTE_BLOCK_INNER_SHARE
}, {
-- 
2.7.4

[PATCH v2 02/10] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq

[Sylwester Nawrocki]

There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly.  This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.

This patch fixes operation of the XHCI controller on RPI4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.

Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
xhci_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234.

Cc: Sergey Temerkhanov 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
Changes since RFC:
 - dropped Kconfig option, switched to not using readq/writeq
   unconditionally.
---
 include/usb/xhci.h | 8 
 1 file changed, 8 deletions(-)

diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 6017504..c16106a 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -,28 +,20 @@ static inline void xhci_writel(uint32_t volatile *regs, 
const unsigned int val)
  */
 static inline u64 xhci_readq(__le64 volatile *regs)
 {
-#if BITS_PER_LONG == 64
-   return readq(regs);
-#else
__u32 *ptr = (__u32 *)regs;
u64 val_lo = readl(ptr);
u64 val_hi = readl(ptr + 1);
return val_lo + (val_hi << 32);
-#endif
 }
 
 static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
 {
-#if BITS_PER_LONG == 64
-   writeq(val, regs);
-#else
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
/* FIXME */
u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
-#endif
 }
 
 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
-- 
2.7.4

[PATCH v2 08/10] pci: Add some PCI Express capability register offset definitions

[Sylwester Nawrocki]

Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
Changes since RFC:
 - ensure the entries are added in order, sorted by ascending
   address values.
---
 include/pci.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/pci.h b/include/pci.h
index dfdbb32..66676c0 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -479,11 +479,17 @@
 #define PCI_EXP_DEVCTL 8   /* Device Control */
 #define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
 #define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
 #define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_CLS0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_NLW0x03f0  /* Negotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
 #define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
+#define PCI_EXP_LNKCTL248  /* Link Control 2 */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v2 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff80 CPU virtual address.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
---
Changes since v1:
 - none.
---
 arch/arm/mach-bcm283x/Kconfig |  1 +
 arch/arm/mach-bcm283x/include/mach/base.h |  7 +
 arch/arm/mach-bcm283x/init.c  | 52 +++
 3 files changed, 60 insertions(+)

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 00419bf..bcb7f1d 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+   select PHYS_64BIT
 
 config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h 
b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae398..1d10dc9 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -6,6 +6,13 @@
 #ifndef _BCM283x_BASE_H_
 #define _BCM283x_BASE_H_
 
+#include 
+
 extern unsigned long rpi_bcm283x_base;
 
+#ifdef CONFIG_ARMV7_LPAE
+extern void *rpi4_phys_to_virt(phys_addr_t paddr);
+#define phys_to_virt(x) rpi4_phys_to_virt(x)
+#endif
+
 #endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 6a748da..5d0d160 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -145,6 +145,58 @@ int mach_cpu_init(void)
 }
 
 #ifdef CONFIG_ARMV7_LPAE
+
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT   0xff80UL
+
+void *rpi4_phys_to_virt(phys_addr_t paddr)
+{
+   if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS)
+   paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS +
+   BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT;
+   return (void *)(unsigned long)paddr;
+}
+
+static void set_section_phys(unsigned int section, phys_addr_t phys,
+enum dcache_option option)
+{
+   u64 *page_table = (u64 *)gd->arch.tlb_addr;
+   /* Need to set the access flag to not fault */
+   u64 value = TTB_SECT_AP | TTB_SECT_AF;
+
+   /* Add the page offset */
+   value |= (phys);
+
+   /* Add caching bits */
+   value |= option;
+
+   /* Set PTE */
+   page_table[section] = value;
+}
+
+static void rpi4_create_pcie_xhci_mapping(void)
+{
+   unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT;
+   phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS;
+   unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE;
+
+   while (size) {
+   set_section_phys(sect, phys_addr, DCACHE_OFF);
+   sect++;
+   phys_addr += MMU_SECTION_SIZE;
+   size -= MMU_SECTION_SIZE;
+   }
+}
+
+void arm_init_domains(void)
+{
+   /*
+* Hijack this function to prepare a mappings for the PCIe MMIO
+* region for the XHCI controller on RPi4 board.
+* This code is called before enabling the MMU in ARM 32bit mode.
+*/
+   rpi4_create_pcie_xhci_mapping();
+}
+
 void enable_caches(void)
 {
dcache_enable();
-- 
2.7.4

[PATCH v2 05/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 4295356..6a748da 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,10 +11,15 @@
 #include 
 #include 
 
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS   0x6UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE   0x80UL
+
 #ifdef CONFIG_ARM64
 #include 
 
-static struct mm_region bcm283x_mem_map[] = {
+#define MAX_MAP_MAX_ENTRIES (4)
+
+static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
 };
 
-static struct mm_region bcm2711_mem_map[] = {
+static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
 PTE_BLOCK_NON_SHARE |
 PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
+   .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+   }, {
/* List terminator */
0,
}
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
 {
int i;
 
-   for (i = 0; i < 2; i++) {
+   for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;
-- 
2.7.4

[PATCH v2 03/10] pci: Move some PCIe register offset definitions to a common header

[Sylwester Nawrocki]

Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
Changes since RFC:
 - whitespace clean up.
---
 drivers/pci/pci-rcar-gen3.c   |  8 
 drivers/pci/pcie_intel_fpga.c |  3 ---
 include/pci.h | 13 +++--
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 30eff67..393f1c9 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
 #define RCAR_PCI_MAX_RESOURCES 4
 #define MAX_NR_INBOUND_MAPS6
 
-#define PCI_EXP_FLAGS  2   /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE 0x00f0  /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
-#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x0010  /* Data Link Layer Link Active 
Reporting Capable */
-#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN 0xfff8  /* Physical Slot Number */
-
 enum {
RCAR_PCI_ACCESS_READ,
RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 6a9f29c..69363a0 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -65,9 +65,6 @@
 #define IS_ROOT_PORT(pcie, bdf)\
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
 
-#define PCI_EXP_LNKSTA 18  /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
-
 /**
  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  * @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index aff56b2..dfdbb32 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
 #define  PCI_EA_FIELD_MASK 0xfffc  /* For Base & Max Offset */
 
 /* PCI Express capabilities */
+#define PCI_EXP_FLAGS  2   /* Capabilities register */
+#define  PCI_EXP_FLAGS_TYPE0x00f0  /* Device/Port type */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
 #define PCI_EXP_DEVCAP 4   /* Device capabilities */
-#define  PCI_EXP_DEVCAP_FLR 0x1000 /* Function Level Reset */
+#define  PCI_EXP_DEVCAP_FLR0x1000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL 8   /* Device Control */
-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
+#define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
+#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
+#define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v2 01/10] usb: xhci: Add missing cache flush in the scratchpad array initialization

[Sylwester Nawrocki]

In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails and there is a timeout while waiting for the command completion
event. After adding the missing cache flush everything seems to be working
as expected.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Bin Meng 
Reviewed-by: Nicolas Saenz Julienne 
---
Changes since v1:
 - none.
---
 drivers/usb/host/xhci-mem.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 93450ee..729bdc3 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
scratchpad->sp_array[i] = cpu_to_le64(ptr);
}
 
+   xhci_flush_cache((uintptr_t)scratchpad->sp_array,
+sizeof(u64) * num_sp);
+
return 0;
 
 fail_sp3:
-- 
2.7.4

[PATCH v2 00/10] USB host support for Raspberry Pi 4 board

[Sylwester Nawrocki]

Hi all,

This patch series adds USB host support for Raspberry Pi 4 board. 
It includes the Broadcom STB PCIe controller driver ported from Linux 
kernel, a memory mapping update for the xHCI controller on PCIe bus
for 32-bit and 64-bit system builds and some related fixes and updates
in the usb/xhci and the pci driver core code.

This iteration includes minor corrections in patches 7, 9, 10 addressing
review comments.

The patch series is based on v2020.07-rc1 tree.

Thanks,
Sylwester

Marek Szyprowski (4):
  rpi4: shorten a mapping for the DRAM
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
64bit)
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
32bit)
  config: Enable support for the XHCI controller on RPI4 board

Nicolas Saenz Julienne (1):
  linux/bitfield.h: Add primitives for manipulating bitfields both in
host- and fixed-endian

Sylwester Nawrocki (5):
  usb: xhci: Add missing cache flush in the scratchpad array
initialization
  usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
  pci: Move some PCIe register offset definitions to a common header
  pci: Add some PCI Express capability register offset definitions
  pci: Add driver for Broadcom STB PCIe controller

 arch/arm/mach-bcm283x/Kconfig |   1 +
 arch/arm/mach-bcm283x/include/mach/base.h |   7 +
 arch/arm/mach-bcm283x/init.c  |  72 +++-
 configs/rpi_4_32b_defconfig   |   9 +
 configs/rpi_4_defconfig   |   9 +
 configs/rpi_arm64_defconfig   |   8 +-
 drivers/pci/Kconfig   |   6 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pci-rcar-gen3.c   |   8 -
 drivers/pci/pcie_brcmstb.c| 594 ++
 drivers/pci/pcie_intel_fpga.c |   3 -
 drivers/usb/host/xhci-mem.c   |   3 +
 include/linux/bitfield.h  |  50 +++
 include/pci.h |  19 +-
 include/usb/xhci.h|   8 -
 15 files changed, 772 insertions(+), 26 deletions(-)
 create mode 100644 drivers/pci/pcie_brcmstb.c

-- 
2.7.4

Re: [PATCH v1 09/10] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

Hi Nicolas,

On 4/28/20 15:59, Nicolas Saenz Julienne wrote:

+   /*
+* For config space accesses on the RC, show the right class for
+* a PCIe-PCIe bridge (the default setting is to be EP mode).
+*/
+   tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
+   u32p_replace_bits(, 0x060400,
+ PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
+   writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
+
+   if (pcie->ssc) {
+   ret = brcm_pcie_set_ssc(base);



This call should be like this:

ret = brcm_pcie_set_ssc(pcie);

It builds alright since base is a void pointer. But it obvioulsy causes issues
further down the line.


Thanks for pointing this out, I have fixed it and re-tested again with
SSC enabled and disabled.

--
Regards,
Sylwester

Re: [PATCH v1 10/10] config: Enable support for the XHCI controller on RPI4 board

[Sylwester Nawrocki]

On 27.04.2020 11:11, Nicolas Saenz Julienne wrote:
> On Fri, 2020-04-24 at 18:50 +0200, Sylwester Nawrocki wrote:
>> +CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y
> This one slipped trough :)

Indeed, I have already removed it for next iteration.

-- 
Regards,
Sylwester

Re: [PATCH v1 07/10] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian.

[Sylwester Nawrocki]

Hi Bin,

On 25.04.2020 03:43, Bin Meng wrote:
> Could we add blank line between macros and functions to improve some 
> readablity?

Thanks for your review. It might be indeed a bit easier to read with 
some extra empty lines, given there is no any comments to those macro 
definitions. I have made a change as follows for the next iteration.

-8<-
diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 4964213..7acba4c 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -117,6 +117,7 @@ static __always_inline u64 field_mask(u64 field)
  {
 return field / field_multiplier(field);
  }
+
  #define MAKE_OP(type,base,to,from) \
  static __always_inline __##type type##_encode_bits(base v, base field) \
  { \
@@ -138,14 +139,17 @@ static __always_inline base 
type##_get_bits(__##type v, base field)   \
  { \
 return (from(v) & field)/field_multiplier(field);   \
  }
+
  #define __MAKE_OP(size) \
MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
 MAKE_OP(u##size,u##size,,)
+
  MAKE_OP(u8,u8,,)
  __MAKE_OP(16)
  __MAKE_OP(32)
  __MAKE_OP(64)
+
  #undef __MAKE_OP
  #undef MAKE_OP
->8-

--
Regards,
Sylwester

[PATCH v1 09/10] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

This patch adds basic driver for the Broadcom STB PCIe host controller.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 4GB region is used.

The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.

Signed-off-by: Nicolas Saenz Julienne 
Signed-off-by: Sylwester Nawrocki 
---
Changes since RFC:
 - reworked to align with current Linux mainline version and u-boot driver
   by Nicolas Saenz Julienne
---
 drivers/pci/Kconfig|   6 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_brcmstb.c | 593 +
 3 files changed, 600 insertions(+)
 create mode 100644 drivers/pci/pcie_brcmstb.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 437cd9a..056a021 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -197,4 +197,10 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable Gen2 PCIe controller,
  which could be found on MT7623 SoC family.
 
+config PCI_BRCMSTB
+   bool "Broadcom STB PCIe controller"
+   depends on DM_PCI
+   depends on ARCH_BCM283X
+   help
+ Say Y here if you want to enable Broadcom STB PCIe controller support.
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc..3e53b1f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
new file mode 100644
index 000..dfe9833
--- /dev/null
+++ b/drivers/pci/pcie_brcmstb.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB PCIe controller driver
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ *
+ * Based on upstream Linux kernel driver:
+ * drivers/pci/controller/pcie-brcmstb.c
+ * Copyright (C) 2009 - 2017 Broadcom
+ *
+ * Based driver by Nicolas Saenz Julienne
+ * Copyright (C) 2020 Nicolas Saenz Julienne 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+/* Broadcom STB PCIe Register Offsets */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1
0x0188
+#define  PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define  PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
+
+#define PCIE_RC_CFG_PRIV1_ID_VAL3  0x043c
+#define  PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xff
+
+#define PCIE_RC_DL_MDIO_ADDR   0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA0x1108
+
+#define PCIE_MISC_MISC_CTRL0x4008
+#define  PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK0x1000
+#define  PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK   0x30
+#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_1280x0
+#define  PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK0xf800
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO   0x400c
+#define PCIE_MEM_WIN0_LO(win)  \
+   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI   0x4010
+#define PCIE_MEM_WIN0_HI(win)  \
+   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+
+#define PCIE_MISC_RC_BAR1_CONFIG_LO0x402c
+#define  PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_RC_BAR2_CONFIG_LO0x4034
+#define  PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_HI0x4038
+
+#define PCIE_MISC_RC_BAR3_CONFIG_LO0x403c
+#define  PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_PCIE_STATUS  0x4068
+#define  PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK  0x80
+#define  PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
+#define  PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
+#define  PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK   0x40
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT0x4070
+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK0xfff0
+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
+#define PCIE_MEM_WIN0_BASE_LIMIT(win)  \
+   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIM

[PATCH v1 10/10] config: Enable support for the XHCI controller on RPI4 board

[Sylwester Nawrocki]

From: Marek Szyprowski 

This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.

Signed-off-by: Marek Szyprowski 
---
Changes since RFC:
 - none.
---
 configs/rpi_4_32b_defconfig |  9 +
 configs/rpi_4_defconfig | 10 ++
 configs/rpi_arm64_defconfig |  9 -
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 72cda5d..0dd763f 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 6d148da..f80e5da 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -28,12 +32,18 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index fea86be..926dfc3 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="usb start"
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
@@ -26,11 +27,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
-- 
2.7.4

[PATCH v1 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff80 CPU virtual address.

Signed-off-by: Marek Szyprowski 
---
Changes since RFC:
 - none.
---
 arch/arm/mach-bcm283x/Kconfig |  1 +
 arch/arm/mach-bcm283x/include/mach/base.h |  7 +
 arch/arm/mach-bcm283x/init.c  | 52 +++
 3 files changed, 60 insertions(+)

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 00419bf..bcb7f1d 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+   select PHYS_64BIT
 
 config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h 
b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae398..1d10dc9 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -6,6 +6,13 @@
 #ifndef _BCM283x_BASE_H_
 #define _BCM283x_BASE_H_
 
+#include 
+
 extern unsigned long rpi_bcm283x_base;
 
+#ifdef CONFIG_ARMV7_LPAE
+extern void *rpi4_phys_to_virt(phys_addr_t paddr);
+#define phys_to_virt(x) rpi4_phys_to_virt(x)
+#endif
+
 #endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 6a748da..5d0d160 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -145,6 +145,58 @@ int mach_cpu_init(void)
 }
 
 #ifdef CONFIG_ARMV7_LPAE
+
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT   0xff80UL
+
+void *rpi4_phys_to_virt(phys_addr_t paddr)
+{
+   if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS)
+   paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS +
+   BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT;
+   return (void *)(unsigned long)paddr;
+}
+
+static void set_section_phys(unsigned int section, phys_addr_t phys,
+enum dcache_option option)
+{
+   u64 *page_table = (u64 *)gd->arch.tlb_addr;
+   /* Need to set the access flag to not fault */
+   u64 value = TTB_SECT_AP | TTB_SECT_AF;
+
+   /* Add the page offset */
+   value |= (phys);
+
+   /* Add caching bits */
+   value |= option;
+
+   /* Set PTE */
+   page_table[section] = value;
+}
+
+static void rpi4_create_pcie_xhci_mapping(void)
+{
+   unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT;
+   phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS;
+   unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE;
+
+   while (size) {
+   set_section_phys(sect, phys_addr, DCACHE_OFF);
+   sect++;
+   phys_addr += MMU_SECTION_SIZE;
+   size -= MMU_SECTION_SIZE;
+   }
+}
+
+void arm_init_domains(void)
+{
+   /*
+* Hijack this function to prepare a mappings for the PCIe MMIO
+* region for the XHCI controller on RPi4 board.
+* This code is called before enabling the MMU in ARM 32bit mode.
+*/
+   rpi4_create_pcie_xhci_mapping();
+}
+
 void enable_caches(void)
 {
dcache_enable();
-- 
2.7.4

[PATCH v1 07/10] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian.

[Sylwester Nawrocki]

From: Nicolas Saenz Julienne 

Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
 e7d4a95da86e0 "bitfield: fix *_encode_bits()",
 37a3862e12382 "bitfield: add u8 helpers".

Signed-off-by: Nicolas Saenz Julienne 
Signed-off-by: Sylwester Nawrocki 
---
Changes since RFC:
 - new patch.
---
 include/linux/bitfield.h | 46 ++
 1 file changed, 46 insertions(+)

diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6ff..4964213 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,50 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
 
+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+static __always_inline u64 field_multiplier(u64 field)
+{
+   if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+   __bad_mask();
+   return field & -field;
+}
+static __always_inline u64 field_mask(u64 field)
+{
+   return field / field_multiplier(field);
+}
+#define MAKE_OP(type,base,to,from) \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{  \
+   if (__builtin_constant_p(v) && (v & ~field_mask(field)))\
+   __field_overflow(); \
+   return to((v & field_mask(field)) * field_multiplier(field));   \
+}  \
+static __always_inline __##type type##_replace_bits(__##type old,  \
+   base val, base field)   \
+{  \
+   return (old & ~to(field)) | type##_encode_bits(val, field); \
+}  \
+static __always_inline void type##p_replace_bits(__##type *p,  \
+   base val, base field)   \
+{  \
+   *p = (*p & ~to(field)) | type##_encode_bits(val, field);\
+}  \
+static __always_inline base type##_get_bits(__##type v, base field)\
+{  \
+   return (from(v) & field)/field_multiplier(field);   \
+}
+#define __MAKE_OP(size)
\
+   MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
+   MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
+   MAKE_OP(u##size,u##size,,)
+MAKE_OP(u8,u8,,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+#undef __MAKE_OP
+#undef MAKE_OP
+
 #endif
-- 
2.7.4

[PATCH v1 05/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.

Signed-off-by: Marek Szyprowski 
---
Changes since RFC:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 4295356..6a748da 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,10 +11,15 @@
 #include 
 #include 
 
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS   0x6UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE   0x80UL
+
 #ifdef CONFIG_ARM64
 #include 
 
-static struct mm_region bcm283x_mem_map[] = {
+#define MAX_MAP_MAX_ENTRIES (4)
+
+static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
 };
 
-static struct mm_region bcm2711_mem_map[] = {
+static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
 PTE_BLOCK_NON_SHARE |
 PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
+   .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+   }, {
/* List terminator */
0,
}
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
 {
int i;
 
-   for (i = 0; i < 2; i++) {
+   for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;
-- 
2.7.4

[PATCH v1 08/10] pci: Add some PCI Express capability register offset definitions

[Sylwester Nawrocki]

Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.

Reviewed-by: Bin Meng 
Signed-off-by: Sylwester Nawrocki 
---
Changes since RFC:
 - ensure the entries are added in order, sorted by ascending
   address values.
---
 include/pci.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/pci.h b/include/pci.h
index 5bf91a4..5307478 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -479,11 +479,17 @@
 #define PCI_EXP_DEVCTL 8   /* Device Control */
 #define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
 #define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
 #define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_CLS0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_NLW0x03f0  /* Negotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
 #define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
+#define PCI_EXP_LNKCTL248  /* Link Control 2 */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v1 04/10] rpi4: shorten a mapping for the DRAM

[Sylwester Nawrocki]

From: Marek Szyprowski 

Remove the overlap between DRAM and device's IO area.

Signed-off-by: Marek Szyprowski 
---
Changes since RFC:
 - none.
---
 arch/arm/mach-bcm283x/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9966d6c..4295356 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
{
.virt = 0xUL,
.phys = 0xUL,
-   .size = 0xfe00UL,
+   .size = 0xfc00UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 PTE_BLOCK_INNER_SHARE
}, {
-- 
2.7.4

[PATCH v1 02/10] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq

[Sylwester Nawrocki]

There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly.  This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.

This patch fixes operation of the XHCI controller on RPI4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.

Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
xhci_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0xabcd1234abcd1234 instead of 0xabcd1234.

Cc: Sergey Temerkhanov 
Signed-off-by: Sylwester Nawrocki 
---
Changes since RFC:
 - dropped Kconfig option, switched to not using readq/writeq
   unconditionally.
---
 include/usb/xhci.h | 8 
 1 file changed, 8 deletions(-)

diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 6017504..c16106a 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -,28 +,20 @@ static inline void xhci_writel(uint32_t volatile *regs, 
const unsigned int val)
  */
 static inline u64 xhci_readq(__le64 volatile *regs)
 {
-#if BITS_PER_LONG == 64
-   return readq(regs);
-#else
__u32 *ptr = (__u32 *)regs;
u64 val_lo = readl(ptr);
u64 val_hi = readl(ptr + 1);
return val_lo + (val_hi << 32);
-#endif
 }
 
 static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
 {
-#if BITS_PER_LONG == 64
-   writeq(val, regs);
-#else
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
/* FIXME */
u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
-#endif
 }
 
 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
-- 
2.7.4

[PATCH v1 03/10] pci: Move some PCIe register offset definitions to a common header

[Sylwester Nawrocki]

Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Reviewed-by: Bin Meng 
Signed-off-by: Sylwester Nawrocki 
---
Changes since RFC:
 - whitespace clean up.
---
 drivers/pci/pci-rcar-gen3.c   |  8 
 drivers/pci/pcie_intel_fpga.c |  3 ---
 include/pci.h | 13 +++--
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 30eff67..393f1c9 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
 #define RCAR_PCI_MAX_RESOURCES 4
 #define MAX_NR_INBOUND_MAPS6
 
-#define PCI_EXP_FLAGS  2   /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE 0x00f0  /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
-#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x0010  /* Data Link Layer Link Active 
Reporting Capable */
-#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN 0xfff8  /* Physical Slot Number */
-
 enum {
RCAR_PCI_ACCESS_READ,
RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 6a9f29c..69363a0 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -65,9 +65,6 @@
 #define IS_ROOT_PORT(pcie, bdf)\
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
 
-#define PCI_EXP_LNKSTA 18  /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
-
 /**
  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  * @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index 174ddd4..5bf91a4 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
 #define  PCI_EA_FIELD_MASK 0xfffc  /* For Base & Max Offset */
 
 /* PCI Express capabilities */
+#define PCI_EXP_FLAGS  2   /* Capabilities register */
+#define  PCI_EXP_FLAGS_TYPE0x00f0  /* Device/Port type */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
 #define PCI_EXP_DEVCAP 4   /* Device capabilities */
-#define  PCI_EXP_DEVCAP_FLR 0x1000 /* Function Level Reset */
+#define  PCI_EXP_DEVCAP_FLR0x1000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL 8   /* Device Control */
-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
+#define  PCI_EXP_DEVCTL_BCR_FLR0x8000  /* Bridge Configuration Retry / 
FLR */
+#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
+#define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
 
 /* Include the ID list */
 
-- 
2.7.4

[PATCH v1 01/10] usb: xhci: Add missing cache flush in the scratchpad array initialization

[Sylwester Nawrocki]

In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails and there is a timeout while waiting for the command completion
event. After adding the missing cache flush everything seems to be working
as expected.

Reviewed-by: Bin Meng 
Signed-off-by: Sylwester Nawrocki 
---
Changes since RFC:
 - none.
---
 drivers/usb/host/xhci-mem.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 93450ee..729bdc3 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
scratchpad->sp_array[i] = cpu_to_le64(ptr);
}
 
+   xhci_flush_cache((uintptr_t)scratchpad->sp_array,
+sizeof(u64) * num_sp);
+
return 0;
 
 fail_sp3:
-- 
2.7.4

[PATCH v1 00/10] USB host support for Raspberry Pi 4 board

[Sylwester Nawrocki]

Hi all,

This patch series adds USB host support for Raspberry Pi 4 board. 
It includes the Broadcom STB PCIe driver ported from Linux kernel,
a memory mapping update for the xHCI controller behind a PCIe bridge
for 32-bit and 64-bit system builds and some related fixes and updates
in the usb/xhci and the pci core code.

Any changes since previous (RFC) version are listed in individual 
patches.  The most significant change was rewriting the PCIe driver 
to align with current mainline Linux kernel version.  As suggested, 
readq/writeq have been removed from xhci_{readq/writeq} helpers 
instead of adding a Kconfig option.

This patch series is based on v2020.04 tag.

Regards,
Sylwester

Marek Szyprowski (4):
  rpi4: shorten a mapping for the DRAM
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
64bit)
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
32bit)
  config: Enable support for the XHCI controller on RPI4 board

Nicolas Saenz Julienne (1):
  linux/bitfield.h: Add primitives for manipulating bitfields both in
host- and fixed-endian.

Sylwester Nawrocki (5):
  usb: xhci: Add missing cache flush in the scratchpad array
initialization
  usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
  pci: Move some PCIe register offset definitions to a common header
  pci: Add some PCI Express capability register offset definitions
  pci: Add driver for Broadcom STB PCIe controller

 arch/arm/mach-bcm283x/Kconfig |   1 +
 arch/arm/mach-bcm283x/include/mach/base.h |   7 +
 arch/arm/mach-bcm283x/init.c  |  72 +++-
 configs/rpi_4_32b_defconfig   |   9 +
 configs/rpi_4_defconfig   |  10 +
 configs/rpi_arm64_defconfig   |   9 +-
 drivers/pci/Kconfig   |   6 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pci-rcar-gen3.c   |   8 -
 drivers/pci/pcie_brcmstb.c| 593 ++
 drivers/pci/pcie_intel_fpga.c |   3 -
 drivers/usb/host/xhci-mem.c   |   3 +
 include/linux/bitfield.h  |  46 +++
 include/pci.h |  19 +-
 include/usb/xhci.h|   8 -
 15 files changed, 769 insertions(+), 26 deletions(-)
 create mode 100644 drivers/pci/pcie_brcmstb.c

-- 
2.7.4

Re: [RFC PATCH 9/9] config: Enable support for the XHCI controller on RPI4 board

[Sylwester Nawrocki]

On 22.04.2020 14:26, Nicolas Saenz Julienne wrote:
> On Wed, 2020-04-22 at 11:50 +0100, Peter Robinson wrote:

>>> Would you mind enabling USB keyboard support too? It's useful for people
>>> using
>>> u-boot/UEFI.
>>
>> And storage too:
>> CONFIG_USB_STORAGE=y
>> CONFIG_USB_KEYBOARD=y
>>
>> In testing these patches I can see the devices with a "usb tree" but
>> even with the keyboard enabled it doesn't appear to work. AFAICT with
>> it enabled there should be support for usb keyboard via console in
>> include/configs/rpi.h but I couldn't see what else might be missing.
> 
> That's surprising, USB keyboard works fine in my case.

USB keyboard also works well for me (but not the one with a built-in 
touchpad). I could add those 2 additional options to the patch but perhaps 
it's better to leave it as is, i.e. enable PCIe/xHCI in one patch and all 
needed USB devices in another?
  
-- 
Regards,
Sylwester

Re: [RFC PATCH 8/9] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

Hi Nicolas,

On 22.04.2020 11:16, Nicolas Saenz Julienne wrote:
 
> I see that you based your code on the downstream PCIe driver (the one 
> available
> in the Raspberry Pi foundation kernel repos). There's a real upstream version
> of it[1], It's properly reviewed and we made a point to remove all non bcm2711
> specific stuff from it, as support for other platforms (like bcm7445) isn't
> there yet (it depends on supporting multiple dma-ranges in Linux, which we
> don't). Also note that the Raspberry Pi foundation is moving towards using 
> this
> driver, see for example their rpi-5.6.y branch, and I belive Broadcom is doing
> the same.
> 
> So I strongly suggest you base this driver on the upstream version. As I was
> working towards the same goal as you I already have an implementation for
> u-boot myself[2]. Feel free to use that if you find it useful. Ultimately,
> whether you base it on my version or the upstream Linux version it's half the
> size and easier to follow.

Thanks, I'm going to reuse you code, it looks much cleaner.
I started working on this PCIe driver back at end of 2019, then that task was
postponed for few months. I should have been following better related Linux
mainline works. Now, when it all more or less works I will try reuse your code.
> [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-brcmstb.c?h=v5.7-rc2
> [2] 
> https://protect2.fireeye.com/url?k=14361ea6-49a8854c-143795e9-0cc47a6cba04-df90fb3bfec30a2d=1=https%3A%2F%2Fgithub.com%2Fvianpl%2Fu-boot%2Fcommits%2Fbrcm-pcie
> 

-- 
Regards,
Sylwester

Re: [RFC PATCH 7/9] pci: Add some PCI Express capability register offset definitions

[Sylwester Nawrocki]

On 22.04.2020 08:16, Bin Meng wrote:
> On Wed, Apr 22, 2020 at 12:51 AM Sylwester Nawrocki
>  wrote:

>>  #define PCI_EXP_LNKCAP 12  /* Link Capabilities */
>> +#define  PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */
>> +#define  PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */
>>  #define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
>> Active Reporting Capable */
>>
>>  #define PCI_EXP_LNKSTA 18  /* Link Status */
>> +#define  PCI_EXP_LNKSTA_CLS0x000f  /* Current Link Speed */
>> +#define  PCI_EXP_LNKSTA_NLW0x03f0  /* Negotiated Link Width */
>> +#define  PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status 
>> */
>> +
>>  #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
>> +#define PCI_EXP_LNKCTL248  /* Link Control 2 */
> 
> Please put PCI_EXP_LNKCTL2 after PCI_EXP_SLTCAP (sorted in order)

Thanks for pointing this out, will be corrected in next iteration.

>>  #define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
>>  #define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */

--
Regards, 
Sylwester

Re: [RFC PATCH 6/9] usb: xhci: Allow accessing 64-bit registers with DWORD accesses only

[Sylwester Nawrocki]

Hi Bin,

On 22.04.2020 08:00, Bin Meng wrote:
> On Wed, Apr 22, 2020 at 12:51 AM Sylwester Nawrocki
>  wrote:
[...]
>> So far I couldn't come up with anything better to make the xHCI host
>> controller working on the rpi4 board. For some reason dereferencing
>> a 64-bit pointer to access 64-bit registers doesn't work there,
>> might be a limitation of the PCIe bridge behind the SCB. In Linux
>> always 2 double word accesses are used.
> 
> If Linux always uses 2 double word accesses, let's simply do the same
> in U-Boot by removing the readq/writeq.

Thanks for your review. That sounds good to me, I will do it that way
in next iteration.

--
Regards, 
Sylwester

Re: [RFC PATCH 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization

[Sylwester Nawrocki]

Hi Nicolas,

(fixed Simon's email address, apologies for mistyping it, I will make sure
it's correct in next iteration)

On 22.04.2020 10:53, Nicolas Saenz Julienne wrote:
> I've been trying to get this working on my own and got stuck with this 
> specific
> issue. I'm glad you found a solution, it was driving me crazy.
> 
> Out of curiosity how did you found the solution?

It took me many days of debugging...given my nearly non existent previous
experience in u-boot development.In short, it started with a suggestion to map 
all memory for CPU as uncached.
As in such a case booting was failing I checked where the xhci shared buffer
allocation fall and created only a small uncached window to cover those
allocations. This was first thing that started working, after fixing the 
64-bit pointers setup in XHCI registers.
Then I discovered "dcache" command and that was also helpful. It was sufficient 
to run "dcache off; usb start; dcache on". Then USB worked even after "usb 
reset"
IIRC. But that was with my old development branch based on v2019.10-rc4 tag.
Marek tried the same with newer tree and dcache_disable() was not helping,
but dcache_flush_all() was.

By moving dcache_disable(), dcache_enable() around I found out that it was 
sufficient to disable dcache before xhci_start() call and to enable it right 
afterwards.

Then I just "bisected" the uncached memory region which narrowed it roughly 
to the scratchpad buffer allocations. By inspecting the code carefully again
it turned there is one more cache flush call needed.

>> diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
>> index 93450ee..729bdc3 100644
>> --- a/drivers/usb/host/xhci-mem.c
>> +++ b/drivers/usb/host/xhci-mem.c
>> @@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
>>  scratchpad->sp_array[i] = cpu_to_le64(ptr);
>>  }
>>  
>> +xhci_flush_cache((uintptr_t)scratchpad->sp_array,
>> + sizeof(u64) * num_sp);
>> +
> 
> Marek, souldn't running 'dcache off; icache off' be equivalent to this (which
> didn't do the trick for me)? or am I missing somthing?


Regards,
-- 
Sylwester Nawrocki
Samsung R Institute Poland

[RFC PATCH 7/9] pci: Add some PCI Express capability register offset definitions

[Sylwester Nawrocki]

Add PCI Express capability definitions required by the Broadcom STB PCIe
driver.

Signed-off-by: Sylwester Nawrocki 
---
 include/pci.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/pci.h b/include/pci.h
index 3d7646d..2b25a17 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -481,10 +481,17 @@
 #define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 
 #define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_SLS0x000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_MLW0x03f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
 
 #define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_CLS0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_NLW0x03f0  /* Negotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4/* start of NLW mask in link status */
+
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
+#define PCI_EXP_LNKCTL248  /* Link Control 2 */
 
 #define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
-- 
2.7.4

[RFC PATCH 9/9] config: Enable support for the XHCI controller on RPI4 board

[Sylwester Nawrocki]

From: Marek Szyprowski 

This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update his environment if it is
already configured to get this feature working out of the box.

Signed-off-by: Marek Szyprowski 
---
 configs/rpi_4_32b_defconfig |  9 +
 configs/rpi_4_defconfig | 10 ++
 configs/rpi_arm64_defconfig |  9 -
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 72cda5d..0dd763f 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 6d148da..f80e5da 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -28,12 +32,18 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index fea86be..926dfc3 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="usb start"
+CONFIG_PREBOOT="pci enum; usb start;"
 CONFIG_MISC_INIT_R=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_OF_BOARD=y
@@ -26,11 +27,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_DM_ETH=y
 CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y
+CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
-- 
2.7.4

[RFC PATCH 8/9] pci: Add driver for Broadcom STB PCIe controller

[Sylwester Nawrocki]

This patch adds basic driver for the Broadcom STB PCIe host controller.
The code is based on Linux upstream driver (pcie-brcmtsb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and is fixed as a 1:1 mapping of
whole RAM.
The patch has been tested on rpi4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.

Signed-off-by: Sylwester Nawrocki 
---
 drivers/pci/Kconfig|   5 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_brcmstb.c | 844 +
 3 files changed, 850 insertions(+)
 create mode 100644 drivers/pci/pcie_brcmstb.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 437cd9a..02dcc57 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -197,4 +197,9 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable Gen2 PCIe controller,
  which could be found on MT7623 SoC family.
 
+config PCI_BRCMSTB
+   bool "Broadcom STB PCIe controller"
+   depends on DM_PCI
+   help
+ Say Y here if you want to enable PCI controller support on BCM2711 
SoC.
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc..3e53b1f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
new file mode 100644
index 000..e96e163
--- /dev/null
+++ b/drivers/pci/pcie_brcmstb.c
@@ -0,0 +1,844 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB PCIe controller driver
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ * Author: Sylwester Nawrocki 
+ *
+ * Based on upstream Linux kernel driver:
+ *
+ *  drivers/pci/controller/pcie-brcmstb.c
+ *  Copyright (C) 2009 - 2017 Broadcom
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+/*
+ * Broadcom Settop Box PCIe Register Offsets. The names are from
+ * the chip's RDB and we use them here so that a script can correlate
+ * this code and the RDB to prevent discrepancies.
+ */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG10x0188
+#define PCIE_RC_CFG_PRIV1_ID_VAL3  0x043c
+#define PCIE_RC_DL_MDIO_ADDR   0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA0x1108
+#define PCIE_MISC_MISC_CTRL0x4008
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO   0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI   0x4010
+#define PCIE_MISC_RC_BAR1_CONFIG_LO0x402c
+#define PCIE_MISC_RC_BAR2_CONFIG_LO0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_HI0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO0x403c
+#define PCIE_MISC_MSI_BAR_CONFIG_LO0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI0x4048
+#define PCIE_MISC_MSI_DATA_CONFIG  0x404c
+#define PCIE_MISC_EOI_CTRL 0x4060
+#define PCIE_MISC_PCIE_CTRL0x4064
+#define PCIE_MISC_PCIE_STATUS  0x4068
+#define PCIE_MISC_REVISION 0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT   0x4070
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI  0x4080
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
+#define PCIE_INTR2_CPU_BASE0x4300
+#define PCIE_MSI_INTR2_BASE0x4500
+
+/*
+ * Broadcom Settop Box PCIe Register Field shift and mask info. The
+ * names are from the chip's RDB and we use them here so that a script
+ * can correlate this code and the RDB to prevent discrepancies.
+ */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK  0xc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK  0xff
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT0xc
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK  0x2000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
+#define PCIE_MISC_MISC_CTRL_MAX_BURST

[RFC PATCH 5/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff80 CPU virtual address.

Signed-off-by: Marek Szyprowski 
---
 arch/arm/mach-bcm283x/Kconfig |  1 +
 arch/arm/mach-bcm283x/include/mach/base.h |  7 +
 arch/arm/mach-bcm283x/init.c  | 52 +++
 3 files changed, 60 insertions(+)

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 00419bf..bcb7f1d 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+   select PHYS_64BIT
 
 config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h 
b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae398..1d10dc9 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -6,6 +6,13 @@
 #ifndef _BCM283x_BASE_H_
 #define _BCM283x_BASE_H_
 
+#include 
+
 extern unsigned long rpi_bcm283x_base;
 
+#ifdef CONFIG_ARMV7_LPAE
+extern void *rpi4_phys_to_virt(phys_addr_t paddr);
+#define phys_to_virt(x) rpi4_phys_to_virt(x)
+#endif
+
 #endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 6a748da..5d0d160 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -145,6 +145,58 @@ int mach_cpu_init(void)
 }
 
 #ifdef CONFIG_ARMV7_LPAE
+
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT   0xff80UL
+
+void *rpi4_phys_to_virt(phys_addr_t paddr)
+{
+   if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS)
+   paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS +
+   BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT;
+   return (void *)(unsigned long)paddr;
+}
+
+static void set_section_phys(unsigned int section, phys_addr_t phys,
+enum dcache_option option)
+{
+   u64 *page_table = (u64 *)gd->arch.tlb_addr;
+   /* Need to set the access flag to not fault */
+   u64 value = TTB_SECT_AP | TTB_SECT_AF;
+
+   /* Add the page offset */
+   value |= (phys);
+
+   /* Add caching bits */
+   value |= option;
+
+   /* Set PTE */
+   page_table[section] = value;
+}
+
+static void rpi4_create_pcie_xhci_mapping(void)
+{
+   unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT;
+   phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS;
+   unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE;
+
+   while (size) {
+   set_section_phys(sect, phys_addr, DCACHE_OFF);
+   sect++;
+   phys_addr += MMU_SECTION_SIZE;
+   size -= MMU_SECTION_SIZE;
+   }
+}
+
+void arm_init_domains(void)
+{
+   /*
+* Hijack this function to prepare a mappings for the PCIe MMIO
+* region for the XHCI controller on RPi4 board.
+* This code is called before enabling the MMU in ARM 32bit mode.
+*/
+   rpi4_create_pcie_xhci_mapping();
+}
+
 void enable_caches(void)
 {
dcache_enable();
-- 
2.7.4

[RFC PATCH 2/9] pci: Move some PCIe register offset definitions to a common header

[Sylwester Nawrocki]

Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.

Signed-off-by: Sylwester Nawrocki 
---
 drivers/pci/pci-rcar-gen3.c   |  8 
 drivers/pci/pcie_intel_fpga.c |  3 ---
 include/pci.h | 13 +
 3 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 30eff67..393f1c9 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
 #define RCAR_PCI_MAX_RESOURCES 4
 #define MAX_NR_INBOUND_MAPS6
 
-#define PCI_EXP_FLAGS  2   /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE 0x00f0  /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
-#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x0010  /* Data Link Layer Link Active 
Reporting Capable */
-#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN 0xfff8  /* Physical Slot Number */
-
 enum {
RCAR_PCI_ACCESS_READ,
RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 6a9f29c..69363a0 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -65,9 +65,6 @@
 #define IS_ROOT_PORT(pcie, bdf)\
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
 
-#define PCI_EXP_LNKSTA 18  /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
-
 /**
  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  * @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index 174ddd4..3d7646d 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,11 +471,24 @@
 #define  PCI_EA_FIELD_MASK 0xfffc  /* For Base & Max Offset */
 
 /* PCI Express capabilities */
+#define PCI_EXP_FLAGS  2   /* Capabilities register */
+#define PCI_EXP_FLAGS_TYPE 0x00f0  /* Device/Port type */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
+
 #define PCI_EXP_DEVCAP 4   /* Device capabilities */
 #define  PCI_EXP_DEVCAP_FLR 0x1000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL 8   /* Device Control */
 #define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 
+#define PCI_EXP_LNKCAP 12  /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_DLLLARC0x0010 /* Data Link Layer Link 
Active Reporting Capable */
+
+#define PCI_EXP_LNKSTA 18  /* Link Status */
+#define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
+
+#define PCI_EXP_SLTCAP 20  /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */
+
 /* Include the ID list */
 
 #include 
-- 
2.7.4

[RFC PATCH 6/9] usb: xhci: Allow accessing 64-bit registers with DWORD accesses only

[Sylwester Nawrocki]

This patch adds a Kconfig option which allows accessing 64-bit xHCI
IO registers only with 2 double word accesses rather than using
a single quad word access. There might be HW configurations where
single quad word access doesn't work, even though the CPU is 64-bit.
That seems to be the case on rpi4 board with Broadcom BCM2711 SoC,
where the VL805 USB xHCI hub is connected to the PCIe controller
behind the SCB bridge.

Signed-off-by: Sylwester Nawrocki 
---
So far I couldn't come up with anything better to make the xHCI host
controller working on the rpi4 board. For some reason dereferencing
a 64-bit pointer to access 64-bit registers doesn't work there,
might be a limitation of the PCIe bridge behind the SCB. In Linux
always 2 double word accesses are used.
---
 drivers/usb/host/Kconfig | 7 +++
 include/usb/xhci.h   | 4 ++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0987ff2..3990b8a 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -15,6 +15,13 @@ config USB_XHCI_HCD
 
 if USB_XHCI_HCD
 
+config XHCI_64BIT_DWORD_ACCESS_ONLY
+   bool "Access xHCI 64-bit registers with double word accesses only"
+   help
+ Choose this option if your hardware does not support quad word 
accesses
+ for registers with 64-bit address pointers.
+ If unsure, say Y.
+
 config USB_XHCI_DWC3
bool "DesignWare USB3 DRD Core Support"
help
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 6017504..459e76b 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -,7 +,7 @@ static inline void xhci_writel(uint32_t volatile *regs, 
const unsigned int val)
  */
 static inline u64 xhci_readq(__le64 volatile *regs)
 {
-#if BITS_PER_LONG == 64
+#if BITS_PER_LONG == 64 && !defined(CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY)
return readq(regs);
 #else
__u32 *ptr = (__u32 *)regs;
@@ -1123,7 +1123,7 @@ static inline u64 xhci_readq(__le64 volatile *regs)
 
 static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
 {
-#if BITS_PER_LONG == 64
+#if BITS_PER_LONG == 64 && !defined(CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY)
writeq(val, regs);
 #else
__u32 *ptr = (__u32 *)regs;
-- 
2.7.4

[RFC PATCH 4/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)

[Sylwester Nawrocki]

From: Marek Szyprowski 

Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.

Signed-off-by: Marek Szyprowski 
---
 arch/arm/mach-bcm283x/init.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 4295356..6a748da 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,10 +11,15 @@
 #include 
 #include 
 
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS   0x6UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE   0x80UL
+
 #ifdef CONFIG_ARM64
 #include 
 
-static struct mm_region bcm283x_mem_map[] = {
+#define MAX_MAP_MAX_ENTRIES (4)
+
+static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
 };
 
-static struct mm_region bcm2711_mem_map[] = {
+static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0xUL,
.phys = 0xUL,
@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
 PTE_BLOCK_NON_SHARE |
 PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
+   .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+   .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+   }, {
/* List terminator */
0,
}
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
 {
int i;
 
-   for (i = 0; i < 2; i++) {
+   for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;
-- 
2.7.4

[RFC PATCH 3/9] rpi4: shorten a mapping for the DRAM

[Sylwester Nawrocki]

From: Marek Szyprowski 

Remove the overlap between DRAM and device's IO area.

Signed-off-by: Marek Szyprowski 
---
 arch/arm/mach-bcm283x/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9966d6c..4295356 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
{
.virt = 0xUL,
.phys = 0xUL,
-   .size = 0xfe00UL,
+   .size = 0xfc00UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 PTE_BLOCK_INNER_SHARE
}, {
-- 
2.7.4

[RFC PATCH 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization

[Sylwester Nawrocki]

In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails and there is a timeout while waiting for the command completion
event. After adding the missing cache flush everything seems to be working
as expected.

Signed-off-by: Sylwester Nawrocki 
---
 drivers/usb/host/xhci-mem.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 93450ee..729bdc3 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
scratchpad->sp_array[i] = cpu_to_le64(ptr);
}
 
+   xhci_flush_cache((uintptr_t)scratchpad->sp_array,
+sizeof(u64) * num_sp);
+
return 0;
 
 fail_sp3:
-- 
2.7.4

[RFC PATCH 0/9] USB host support for Raspberry Pi 4 board

[Sylwester Nawrocki]

Hi all,

This patch series adds USB host support for Raspberry Pi 4 board. 
It includes the Broadcom STB PCIe driver ported from Linux kernel,
a memory mapping update for the xHCI controller behind the PCIe bridge
for 32-bit and 64-bit system builds and some related fixes and updates
in the usb/xhci and the pci driver core code.

One of the issues I run into with RPI4 was not working accesses to 
64-bit xHCI IO registers with readq/writeq.  I am not entirely sure 
if that limitation comes from the VL805 USB host controller or from the
BCM2711 PCI Express Root Complex, or if it's a matter of some missing 
configuration steps for one of these devices.
In Linux kernel quad word accesses for 64-bit xHCI registers are never
used, the best I could come up with so far is a Kconfig option which 
allows to disable readq/writeq for selected target.  Any suggestions 
on how to better solve this are appreciated.

This patch series is based on v2020.04 tag.

Regards,
Sylwester


Marek Szyprowski (4):
  rpi4: shorten a mapping for the DRAM
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
64bit)
  rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
32bit)
  config: Enable support for the XHCI controller on RPI4 board

Sylwester Nawrocki (5):
  usb: xhci: Add missing cache flush in the scratchpad array
initialization
  pci: Move some PCIe register offset definitions to a common header
  usb: xhci: Allow accessing 64-bit registers with DWORD accesses only
  pci: Add some PCI Express capability register offset definitions
  pci: Add driver for Broadcom STB PCIe controller

 arch/arm/mach-bcm283x/Kconfig |   1 +
 arch/arm/mach-bcm283x/include/mach/base.h |   7 +
 arch/arm/mach-bcm283x/init.c  |  72 ++-
 configs/rpi_4_32b_defconfig   |   9 +
 configs/rpi_4_defconfig   |  10 +
 configs/rpi_arm64_defconfig   |   9 +-
 drivers/pci/Kconfig   |   5 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pci-rcar-gen3.c   |   8 -
 drivers/pci/pcie_brcmstb.c| 844 ++
 drivers/pci/pcie_intel_fpga.c |   3 -
 drivers/usb/host/Kconfig  |   7 +
 drivers/usb/host/xhci-mem.c   |   3 +
 include/pci.h |  20 +
 include/usb/xhci.h|   4 +-
 15 files changed, 985 insertions(+), 18 deletions(-)
 create mode 100644 drivers/pci/pcie_brcmstb.c

-- 
2.7.4