Freescale ARM-based Layerscape LS2080A contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds and ls2080ardb boards.
Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
---
depends on p
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
-off-by: Tang Yuantian <yuantian.t...@freescale.com>
---
board/freescale/common/arm_sleep.c | 4
board/freescale/ls1021atwr/ls1021atwr.c | 19 +--
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/board/freescale/common/arm_sleep.c
b/board/freescale/
.
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
common/cmd_scsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index a0a62eb..f80f549 100644
--- a/common/cmd_scsi.c
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t102xqds/ddr.c | 19 +++
board/freescale/t102xqds/t102xqds.c | 23
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/ddr.c | 19 +++
board/freescale/t1040qds/t1040qds.c | 23
All the boards that support deep sleep feature are converted
to deep sleep generic board interface. The old interface which
support non-generic board is not used anymore. So clean it up.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10
Add deep sleep support on Freescale LS1021QDS platform.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
based on: u-boot-fsl-qoriq master.
depends on patch: http://patchwork.ozlabs.org/patch/420999/
which is applied to u-boot-mpc85xx master, awaiting upstream.
v2:
- added sd
referring gic_dist_addr.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- change variable gic_dist_addr back as local
arch/arm/cpu/armv7/virt-v7.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Besides, added SPI/SD/NAND boot deep sleep support.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t102xrdb/ddr.c | 19 +++
board
There are 8 SCFG_SPARECR registers in SCFG memory block, not
just one.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa
Defining variable gic_dist_addr as a globe one prevents some
functions, which use this variable, from being used before relocation
which happened in the deep sleep resume process on Freescale SoC
platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/arm/cpu/armv7/virt-v7.c
referring gic_dist_addr.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- refine the subjuct and commit message.
arch/arm/cpu/armv7/virt-v7.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
From: Tang Yuantian yuantian.t...@freescale.com
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them
From: Tang Yuantian yuantian.t...@freescale.com
T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board
From: Tang Yuantian yuantian.t...@freescale.com
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T1040QDS platform.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/t1040qds.c | 12
include/configs/T1040QDS.h | 4
2 files changed, 16 insertions(+)
diff
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T104xRDB platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t104xrdb/t104xrdb.c | 10 ++
include/configs/T104xRDB.h | 4
2 files changed, 14 insertions(+)
diff
From: Tang Yuantian yuantian.t...@freescale.com
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers
From: Tang Yuantian yuantian.t...@freescale.com
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed
On 2014/2/25 星期二 3:11, Scott Wood wrote:
Why what? Why we need it?
It is a help function and used by ASM code in which
we can't determine whether it is a warm reset boot.
Why don't you just open code it?
I can't check the warmboot status in ASM code.
In order to get the warmboot status in
On 2014/2/25 星期二 3:11, Scott Wood wrote:
On Mon, 2014-02-24 at 14:44 +0800, Tang Yuantian-B29983 wrote:
On 2014/2/18 星期二 3:18, Scott Wood wrote:
On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote:
-Original Message-
From: Wood Scott-B07421
To: Tang Yuantian-B29983
Cc: Sun
On 2014/2/25 星期二 3:11, Scott Wood wrote:
On Mon, 2014-02-24 at 15:47 +0800, Tang Yuantian-B29983 wrote:
On 2014/2/15 星期六 6:21, Scott Wood wrote:
On Thu, 2014-02-13 at 01:05 -0600, Tang Yuantian-B29983 wrote:
Thanks for your review. Please see the reply inline.
Thanks,
Yuantian
On 2014/2/18 星期二 3:18, Scott Wood wrote:
On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote:
-Original Message-
From: Wood Scott-B07421
To: Tang Yuantian-B29983
Cc: Sun York-R58495; Li Yang-Leo-R58472; u-boot@lists.denx.de; Kushwaha
Prabhakar-B32579; Jin Zhengxiong-R64188
On 2014/2/15 星期六 6:21, Scott Wood wrote:
On Thu, 2014-02-13 at 01:05 -0600, Tang Yuantian-B29983 wrote:
Thanks for your review. Please see the reply inline.
Thanks,
Yuantian
-Original Message-
From: Wood Scott-B07421
Sent: 2014年2月13日 星期四 8:44
To: Tang Yuantian-B29983
Cc: Sun York
test.
于 2014/2/15 星期六 6:59, Scott Wood 写道:
On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote:
Use an I/O accessor.
In_be64?? No such function.
Why do you need in_be64() rather than two in_be32()s?
-Scott
___
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From: Tang Yuantian yuantian.t...@freescale.com
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T1040QDS platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/t1040qds.c | 12
include/configs/T1040QDS.h | 4
2 files changed, 16 insertions
From: Tang Yuantian yuantian.t...@freescale.com
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers
From: Tang Yuantian yuantian.t...@freescale.com
When system wakes up from warm reset, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T1040QDS platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/t1040qds.c | 12
include/configs/T1040QDS.h | 4
2 files changed, 16 insertions
Hi York,
I double checked the offset address of GPIO, I found that the offset
addresses of GPIO on the boards you mentioned above are all changed to
0x0, not 0xc00 according to the newest RM.
I do found that the offset address is 0xc00 in some old RMs.
You can find the newest RM
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h
b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 3d11884..87bb4a0 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
static inline void mpc85xx_gpio_set(unsigned int
From: Tang Yuantian yuantian.t...@freescale.com
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR, no reason to add 0xc00.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/include/asm/mpc85xx_gpio.h | 4 ++--
1 file changed, 2
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