[U-Boot] [PATCH v3] arm: ls2080a: Add sata support on qds and rdb board
Freescale ARM-based Layerscape LS2080A contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds and ls2080ardb boards.
Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
---
depends on patches:
http://patchwork.ozlabs.org/patch/530576/
armv8: LS2080A: Rename LS2085A to reflect LS2080A
http://patchwork.ozlabs.org/patch/530575/
armv8: ls2085a: Add support of LS2085A SoC
v3:
- rename ls2085a to ls2080a
- rebase to the latest git tree
- replace the magic number with micro variable
v2:
- rebase to the latest git tree
arch/arm/cpu/armv8/fsl-lsch3/soc.c| 36 +++
arch/arm/include/asm/arch-fsl-lsch3/config.h | 20 +
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 25
arch/arm/include/asm/arch-fsl-lsch3/soc.h | 3 ++
board/freescale/ls2080aqds/ls2080aqds.c | 11 +++
board/freescale/ls2080ardb/ls2080ardb.c | 11 +++
6 files changed, 106 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 2538001..4f9489e 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -11,6 +11,9 @@
#include
#include
#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -78,6 +81,39 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
}
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int ls2080a_sata_init(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_ahci __iomem *ahci_base;
+ u32 cfg;
+ int rc = -1;
+
+ ahci_base = (void __iomem *)CONFIG_SYS_SATA2;
+ out_le32(_base->ppcfg, AHCI_PORT_PHY_1_CFG);
+
+ ahci_base = (void __iomem *)CONFIG_SYS_SATA1;
+ out_le32(_base->ppcfg, AHCI_PORT_PHY_1_CFG);
+
+ cfg = in_le32(>rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ if ((cfg != 0x41) && (cfg != 0x42) && (cfg != 0x43) &&
+ (cfg != 0x44) && (cfg != 0x49) && (cfg != 0x4A)) {
+ printf("SATA disabled: serdes protocol doesn't support\n");
+ return rc;
+ }
+
+ rc = ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+ if (rc)
+ return rc;
+
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 0733852..1616bea 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -68,6 +68,26 @@
#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210)
#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x0211)
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + 0x0220)
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + 0x0221)
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x0220
#define TZPCR0SIZE_BASE(TZPC_BASE)
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index 941f99a..ce04018 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -182,4 +182,29 @@ struct ccsr_reset {
u32 ip_rev1;/* 0xbf8 */
u32 ip_rev2;/* 0xbfc */
};
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+ u32 pcfg; /* port config */
+ u32 ppcfg; /* port phy1 config */
+ u32 pp2c; /* port phy2 config */
+ u32 pp3c; /* port phy3 config */
+ u32 pp4c; /* port phy4 config */
+ u32 pp5c; /* port phy5 config */
+ u32 axicc; /* AXI cache control */
+ u32 paxic; /* port AXI config */
+ u32 axipc; /* AXI PROT control */
+ u32 ptc;/* port Trans Config */
+ u32 pts;/* port Trans Status */
+ u32 plc;/* port link config */
+ u32 plc1;
[U-Boot] [PATCH v3] arm: ls1021a: Add sata support on qds and twr board
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
---
v3:
- refactor the framework
- replace hard coding with MICRO
v2:
- rebase to latest git tree
- use micro SATA_ECC_REG_ADDR instead of hard coding
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 42 +++
arch/arm/include/asm/arch-ls102xa/config.h| 15
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +
arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h | 11 ++
board/freescale/ls1021aqds/ls1021aqds.c | 12 +++
board/freescale/ls1021atwr/ls1021atwr.c | 12 +++
7 files changed, 117 insertions(+)
create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2d55782..2311468 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -9,6 +9,7 @@ obj-y += clock.o
obj-y += timer.o
obj-y += fsl_epu.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
new file mode 100644
index 000..deeb674
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+#include
+#include
+
+/* port register default value */
+#define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY_2_CFG0x28183411
+#define AHCI_PORT_PHY_3_CFG0x0e081004
+#define AHCI_PORT_PHY_4_CFG0x00480811
+#define AHCI_PORT_PHY_5_CFG0x192c96a4
+#define AHCI_PORT_TRANS_CFG0x0825
+
+#define SATA_ECC_REG_ADDR 0x20220520
+#define SATA_ECC_DISABLE 0x0002
+
+int ls1021a_sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+ out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
+
+ out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+ out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+ out_le32(_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
+ out_le32(_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
+ out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)AHCI_BASE_ADDR);
+ scsi_scan(0);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index bcaf7bf..f066480 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,6 +79,21 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
CONFIG_SYS_PCIE2_VIRT_ADDR)
+/* SATA */
+#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220)
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_ERRATUM_A008407
+
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 60aa0d3..5e49703 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -397,4 +397,28 @@ struct ccsr_cci400 {
u8 res_e004[0x1 - 0xe004];
};
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+ u32 pcfg; /* port config */
+ u32 ppcfg; /* port phy1 config */
+ u32 pp2c; /* port phy2 config */
+ u32 pp3c; /* port phy3 config */
+ u32 pp4c; /* port phy4 config */
+ u32 pp5c; /* port phy5 config */
+ u32 paxic; /* port AXI config */
+ u32 axicc; /* AXI cache control */
+ u32 axipc; /* AXI PROT control */
+ u32 ptc;/* port Trans Config */
+ u32 pts;/* port Trans S
[U-Boot] [PATCH] arm: ls1021atwr: optimize the deep sleep latency
It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot
Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
---
board/freescale/common/arm_sleep.c | 4
board/freescale/ls1021atwr/ls1021atwr.c | 19 +--
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/board/freescale/common/arm_sleep.c
b/board/freescale/common/arm_sleep.c
index 8e8b7fa..a498c65 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -12,7 +12,6 @@
#include
#endif
#include
-#include
#if defined(CONFIG_LS102XA)
#include
@@ -65,8 +64,6 @@ static void dp_ddr_restore(void)
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst++ = *src++;
-
- flush_dcache_all();
}
static void dp_resume_prepare(void)
@@ -74,7 +71,6 @@ static void dp_resume_prepare(void)
dp_ddr_restore();
board_sleep_prepare();
armv7_init_nonsec();
- cleanup_before_linux();
#ifdef CONFIG_U_QE
u_qe_resume();
#endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 228dbf8..236376b 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -521,8 +521,10 @@ int board_early_init_f(void)
}
#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
+ if (is_warm_boot()) {
+ timer_init();
+ dram_init();
+ }
#endif
return 0;
@@ -531,6 +533,8 @@ int board_early_init_f(void)
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
+ void (*second_uboot)(void);
+
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -551,6 +555,17 @@ void board_init_f(ulong dummy)
enable_devices_ns_access(_dev[7], 1);
#endif
+ /*
+* if it is woken up from deep sleep, then jump to second
+* stage uboot and continue executing without recopying
+* it from SD since it has already been reserved in memeory
+* in last boot.
+*/
+ if (is_warm_boot()) {
+ second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+ second_uboot();
+ }
+
board_init_r(NULL, 0);
}
#endif
--
2.1.0.27.g96db324
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[U-Boot] [PATCH] cmd_scsi: Enable SoC AHCI device on platforms with PCI
Current driver assumes the AHCI is connected to PCI, this is not
true on some SoCs, e.g. LS1021A, which has PCI but the AHCI is
in SoC. This patch will enable embedded AHCI devices on platforms
with PCI.
PCI AHCI devices still can be used by commenting CONFIG_SCSI_AHCI_PLAT
option in head file.
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
common/cmd_scsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index a0a62eb..f80f549 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -37,7 +37,7 @@
#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
#endif
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) !defined(CONFIG_SCSI_AHCI_PLAT)
const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
#endif
static ccb tempccb;/* temporary scsi command buffer */
@@ -179,7 +179,7 @@ int scsi_get_disk_count(void)
return scsi_max_devs;
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) !defined(CONFIG_SCSI_AHCI_PLAT)
void scsi_init(void)
{
int busdevfunc;
--
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[U-Boot] [PATCH] mpc85xx/t102xqds: convert deep sleep to generic board interface
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t102xqds/ddr.c | 19 +++
board/freescale/t102xqds/t102xqds.c | 23 +++
include/configs/T102xQDS.h | 3 +++
3 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 46fc64e..2d4d10f 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -11,6 +11,7 @@
#include fsl_ddr_sdram.h
#include fsl_ddr_dimm_params.h
#include asm/fsl_law.h
+#include asm/mpc85xx_gpio.h
DECLARE_GLOBAL_DATA_PTR;
@@ -152,6 +153,19 @@ found:
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -166,5 +180,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t102xqds/t102xqds.c
b/board/freescale/t102xqds/t102xqds.c
index f3141b5..708afca 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -19,10 +19,10 @@
#include asm/fsl_liodn.h
#include fm_eth.h
#include hwconfig.h
-#include asm/mpc85xx_gpio.h
#include ../common/qixis.h
#include t102xqds.h
#include t102xqds_qixis.h
+#include ../common/sleep.h
DECLARE_GLOBAL_DATA_PTR;
@@ -242,6 +242,16 @@ void board_retimer_ds125df111_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, reg, 1);
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -395,14 +405,3 @@ void qixis_dump_switch(void)
printf(SW%d = (0x%02x)\n, i, QIXIS_READ(cms[1]));
}
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) ~0x2));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index c2bdbb9..3f02ced 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -35,7 +35,10 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
--
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[U-Boot] [PATCH] mpc85xx/t1040qds: convert deep sleep to generic board interface
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/ddr.c | 19 +++
board/freescale/t1040qds/t1040qds.c | 23 +++
include/configs/T1040QDS.h | 3 +++
3 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 43f952f..8240240 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -11,6 +11,7 @@
#include fsl_ddr_sdram.h
#include fsl_ddr_dimm_params.h
#include asm/fsl_law.h
+#include asm/mpc85xx_gpio.h
#include ddr.h
DECLARE_GLOBAL_DATA_PTR;
@@ -100,6 +101,19 @@ found:
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -112,5 +126,10 @@ phys_size_t initdram(int board_type)
dram_size *= 0x10;
puts(DDR: );
+
+#if defined(CONFIG_DEEP_SLEEP) !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t1040qds/t1040qds.c
b/board/freescale/t1040qds/t1040qds.c
index 13285be..eaca57f 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -19,8 +19,8 @@
#include asm/fsl_liodn.h
#include fm_eth.h
#include hwconfig.h
-#include asm/mpc85xx_gpio.h
+#include ../common/sleep.h
#include ../common/qixis.h
#include t1040qds.h
#include t1040qds_qixis.h
@@ -115,6 +115,16 @@ static void qe_board_setup(void)
}
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -281,14 +291,3 @@ int board_need_mem_reset(void)
{
return 1;
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) ~0x2));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index b70bdfe..5ebc870 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -47,7 +47,10 @@
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff4
--
2.1.0.27.g96db324
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[U-Boot] [PATCH] mpc85xx: clean up the old deep sleep framework
All the boards that support deep sleep feature are converted
to deep sleep generic board interface. The old interface which
support non-generic board is not used anymore. So clean it up.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 +-
arch/powerpc/lib/board.c| 21 -
2 files changed, 1 insertion(+), 30 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 85d32fc..4cf8853 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -424,7 +424,6 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
- ulong flag = 0;
extern void m8560_cpm_reset (void);
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) defined(CONFIG_FSL_CORENET))
@@ -499,18 +498,11 @@ ulong cpu_init_f(void)
in_be32(gur-dcsrcr);
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-#ifdef CONFIG_DEEP_SLEEP
- /* disable the console if boot from deep sleep */
- if (in_be32(gur-scrtsr[0]) (1 3))
- flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#endif
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
- return flag;
+ return 0;
}
/* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index e6d5355..91645d3 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -346,13 +346,6 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM
ulong reg;
#endif
-#ifdef CONFIG_DEEP_SLEEP
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
- u32 start_addr;
- typedef void (*func_t)(void);
- func_t kernel_resume;
-#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -372,20 +365,6 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0)
hang();
-#ifdef CONFIG_DEEP_SLEEP
- /* Jump to kernel in deep sleep case */
- if (in_be32(gur-scrtsr[0]) (1 3)) {
- l2cache_init();
-#if defined(CONFIG_RAMBOOT_PBL)
- disable_cpc_sram();
-#endif
- enable_cpc();
- start_addr = in_be32(scfg-sparecr[1]);
- kernel_resume = (func_t)start_addr;
- kernel_resume();
- }
-#endif
-
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
--
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[U-Boot] [PATCH v2 2/2] fsl/ls1021qds: Add deep sleep support
Add deep sleep support on Freescale LS1021QDS platform.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
based on: u-boot-fsl-qoriq master.
depends on patch: http://patchwork.ozlabs.org/patch/420999/
which is applied to u-boot-mpc85xx master, awaiting upstream.
v2:
- added sd boot deep sleep support
arch/arm/cpu/armv7/ls102xa/fdt.c| 19 +++
board/freescale/ls1021aqds/ddr.c| 17 +
board/freescale/ls1021aqds/ls1021aqds.c | 26 ++
include/configs/ls1021aqds.h| 8 +++-
4 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 989780d..4f226e9 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -133,4 +133,23 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, fsl, ls1021a-flexcan,
clock-frequency, busclk / 2, 1);
+
+#if defined(CONFIG_DEEP_SLEEP) defined(CONFIG_SD_BOOT)
+#define UBOOT_HEAD_LEN 0x1000
+ /*
+* Reserved memory in SD boot deep sleep case.
+* Second stage uboot binary and malloc space should be reserved.
+* If the memory they occupied has not been reserved, then this
+* space would be used by kernel and overwritten in uboot when
+* deep sleep resume, which cause deep sleep failed.
+* Since second uboot binary has a head, that space need to be
+* reserved either(assuming its size is less than 0x1000).
+*/
+ off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
+ CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
+ UBOOT_HEAD_LEN);
+ if (off 0)
+ printf(Failed to reserve memory for SD boot deep sleep: %s\n,
+ fdt_strerror(off));
+#endif
}
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index a539ff9..6435bf9 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -7,6 +7,7 @@
#include common.h
#include fsl_ddr_sdram.h
#include fsl_ddr_dimm_params.h
+#include asm/io.h
#include ddr.h
DECLARE_GLOBAL_DATA_PTR;
@@ -149,6 +150,17 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
}
#endif
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -159,6 +171,11 @@ phys_size_t initdram(int board_type)
#else
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index f08e54f..97da47d 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -20,6 +20,7 @@
#include fsl_sec.h
#include spl.h
+#include ../common/sleep.h
#include ../common/qixis.h
#include ls1021aqds_qixis.h
#ifdef CONFIG_U_QE
@@ -195,6 +196,11 @@ int board_early_init_f(void)
* allow barrier transaction to DDR again */
out_le32(cci-ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
return 0;
}
@@ -231,6 +237,11 @@ void board_init_f(ulong dummy)
get_clocks();
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
@@ -503,6 +514,21 @@ int board_init(void)
return 0;
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to
+* enable barrier transaction */
+ out_le32(cci-ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 8dc04f2..4b434ad 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -19,6 +19,11 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
+#define CONFIG_SILENT_CONSOLE
+#endif
+
/*
* Size of malloc() pool
*/
@@ -72,7 +77,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SPL_PAD_TO 0x1c000
#define CONFIG_SYS_TEXT_BASE 0x8200
[U-Boot] [PATCH v2 1/2] ARM: HYP/non-sec: Make variable gic_dist_addr as a local one
Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- change variable gic_dist_addr back as local
arch/arm/cpu/armv7/virt-v7.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 651ca40..b69fd37 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -15,8 +15,6 @@
#include asm/io.h
#include asm/secure.h
-unsigned long gic_dist_addr;
-
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long gicdaddr)
void __weak smp_kick_all_cpus(void)
{
+ unsigned long gic_dist_addr;
+
+ gic_dist_addr = get_gicd_base_address();
+ if (gic_dist_addr == -1)
+ return;
+
kick_secondary_cpus_gic(gic_dist_addr);
}
@@ -75,6 +79,7 @@ int armv7_init_nonsec(void)
{
unsigned int reg;
unsigned itlinesnr, i;
+ unsigned long gic_dist_addr;
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
--
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[U-Boot] [PATCH] mpc85xx/t102xrdb: convert deep sleep to generic board interface
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Besides, added SPI/SD/NAND boot deep sleep support.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t102xrdb/ddr.c | 19 +++
board/freescale/t102xrdb/spl.c | 7 +++
board/freescale/t102xrdb/t102xrdb.c | 23 +++
include/configs/T102xRDB.h | 21 -
4 files changed, 49 insertions(+), 21 deletions(-)
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a20330b..a2a8f4c 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -11,6 +11,7 @@
#include fsl_ddr_sdram.h
#include fsl_ddr_dimm_params.h
#include asm/fsl_law.h
+#include asm/mpc85xx_gpio.h
DECLARE_GLOBAL_DATA_PTR;
@@ -136,6 +137,19 @@ found:
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(cpld_base + 0x17, 0x40);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -150,5 +164,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index dd2dec4..1a3a996 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -11,6 +11,7 @@
#include mmc.h
#include fsl_esdhc.h
#include spi_flash.h
+#include ../common/sleep.h
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,12 @@ void board_init_f(ulong bootflag)
console_init_f();
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(gur-rcwsr[0]) 25) 0x1f;
diff --git a/board/freescale/t102xrdb/t102xrdb.c
b/board/freescale/t102xrdb/t102xrdb.c
index f5c438d..96457cf 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -16,10 +16,10 @@
#include asm/fsl_serdes.h
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
-#include asm/mpc85xx_gpio.h
#include fm_eth.h
#include t102xrdb.h
#include cpld.h
+#include ../common/sleep.h
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +55,16 @@ int checkboard(void)
return 0;
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -131,14 +141,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) ~0x40));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 82b669b..e6222f3 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -36,7 +36,10 @@
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
@@ -51,7 +54,7 @@
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_FSL_LAW /* Use common FSL init code */
-#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x4
#define CONFIG_SPL_MAX_SIZE0x28000
@@ -67,21 +70,21 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE(768 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x0020
-#define CONFIG_SYS_NAND_U_BOOT_START 0x0020
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x3000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x3000
#define CONFIG_SYS_NAND_U_BOOT_OFFS(256 10)
#define CONFIG_SYS_LDSCRIPTarch/powerpc/cpu/mpc85xx/u-boot-nand.lds
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS0x200FFC
+#define CONFIG_RESET_VECTOR_ADDRESS0x3FFC
#define CONFIG_SPL_SPI_SUPPORT
#define
[U-Boot] [PATCH] arm: ls102xa: Fixed a register definition error
There are 8 SCFG_SPARECR registers in SCFG memory block, not
just one.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b5db720 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,7 +182,7 @@ struct ccsr_scfg {
u32 etsecmcr;
u32 sdhciovserlcr;
u32 resv14[61];
- u32 sparecr;
+ u32 sparecr[8];
};
/* Clocking */
--
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[U-Boot] [PATCH] ARM: HYP/non-sec: Make a variable as a local one
Defining variable gic_dist_addr as a globe one prevents some
functions, which use this variable, from being used before relocation
which happened in the deep sleep resume process on Freescale SoC
platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/arm/cpu/armv7/virt-v7.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 651ca40..b69fd37 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -15,8 +15,6 @@
#include asm/io.h
#include asm/secure.h
-unsigned long gic_dist_addr;
-
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long gicdaddr)
void __weak smp_kick_all_cpus(void)
{
+ unsigned long gic_dist_addr;
+
+ gic_dist_addr = get_gicd_base_address();
+ if (gic_dist_addr == -1)
+ return;
+
kick_secondary_cpus_gic(gic_dist_addr);
}
@@ -75,6 +79,7 @@ int armv7_init_nonsec(void)
{
unsigned int reg;
unsigned itlinesnr, i;
+ unsigned long gic_dist_addr;
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
--
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[U-Boot] [PATCH v2] ARM: HYP/non-sec: Make variable gic_dist_addr as a local one
Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- refine the subjuct and commit message.
arch/arm/cpu/armv7/virt-v7.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 651ca40..b69fd37 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -15,8 +15,6 @@
#include asm/io.h
#include asm/secure.h
-unsigned long gic_dist_addr;
-
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long gicdaddr)
void __weak smp_kick_all_cpus(void)
{
+ unsigned long gic_dist_addr;
+
+ gic_dist_addr = get_gicd_base_address();
+ if (gic_dist_addr == -1)
+ return;
+
kick_secondary_cpus_gic(gic_dist_addr);
}
@@ -75,6 +79,7 @@ int armv7_init_nonsec(void)
{
unsigned int reg;
unsigned itlinesnr, i;
+ unsigned long gic_dist_addr;
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
--
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[U-Boot] [PATCH] mpc85xx/t104x: Enable L2 and CPC cache when resume
From: Tang Yuantian yuantian.t...@freescale.com
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
based on u-boot-mpc85xx.
there are some warning in exsiting code, so they are in this patch.
I like to address it if needed in following patch.
arch/powerpc/cpu/mpc85xx/cpu_init.c | 163 +++-
arch/powerpc/include/asm/cache.h| 6 ++
arch/powerpc/lib/board.c| 5 ++
3 files changed, 98 insertions(+), 76 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 78316a6..55f0bc7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -200,7 +200,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
#ifdef CONFIG_SYS_FSL_CPC
#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
-static void disable_cpc_sram(void)
+void disable_cpc_sram(void)
{
int i;
@@ -251,7 +251,7 @@ static void enable_tdm_law(void)
}
#endif
-static void enable_cpc(void)
+void enable_cpc(void)
{
int i;
u32 size = 0;
@@ -306,6 +306,7 @@ static void invalidate_cpc(void)
#else
#define enable_cpc()
#define invalidate_cpc()
+#define disable_cpc_sram()
#endif /* CONFIG_SYS_FSL_CPC */
/*
@@ -545,88 +546,15 @@ int enable_cluster_l2(void)
/*
* Initialize L2 as cache.
- *
- * The newer 8548, etc, parts have twice as much cache, but
- * use the same bit-encoding as the older 8555, etc, parts.
- *
*/
-int cpu_init_r(void)
+int l2cache_init(void)
{
__maybe_unused u32 svr = get_svr();
-#ifdef CONFIG_SYS_LBC_LCRR
- fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
-#endif
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) defined(CONFIG_E6500)
struct ccsr_cluster_l2 * l2cache = (void __iomem
*)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
-#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) defined(CONFIG_MP)
- extern int spin_table_compat;
- const char *spin;
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
- ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
-#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
- defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
- /*
-* CPU22 and NMG_CPU_A011 share the same workaround.
-* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
-* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
-* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
-* fixed in 2.0. NMG_CPU_A011 is activated by default and can
-* be disabled by hwconfig with syntax:
-*
-* fsl_cpu_a011:disable
-*/
- extern int enable_cpu_a011_workaround;
-#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
- enable_cpu_a011_workaround = (SVR_MAJ(svr) 3);
-#else
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
- int n, res;
-
- n = getenv_f(hwconfig, buffer, sizeof(buffer));
- if (n 0)
- buf = buffer;
-
- res = hwconfig_arg_cmp_f(fsl_cpu_a011, disable, buf);
- if (res 0)
- enable_cpu_a011_workaround = 0;
- else {
- if (n = HWCONFIG_BUFFER_SIZE) {
- printf(fsl_cpu_a011 was not found. hwconfig variable
- may be too long\n);
- }
- enable_cpu_a011_workaround =
- (SVR_SOC_VER(svr) == SVR_P4080 SVR_MAJ(svr) 3) ||
- (SVR_SOC_VER(svr) != SVR_P4080 SVR_MAJ(svr) 2);
- }
-#endif
- if (enable_cpu_a011_workaround) {
- flush_dcache();
- mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
- sync();
- }
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
- /*
-* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
-* in write shadow mode. Checking DCWS before setting SPR 976.
-*/
- if (mfspr(L1CSR2) L1CSR2_DCWS)
- mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x8000));
-#endif
-
-#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) defined(CONFIG_MP)
- spin = getenv(spin_table_compat);
- if (spin (*spin == 'n'))
- spin_table_compat = 0;
- else
- spin_table_compat = 1;
-#endif
puts (L2:);
@@ -751,6 +679,89 @@ skip_l2:
puts(disabled\n);
#endif
+ return 0;
+}
+
+/*
+ *
+ * The newer 8548, etc, parts have twice as much cache, but
+ * use the same bit-encoding as the older 8555, etc, parts.
+ *
+ */
+int cpu_init_r(void)
+{
+ __maybe_unused u32 svr = get_svr();
+#ifdef
[U-Boot] [PATCH] powerpc/t104xrdb: Toggle deep sleep management signals after resume
From: Tang Yuantian yuantian.t...@freescale.com
T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t104xrdb/t104xrdb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/t104xrdb/t104xrdb.c
b/board/freescale/t104xrdb/t104xrdb.c
index 24b8dba..c87519c 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -108,6 +108,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
+ /* does not provide HW signals for power management */
+ CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
--
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[U-Boot] [PATCH v4] mpc85xx/t104x: Add deep sleep framework support
From: Tang Yuantian yuantian.t...@freescale.com
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
based on: git://git.denx.de/u-boot-mpc85xx.git
branch: next
tested on: t1040qds and t1040rdb platforms.
v4:
- refactor the framework. In the new patch, the entry is placed
just after DDRC's initialization when resume.
v3:
- fix out-of-tree compile warning
v2:
- added explaination for CONFIG_DEEP_SLEEP
- fixed some issues
README | 4 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++
arch/powerpc/lib/board.c| 16
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 52 ++---
include/fsl_ddr_sdram.h | 4 +++
5 files changed, 80 insertions(+), 4 deletions(-)
diff --git a/README b/README
index 83a1b25..31e37cb 100644
--- a/README
+++ b/README
@@ -431,6 +431,10 @@ The following options need to be configured:
This CONFIG is defined when the CPC is configured as SRAM at the
time of U-boot entry and is required to be re-initialized.
+ CONFIG_DEEP_SLEEP
+ Inidcates this SoC supports deep sleep feature. If deep sleep is
+ supported, core will start to execute uboot when wakes up.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 941c20e..867abb6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -350,6 +350,7 @@ void cpu_init_f (void)
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
@@ -414,6 +415,13 @@ void cpu_init_f (void)
in_be32(gur-dcsrcr);
#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (in_be32(gur-scrtsr[0]) (1 3))
+ gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index f86c6f3..8b03d3a 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -343,6 +343,13 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM
ulong reg;
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+ u32 start_addr;
+ typedef void (*func_t)(void);
+ func_t kernel_resume;
+#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -360,6 +367,15 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0)
hang();
+#ifdef CONFIG_DEEP_SLEEP
+ /* Jump to kernel in deep sleep case */
+ if (in_be32(gur-scrtsr[0]) (1 3)) {
+ start_addr = in_be32(scfg-sparecr[1]);
+ kernel_resume = (func_t)start_addr;
+ kernel_resume();
+ }
+#endif
+
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index c805086..4d5572e 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -15,6 +15,7 @@
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
+DECLARE_GLOBAL_DATA_PTR;
/*
* regs has the to-be-set values for DDR controller registers
@@ -43,6 +44,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 save1, save2;
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool sleep_flag = 0;
+#endif
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (in_be32(gur-scrtsr[0]) (1 3))
+ sleep_flag = 1;
+#endif
+
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -119,7 +130,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs,
out_be32(ddr-timing_cfg_0, regs-timing_cfg_0);
out_be32(ddr-timing_cfg_1, regs-timing_cfg_1);
out_be32(ddr-timing_cfg_2, regs-timing_cfg_2);
- out_be32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2);
+#ifdef CONFIG_DEEP_SLEEP
[U-Boot] [PATCH 1/2] mpc85xx: Add deep sleep support on T1040QDS
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T1040QDS platform.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/t1040qds.c | 12
include/configs/T1040QDS.h | 4
2 files changed, 16 insertions(+)
diff --git a/board/freescale/t1040qds/t1040qds.c
b/board/freescale/t1040qds/t1040qds.c
index 3dec447..f1d7cde 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -18,6 +18,7 @@
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
#include fm_eth.h
+#include asm/mpc85xx_gpio.h
#include ../common/qixis.h
#include t1040qds.h
@@ -245,3 +246,14 @@ int board_need_mem_reset(void)
{
return 1;
}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) ~0x2));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 030ea7e..745a2f2 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -43,6 +43,10 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff4
#endif
--
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[U-Boot] [PATCH] mpc85xx: Add deep sleep support on T104xRDB
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T104xRDB platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t104xrdb/t104xrdb.c | 10 ++
include/configs/T104xRDB.h | 4
2 files changed, 14 insertions(+)
diff --git a/board/freescale/t104xrdb/t104xrdb.c
b/board/freescale/t104xrdb/t104xrdb.c
index b48133a..fb5b849 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -17,6 +17,7 @@
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
#include fm_eth.h
+#include asm/mpc85xx_gpio.h
#include t104xrdb.h
#include cpld.h
@@ -104,3 +105,12 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
#endif
}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index eaaf37d..0159b97 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -25,6 +25,10 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff4
#endif
--
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[U-Boot] [PATCH 1/2 v2] mpc85xx: Add support for the supplement configuration unit register
From: Tang Yuantian yuantian.t...@freescale.com
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- fix checkpatch warning
arch/powerpc/include/asm/immap_85xx.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 4b6f9d0..0f0f3d4 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -3151,4 +3151,26 @@ struct dcsr_dcfg_regs {
#defineDCSR_DCFG_ECC_DISABLE_USB2 0x4000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+ u32 dpslpcr;/* 0x000 Deep Sleep Control register */
+ u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
+ u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
+ u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
+ u32 res1[4];
+ u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
+ u32 res2;
+ u32 pixclkcr; /* 0x028 Pixel Clock Control register */
+ u32 res3[245];
+ u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
+ u32 emiiocr;/* 0x404 EMI MDIO Control Register */
+ u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
+ u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
+ u32 res4[60];
+ u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
+};
#endif /*__IMMAP_85xx__*/
--
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[U-Boot] [PATCH 2/2 v3] mpc85xx/t104x: Add deep sleep framework support
From: Tang Yuantian yuantian.t...@freescale.com
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v3:
- fix out-of-tree compile warning
v2:
- added explaination for CONFIG_DEEP_SLEEP
- fixed some issues
README | 4 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c| 7
arch/powerpc/cpu/mpc85xx/fdt.c | 22
arch/powerpc/cpu/mpc85xx/liodn.c | 27 ++
arch/powerpc/cpu/mpc85xx/start.S | 9 +
arch/powerpc/include/asm/global_data.h | 2 ++
arch/powerpc/lib/board.c | 66 +++---
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 42 +++---
include/fdt_support.h | 4 +++
include/fsl_ddr_sdram.h| 4 +++
10 files changed, 171 insertions(+), 16 deletions(-)
diff --git a/README b/README
index 216f0c7..25ffb90 100644
--- a/README
+++ b/README
@@ -427,6 +427,10 @@ The following options need to be configured:
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
+ CONFIG_DEEP_SLEEP
+ Inidcates this SoC supports deep sleep feature. If deep sleep is
+ supported, core will start to execute uboot when wakes up.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 81aeadd..1be29f8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -279,6 +279,7 @@ void cpu_init_f (void)
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/*
* CPU2 errata workaround: A core hang possible while executing
@@ -330,6 +331,12 @@ void cpu_init_f (void)
in_be32(gur-dcsrcr);
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (in_be32(gur-scrtsr[0]) (1 3))
+ gd-flags |= GD_FLG_SILENT |
+ GD_FLG_DEEP_SLEEP | GD_FLG_DISABLE_CONSOLE;
+#endif
}
/* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 33bc900..9351f63 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -35,6 +35,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#ifdef CONFIG_DEEP_SLEEP
+ ulong len;
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, device_type, cpu, 4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -108,6 +111,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
printf(Failed to reserve memory for spin table: %s\n,
fdt_strerror(off));
}
+
+#ifdef CONFIG_DEEP_SLEEP
+ /*
+* reserve the memory space for deep sleep.
+* This space will be re-used next time when boot from deep sleep.
+* The space includes bd_t, gd_t, stack and uboot image.
+* Reserve 1K for stack.
+*/
+ len = sizeof(bd_t) + sizeof(gd_t) + (1 10);
+ /* round up to 4K */
+ len = (len + (4096 - 1)) ~(4096 - 1);
+
+ off = fdt_add_mem_rsv(blob, gd-relocaddr - len,
+ len + ((ulong)__bss_end - gd-relocaddr));
+ if (off 0)
+ printf(Failed to reserve memory for deep sleep: %s\n,
+ fdt_strerror(off));
+
+#endif
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 19e130e..a166765 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -14,6 +14,8 @@
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
+DECLARE_GLOBAL_DATA_PTR;
+
int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset)
{
liodns[0] = liodn_bases[dpaa_dev].id[0] + liodn_offset;
@@ -164,6 +166,8 @@ static void setup_rman_liodn_base(struct liodn_id_table
*tbl, int size)
void set_liodns(void)
{
+ bool is_deepsleep = false;
+
/* setup general liodn offsets */
set_liodn(liodn_tbl, liodn_tbl_sz);
@@ -179,16 +183,25 @@ void set_liodns(void)
}
/* setup FMAN block(s) liodn bases offsets if we have one */
+#ifdef CONFIG_DEEP_SLEEP
+ if (gd-flags GD_FLG_DEEP_SLEEP)
+ is_deepsleep = true;
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
Re: [U-Boot] [U-Boot, 2/3] mpc85xx: Add deep sleep framework support
On 2014/2/25 星期二 3:11, Scott Wood wrote:
Why what? Why we need it?
It is a help function and used by ASM code in which
we can't determine whether it is a warm reset boot.
Why don't you just open code it?
I can't check the warmboot status in ASM code.
In order to get the warmboot status in ASM code, I wrote this function.
Why can't you check it in asm code? See lib/asm-offsets.c.
Found it. Still learn how to use it.
Thanks,
Yuantian
+ if (gd-flags GD_FLG_WARM_BOOT) {
+ src = (u64 *)in_be32(scfg-sparecr[2]);
+ dst = (u64 *)(0);
+ for (i = 0; i 128/sizeof(u64); i++) {
+ *dst = *src;
+ dst++;
+ src++;
+ }
+ }
(u64 *)(0) is a NULL pointer. Dereferencing NULL pointers is undefined
and GCC has been getting increasingly free with making surprising
optimizations based on that (such as assuming any code path that it knows
can reach a NULL dereference is dead code and can be removed).
Then how we operate 0 address if not dereferencing NULL pointer?
With an I/O accessor (or other inline asm), a TLB mapping, or using a
different memory location.
we found the zero address has benefit.
I don't know how to achieve this in inline asm or TLB mapping, could you
be more specific or write a example for me?
Inline asm would be something like:
asm(stw %1, 0(%0); stw %2, 4(%0) : =r (dst) :
r ((u32)(src 32)), r ((u32)src));
-Scott
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Re: [U-Boot] [U-Boot, 2/3] mpc85xx: Add deep sleep framework support
On 2014/2/25 星期二 3:11, Scott Wood wrote: On Mon, 2014-02-24 at 14:44 +0800, Tang Yuantian-B29983 wrote: On 2014/2/18 星期二 3:18, Scott Wood wrote: On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote: -Original Message- From: Wood Scott-B07421 To: Tang Yuantian-B29983 Cc: Sun York-R58495; Li Yang-Leo-R58472; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin Zhengxiong-R64188 Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote: Use an I/O accessor. In_be64?? No such function. Why do you need in_be64() rather than two in_be32()s? Avoid ECC error. Although, according to my test, in_be32() works too. Why would you get an ECC error? -Scott DDR operation is always in 64bits. if writing a 32bits to memory, you need to read a 32bits first, and combine it to form a 64bits. when the new 64bits is written to memory, ECC occurs. I was required to do so by hardware team. U-Boot on PPC is a 32-bit binary (even on 64-bit hardware), so the compiler is already turning that into two 32-bit writes. -Scott I quote: (from Welker James A.-RA8497 ) 3) You only need 8-byte (or multiple of 8-byte) transactions when initializing the memory. Typically, we would simply use 2, 64-byte writes to DRAM. This is because a sub-doubleword transactions will result in a read-modify-write, which would encounter an ECC error (and then mask the write data). After the first 128-bytes of memory have been re-initialized, you can issue any transactions to those locations again. I think the transactions between CPU and DDRC are always in 64 bits physically because DDRC has 64 bits data bus. But I am sure about this. If you are sure about this, I will change as your suggestion. Regards, Yuantian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/3] mpc85xx: Add deep sleep framework support
On 2014/2/25 星期二 3:11, Scott Wood wrote:
On Mon, 2014-02-24 at 15:47 +0800, Tang Yuantian-B29983 wrote:
On 2014/2/15 星期六 6:21, Scott Wood wrote:
On Thu, 2014-02-13 at 01:05 -0600, Tang Yuantian-B29983 wrote:
Thanks for your review. Please see the reply inline.
Thanks,
Yuantian
-Original Message-
From: Wood Scott-B07421
Sent: 2014年2月13日 星期四 8:44
To: Tang Yuantian-B29983
Cc: Sun York-R58495; Wood Scott-B07421; Li Yang-Leo-R58472;
t...@theia.denx.de; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin
Zhengxiong-R64188
Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support
On Sun, Jan 26, 2014 at 02:00:40PM +0800, tang yuantian wrote:
From: Tang Yuantian yuantian.t...@freescale.com
When system wakes up from warm reset, control is passed to the primary
core that starts executing uboot. After re-initialized some IP blocks,
like DDRC, kernel will take responsibility to continue to restore
environment it leaves before.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Is this for some specific mpc85xx chip (e.g. T1040)? I'm pretty sure
this isn't necessary for deep sleep on mpc8536, for example.
Currently, it is used by t1040. But we want it to be more general so that
It can be used by later new chips.
But the mechanism is not the same for all mpc85xx derivatives. You'll
need a more specific name.
OK, will name it as t104x
+#ifdef CONFIG_DEEP_SLEEP
CONFIG symbols need to be documented in README...
Where should I add this README?
Under 85xx CPU Options in the top-level README.
Thanks.
+ /* disable the console if boot from warm reset */
+ if (in_be32(gur-scrtsr[0]) (1 3))
+ gd-flags |=
+ GD_FLG_SILENT | GD_FLG_WARM_BOOT |
GD_FLG_DISABLE_CONSOLE; #endif
...and it should probably be a more specific CONFIG_SYS symbol that
indicates the presence of this guts bit.
where should I put this CONFIG_SYS_'s definition?
Under 85xx CPU Options in the top-level README. :-)
I don't find other gut bit that defined in this README. Do I need to?
Just we are clear that you want me to add a CONFIG_SYS_'s definition for
(1 3) bit in GUTS, right?
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c
b/arch/powerpc/cpu/mpc85xx/fdt.c index 33bc900..b3b9250 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -24,6 +24,9 @@ DECLARE_GLOBAL_DATA_PTR; extern void
ft_qe_setup(void *blob); extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
+#ifdef CONFIG_DEEP_SLEEP
+extern ulong __bss_end;
+#endif
Don't ifdef declarations.
#ifdef CONFIG_MP
#include mp.h
@@ -35,6 +38,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#ifdef CONFIG_DEEP_SLEEP
+ ulong len;
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, device_type, cpu,
4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
device_type, cpu, 4);
}
+#ifdef CONFIG_DEEP_SLEEP
+ /*
+* reserve the memory space for warm reset.
+* This space will be re-used next time when boot from deep sleep.
+* The space includes bd_t, gd_t, stack and uboot image.
+* Reserve 1K for stack.
+*/
+ len = sizeof(bd_t) + sizeof(gd_t) + (1 10);
+ /* round up to 4K */
+ len = (len + (4096 - 1)) ~(4096 - 1);
+
+ off = fdt_add_mem_rsv(blob, gd-relocaddr - len,
+ len + ((ulong)__bss_end - gd-relocaddr));
+ if (off 0)
+ printf(Failed to reserve memory for warm reset: %s\n,
+ fdt_strerror(off));
+
+#endif
Why do you need to reserve memory for this? We didn't need to for deep
sleep on MPC8313ERDB, which also goes through U-Boot on wake. On
MPC8313ERDB we transfer control to the kernel before relocating, so U-
Boot never touches DDR. bd_t, gd_t, and the stack should be in locked
L1 cache, and the u-boot image should be in flash (or locked CPC if this
is not a NOR flash boot).
In deep sleep many IP blocks are powered off like DDRC, LIODN, cpu. These IPs
are re-initialized after relocating.
So, we must jump to kernel after relocating.
The DDR controller is initialized before relocating -- and of course the
CPU is powered off on MPC8313ERDB deep sleep as well.
LIODNs are a new concern for deep sleep, but that doesn't mean we should
go through a bunch of unrelated code to get there. Refactor the LIODN
code to be usable before relocation, and not be tied to fdt fixups.
There are other IP blocks that need to be re-initialized, like SerDes,
SMP, PCIe and
a lot of Errata. I don't want to refactor one by one.
Besides, coding in this way will not change the current execute flow.
Changing the execution flow is better than adding a bunch of special
cases to the current execution flow
Re: [U-Boot] [U-Boot, 2/3] mpc85xx: Add deep sleep framework support
On 2014/2/18 星期二 3:18, Scott Wood wrote: On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote: -Original Message- From: Wood Scott-B07421 To: Tang Yuantian-B29983 Cc: Sun York-R58495; Li Yang-Leo-R58472; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin Zhengxiong-R64188 Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote: Use an I/O accessor. In_be64?? No such function. Why do you need in_be64() rather than two in_be32()s? Avoid ECC error. Although, according to my test, in_be32() works too. Why would you get an ECC error? -Scott DDR operation is always in 64bits. if writing a 32bits to memory, you need to read a 32bits first, and combine it to form a 64bits. when the new 64bits is written to memory, ECC occurs. I was required to do so by hardware team. Regards, Yuantian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/3] mpc85xx: Add deep sleep framework support
On 2014/2/15 星期六 6:21, Scott Wood wrote:
On Thu, 2014-02-13 at 01:05 -0600, Tang Yuantian-B29983 wrote:
Thanks for your review. Please see the reply inline.
Thanks,
Yuantian
-Original Message-
From: Wood Scott-B07421
Sent: 2014年2月13日 星期四 8:44
To: Tang Yuantian-B29983
Cc: Sun York-R58495; Wood Scott-B07421; Li Yang-Leo-R58472;
t...@theia.denx.de; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin
Zhengxiong-R64188
Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support
On Sun, Jan 26, 2014 at 02:00:40PM +0800, tang yuantian wrote:
From: Tang Yuantian yuantian.t...@freescale.com
When system wakes up from warm reset, control is passed to the primary
core that starts executing uboot. After re-initialized some IP blocks,
like DDRC, kernel will take responsibility to continue to restore
environment it leaves before.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Is this for some specific mpc85xx chip (e.g. T1040)? I'm pretty sure
this isn't necessary for deep sleep on mpc8536, for example.
Currently, it is used by t1040. But we want it to be more general so that
It can be used by later new chips.
But the mechanism is not the same for all mpc85xx derivatives. You'll
need a more specific name.
OK, will name it as t104x
+#ifdef CONFIG_DEEP_SLEEP
CONFIG symbols need to be documented in README...
Where should I add this README?
Under 85xx CPU Options in the top-level README.
Thanks.
+ /* disable the console if boot from warm reset */
+ if (in_be32(gur-scrtsr[0]) (1 3))
+ gd-flags |=
+ GD_FLG_SILENT | GD_FLG_WARM_BOOT |
GD_FLG_DISABLE_CONSOLE; #endif
...and it should probably be a more specific CONFIG_SYS symbol that
indicates the presence of this guts bit.
where should I put this CONFIG_SYS_'s definition?
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c
b/arch/powerpc/cpu/mpc85xx/fdt.c index 33bc900..b3b9250 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -24,6 +24,9 @@ DECLARE_GLOBAL_DATA_PTR; extern void
ft_qe_setup(void *blob); extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
+#ifdef CONFIG_DEEP_SLEEP
+extern ulong __bss_end;
+#endif
Don't ifdef declarations.
#ifdef CONFIG_MP
#include mp.h
@@ -35,6 +38,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#ifdef CONFIG_DEEP_SLEEP
+ ulong len;
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, device_type, cpu,
4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
device_type, cpu, 4);
}
+#ifdef CONFIG_DEEP_SLEEP
+ /*
+* reserve the memory space for warm reset.
+* This space will be re-used next time when boot from deep sleep.
+* The space includes bd_t, gd_t, stack and uboot image.
+* Reserve 1K for stack.
+*/
+ len = sizeof(bd_t) + sizeof(gd_t) + (1 10);
+ /* round up to 4K */
+ len = (len + (4096 - 1)) ~(4096 - 1);
+
+ off = fdt_add_mem_rsv(blob, gd-relocaddr - len,
+ len + ((ulong)__bss_end - gd-relocaddr));
+ if (off 0)
+ printf(Failed to reserve memory for warm reset: %s\n,
+ fdt_strerror(off));
+
+#endif
Why do you need to reserve memory for this? We didn't need to for deep
sleep on MPC8313ERDB, which also goes through U-Boot on wake. On
MPC8313ERDB we transfer control to the kernel before relocating, so U-
Boot never touches DDR. bd_t, gd_t, and the stack should be in locked
L1 cache, and the u-boot image should be in flash (or locked CPC if this
is not a NOR flash boot).
In deep sleep many IP blocks are powered off like DDRC, LIODN, cpu. These IPs
are re-initialized after relocating.
So, we must jump to kernel after relocating.
The DDR controller is initialized before relocating -- and of course the
CPU is powered off on MPC8313ERDB deep sleep as well.
LIODNs are a new concern for deep sleep, but that doesn't mean we should
go through a bunch of unrelated code to get there. Refactor the LIODN
code to be usable before relocation, and not be tied to fdt fixups.
There are other IP blocks that need to be re-initialized, like SerDes,
SMP, PCIe and
a lot of Errata. I don't want to refactor one by one.
Besides, coding in this way will not change the current execute flow.
+#ifndef CONFIG_DEEP_SLEEP
/* Reserve spin table page */
if (spin_tbl_addr memory_limit) {
off = fdt_add_mem_rsv(blob,
@@ -108,6 +134,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
printf(Failed to reserve memory for spin table: %s\n,
fdt_strerror(off));
}
+#endif
Explain.
Spin_tbl_addr has been reserved already.
Where, and why
[U-Boot] test
test. 于 2014/2/15 星期六 6:59, Scott Wood 写道: On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote: Use an I/O accessor. In_be64?? No such function. Why do you need in_be64() rather than two in_be32()s? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] mpc85xx: Add support for the supplement configuration unit register
From: Tang Yuantian yuantian.t...@freescale.com
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 68c3c82..71d803b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -3113,4 +3113,26 @@ struct dcsr_dcfg_regs {
#defineDCSR_DCFG_ECC_DISABLE_USB2 0x4000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+ u32 dpslpcr;/* 0x000 Deep Sleep Control register */
+ u32 usb1dpslpcsr; /* 0x004 USB1 Deep Sleep Control Status
register */
+ u32 usb2dpslpcsr; /* 0x008 USB2 Deep Sleep Control Status
register */
+ u32 fmclkdpslpcr; /* 0x00c FM Clock Deep Sleep Control register */
+ u32 res1[4];
+ u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control
register */
+ u32 res2;
+ u32 pixclkcr; /* 0x028 Pixel Clock Control register */
+ u32 res3[245];
+ u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register
*/
+ u32 emiiocr;/* 0x404 EMI MDIO Control Register */
+ u32 sdhciovselcr; /* 0x408 SDHC IO VSEL Control register */
+ u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register
*/
+ u32 res4[60];
+ u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
+};
#endif /*__IMMAP_85xx__*/
--
1.8.0
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[U-Boot] [PATCH 3/3] mpc85xx: Add deep sleep support on T1040QDS
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T1040QDS platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/t1040qds.c | 12
include/configs/T1040QDS.h | 4
2 files changed, 16 insertions(+)
diff --git a/board/freescale/t1040qds/t1040qds.c
b/board/freescale/t1040qds/t1040qds.c
index de3ea5c..2494da6 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -18,6 +18,7 @@
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
#include fm_eth.h
+#include asm/mpc85xx_gpio.h
#include ../common/qixis.h
#include t1040qds.h
@@ -244,3 +245,14 @@ int board_need_mem_reset(void)
{
return 1;
}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) ~0x2));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 91b511b..9c5daf1 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -36,6 +36,10 @@
#define CONFIG_SYS_FSL_PBL_RCW
$(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
#endif
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500/* BOOKE e500 family */
--
1.8.0
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[U-Boot] [PATCH 1/3] mpc85xx: Add support for the supplement configuration unit register
From: Tang Yuantian yuantian.t...@freescale.com
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 68c3c82..71d803b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -3113,4 +3113,26 @@ struct dcsr_dcfg_regs {
#defineDCSR_DCFG_ECC_DISABLE_USB2 0x4000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+ u32 dpslpcr;/* 0x000 Deep Sleep Control register */
+ u32 usb1dpslpcsr; /* 0x004 USB1 Deep Sleep Control Status
register */
+ u32 usb2dpslpcsr; /* 0x008 USB2 Deep Sleep Control Status
register */
+ u32 fmclkdpslpcr; /* 0x00c FM Clock Deep Sleep Control register */
+ u32 res1[4];
+ u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control
register */
+ u32 res2;
+ u32 pixclkcr; /* 0x028 Pixel Clock Control register */
+ u32 res3[245];
+ u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register
*/
+ u32 emiiocr;/* 0x404 EMI MDIO Control Register */
+ u32 sdhciovselcr; /* 0x408 SDHC IO VSEL Control register */
+ u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register
*/
+ u32 res4[60];
+ u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
+};
#endif /*__IMMAP_85xx__*/
--
1.8.0
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[U-Boot] [PATCH 2/3] mpc85xx: Add deep sleep framework support
From: Tang Yuantian yuantian.t...@freescale.com
When system wakes up from warm reset, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c| 7
arch/powerpc/cpu/mpc85xx/fdt.c | 27 +++
arch/powerpc/cpu/mpc85xx/liodn.c | 24 +
arch/powerpc/cpu/mpc85xx/start.S | 8 +
arch/powerpc/include/asm/global_data.h | 1 +
arch/powerpc/lib/board.c | 61 +++---
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 44 +---
include/fsl_ddr_sdram.h| 6
8 files changed, 163 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..376c659 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -231,6 +231,7 @@ void cpu_init_f (void)
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/*
* CPU2 errata workaround: A core hang possible while executing
@@ -282,6 +283,12 @@ void cpu_init_f (void)
in_be32(gur-dcsrcr);
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from warm reset */
+ if (in_be32(gur-scrtsr[0]) (1 3))
+ gd-flags |=
+ GD_FLG_SILENT | GD_FLG_WARM_BOOT |
GD_FLG_DISABLE_CONSOLE;
+#endif
}
/* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 33bc900..b3b9250 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -24,6 +24,9 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob);
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
+#ifdef CONFIG_DEEP_SLEEP
+extern ulong __bss_end;
+#endif
#ifdef CONFIG_MP
#include mp.h
@@ -35,6 +38,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#ifdef CONFIG_DEEP_SLEEP
+ ulong len;
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, device_type, cpu, 4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
device_type, cpu, 4);
}
+#ifdef CONFIG_DEEP_SLEEP
+ /*
+* reserve the memory space for warm reset.
+* This space will be re-used next time when boot from deep sleep.
+* The space includes bd_t, gd_t, stack and uboot image.
+* Reserve 1K for stack.
+*/
+ len = sizeof(bd_t) + sizeof(gd_t) + (1 10);
+ /* round up to 4K */
+ len = (len + (4096 - 1)) ~(4096 - 1);
+
+ off = fdt_add_mem_rsv(blob, gd-relocaddr - len,
+ len + ((ulong)__bss_end - gd-relocaddr));
+ if (off 0)
+ printf(Failed to reserve memory for warm reset: %s\n,
+ fdt_strerror(off));
+
+#endif
+
/* Reserve the boot page so OSes dont use it */
if ((u64)bootpg memory_limit) {
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
@@ -100,6 +125,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
}
#endif
+#ifndef CONFIG_DEEP_SLEEP
/* Reserve spin table page */
if (spin_tbl_addr memory_limit) {
off = fdt_add_mem_rsv(blob,
@@ -108,6 +134,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
printf(Failed to reserve memory for spin table: %s\n,
fdt_strerror(off));
}
+#endif
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 19e130e..898685b 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -14,6 +14,10 @@
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
+#ifdef CONFIG_DEEP_SLEEP
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset)
{
liodns[0] = liodn_bases[dpaa_dev].id[0] + liodn_offset;
@@ -180,14 +184,22 @@ void set_liodns(void)
/* setup FMAN block(s) liodn bases offsets if we have one */
#ifdef CONFIG_SYS_DPAA_FMAN
- set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz);
- setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl,
- fman1_liodn_tbl_sz);
+#ifdef CONFIG_DEEP_SLEEP
+ if ((gd-flags GD_FLG_WARM_BOOT) == 0) {
+ set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz
[U-Boot] [PATCH 3/3] mpc85xx: Add deep sleep support on T1040QDS
From: Tang Yuantian yuantian.t...@freescale.com
Add deep sleep support on T1040QDS platforms.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t1040qds/t1040qds.c | 12
include/configs/T1040QDS.h | 4
2 files changed, 16 insertions(+)
diff --git a/board/freescale/t1040qds/t1040qds.c
b/board/freescale/t1040qds/t1040qds.c
index de3ea5c..2494da6 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -18,6 +18,7 @@
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
#include fm_eth.h
+#include asm/mpc85xx_gpio.h
#include ../common/qixis.h
#include t1040qds.h
@@ -244,3 +245,14 @@ int board_need_mem_reset(void)
{
return 1;
}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) ~0x2));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 91b511b..9c5daf1 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -36,6 +36,10 @@
#define CONFIG_SYS_FSL_PBL_RCW
$(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
#endif
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500/* BOOKE e500 family */
--
1.8.0
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Re: [U-Boot] [PATCH] mpc85xx: Fix the offset of register address error
Hi York, I double checked the offset address of GPIO, I found that the offset addresses of GPIO on the boards you mentioned above are all changed to 0x0, not 0xc00 according to the newest RM. I do found that the offset address is 0xc00 in some old RMs. You can find the newest RM here: For MPC8572: http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/ 200815/108253488/223469393/223503931/226628079/226445024/MPC8572ERM_Re v3_DRAFT1.pdf?nodeid=226438746vernum=-2 For p1023: http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/ 200815/108253488/223469393/223506436/223521755/223743960/P1023RM_Mark- up.pdf?nodeid=229647544vernum=-2 for 1020: http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/ 200815/108253488/223469393/223506436/223522385/224515312/P1020RM_Rev6_ Mark-up.pdf?nodeid=228476444vernum=-2 If the offset addresses on these boards were 0xc00, the driver is still wrong, because in that case The GPIO address should be: CONFIG_SYS_IMMR + 0xc00, not CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00. (CONFIG_SYS_MPC85xx_GPIO_ADDR == CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET). So, please apply this patch, I need the GPIO driver to operate GPIO. Please update the commit message to list all SoCs you have confirmed the offset. And don't say no reason to add 0xc00. The reason was clear when the code was written. Reference manuals said so. York OK, I will resend this patch once the offset is confirmed by the RM owner. Thanks, Yuantian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpc85xx: Fix the offset of register address error
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h
b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 3d11884..87bb4a0 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
static inline void mpc85xx_gpio_set(unsigned int mask,
unsigned int dir, unsigned int val) {
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
/* First mask off the unwanted parts of dir and val */
dir = mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned
int gpios)
static inline unsigned int mpc85xx_gpio_get(unsigned int mask) {
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
/* Read the requested values */
return in_be32(gpio-gpdat) mask;
Yuantian,
Please go through the base address again. I think some SoCs do use 0xc00
offset from 0xF000, for eample P1020, P1023, MPC8572. I only spot checked
several.
Hi York,
I double checked the offset address of GPIO, I found that the offset addresses
of
GPIO on the boards you mentioned above are all changed to 0x0, not 0xc00
according
to the newest RM.
I do found that the offset address is 0xc00 in some old RMs.
You can find the newest RM here:
For MPC8572:
http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/200815/108253488/223469393/223503931/226628079/226445024/MPC8572ERM_Rev3_DRAFT1.pdf?nodeid=226438746vernum=-2
For p1023:
http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/200815/108253488/223469393/223506436/223521755/223743960/P1023RM_Mark-up.pdf?nodeid=229647544vernum=-2
for 1020:
http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/200815/108253488/223469393/223506436/223522385/224515312/P1020RM_Rev6_Mark-up.pdf?nodeid=228476444vernum=-2
If the offset addresses on these boards were 0xc00, the driver is still wrong,
because in that case
The GPIO address should be: CONFIG_SYS_IMMR + 0xc00, not
CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00.
(CONFIG_SYS_MPC85xx_GPIO_ADDR == CONFIG_SYS_IMMR +
CONFIG_SYS_MPC85xx_GPIO_OFFSET).
So, please apply this patch, I need the GPIO driver to operate GPIO.
Regards,
Yuantian
York
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[U-Boot] [PATCH] mpc85xx: Fix the offset of register address error
From: Tang Yuantian yuantian.t...@freescale.com
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR, no reason to add 0xc00.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
arch/powerpc/include/asm/mpc85xx_gpio.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h
b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 3d11884..87bb4a0 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
static inline void mpc85xx_gpio_set(unsigned int mask,
unsigned int dir, unsigned int val)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
/* First mask off the unwanted parts of dir and val */
dir = mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
/* Read the requested values */
return in_be32(gpio-gpdat) mask;
--
1.8.0
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