[U-Boot] [UBOOT PATCH] Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq

[Vipul Kumar]

From: Siva Durga Prasad Paladugu 

This patch moves the the config SYS_MALLOC_LEN to
Kconfig. It will be just for Zynq arch and to do
will be for all other archs.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Vipul Kumar 
---
 Kconfig | 7 +++
 arch/arm/mach-zynq/Kconfig  | 3 +++
 configs/zynq_cse_nand_defconfig | 1 +
 configs/zynq_cse_nor_defconfig  | 1 +
 configs/zynq_cse_qspi_defconfig | 1 +
 include/configs/zynq-common.h   | 2 --
 include/configs/zynq_cse.h  | 3 ---
 7 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/Kconfig b/Kconfig
index c8b86cd..61795e3 100644
--- a/Kconfig
+++ b/Kconfig
@@ -136,6 +136,13 @@ config SYS_MALLOC_F_LEN
  particular needs this to operate, so that it can allocate the
  initial serial device and any others that are needed.
 
+config SYS_MALLOC_LEN
+   hex "Define memory for Dynamic allocation"
+   depends on ARCH_ZYNQ
+   help
+ This defines memory to be allocated for Dynamic allocation
+ TODO: Use for other architectures
+
 config SPL_SYS_MALLOC_F_LEN
 hex "Size of malloc() pool in SPL before relocation"
 depends on SYS_MALLOC_F
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 1352359..a599ed6 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -57,6 +57,9 @@ config SYS_CONFIG_NAME
 config SYS_MALLOC_F_LEN
default 0x600
 
+config SYS_MALLOC_LEN
+   default 0x140
+
 config BOOT_INIT_FILE
string "boot.bin init register filename"
default ""
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index eb7e574..d228f9a 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x10
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x20
+CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 95b31a0..3052c5b 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0xFFFC
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x20
+CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
 CONFIG_BOOTDELAY=-1
 # CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index c094a5e..2410806 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEBUG_UART_BASE=0x0
 CONFIG_DEBUG_UART_CLOCK=0
 CONFIG_SPL_STACK_R_ADDR=0x20
 # CONFIG_ZYNQ_DDRC_INIT is not set
+CONFIG_SYS_MALLOC_LEN=0x1000
 # CONFIG_CMD_ZYNQ is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
 CONFIG_DEBUG_UART=y
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index c41dc2c..3c2987b 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -236,8 +236,6 @@
 #define CONFIG_SYS_MEMTEST_START   0
 #define CONFIG_SYS_MEMTEST_END 0x1000
 
-#define CONFIG_SYS_MALLOC_LEN  0x140
-
 #define CONFIG_SYS_INIT_RAM_ADDR   0x
 #define CONFIG_SYS_INIT_RAM_SIZE   0x1000
 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR + \
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
index 36fbe0e..c4587a1 100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h
@@ -36,7 +36,4 @@
 #define CONFIG_SPL_BSS_START_ADDR  0x2
 #define CONFIG_SPL_BSS_MAX_SIZE0x8000
 
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN  0x1000
-
 #endif /* __CONFIG_ZYNQ_CSE_H */
-- 
2.7.4

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[U-Boot] [UBOOT PATCH] gpio: zynq: Used platdata structure for storing static data instead of priv

[Vipul Kumar]

This patch used platdata structure instead of priv for storing static
information read from DT.

Signed-off-by: Vipul Kumar 
---
 drivers/gpio/zynq_gpio.c | 67 
 1 file changed, 34 insertions(+), 33 deletions(-)

diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index f793ee5..6fbaafb 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -93,7 +93,7 @@
 /* GPIO upper 16 bit mask */
 #define ZYNQ_GPIO_UPPER_MASK 0x
 
-struct zynq_gpio_privdata {
+struct zynq_gpio_platdata {
phys_addr_t base;
const struct zynq_platform_data *p_data;
 };
@@ -162,20 +162,20 @@ static inline void zynq_gpio_get_bank_pin(unsigned int 
pin_num,
  unsigned int *bank_pin_num,
  struct udevice *dev)
 {
-   struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+   struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
u32 bank;
 
-   for (bank = 0; bank < priv->p_data->max_bank; bank++) {
-   if ((pin_num >= priv->p_data->bank_min[bank]) &&
-   (pin_num <= priv->p_data->bank_max[bank])) {
-   *bank_num = bank;
-   *bank_pin_num = pin_num -
-   priv->p_data->bank_min[bank];
-   return;
+   for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
+   if (pin_num >= platdata->p_data->bank_min[bank] &&
+   pin_num <= platdata->p_data->bank_max[bank]) {
+   *bank_num = bank;
+   *bank_pin_num = pin_num -
+   platdata->p_data->bank_min[bank];
+   return;
}
}
 
-   if (bank >= priv->p_data->max_bank) {
+   if (bank >= platdata->p_data->max_bank) {
printf("Invalid bank and pin num\n");
*bank_num = 0;
*bank_pin_num = 0;
@@ -184,9 +184,9 @@ static inline void zynq_gpio_get_bank_pin(unsigned int 
pin_num,
 
 static int gpio_is_valid(unsigned gpio, struct udevice *dev)
 {
-   struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+   struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
-   return gpio < priv->p_data->ngpio;
+   return gpio < platdata->p_data->ngpio;
 }
 
 static int check_gpio(unsigned gpio, struct udevice *dev)
@@ -202,14 +202,14 @@ static int zynq_gpio_get_value(struct udevice *dev, 
unsigned gpio)
 {
u32 data;
unsigned int bank_num, bank_pin_num;
-   struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+   struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
if (check_gpio(gpio, dev) < 0)
return -1;
 
zynq_gpio_get_bank_pin(gpio, _num, _pin_num, dev);
 
-   data = readl(priv->base +
+   data = readl(platdata->base +
 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
 
return (data >> bank_pin_num) & 1;
@@ -218,7 +218,7 @@ static int zynq_gpio_get_value(struct udevice *dev, 
unsigned gpio)
 static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
 {
unsigned int reg_offset, bank_num, bank_pin_num;
-   struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+   struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
if (check_gpio(gpio, dev) < 0)
return -1;
@@ -241,7 +241,7 @@ static int zynq_gpio_set_value(struct udevice *dev, 
unsigned gpio, int value)
value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
 
-   writel(value, priv->base + reg_offset);
+   writel(value, platdata->base + reg_offset);
 
return 0;
 }
@@ -250,7 +250,7 @@ static int zynq_gpio_direction_input(struct udevice *dev, 
unsigned gpio)
 {
u32 reg;
unsigned int bank_num, bank_pin_num;
-   struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+   struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
if (check_gpio(gpio, dev) < 0)
return -1;
@@ -262,9 +262,9 @@ static int zynq_gpio_direction_input(struct udevice *dev, 
unsigned gpio)
return -1;
 
/* clear the bit in direction mode reg to set the pin as input */
-   reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+   reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
-   writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+   writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 
return 0;
 }
@@ -274,

[U-Boot] [UBOOT PATCH v2] env: Added support to save env to spi through Kconfig

[Vipul Kumar]

This patch added support to enable CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET
and CONFIG_ENV_SECT_SIZE through Kconfig for Zynq and Zynqmp.

Signed-off-by: Vipul Kumar 
---
Changes in v2:
- Changed if condition of ENV_SIZE for Zynqmp
- Changed if condition for ENV_SECT_SIZE
---
 env/Kconfig | 28 
 include/configs/xilinx_zynqmp.h |  3 ---
 include/configs/zynq-common.h   | 13 -
 3 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/env/Kconfig b/env/Kconfig
index 8618376..b37dcd7 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -480,6 +480,34 @@ config ENV_SIZE
 
 endif
 
+if ARCH_ZYNQMP || ARCH_ZYNQ
+
+config ENV_OFFSET
+   hex "Environment Offset"
+   depends on !ENV_IS_NOWHERE
+   default 0x1E0 if ARCH_ZYNQMP
+   default 0xE if ARCH_ZYNQ
+   help
+ Offset from the start of the device (or partition)
+
+config ENV_SIZE
+   hex "Environment Size"
+   default 0x4 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
+   default 0x8000 if ARCH_ZYNQMP
+   default 0x2 if ARCH_ZYNQ
+   help
+ Size of the environment storage area.
+
+config ENV_SECT_SIZE
+   hex "Environment Sector-Size"
+   depends on !ENV_IS_NOWHERE
+   default 0x4 if ARCH_ZYNQMP
+   default 0x2 if ARCH_ZYNQ
+   help
+ Size of the sector containing the environment.
+
+endif
+
 config USE_DEFAULT_ENV_FILE
bool "Create default environment from file"
help
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ebc6c6f..ef242c7 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -99,9 +99,6 @@
 # define PARTS_DEFAULT
 #endif
 
-/* Do not preserve environment */
-#define CONFIG_ENV_SIZE0x8000
-
 /* Monitor Command Prompt */
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE  2048
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index a6f2ace..c41dc2c 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -121,22 +121,9 @@
 # define CONFIG_SYS_EEPROM_SIZE1024 /* Bytes */
 #endif
 
-/* Total Size of Environment Sector */
-#ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE   (128 << 10)
-#endif
-
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-/* Environment */
-#ifndef CONFIG_ENV_IS_NOWHERE
-# define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# ifndef CONFIG_ENV_OFFSET
-#  define CONFIG_ENV_OFFSET0xE
-# endif
-#endif
-
 /* enable preboot to be loaded before CONFIG_BOOTDELAY */
 #define CONFIG_PREBOOT
 
-- 
2.7.4

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[U-Boot] [UBOOT PATCH v5 0/4] spi:xilinx_spi: Modify xilinx spi driver

[Vipul Kumar]

This series of patches do the following:
- This patch added support to get reg base address from DTS file
- Added rxfifo() and txfifo() functions to add the modularity
- Added support to read JEDEC-id twice at the boot time
- Added live-tree support

Changes in v2:
- Split single patch into the series of patches

Changes in v3:
- Read reg in probe function
- Removed xilinx_spi_ofdata_to_platdata function
- Added fifo_depth read support in 2/3 and removed from 1/3

Changes in v4:
- Moved static startup variable to private structure
- Added live-tree support

Changes in v5:
- Changed function name to xilinx_spi_startup_block()

Michal Simek (1):
  spi: xilinx: Read reg base address from DTS file

Vipul Kumar (3):
  spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function
  spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time
  spi: xilinx_spi: convert to livetree

 drivers/spi/xilinx_spi.c | 152 ++-
 1 file changed, 110 insertions(+), 42 deletions(-)

-- 
2.7.4

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[U-Boot] [UBOOT PATCH v5 1/4] spi: xilinx: Read reg base address from DTS file

[Vipul Kumar]

From: Michal Simek 

This patch added support to read register base address from DTS file.

Signed-off-by: Michal Simek 
Signed-off-by: Vipul Kumar 
---
Changes in v5:
- No change
---
 drivers/spi/xilinx_spi.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8f0f32f..cc5ac51 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -77,10 +77,6 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif
 
-#ifndef CONFIG_SYS_XILINX_SPI_LIST
-#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
-#endif
-
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -107,13 +103,12 @@ struct xilinx_spi_priv {
unsigned int mode;
 };
 
-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
 static int xilinx_spi_probe(struct udevice *bus)
 {
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
 
-   priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
+   priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
 
writel(SPISSR_RESET_VALUE, >srr);
 
-- 
2.7.4

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[U-Boot] [UBOOT PATCH v5 4/4] spi: xilinx_spi: convert to livetree

[Vipul Kumar]

Update the xilinx spi driver to support a live tree.

Signed-off-by: Vipul Kumar 
---
Changes in v5:
- No change
---
 drivers/spi/xilinx_spi.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8621738..2b5f2cf 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -113,10 +113,9 @@ static int xilinx_spi_probe(struct udevice *bus)
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
 
-   priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
+   priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
 
-   priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
- "fifo-size", 0);
+   priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
 
writel(SPISSR_RESET_VALUE, >srr);
 
-- 
2.7.4

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[U-Boot] [UBOOT PATCH v5 2/4] spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function

[Vipul Kumar]

This patch modify xilinx_spi_xfer() function and add rxfifo() and
txfifo() functions to add the modularity so that these functions
can be used by other functions within the same file.

This patch also added support to read fifo_size from dts.

Signed-off-by: Vipul Kumar 
Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes in v5:
- No change
---
 drivers/spi/xilinx_spi.c | 103 +++
 1 file changed, 68 insertions(+), 35 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index cc5ac51..11b7343 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * [0]: http://www.xilinx.com/support/documentation
@@ -77,6 +78,8 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif
 
+#define XILINX_SPISR_TIMEOUT   1 /* in milliseconds */
+
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -101,6 +104,7 @@ struct xilinx_spi_priv {
struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+   unsigned int fifo_depth;
 };
 
 static int xilinx_spi_probe(struct udevice *bus)
@@ -110,6 +114,9 @@ static int xilinx_spi_probe(struct udevice *bus)
 
priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
 
+   priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
+ "fifo-size", 0);
+
writel(SPISSR_RESET_VALUE, >srr);
 
return 0;
@@ -157,6 +164,47 @@ static int xilinx_spi_release_bus(struct udevice *dev)
return 0;
 }
 
+static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
+ u32 txbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   u32 i = 0;
+
+   while (txbytes && !(readl(>spisr) & SPISR_TX_FULL) &&
+  i < priv->fifo_depth) {
+   d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+   debug("spi_xfer: tx:%x ", d);
+   /* write out and wait for processing (receive data) */
+   writel(d & SPIDTR_8BIT_MASK, >spidtr);
+   txbytes--;
+   i++;
+   }
+
+   return i;
+}
+
+static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   unsigned int i = 0;
+
+   while (rxbytes && !(readl(>spisr) & SPISR_RX_EMPTY)) {
+   d = readl(>spidrr) & SPIDRR_8BIT_MASK;
+   if (rxp)
+   *rxp++ = d;
+   debug("spi_xfer: rx:%x\n", d);
+   rxbytes--;
+   i++;
+   }
+   debug("Rx_done\n");
+
+   return i;
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -168,8 +216,10 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
unsigned char *rxp = din;
-   unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
-   unsigned global_timeout;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+   u32 reg, count, timeout;
+   int ret;
 
debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
  bus->seq, slave_plat->cs, bitlen, bytes, flags);
@@ -184,48 +234,31 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
goto done;
}
 
-   /* empty read buffer */
-   while (rxecount && !(readl(>spisr) & SPISR_RX_EMPTY)) {
-   readl(>spidrr);
-   rxecount--;
-   }
-
-   if (!rxecount) {
-   printf("XILSPI error: Rx buffer not empty\n");
-   return -1;
-   }
-
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);
 
-   /* at least 1usec or greater, leftover 1 */
-   global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 100 ? 2 :
-   (XILSPI_MAX_XFER_BITS * 100 / priv->freq) + 1;
 
-   while (bytes--) {
-   unsigned timeout = global_timeout;
-   /* get Tx element from data out buffer and count up */
-   unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
-   debug("spi_xfer: tx:%x ", d);
+   while (txbytes && rxbytes) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   reg = readl(>spicr) &

[U-Boot] [UBOOT PATCH v5 3/4] spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

[Vipul Kumar]

This patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.

This patch added support to read JEDEC id in xilinx_spi_xfer ().

Signed-off-by: Vipul Kumar 
---
Changes in v5:
- Changed function name to xilinx_spi_startup_block()
---
 drivers/spi/xilinx_spi.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 11b7343..8621738 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -105,6 +105,7 @@ struct xilinx_spi_priv {
unsigned int freq;
unsigned int mode;
unsigned int fifo_depth;
+   u8 startup;
 };
 
 static int xilinx_spi_probe(struct udevice *bus)
@@ -205,6 +206,39 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 
*rxp, u32 rxbytes)
return i;
 }
 
+static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
+const void *dout, void *din)
+{
+   struct udevice *bus = dev_get_parent(dev);
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   const unsigned char *txp = dout;
+   unsigned char *rxp = din;
+   u32 reg, count;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+
+   /*
+* This loop runs two times. First time to send the command.
+* Second time to transfer data. After transferring data,
+* it sets txp to the initial value for the normal operation.
+*/
+   for ( ; priv->startup < 2; priv->startup++) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   reg = readl(>spicr) & ~SPICR_MASTER_INHIBIT;
+   writel(reg, >spicr);
+   count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
+   txp = din;
+
+   if (priv->startup) {
+   spi_cs_deactivate(dev);
+   spi_cs_activate(dev, slave_plat->cs);
+   txp = dout;
+   }
+   }
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -237,6 +271,13 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);
 
+   /*
+* This is the work around for the startup block issue in
+* the spi controller. SPI clock is passing through STARTUP
+* block to FLASH. STARTUP block don't provide clock as soon
+* as QSPI provides command. So first command fails.
+*/
+   xilinx_spi_startup_block(dev, bytes, dout, din);
 
while (txbytes && rxbytes) {
count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
-- 
2.7.4

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[U-Boot] [UBOOT PATCH v4 3/4] spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

[Vipul Kumar]

This patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.

This patch added support to read JEDEC id in xilinx_spi_xfer ().

Signed-off-by: Vipul Kumar 
---
Changes in v4:
- Moved static startup variable to private data structure
- Link to AR: https://www.xilinx.com/support/answers/52626.html
---
 drivers/spi/xilinx_spi.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 11b7343..f66ea15 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -105,6 +105,7 @@ struct xilinx_spi_priv {
unsigned int freq;
unsigned int mode;
unsigned int fifo_depth;
+   u8 startup;
 };
 
 static int xilinx_spi_probe(struct udevice *bus)
@@ -205,6 +206,39 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 
*rxp, u32 rxbytes)
return i;
 }
 
+static void xilinx_startup_block(struct udevice *dev, unsigned int bytes,
+const void *dout, void *din)
+{
+   struct udevice *bus = dev_get_parent(dev);
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   const unsigned char *txp = dout;
+   unsigned char *rxp = din;
+   u32 reg, count;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+
+   /*
+* This loop runs two times. First time to send the command.
+* Second time to transfer data. After transferring data,
+* it sets txp to the initial value for the normal operation.
+*/
+   for ( ; priv->startup < 2; priv->startup++) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   reg = readl(>spicr) & ~SPICR_MASTER_INHIBIT;
+   writel(reg, >spicr);
+   count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
+   txp = din;
+
+   if (priv->startup) {
+   spi_cs_deactivate(dev);
+   spi_cs_activate(dev, slave_plat->cs);
+   txp = dout;
+   }
+   }
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -237,6 +271,13 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);
 
+   /*
+* This is the work around for the startup block issue in
+* the spi controller. SPI clock is passing through STARTUP
+* block to FLASH. STARTUP block don't provide clock as soon
+* as QSPI provides command. So first command fails.
+*/
+   xilinx_startup_block(dev, bytes, dout, din);
 
while (txbytes && rxbytes) {
count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
-- 
2.7.4

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[U-Boot] [UBOOT PATCH v4 2/4] spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function

[Vipul Kumar]

This patch modify xilinx_spi_xfer() function and add rxfifo() and
txfifo() functions to add the modularity so that these functions
can be used by other functions within the same file.

This patch also added support to read fifo_size from dts.

Signed-off-by: Vipul Kumar 
Signed-off-by: Siva Durga Prasad Paladugu 
---
Changes in v4:
- Added space before "return i"
---
 drivers/spi/xilinx_spi.c | 103 +++
 1 file changed, 68 insertions(+), 35 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index cc5ac51..11b7343 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * [0]: http://www.xilinx.com/support/documentation
@@ -77,6 +78,8 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif
 
+#define XILINX_SPISR_TIMEOUT   1 /* in milliseconds */
+
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -101,6 +104,7 @@ struct xilinx_spi_priv {
struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+   unsigned int fifo_depth;
 };
 
 static int xilinx_spi_probe(struct udevice *bus)
@@ -110,6 +114,9 @@ static int xilinx_spi_probe(struct udevice *bus)
 
priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
 
+   priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
+ "fifo-size", 0);
+
writel(SPISSR_RESET_VALUE, >srr);
 
return 0;
@@ -157,6 +164,47 @@ static int xilinx_spi_release_bus(struct udevice *dev)
return 0;
 }
 
+static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
+ u32 txbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   u32 i = 0;
+
+   while (txbytes && !(readl(>spisr) & SPISR_TX_FULL) &&
+  i < priv->fifo_depth) {
+   d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+   debug("spi_xfer: tx:%x ", d);
+   /* write out and wait for processing (receive data) */
+   writel(d & SPIDTR_8BIT_MASK, >spidtr);
+   txbytes--;
+   i++;
+   }
+
+   return i;
+}
+
+static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   unsigned int i = 0;
+
+   while (rxbytes && !(readl(>spisr) & SPISR_RX_EMPTY)) {
+   d = readl(>spidrr) & SPIDRR_8BIT_MASK;
+   if (rxp)
+   *rxp++ = d;
+   debug("spi_xfer: rx:%x\n", d);
+   rxbytes--;
+   i++;
+   }
+   debug("Rx_done\n");
+
+   return i;
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -168,8 +216,10 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
unsigned char *rxp = din;
-   unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
-   unsigned global_timeout;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+   u32 reg, count, timeout;
+   int ret;
 
debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
  bus->seq, slave_plat->cs, bitlen, bytes, flags);
@@ -184,48 +234,31 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
goto done;
}
 
-   /* empty read buffer */
-   while (rxecount && !(readl(>spisr) & SPISR_RX_EMPTY)) {
-   readl(>spidrr);
-   rxecount--;
-   }
-
-   if (!rxecount) {
-   printf("XILSPI error: Rx buffer not empty\n");
-   return -1;
-   }
-
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);
 
-   /* at least 1usec or greater, leftover 1 */
-   global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 100 ? 2 :
-   (XILSPI_MAX_XFER_BITS * 100 / priv->freq) + 1;
 
-   while (bytes--) {
-   unsigned timeout = global_timeout;
-   /* get Tx element from data out buffer and count up */
-   unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
-   debug("spi_xfer: tx:%x ", d);
+   while (txbytes && rxbytes) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   r

[U-Boot] [UBOOT PATCH v4 1/4] spi: xilinx: Read reg base address from DTS file

[Vipul Kumar]

From: Michal Simek 

This patch added support to read register base address from DTS file.

Signed-off-by: Vipul Kumar 
---
Changes in v4:
- No change
---
 drivers/spi/xilinx_spi.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8f0f32f..cc5ac51 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -77,10 +77,6 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif
 
-#ifndef CONFIG_SYS_XILINX_SPI_LIST
-#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
-#endif
-
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -107,13 +103,12 @@ struct xilinx_spi_priv {
unsigned int mode;
 };
 
-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
 static int xilinx_spi_probe(struct udevice *bus)
 {
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
 
-   priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
+   priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
 
writel(SPISSR_RESET_VALUE, >srr);
 
-- 
2.7.4

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[U-Boot] [UBOOT PATCH v4 0/4] spi:xilinx_spi: Modify xilinx spi driver

[Vipul Kumar]

This series of patches do the following:
- This patch added support to get reg base address from DTS file
- Added rxfifo() and txfifo() functions to add the modularity
- Added support to read JEDEC-id twice at the boot time
- Added live-tree support

Changes in v2:
- Split single patch into the series of patches

Changes in v3:
- Read reg in probe function
- Removed xilinx_spi_ofdata_to_platdata function
- Added fifo_depth read support in 2/3 and removed from 1/3

Changes in v4:
- Moved static startup variable to private structure
- Added live-tree support

Michal Simek (1):
  spi: xilinx: Read reg base address from DTS file

Vipul Kumar (3):
  spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function
  spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time
  spi: xilinx_spi: convert to livetree

 drivers/spi/xilinx_spi.c | 152 ++-
 1 file changed, 110 insertions(+), 42 deletions(-)

-- 
2.7.4

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[U-Boot] [UBOOT PATCH v4 4/4] spi: xilinx_spi: convert to livetree

[Vipul Kumar]

Update the xilinx spi driver to support a live tree.

Signed-off-by: Vipul Kumar 
---
 drivers/spi/xilinx_spi.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index f66ea15..59ac851 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -113,10 +113,9 @@ static int xilinx_spi_probe(struct udevice *bus)
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
 
-   priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
+   priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
 
-   priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
- "fifo-size", 0);
+   priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
 
writel(SPISSR_RESET_VALUE, >srr);
 
-- 
2.7.4

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[U-Boot] [UBOOT PATCH] env: Added support to save env to spi through Kconfig

[Vipul Kumar]

This patch added support to enable CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET
and CONFIG_ENV_SECT_SIZE through Kconfig for Zynq and Zynqmp.

Signed-off-by: Vipul Kumar 
---
 env/Kconfig | 27 +++
 include/configs/xilinx_zynqmp.h |  3 ---
 include/configs/zynq-common.h   | 13 -
 3 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/env/Kconfig b/env/Kconfig
index 8618376..640a43f 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -480,6 +480,33 @@ config ENV_SIZE

 endif

+if ARCH_ZYNQMP || ARCH_ZYNQ
+
+config ENV_OFFSET
+   hex "Environment Offset"
+   depends on !ENV_IS_NOWHERE
+   default 0x1E0 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
+   default 0xE if ARCH_ZYNQ
+   help
+ Offset from the start of the device (or partition)
+
+config ENV_SIZE
+   hex "Environment Size"
+   default 0x4 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
+   default 0x8000 if !ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
+   default 0x2 if ARCH_ZYNQ
+   help
+ Size of the environment storage area.
+
+config ENV_SECT_SIZE
+   hex "Environment Sector-Size"
+   default 0x4 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
+   default 0x2 if !ENV_IS_NOWHERE && ARCH_ZYNQ
+   help
+ Size of the sector containing the environment.
+
+endif
+
 config USE_DEFAULT_ENV_FILE
bool "Create default environment from file"
help
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index e9086f9..7add9ea 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -102,9 +102,6 @@
 # define PARTS_DEFAULT
 #endif

-/* Do not preserve environment */
-#define CONFIG_ENV_SIZE0x8000
-
 /* Monitor Command Prompt */
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE  2048
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 55b983f..16426a7 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -125,22 +125,9 @@
 # define CONFIG_SYS_EEPROM_SIZE1024 /* Bytes */
 #endif

-/* Total Size of Environment Sector */
-#ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE   (128 << 10)
-#endif
-
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE

-/* Environment */
-#ifndef CONFIG_ENV_IS_NOWHERE
-# define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# ifndef CONFIG_ENV_OFFSET
-#  define CONFIG_ENV_OFFSET0xE
-# endif
-#endif
-
 /* enable preboot to be loaded before CONFIG_BOOTDELAY */
 #define CONFIG_PREBOOT

--
2.7.4

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[U-Boot] [UBOOT PATCH] clk: zynqmp: Fixed the same if/else part error reported by coverity

[Vipul Kumar]

This patch fixed the same if/else part error by adding the required
source select on the basis of is_pre_src check.

Signed-off-by: Vipul Kumar 
---
 drivers/clk/clk_zynqmp.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index a9e4500..167f3f7 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -103,6 +103,8 @@ static const resource_size_t zynqmp_crl_apb_clkc_base = 
0xff5e0020;
 #define PLLCTRL_BYPASS_SHFT3
 #define PLLCTRL_POST_SRC_SHFT  24
 #define PLLCTRL_POST_SRC_MASK  (0x7 << PLLCTRL_POST_SRC_SHFT)
+#define PLLCTRL_PRE_SRC_SHFT   20
+#define PLLCTRL_PRE_SRC_MASK   (0x7 << PLLCTRL_PRE_SRC_SHFT)


 #define NUM_MIO_PINS   77
@@ -310,8 +312,8 @@ static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
u32 src_sel;

if (is_pre_src)
-   src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
-  PLLCTRL_POST_SRC_SHFT;
+   src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >>
+  PLLCTRL_PRE_SRC_SHFT;
else
src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
   PLLCTRL_POST_SRC_SHFT;
--
2.7.4

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Delete this email message and any attachments immediately.
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Re: [U-Boot] [UBOOT PATCH v3 3/3] spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

[Vipul Kumar]

Hi Jagan,

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Monday, June 25, 2018 3:47 PM
> To: Vipul Kumar 
> Cc: U-Boot Mailing List ; Michal Simek
> 
> Subject: Re: [U-Boot] [UBOOT PATCH v3 3/3] spi: xilinx_spi: Added support to
> read JEDEC-id twice at the boot time
> 
> On Thu, Jun 21, 2018 at 2:53 PM, Vipul Kumar 
> wrote:
> > This patch is for the startup block issue in the spi controller.
> > SPI clock is passing through STARTUP block to FLASH. STARTUP block
> > don't provide clock as soon as QSPI provides command. So, first
> > command fails.
> 
> Does this a controller issue?

Yes, this is a controller issue.

> 
> >
> > This patch added support to read JEDEC id in xilinx_spi_xfer ().
> >
> > Signed-off-by: Vipul Kumar 
> > ---
> > Changes in v3:
> > - No change
> > ---
> >  drivers/spi/xilinx_spi.c | 41
> > +
> >  1 file changed, 41 insertions(+)
> >
> > diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index
> > 4026540..61301c2 100644
> > --- a/drivers/spi/xilinx_spi.c
> > +++ b/drivers/spi/xilinx_spi.c
> > @@ -204,6 +204,40 @@ static u32 xilinx_spi_read_rxfifo(struct udevice
> *bus, u8 *rxp, u32 rxbytes)
> > return i;
> >  }
> >
> > +static void xilinx_startup_block(struct udevice *dev, unsigned int bytes,
> > +const void *dout, void *din) {
> > +   struct udevice *bus = dev_get_parent(dev);
> > +   struct xilinx_spi_priv *priv = dev_get_priv(bus);
> > +   struct xilinx_spi_regs *regs = priv->regs;
> > +   struct dm_spi_slave_platdata *slave_plat =
> dev_get_parent_platdata(dev);
> > +   const unsigned char *txp = dout;
> > +   unsigned char *rxp = din;
> > +   static int startup;
> > +   u32 reg, count;
> > +   u32 txbytes = bytes;
> > +   u32 rxbytes = bytes;
> > +
> > +   /*
> > +* This loop runs two times. First time to send the command.
> > +* Second time to transfer data. After transferring data,
> > +* it sets txp to the initial value for the normal operation.
> > +*/
> > +   for ( ; startup < 2; startup++) {
> > +   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
> > +   reg = readl(>spicr) & ~SPICR_MASTER_INHIBIT;
> > +   writel(reg, >spicr);
> > +   count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
> > +   txp = din;
> > +
> > +   if (startup) {
> > +   spi_cs_deactivate(dev);
> > +   spi_cs_activate(dev, slave_plat->cs);
> > +   txp = dout;
> > +   }
> > +   }
> > +}
> > +
> >  static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
> > const void *dout, void *din, unsigned long
> > flags)  { @@ -236,6 +270,13 @@ static int xilinx_spi_xfer(struct
> > udevice *dev, unsigned int bitlen,
> > if (flags & SPI_XFER_BEGIN)
> > spi_cs_activate(dev, slave_plat->cs);
> >
> > +   /*
> > +* This is the work around for the startup block issue in
> > +* the spi controller. SPI clock is passing through STARTUP
> > +* block to FLASH. STARTUP block don't provide clock as soon
> > +* as QSPI provides command. So first command fails.
> > +*/
> > +   xilinx_startup_block(dev, bytes, dout, din);
> 
> But not every spi_xfer from flash side is to read JEDEC ID? during probe of 
> sf,
> the relevant spi_xfer is to read JEDEC ID

Inside xilinx_startup_block() function, we are using static variable, so that 
code will execute only first time.

Regards,
Vipul
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[U-Boot] [UBOOT PATCH v3 2/3] spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function

[Vipul Kumar]

This patch modify xilinx_spi_xfer() function and add rxfifo() and
txfifo() functions to add the modularity so that these functions
can be used by other functions within the same file.

This patch also added support to read fifo_size from dts.

Signed-off-by: Vipul Kumar 
Signed-off-by: Siva Durga Prasad Paladugu 
---
- Changes in v3:
- Added fifo_depth read support and removed from 1/3
---
 drivers/spi/xilinx_spi.c | 102 +++
 1 file changed, 67 insertions(+), 35 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index cc5ac51..4026540 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 

 /*
  * [0]: http://www.xilinx.com/support/documentation
@@ -77,6 +78,8 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif

+#define XILINX_SPISR_TIMEOUT   1 /* in milliseconds */
+
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -101,6 +104,7 @@ struct xilinx_spi_priv {
struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+   unsigned int fifo_depth;
 };

 static int xilinx_spi_probe(struct udevice *bus)
@@ -110,6 +114,9 @@ static int xilinx_spi_probe(struct udevice *bus)

priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);

+   priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
+ "fifo-size", 0);
+
writel(SPISSR_RESET_VALUE, >srr);

return 0;
@@ -157,6 +164,46 @@ static int xilinx_spi_release_bus(struct udevice *dev)
return 0;
 }

+static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
+ u32 txbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   u32 i = 0;
+
+   while (txbytes && !(readl(>spisr) & SPISR_TX_FULL) &&
+  i < priv->fifo_depth) {
+   d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+   debug("spi_xfer: tx:%x ", d);
+   /* write out and wait for processing (receive data) */
+   writel(d & SPIDTR_8BIT_MASK, >spidtr);
+   txbytes--;
+   i++;
+   }
+   return i;
+}
+
+static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   unsigned int i = 0;
+
+   while (rxbytes && !(readl(>spisr) & SPISR_RX_EMPTY)) {
+   d = readl(>spidrr) & SPIDRR_8BIT_MASK;
+   if (rxp)
+   *rxp++ = d;
+   debug("spi_xfer: rx:%x\n", d);
+   rxbytes--;
+   i++;
+   }
+   debug("Rx_done\n");
+
+   return i;
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -168,8 +215,10 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
unsigned char *rxp = din;
-   unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
-   unsigned global_timeout;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+   u32 reg, count, timeout;
+   int ret;

debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
  bus->seq, slave_plat->cs, bitlen, bytes, flags);
@@ -184,48 +233,31 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
goto done;
}

-   /* empty read buffer */
-   while (rxecount && !(readl(>spisr) & SPISR_RX_EMPTY)) {
-   readl(>spidrr);
-   rxecount--;
-   }
-
-   if (!rxecount) {
-   printf("XILSPI error: Rx buffer not empty\n");
-   return -1;
-   }
-
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);

-   /* at least 1usec or greater, leftover 1 */
-   global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 100 ? 2 :
-   (XILSPI_MAX_XFER_BITS * 100 / priv->freq) + 1;

-   while (bytes--) {
-   unsigned timeout = global_timeout;
-   /* get Tx element from data out buffer and count up */
-   unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
-   debug("spi_xfer: tx:%x ", d);
+   while (txbytes && rxbytes) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);

[U-Boot] [UBOOT PATCH v3 3/3] spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

[Vipul Kumar]

This patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.

This patch added support to read JEDEC id in xilinx_spi_xfer ().

Signed-off-by: Vipul Kumar 
---
Changes in v3:
- No change
---
 drivers/spi/xilinx_spi.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 4026540..61301c2 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -204,6 +204,40 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 
*rxp, u32 rxbytes)
return i;
 }

+static void xilinx_startup_block(struct udevice *dev, unsigned int bytes,
+const void *dout, void *din)
+{
+   struct udevice *bus = dev_get_parent(dev);
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   const unsigned char *txp = dout;
+   unsigned char *rxp = din;
+   static int startup;
+   u32 reg, count;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+
+   /*
+* This loop runs two times. First time to send the command.
+* Second time to transfer data. After transferring data,
+* it sets txp to the initial value for the normal operation.
+*/
+   for ( ; startup < 2; startup++) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   reg = readl(>spicr) & ~SPICR_MASTER_INHIBIT;
+   writel(reg, >spicr);
+   count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
+   txp = din;
+
+   if (startup) {
+   spi_cs_deactivate(dev);
+   spi_cs_activate(dev, slave_plat->cs);
+   txp = dout;
+   }
+   }
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -236,6 +270,13 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);

+   /*
+* This is the work around for the startup block issue in
+* the spi controller. SPI clock is passing through STARTUP
+* block to FLASH. STARTUP block don't provide clock as soon
+* as QSPI provides command. So first command fails.
+*/
+   xilinx_startup_block(dev, bytes, dout, din);

while (txbytes && rxbytes) {
count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
--
2.7.4

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[U-Boot] [UBOOT PATCH v3 0/3] spi:xilinx_spi: Modify xilinx spi driver

[Vipul Kumar]

This series of patches do the following:
- This patch added support to get reg base address from DTS file
- Added rxfifo() and txfifo() functions to add the modularity
- Added support to read JEDEC-id twice at the boot time

Changes in v2:
- Split single patch into the series of patches

Changes in V3:
- Read reg in probe function
- Removed xilinx_spi_ofdata_to_platdata function
- Added fifo_depth read support in 2/3 and removed from 1/3

Michal Simek (1):
  spi: xilinx: Read reg base address from DTS file

Vipul Kumar (2):
  spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function
  spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

 drivers/spi/xilinx_spi.c | 153 ++-
 1 file changed, 111 insertions(+), 42 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH v3 1/3] spi: xilinx: Read reg base address from DTS file

[Vipul Kumar]

From: Michal Simek 

This patch added support to read register base address
from DTS file.

Signed-off-by: Michal Simek 
Signed-off-by: Vipul Kumar 
---
Changes in v3:
- Read reg in probe function
- Removed xilinx_spi_ofdata_to_platdata function
- Removed reading of fifo_depth
---
 drivers/spi/xilinx_spi.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8f0f32f..cc5ac51 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -77,10 +77,6 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif

-#ifndef CONFIG_SYS_XILINX_SPI_LIST
-#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
-#endif
-
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -107,13 +103,12 @@ struct xilinx_spi_priv {
unsigned int mode;
 };

-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
 static int xilinx_spi_probe(struct udevice *bus)
 {
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;

-   priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
+   priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);

writel(SPISSR_RESET_VALUE, >srr);

--
2.7.4

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Re: [U-Boot] [UBOOT PATCH v2 0/3] spi:xilinx_spi: Modify xilinx spi driver

[Vipul Kumar]

Hi Jagan,

Do you have any comment on this series of patch ?

Regards,
Vipul

> -Original Message-
> From: Vipul Kumar [mailto:vipul.ku...@xilinx.com]
> Sent: Tuesday, June 12, 2018 11:34 AM
> To: u-boot@lists.denx.de
> Cc: michal.si...@xilinx.com; Siva Durga Prasad Paladugu
> ; ja...@openedev.com; Vipul Kumar
> 
> Subject: [UBOOT PATCH v2 0/3] spi:xilinx_spi: Modify xilinx spi driver
> 
> This series of patches do the following:
> - This patch added support to get reg base address from DTS file
> - Added rxfifo() and txfifo() functions to add the modularity
> - Added support to read JEDEC-id twice at the boot time
> 
> Changes in v2:
> - Split single patch into the series of patches
> 
> Michal Simek (1):
>   spi: xilinx: Read reg base address from DTS file
> 
> Vipul Kumar (2):
>   spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function
>   spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time
> 
>  drivers/spi/xilinx_spi.c | 165 +++--
> --
>  1 file changed, 122 insertions(+), 43 deletions(-)
> 
> --
> 2.7.4

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Re: [U-Boot] Issue with fat16 format

[Vipul Kumar]

Hi Heinrich,

> -Original Message-
> From: Heinrich Schuchardt [mailto:xypron.deb...@gmx.de]
> Sent: Sunday, June 17, 2018 1:07 AM
> To: Vipul Kumar ; u-boot@lists.denx.de
> Cc: Michal Simek ; Siva Durga Prasad Paladugu
> ; Rob Clark ; Łukasz Majewski
> ; Simon Glass 
> Subject: Re: [U-Boot] Issue with fat16 format
> 
> On 06/15/2018 08:37 AM, Vipul Kumar wrote:
> > Hi,
> >
> > After formatting SD card in fat16 format in windows, we are facing issue. I
> used git bisect and came to know that this issue is due to
> 8eafae209c35932d9a6560809c55ee4641534236 commit.
> >
> > When we use "gparted" utility for formatting SD card in fat16 in linux, it
> works fine.
> >
> > Please give your comments on this issue and point out what's causing this
> issue.
> >
> > Regards,
> > Vipul Kumar
> >
> >
> 
> Hello Vipul,
> 
> >> we are facing issue
> could you, please, indicate what issue you face. Please, also tell which
> configuration file you are using.

Configuration file: zynq_zc702_defconfig

Issue: We are using BOOT.BIN and fit image (Kernel image + dtb + rootfs) to 
boot the board. Board is booting till u-boot successfully but when it goes to 
read image.ub   for further booting, it gives below message:

ERROR: 
Hit any key to stop autoboot:  0 
Copying FIT from SD to RAM...
** Unable to read file image.ub ** 

After this, I run the fatls command and it seems that it removed both BOOT.BIN 
and image.ub files.

Zynq> mmc info
Device: sdhci@e010
Manufacturer ID: 27
OEM: 5048
Name: SD04G 
Bus Speed: 5000
Mode : SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 3.7 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes

Zynq> fatls mmc 0:1

0 file(s), 0 dir(s)

Zynq>


Regards,
Vipul
> 
> As you are complaining about Rob's patch I put him and the reviewers of the
> patch on CC.
> 
> Best regards
> 
> Heinrich
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[U-Boot] Issue with fat16 format

[Vipul Kumar]

Hi,

After formatting SD card in fat16 format in windows, we are facing issue. I 
used git bisect and came to know that this issue is due to 
8eafae209c35932d9a6560809c55ee4641534236 commit.

When we use "gparted" utility for formatting SD card in fat16 in linux, it 
works fine.

Please give your comments on this issue and point out what's causing this issue.

Regards,
Vipul Kumar


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[U-Boot] [UBOOT PATCH] spi: zynq_qspi: Fixed incorrect return value error

[Vipul Kumar]

This patch replaced "return 0" with "return status" to fix the
incorrect return value error reported by the coverity.

Signed-off-by: Vipul Kumar 
---
 drivers/spi/zynq_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index ee8796d..9ad1927 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -486,7 +486,7 @@ static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
break;
}

-   return 0;
+   return status;
 }

 static int zynq_qspi_claim_bus(struct udevice *dev)
--
2.7.4

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[U-Boot] [UBOOT PATCH v2 3/3] spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

[Vipul Kumar]

This patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.

This patch added support to read JEDEC id in xilinx_spi_xfer ().

Signed-off-by: Vipul Kumar 
---
 drivers/spi/xilinx_spi.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 70a110a..08c2883 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -199,6 +199,40 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 
*rxp, u32 rxbytes)
return i;
 }

+static void xilinx_startup_block(struct udevice *dev, unsigned int bytes,
+const void *dout, void *din)
+{
+   struct udevice *bus = dev_get_parent(dev);
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   const unsigned char *txp = dout;
+   unsigned char *rxp = din;
+   static int startup;
+   u32 reg, count;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+
+   /*
+* This loop runs two times. First time to send the command.
+* Second time to transfer data. After transferring data,
+* it sets txp to the initial value for the normal operation.
+*/
+   for ( ; startup < 2; startup++) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   reg = readl(>spicr) & ~SPICR_MASTER_INHIBIT;
+   writel(reg, >spicr);
+   count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
+   txp = din;
+
+   if (startup) {
+   spi_cs_deactivate(dev);
+   spi_cs_activate(dev, slave_plat->cs);
+   txp = dout;
+   }
+   }
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -231,6 +265,13 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);

+   /*
+* This is the work around for the startup block issue in
+* the spi controller. SPI clock is passing through STARTUP
+* block to FLASH. STARTUP block don't provide clock as soon
+* as QSPI provides command. So first command fails.
+*/
+   xilinx_startup_block(dev, bytes, dout, din);

while (txbytes && rxbytes) {
count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
--
2.7.4

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[U-Boot] [UBOOT PATCH v2 2/3] spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function

[Vipul Kumar]

This patch modify xilinx_spi_xfer() function and add rxfifo() and
txfifo() functions to add the modularity.

Signed-off-by: Vipul Kumar 
Signed-off-by: Siva Durga Prasad Paladugu 
---
 drivers/spi/xilinx_spi.c | 98 +++-
 1 file changed, 63 insertions(+), 35 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 615106b..70a110a 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 

 /*
  * [0]: http://www.xilinx.com/support/documentation
@@ -77,6 +78,8 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif

+#define XILINX_SPISR_TIMEOUT   1 /* in milliseconds */
+
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -156,6 +159,46 @@ static int xilinx_spi_release_bus(struct udevice *dev)
return 0;
 }

+static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
+ u32 txbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   u32 i = 0;
+
+   while (txbytes && !(readl(>spisr) & SPISR_TX_FULL) &&
+  i < priv->fifo_depth) {
+   d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+   debug("spi_xfer: tx:%x ", d);
+   /* write out and wait for processing (receive data) */
+   writel(d & SPIDTR_8BIT_MASK, >spidtr);
+   txbytes--;
+   i++;
+   }
+   return i;
+}
+
+static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   unsigned int i = 0;
+
+   while (rxbytes && !(readl(>spisr) & SPISR_RX_EMPTY)) {
+   d = readl(>spidrr) & SPIDRR_8BIT_MASK;
+   if (rxp)
+   *rxp++ = d;
+   debug("spi_xfer: rx:%x\n", d);
+   rxbytes--;
+   i++;
+   }
+   debug("Rx_done\n");
+
+   return i;
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -167,8 +210,10 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
unsigned char *rxp = din;
-   unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
-   unsigned global_timeout;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+   u32 reg, count, timeout;
+   int ret;

debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
  bus->seq, slave_plat->cs, bitlen, bytes, flags);
@@ -183,48 +228,31 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
goto done;
}

-   /* empty read buffer */
-   while (rxecount && !(readl(>spisr) & SPISR_RX_EMPTY)) {
-   readl(>spidrr);
-   rxecount--;
-   }
-
-   if (!rxecount) {
-   printf("XILSPI error: Rx buffer not empty\n");
-   return -1;
-   }
-
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);

-   /* at least 1usec or greater, leftover 1 */
-   global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 100 ? 2 :
-   (XILSPI_MAX_XFER_BITS * 100 / priv->freq) + 1;

-   while (bytes--) {
-   unsigned timeout = global_timeout;
-   /* get Tx element from data out buffer and count up */
-   unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
-   debug("spi_xfer: tx:%x ", d);
-
-   /* write out and wait for processing (receive data) */
-   writel(d & SPIDTR_8BIT_MASK, >spidtr);
-   while (timeout && readl(>spisr)
-   & SPISR_RX_EMPTY) {
-   timeout--;
-   udelay(1);
-   }
+   while (txbytes && rxbytes) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   reg = readl(>spicr) & ~SPICR_MASTER_INHIBIT;
+   writel(reg, >spicr);
+   txbytes -= count;
+   if (txp)
+   txp += count;

-   if (!timeout) {
+   ret = wait_for_bit_le32(>spisr, SPISR_TX_EMPTY, true,
+   XILINX_SPISR_TIMEOUT, false);
+   if (ret < 0) {
printf("

[U-Boot] [UBOOT PATCH v2 0/3] spi:xilinx_spi: Modify xilinx spi driver

[Vipul Kumar]

This series of patches do the following:
- This patch added support to get reg base address from DTS file
- Added rxfifo() and txfifo() functions to add the modularity
- Added support to read JEDEC-id twice at the boot time

Changes in v2:
- Split single patch into the series of patches

Michal Simek (1):
  spi: xilinx: Read reg base address from DTS file

Vipul Kumar (2):
  spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function
  spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

 drivers/spi/xilinx_spi.c | 165 +++
 1 file changed, 122 insertions(+), 43 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH v2 1/3] spi: xilinx: Read reg base address from DTS file

[Vipul Kumar]

From: Michal Simek 

This patch added support to read register base address
from DTS file.

Signed-off-by: Michal Simek 
Signed-off-by: Vipul Kumar 
---
 drivers/spi/xilinx_spi.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8f0f32f..615106b 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -77,10 +77,6 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif

-#ifndef CONFIG_SYS_XILINX_SPI_LIST
-#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
-#endif
-
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -105,16 +101,14 @@ struct xilinx_spi_priv {
struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+   unsigned int fifo_depth;
 };

-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
 static int xilinx_spi_probe(struct udevice *bus)
 {
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;

-   priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
-
writel(SPISSR_RESET_VALUE, >srr);

return 0;
@@ -285,6 +279,21 @@ static const struct dm_spi_ops xilinx_spi_ops = {
.set_mode   = xilinx_spi_set_mode,
 };

+static int xilinx_spi_ofdata_to_platdata(struct udevice *bus)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct udevice *dev = dev_get_parent(bus);
+
+   priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
+
+   debug("%s: regs=%p\n", __func__, priv->regs);
+
+   priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
+ "fifo-size", 0);
+
+   return 0;
+}
+
 static const struct udevice_id xilinx_spi_ids[] = {
{ .compatible = "xlnx,xps-spi-2.00.a" },
{ .compatible = "xlnx,xps-spi-2.00.b" },
@@ -296,6 +305,7 @@ U_BOOT_DRIVER(xilinx_spi) = {
.id = UCLASS_SPI,
.of_match = xilinx_spi_ids,
.ops= _spi_ops,
+   .ofdata_to_platdata = xilinx_spi_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
.probe  = xilinx_spi_probe,
 };
--
2.7.4

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recipient(s) and contain(s) confidential information that may be proprietary, 
privileged or copyrighted under applicable law. If you are not the intended 
recipient, do not read, copy, or forward this email message or any attachments. 
Delete this email message and any attachments immediately.
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[U-Boot] [UBOOT PATCH] usb: dwc3: convert to livetree

[Vipul Kumar]

Update the DWC3 USB driver to support a live tree.

Signed-off-by: Vipul Kumar 
---
 drivers/usb/common/common.c | 11 +--
 drivers/usb/dwc3/dwc3-generic.c | 17 +++--
 drivers/usb/host/xhci-dwc3.c|  3 ++-
 drivers/usb/host/xhci-zynqmp.c  |  3 +--
 include/linux/usb/otg.h |  6 --
 5 files changed, 19 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
index a55def5..3dea79b 100644
--- a/drivers/usb/common/common.c
+++ b/drivers/usb/common/common.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 

 DECLARE_GLOBAL_DATA_PTR;

@@ -20,13 +21,12 @@ static const char *const usb_dr_modes[] = {
[USB_DR_MODE_OTG]   = "otg",
 };

-enum usb_dr_mode usb_get_dr_mode(int node)
+enum usb_dr_mode usb_get_dr_mode(ofnode node)
 {
-   const void *fdt = gd->fdt_blob;
const char *dr_mode;
int i;

-   dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
+   dr_mode = ofnode_get_property(node, "dr_mode", NULL);
if (!dr_mode) {
pr_err("usb dr_mode not found\n");
return USB_DR_MODE_UNKNOWN;
@@ -48,13 +48,12 @@ static const char *const speed_names[] = {
[USB_SPEED_SUPER] = "super-speed",
 };

-enum usb_device_speed usb_get_maximum_speed(int node)
+enum usb_device_speed usb_get_maximum_speed(ofnode node)
 {
-   const void *fdt = gd->fdt_blob;
const char *max_speed;
int i;

-   max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
+   max_speed = ofnode_get_property(node, "maximum-speed", NULL);
if (!max_speed) {
pr_err("usb maximum-speed not found\n");
return USB_SPEED_UNKNOWN;
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index ca63eac..ef72c8c 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -61,18 +61,17 @@ static int dwc3_generic_peripheral_remove(struct udevice 
*dev)
 static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
 {
struct dwc3 *priv = dev_get_priv(dev);
-   int node = dev_of_offset(dev);

-   priv->regs = (void *)devfdt_get_addr(dev);
+   priv->regs = (void *)dev_read_addr(dev);
priv->regs += DWC3_GLOBALS_REGS_START;

-   priv->maximum_speed = usb_get_maximum_speed(node);
+   priv->maximum_speed = usb_get_maximum_speed(dev->node);
if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
pr_err("Invalid usb maximum speed\n");
return -ENODEV;
}

-   priv->dr_mode = usb_get_dr_mode(node);
+   priv->dr_mode = usb_get_dr_mode(dev->node);
if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
pr_err("Invalid usb mode setup\n");
return -ENODEV;
@@ -100,13 +99,11 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {

 static int dwc3_generic_bind(struct udevice *parent)
 {
-   const void *fdt = gd->fdt_blob;
-   int node;
+   ofnode node;
int ret;

-   for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
-node = fdt_next_subnode(fdt, node)) {
-   const char *name = fdt_get_name(fdt, node, NULL);
+   dev_for_each_subnode(node, parent) {
+   const char *name = (char *)ofnode_get_name(node);
enum usb_dr_mode dr_mode;
struct udevice *dev;
const char *driver;
@@ -133,7 +130,7 @@ static int dwc3_generic_bind(struct udevice *parent)
};

ret = device_bind_driver_to_node(parent, driver, name,
-offset_to_ofnode(node), );
+node, );
if (ret) {
debug("%s: not able to bind usb device mode\n",
  __func__);
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 80754d7..cbab436 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -202,6 +202,7 @@ static int xhci_dwc3_probe(struct udevice *dev)
struct dwc3 *dwc3_reg;
enum usb_dr_mode dr_mode;
int ret;
+   ofnode node;

hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
hcor = (struct xhci_hcor *)((uintptr_t)hccr +
@@ -215,7 +216,7 @@ static int xhci_dwc3_probe(struct udevice *dev)

dwc3_core_init(dwc3_reg);

-   dr_mode = usb_get_dr_mode(dev_of_offset(dev));
+   dr_mode = usb_get_dr_mode(node);
if (dr_mode == USB_DR_MODE_UNKNOWN)
/* by default set dual role mode to HOST */
dr_mode = USB_DR_MODE_HOST;
diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c
index e44e1ae..5a5b870 100644

Re: [U-Boot] [UBOOT PATCH] spi: xilinx_spi: Modify xilinx spi driver

[Vipul Kumar]

Hi Jagan,

Do you have any comments on this? If not, could you please take it up.

Thanks,
Vipul

> -Original Message-
> From: Vipul Kumar [mailto:vipul.ku...@xilinx.com]
> Sent: Monday, May 28, 2018 6:06 PM
> To: u-boot@lists.denx.de
> Cc: michal.si...@xilinx.com; Siva Durga Prasad Paladugu
> ; Vipul Kumar 
> Subject: [UBOOT PATCH] spi: xilinx_spi: Modify xilinx spi driver
> 
> This patch added support to get reg base address from DTS file and added
> rxfifo() and txfifo() functions to add the modularity.
> 
> Also, this patch is for the startup block issue in the spi controller.
> SPI clock is passing through STARTUP block to FLASH. STARTUP block don't
> provide clock as soon as QSPI provides command. So, first command fails.
> 
> This patch added support to read JEDEC id in xilinx_spi_xfer () before
> performing the spi operations.
> 
> Signed-off-by: Vipul Kumar 
> ---
>  drivers/spi/xilinx_spi.c | 161 +++--
> --
>  1 file changed, 121 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index
> 8f0f32f..12097ce 100644
> --- a/drivers/spi/xilinx_spi.c
> +++ b/drivers/spi/xilinx_spi.c
> @@ -77,10 +77,6 @@
>  #define CONFIG_XILINX_SPI_IDLE_VAL   GENMASK(7, 0)
>  #endif
> 
> -#ifndef CONFIG_SYS_XILINX_SPI_LIST
> -#define CONFIG_SYS_XILINX_SPI_LIST   { CONFIG_SYS_SPI_BASE }
> -#endif
> -
>  /* xilinx spi register set */
>  struct xilinx_spi_regs {
>   u32 __space0__[7];
> @@ -105,16 +101,14 @@ struct xilinx_spi_priv {
>   struct xilinx_spi_regs *regs;
>   unsigned int freq;
>   unsigned int mode;
> + unsigned int fifo_depth;
>  };
> 
> -static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
> static int xilinx_spi_probe(struct udevice *bus)  {
>   struct xilinx_spi_priv *priv = dev_get_priv(bus);
>   struct xilinx_spi_regs *regs = priv->regs;
> 
> - priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
> -
>   writel(SPISSR_RESET_VALUE, >srr);
> 
>   return 0;
> @@ -134,8 +128,12 @@ static void spi_cs_deactivate(struct udevice *dev)
>   struct udevice *bus = dev_get_parent(dev);
>   struct xilinx_spi_priv *priv = dev_get_priv(bus);
>   struct xilinx_spi_regs *regs = priv->regs;
> + u32 reg;
> 
> + reg = readl(>spicr) | SPICR_RXFIFO_RESEST |
> SPICR_TXFIFO_RESEST;
> + writel(reg, >spicr);
>   writel(SPISSR_OFF, >spissr);
> +
>  }
> 
>  static int xilinx_spi_claim_bus(struct udevice *dev) @@ -162,6 +160,80 @@
> static int xilinx_spi_release_bus(struct udevice *dev)
>   return 0;
>  }
> 
> +static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
> +   u32 txbytes)
> +{
> + struct xilinx_spi_priv *priv = dev_get_priv(bus);
> + struct xilinx_spi_regs *regs = priv->regs;
> + unsigned char d;
> + u32 i = 0;
> +
> + while (txbytes && !(readl(>spisr) & SPISR_TX_FULL) &&
> +i < priv->fifo_depth) {
> + d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
> + debug("spi_xfer: tx:%x ", d);
> + /* write out and wait for processing (receive data) */
> + writel(d & SPIDTR_8BIT_MASK, >spidtr);
> + txbytes--;
> + i++;
> + }
> + return i;
> +}
> +
> +static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32
> +rxbytes) {
> + struct xilinx_spi_priv *priv = dev_get_priv(bus);
> + struct xilinx_spi_regs *regs = priv->regs;
> + unsigned char d;
> + unsigned int i = 0;
> +
> + while (rxbytes && !(readl(>spisr) & SPISR_RX_EMPTY)) {
> + d = readl(>spidrr) & SPIDRR_8BIT_MASK;
> + if (rxp)
> + *rxp++ = d;
> + debug("spi_xfer: rx:%x\n", d);
> + rxbytes--;
> + i++;
> + }
> + debug("Rx_done\n");
> +
> + return i;
> +}
> +
> +static void xilinx_startup_block(struct udevice *dev, unsigned int bytes,
> +  const void *dout, void *din)
> +{
> + struct udevice *bus = dev_get_parent(dev);
> + struct xilinx_spi_priv *priv = dev_get_priv(bus);
> + struct xilinx_spi_regs *regs = priv->regs;
> + struct dm_spi_slave_platdata *slave_plat =
> dev_get_parent_platdata(dev);
> + const unsigned char *txp = dout;
> + unsigned char *rxp = din;
> + static int startup;
> + u32 reg, count;
> + u32 txbytes = bytes;
> + u32 rxbyte

[U-Boot] [UBOOT PATCH] spi: xilinx_spi: Modify xilinx spi driver

[Vipul Kumar]

This patch added support to get reg base address from DTS file
and added rxfifo() and txfifo() functions to add the modularity.

Also, this patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.

This patch added support to read JEDEC id in xilinx_spi_xfer ()
before performing the spi operations.

Signed-off-by: Vipul Kumar <vipul.ku...@xilinx.com>
---
 drivers/spi/xilinx_spi.c | 161 +++
 1 file changed, 121 insertions(+), 40 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8f0f32f..12097ce 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -77,10 +77,6 @@
 #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif

-#ifndef CONFIG_SYS_XILINX_SPI_LIST
-#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
-#endif
-
 /* xilinx spi register set */
 struct xilinx_spi_regs {
u32 __space0__[7];
@@ -105,16 +101,14 @@ struct xilinx_spi_priv {
struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+   unsigned int fifo_depth;
 };

-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
 static int xilinx_spi_probe(struct udevice *bus)
 {
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;

-   priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
-
writel(SPISSR_RESET_VALUE, >srr);

return 0;
@@ -134,8 +128,12 @@ static void spi_cs_deactivate(struct udevice *dev)
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
+   u32 reg;

+   reg = readl(>spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST;
+   writel(reg, >spicr);
writel(SPISSR_OFF, >spissr);
+
 }

 static int xilinx_spi_claim_bus(struct udevice *dev)
@@ -162,6 +160,80 @@ static int xilinx_spi_release_bus(struct udevice *dev)
return 0;
 }

+static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
+ u32 txbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   u32 i = 0;
+
+   while (txbytes && !(readl(>spisr) & SPISR_TX_FULL) &&
+  i < priv->fifo_depth) {
+   d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+   debug("spi_xfer: tx:%x ", d);
+   /* write out and wait for processing (receive data) */
+   writel(d & SPIDTR_8BIT_MASK, >spidtr);
+   txbytes--;
+   i++;
+   }
+   return i;
+}
+
+static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
+{
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   unsigned char d;
+   unsigned int i = 0;
+
+   while (rxbytes && !(readl(>spisr) & SPISR_RX_EMPTY)) {
+   d = readl(>spidrr) & SPIDRR_8BIT_MASK;
+   if (rxp)
+   *rxp++ = d;
+   debug("spi_xfer: rx:%x\n", d);
+   rxbytes--;
+   i++;
+   }
+   debug("Rx_done\n");
+
+   return i;
+}
+
+static void xilinx_startup_block(struct udevice *dev, unsigned int bytes,
+const void *dout, void *din)
+{
+   struct udevice *bus = dev_get_parent(dev);
+   struct xilinx_spi_priv *priv = dev_get_priv(bus);
+   struct xilinx_spi_regs *regs = priv->regs;
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   const unsigned char *txp = dout;
+   unsigned char *rxp = din;
+   static int startup;
+   u32 reg, count;
+   u32 txbytes = bytes;
+   u32 rxbytes = bytes;
+
+   /*
+* This loop runs two times. First time to send the command.
+* Second time to transfer data. After transferring data,
+* it sets txp to the initial value for the normal operation.
+*/
+   for ( ; startup < 2; startup++) {
+   count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+   reg = readl(>spicr) & ~SPICR_MASTER_INHIBIT;
+   writel(reg, >spicr);
+   count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
+   txp = din;
+
+   if (startup) {
+   spi_cs_deactivate(dev);
+   spi_cs_activate(dev, slave_plat->cs);
+   txp = dout;
+   }
+   }
+}
+
 static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
   

Re: [U-Boot] [UBOOT PATCH] env: mmc: Fix misaligned buffer address when saving envvars to FAT

[Vipul Kumar]

Hi,

> -Original Message-
> From: Alex Kiernan [mailto:alex.kier...@gmail.com]
> Sent: Thursday, May 17, 2018 1:31 PM
> To: Vipul Kumar <vip...@xilinx.com>
> Cc: u-boot <u-boot@lists.denx.de>; gmus...@ciena.com; Michal Simek
> <michal.si...@xilinx.com>; Siva Durga Prasad Paladugu
> <siva...@xilinx.com>
> Subject: Re: [U-Boot] [UBOOT PATCH] env: mmc: Fix misaligned buffer
> address when saving envvars to FAT
> 
> On Thu, May 17, 2018 at 8:46 AM Vipul Kumar <vipul.ku...@xilinx.com>
> wrote:
> 
> > From: Gary Mussar <gmus...@ciena.com>
> 
> > When doing a u-boot saveenv with the environment in FAT we see the
> > following warning:
> 
> > ZynqMP> saveenv
> > Saving Environment to FAT...
> > writing uboot.env
> > FAT: Misaligned buffer address (7deb9b60) done
> 
> > This can be eliminated by aligning the environment to an appropriate
> > boundary.
> 
> 
> Are you still seeing after this commit?

With cda87ec commit, it's working fine. I didn’t test with this commit earlier. 
So, there is no need of this patch.

Regards,
Vipul

> 
> cda87ec Fix misaligned buffer in env_fat_save
> 
> > Signed-off-by: Gary Mussar <gmus...@ciena.com>
> > Signed-off-by: Vipul Kumar <vipul.ku...@xilinx.com>
> > ---
> >   include/environment.h | 6 +-
> >   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> > diff --git a/include/environment.h b/include/environment.h index
> > 50c62c5..d6c530d 100644
> > --- a/include/environment.h
> > +++ b/include/environment.h
> > @@ -150,7 +150,11 @@ typedef struct environment_s {
> >  unsigned char   flags;  /* active/obsolete flags*/
> >   #endif
> >  unsigned char   data[ENV_SIZE]; /* Environment data */
> > -} env_t;
> > +} env_t
> > +#ifdef ARCH_DMA_MINALIGN
> > +__aligned(ARCH_DMA_MINALIGN)
> > +#endif
> > +;
> 
> >   #ifdef ENV_IS_EMBEDDED
> >   extern env_t environment;
> > --
> > 2.7.4
> 
> > This email and any attachments are intended for the sole use of the
> > named
> recipient(s) and contain(s) confidential information that may be proprietary,
> privileged or copyrighted under applicable law. If you are not the intended
> recipient, do not read, copy, or forward this email message or any
> attachments. Delete this email message and any attachments immediately.
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
> 
> 
> 
> --
> Alex Kiernan
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[U-Boot] [UBOOT PATCH] env: mmc: Fix misaligned buffer address when saving envvars to FAT

[Vipul Kumar]

From: Gary Mussar <gmus...@ciena.com>

When doing a u-boot saveenv with the environment in FAT we see the
following warning:

ZynqMP> saveenv
Saving Environment to FAT...
writing uboot.env
FAT: Misaligned buffer address (7deb9b60)
done

This can be eliminated by aligning the environment to an appropriate
boundary.

Signed-off-by: Gary Mussar <gmus...@ciena.com>
Signed-off-by: Vipul Kumar <vipul.ku...@xilinx.com>
---
 include/environment.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/environment.h b/include/environment.h
index 50c62c5..d6c530d 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -150,7 +150,11 @@ typedef struct environment_s {
unsigned char   flags;  /* active/obsolete flags*/
 #endif
unsigned char   data[ENV_SIZE]; /* Environment data */
-} env_t;
+} env_t
+#ifdef ARCH_DMA_MINALIGN
+__aligned(ARCH_DMA_MINALIGN)
+#endif
+;

 #ifdef ENV_IS_EMBEDDED
 extern env_t environment;
--
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[U-Boot] [UBOOT PATCH v3] microblaze: wdt: Added Kconfig support for CONFIG_XILINX_TB_WATCHDOG

[Vipul Kumar]

This patch added Kconfig support for CONFIG_XILINX_TB_WATCHDOG
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
Changes in v3:
- Removed select hw_watchdog
- Branch: u-boot-microblaze/kconfig
---
 configs/microblaze-generic_defconfig | 1 +
 drivers/watchdog/Kconfig | 6 ++
 include/configs/microblaze-generic.h | 1 -
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index 699dc44..fba3820 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -63,3 +63,4 @@ CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_SYS_NS16550=y
 CONFIG_XILINX_UARTLITE=y
+CONFIG_XILINX_TB_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index fc46b67..bd209fa 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -78,4 +78,10 @@ config WDT_ORION
   Select this to enable Orion watchdog timer, which can be found on 
some
   Marvell Armada chips.

+config XILINX_TB_WATCHDOG
+   bool "Xilinx watchdog timer support"
+   depends on MICROBLAZE && !SPL_BUILD
+   help
+ Available for Xilinx Axi platforms to service timebase watchdog timer.
+
 endmenu
diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index 73c3c2a..391b26a 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -50,7 +50,6 @@
 # define CONFIG_WATCHDOG_IRQ   XILINX_WATCHDOG_IRQ
 # ifndef CONFIG_SPL_BUILD
 #  define CONFIG_HW_WATCHDOG
-#  define CONFIG_XILINX_TB_WATCHDOG
 # endif
 #endif

--
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Re: [U-Boot] [UBOOT PATCH v2 2/2] arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI1

[Vipul Kumar]

Hi Jaehoon,

> -Original Message-
> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Sent: Wednesday, February 28, 2018 1:13 PM
> To: Vipul Kumar <vip...@xilinx.com>; u-boot@lists.denx.de
> Cc: Vipul Kumar <vip...@xilinx.com>; michal.si...@xilinx.com; Siva Durga
> Prasad Paladugu <siva...@xilinx.com>
> Subject: Re: [U-Boot] [UBOOT PATCH v2 2/2] arm64: zynqmp: mmc: Added
> Kconfig support for CONFIG_ZYNQ_SDHCI1
> 
> Hi,
> 
> On 02/28/2018 03:28 PM, Vipul Kumar wrote:
> > This patch added Kconfig support for CONFIG_ZYNQ_SDHCI1 and enabled it
> > in defconfig.
> 
> I think that CONFIG_ZYNQ_SDHCI1 is meaningful when
> CONFIG_ZYNQ_SDHCI0 is enabled.
> It's used in zynqmp.c and spl.c ..like below..
> 
> #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) 
> #endif
> 
> If CONFIG_ZYNQ_SDHCI0 isn't enabled, doesn't it need to set
> CONFIG_ZYNQ_SDHCI1 in defconfigs.
> 
> If i missed something, let me know, plz.

Even though CONFIG_ZYNQ_SDHCI0 is not enabled anywhere, this particular code in 
zynqmp.c and spl.c will
be needed if any of the custom boards have both SDHCI0 and SDHCI1 enabled as 
ZynqMP has two sd controllers.

Thanks,
Vipul.
> 
> Best Regards,
> Jaehoon Chung
> 
> >
> > Signed-off-by: Vipul Kumar <vip...@xilinx.com>
> > Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> > ---
> > - Changes in v2:
> > - Added depends on MMC_SDHCI_ZYNQ
> > - Branch: u-boot-microblaze/kconfig
> > ---
> >  arch/arm/cpu/armv8/zynqmp/Kconfig| 6 ++
> >  configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
> >  configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 +
> >  configs/xilinx_zynqmp_zcu102_revA_defconfig  | 1 +
> >  configs/xilinx_zynqmp_zcu102_revB_defconfig  | 1 +
> >  include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 1 -
> >  include/configs/xilinx_zynqmp_zcu102.h   | 1 -
> >  7 files changed, 10 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig
> > b/arch/arm/cpu/armv8/zynqmp/Kconfig
> > index 6eddea7..a903344 100644
> > --- a/arch/arm/cpu/armv8/zynqmp/Kconfig
> > +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
> > @@ -95,6 +95,12 @@ config ZYNQ_SDHCI0
> > help
> >   Enable the SDHCI0 controller for Xilinx ZynqMP.
> >
> > +config ZYNQ_SDHCI1
> > +   bool "Xilinx SDHCI1 controller"
> > +   depends on MMC_SDHCI_ZYNQ
> > +   help
> > + Enable the SDHCI1 controller for Xilinx ZynqMP.
> > +
> >  config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
> > bool "Overwrite SPL bootmode"
> > depends on SPL
> > diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> > b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> > index 05d98c0..be0e37f 100644
> > --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> > +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> > @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
> CONFIG_IDENT_STRING="
> > Xilinx ZynqMP ZC1751 xm015 dc1"
> >  CONFIG_ZYNQMP_USB=y
> >  CONFIG_ZYNQ_SDHCI0=y
> > +CONFIG_ZYNQ_SDHCI1=y
> >  CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
> >  CONFIG_DEBUG_UART=y
> >  CONFIG_AHCI=y
> > diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
> > b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
> > index 1df5b0b..67d3fa6 100644
> > --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
> > +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
> > @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
> >  CONFIG_SYS_MALLOC_F_LEN=0x8000
> >  CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
> >  CONFIG_ZYNQMP_USB=y
> > +CONFIG_ZYNQ_SDHCI1=y
> >  CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
> >  CONFIG_DEBUG_UART=y
> >  CONFIG_AHCI=y
> > diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig
> > b/configs/xilinx_zynqmp_zcu102_revA_defconfig
> > index c8a8362..76f7993 100644
> > --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
> > +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
> > @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
> >  CONFIG_SYS_MALLOC_F_LEN=0x8000
> >  CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
> >  CONFIG_ZYNQMP_USB=y
> > +CONFIG_ZYNQ_SDHCI1=y
> >  CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
> >  CONFIG_DEBUG_UART=y
> >  CONFIG_AHCI=y
> > diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig
> > b/configs/xilinx_

[U-Boot] [UBOOT PATCH v2 0/2] mmc: Added Kconfig support to set minimum and maximum frequency of the mmc controller

[Vipul Kumar]

This series of patch added Kconfig support for
CONFIG_ZYNQ_SDHCI_MAX_FREQ and CONFIG_ZYNQ_SDHCI_MIN_FREQ and
set the default values.

-Changes in V2:
-Set min. frequency for ep 100KHz
-Branch: u-boot-microblaze/kconfig

Vipul Kumar (2):
  mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
  mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ

 arch/arm/cpu/armv8/zynqmp/Kconfig  |  3 +++
 arch/arm/mach-zynq/Kconfig |  3 +++
 configs/xilinx_zynqmp_ep_defconfig |  2 ++
 drivers/mmc/Kconfig| 13 +
 drivers/mmc/zynq_sdhci.c   |  4 
 include/configs/xilinx_zynqmp.h|  3 ---
 include/configs/xilinx_zynqmp_ep.h |  2 --
 include/configs/zynq-common.h  |  5 -
 8 files changed, 21 insertions(+), 14 deletions(-)

--
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[U-Boot] [UBOOT PATCH v2 2/2] mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in v2:
- Set min. frequency for ep 100KHz
- Branch: u-boot-microblaze/kconfig
---
 configs/xilinx_zynqmp_ep_defconfig | 1 +
 drivers/mmc/Kconfig| 7 +++
 drivers/mmc/zynq_sdhci.c   | 4 
 include/configs/xilinx_zynqmp_ep.h | 1 -
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index 00db5e3..a0c8f28 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -62,6 +62,7 @@ CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_SDHCI_MIN_FREQ=10
 CONFIG_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 42b7d21..4f2993c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -478,6 +478,13 @@ config ZYNQ_SDHCI_MAX_FREQ
help
  Set the maximum frequency for the SDHCI controller.

+config ZYNQ_SDHCI_MIN_FREQ
+   int "Set the minimum frequencyof the controller"
+   depends on MMC_SDHCI_ZYNQ
+   default 0
+   help
+ Set the minimum frequencyof the controller.
+
 config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 0fddb42..414778c 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -16,10 +16,6 @@

 DECLARE_GLOBAL_DATA_PTR;

-#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
-# define CONFIG_ZYNQ_SDHCI_MIN_FREQ0
-#endif
-
 struct arasan_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
diff --git a/include/configs/xilinx_zynqmp_ep.h 
b/include/configs/xilinx_zynqmp_ep.h
index a77eeea..a26377a 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_ZYNQMP_EP_H
 #define __CONFIG_ZYNQMP_EP_H

-#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
 ZYNQMP_USB1_XHCI_BASEADDR}
--
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[U-Boot] [UBOOT PATCH v2 1/2] mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 arch/arm/cpu/armv8/zynqmp/Kconfig  | 3 +++
 arch/arm/mach-zynq/Kconfig | 3 +++
 configs/xilinx_zynqmp_ep_defconfig | 1 +
 drivers/mmc/Kconfig| 6 ++
 include/configs/xilinx_zynqmp.h| 3 ---
 include/configs/xilinx_zynqmp_ep.h | 1 -
 include/configs/zynq-common.h  | 5 -
 7 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig 
b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 9e521ed..8a311e1 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -96,6 +96,9 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
  Overwrite bootmode selected via boot mode pins to tell SPL what should
  be the next boot device.

+config ZYNQ_SDHCI_MAX_FREQ
+   default 2
+
 config SPL_ZYNQMP_ALT_BOOTMODE
hex
default 0x0 if JTAG_MODE
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index b9cd45b..8772904 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -63,4 +63,7 @@ config BOOT_INIT_FILE
  Add register writes to boot.bin format (max 256 pairs).
  Expect a table of register-value pairs, e.g. "0x12345678 0x4321"

+config ZYNQ_SDHCI_MAX_FREQ
+   default 5200
+
 endif
diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index 7f8e774..00db5e3 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=5200
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
 CONFIG_DEBUG_UART=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f2d8256..42b7d21 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -472,6 +472,12 @@ config MMC_SDHCI_ZYNQ
help
  Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs 
platform

+config ZYNQ_SDHCI_MAX_FREQ
+   int "Set the maximum frequency of cotroller"
+   depends on MMC_SDHCI_ZYNQ
+   help
+ Set the maximum frequency for the SDHCI controller.
+
 config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 825af80..f5fc245 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -56,9 +56,6 @@

 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define CONFIG_SUPPORT_EMMC_BOOT
-# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
-#  define CONFIG_ZYNQ_SDHCI_MAX_FREQ   2
-# endif
 #endif

 #ifdef CONFIG_NAND_ARASAN
diff --git a/include/configs/xilinx_zynqmp_ep.h 
b/include/configs/xilinx_zynqmp_ep.h
index 3a572b7..a77eeea 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_ZYNQMP_EP_H
 #define __CONFIG_ZYNQMP_EP_H

-#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 5200
 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 0ebb66b..554fb66 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -73,11 +73,6 @@
 #define CONFIG_MTD_DEVICE
 #endif

-/* MMC */
-#if defined(CONFIG_MMC_SDHCI_ZYNQ)
-# define CONFIG_ZYNQ_SDHCI_MAX_FREQ5200
-#endif
-
 #ifdef CONFIG_USB_EHCI_ZYNQ
 # define CONFIG_EHCI_IS_TDI

--
2.7.4

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[U-Boot] [UBOOT PATCH v2 2/2] eeprom: Added Kconfig support for eeprom u-boot headers

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_EEPROM_BUS
and CONFIG_ZYNQ_GEM_EEPROM_ADDR and enabled it in
respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in V2:
- Added depends on ARCH_ZYNQ
- Branch: u-boot-microblaze/kconfig
---
 configs/syzygy_hub_defconfig  |  1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig |  2 ++
 configs/xilinx_zynqmp_zcu102_revA_defconfig   |  2 ++
 configs/xilinx_zynqmp_zcu102_revB_defconfig   |  2 ++
 configs/zynq_zybo_defconfig   |  1 +
 drivers/misc/Kconfig  | 14 ++
 include/configs/syzygy_hub.h  |  1 -
 include/configs/xilinx_zynqmp_zcu102.h|  2 --
 include/configs/zynq_zybo.h   |  1 -
 9 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 67d1f54..eda5a60 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -37,6 +37,7 @@ CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C1=y
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x57
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 1df5b0b..fe6b6c3 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -57,6 +57,8 @@ CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_EEPROM_BUS=5
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x54
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index c8a8362..3ee241d 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -57,6 +57,8 @@ CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_EEPROM_BUS=5
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x54
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 8f85b5f..75ca1f0 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -57,6 +57,8 @@ CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_EEPROM_BUS=5
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x54
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 92f3e1e..4cb46b8 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -43,6 +43,7 @@ CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x50
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index d774569..aa1089a 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -214,6 +214,20 @@ config SPL_I2C_EEPROM
  This option is an SPL-variant of the I2C_EEPROM option.
  See the help of I2C_EEPROM for details.

+config ZYNQ_EEPROM_BUS
+   int "Define the EEPROM bus number"
+   depends on ARCH_ZYNQMP || ARCH_ZYNQ
+   default -1
+   help
+ Define the EEPROM bus number.
+
+config ZYNQ_GEM_EEPROM_ADDR
+   hex "Define GEM EEPROM address"
+   depends on ARCH_ZYNQMP || ARCH_ZYNQ
+   default 0x0
+   help
+ Define the EEPROM address for GEM.
+
 config ZYNQ_GEM_I2C_MAC_OFFSET
hex "Set the I2C MAC offset"
default 0x0
diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h
index 73c9189..362a6c9 100644
--- a/include/configs/syzygy_hub.h
+++ b/include/configs/syzygy_hub.h
@@ -12,7 +12,6 @@
 #define __CONFIG_SYZYGY_HUB_H

 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x57

 #define CONFIG_EXTRA_ENV_SETTINGS   \
"fit_image=fit.itb\0"   \
diff --git a/include/configs/xilinx_zynqmp_zcu102.h 
b/include/configs/xilinx_zynqmp_zcu102.h
index 27d9d6a..1166343 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -39,8 +39,6 @@
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}

 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_EEPROM_BUS 5
-#define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x54

 #include 

diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
index 8f4e088..aca867c 100644
--- a/include/configs/zynq_zybo.h
+++ b/include/configs/zynq_zybo.h
@@ -12,7 +12,6 @@
 #define __CONFIG_ZYNQ_ZYBO_H

 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_GEM_

[U-Boot] [UBOOT PATCH v2 1/2] eeprom: Enabled eeprom u-boot headers in defconfig

[Vipul Kumar]

This patch enabled eeprom related u-boot headers in
the respective defconfig and removed CONFIG_ZYNQ_EEPROM.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in v2:
- Removed CONFIG_ZYNQ_EEPROM for zynqmp.
- Enabled configs defined under CONFIG_ZYNQ_EEPROM for zynq
  in defconfig and removed CONFIG_ZYNQ_EEPROM.
- Branch: u-boot-microblaze/kconfig
---
 configs/zynq_zc702_defconfig   | 6 ++
 configs/zynq_zc706_defconfig   | 6 ++
 include/configs/xilinx_zynqmp_ep.h | 1 -
 include/configs/zynq-common.h  | 9 -
 include/configs/zynq_zc70x.h   | 2 --
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 8e8b800..2970ef8 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -43,6 +43,12 @@ CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x54
+CONFIG_SYS_EEPROM_SIZE=1024
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 8f83d17..b51567c 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -43,6 +43,12 @@ CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x54
+CONFIG_SYS_EEPROM_SIZE=1024
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/include/configs/xilinx_zynqmp_ep.h 
b/include/configs/xilinx_zynqmp_ep.h
index 3a572b7..6c48e15 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -15,7 +15,6 @@

 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 5200
 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
-#define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
 ZYNQMP_USB1_XHCI_BASEADDR}

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 0ebb66b..4622d39 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -122,15 +122,6 @@
 # define CONFIG_SYS_I2C
 #endif

-/* EEPROM */
-#ifdef CONFIG_ZYNQ_EEPROM
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN1
-# define CONFIG_SYS_I2C_EEPROM_ADDR0x54
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-# define CONFIG_SYS_EEPROM_SIZE1024 /* Bytes */
-#endif
-
 /* Total Size of Environment Sector */
 #define CONFIG_ENV_SIZE(128 << 10)

diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index 720f953..715ea80 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_ZYNQ_ZC70X_H
 #define __CONFIG_ZYNQ_ZC70X_H

-#define CONFIG_ZYNQ_EEPROM
-
 #include 

 #endif /* __CONFIG_ZYNQ_ZC70X_H */
--
2.7.4

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recipient(s) and contain(s) confidential information that may be proprietary, 
privileged or copyrighted under applicable law. If you are not the intended 
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Delete this email message and any attachments immediately.
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[U-Boot] [UBOOT PATCH v2 0/2] eeprom: Moved eeprom u-boot headers to the Kconfig

[Vipul Kumar]

This series of patch added Kconfig support for eeprom u-boot
headers and enabled in respective defconfig.

These are the configs:
-CONFIG_ZYNQ_EEPROM_BUS
-CONFIG_ZYNQ_GEM_EEPROM_ADDR

-Changes in v2:
- Removed CONFIG_ZYNQ_EEPROM for zynqmp
- Enabled configs defined under CONFIG_ZYNQ_EEPROM for zynq
 - in defconfig and removed CONFIG_ZYNQ_EEPROM.
- Added depends on ARCH_ZYNQ
- Branch: u-boot-microblaze/kconfig

Vipul Kumar (2):
  eeprom: Enabled eeprom u-boot headers in defconfig
  eeprom: Added Kconfig support for eeprom u-boot headers

 configs/syzygy_hub_defconfig  |  1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig |  2 ++
 configs/xilinx_zynqmp_zcu102_revA_defconfig   |  2 ++
 configs/xilinx_zynqmp_zcu102_revB_defconfig   |  2 ++
 configs/zynq_zc702_defconfig  |  6 ++
 configs/zynq_zc706_defconfig  |  6 ++
 configs/zynq_zybo_defconfig   |  1 +
 drivers/misc/Kconfig  | 14 ++
 include/configs/syzygy_hub.h  |  1 -
 include/configs/xilinx_zynqmp_ep.h|  1 -
 include/configs/xilinx_zynqmp_zcu102.h|  2 --
 include/configs/zynq-common.h |  9 -
 include/configs/zynq_zc70x.h  |  2 --
 include/configs/zynq_zybo.h   |  1 -
 14 files changed, 34 insertions(+), 16 deletions(-)

--
2.7.4

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privileged or copyrighted under applicable law. If you are not the intended 
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[U-Boot] [UBOOT PATCH v2 1/2] arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI0

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI0 and
enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in v2:
- Added depends on MMC_SDHCI_ZYNQ
- Branch: u-boot-microblaze/kconfig
---
 arch/arm/cpu/armv8/zynqmp/Kconfig| 6 ++
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 +
 include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 1 -
 include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h | 1 -
 5 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig 
b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 9e521ed..6eddea7 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -89,6 +89,12 @@ config ZYNQMP_PSU_INIT_ENABLED
help
  Include psu_init to full u-boot. SPL include psu_init by default.

+config ZYNQ_SDHCI0
+   bool "Xilinx SDHCI0 controller"
+   depends on MMC_SDHCI_ZYNQ
+   help
+ Enable the SDHCI0 controller for Xilinx ZynqMP.
+
 config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
bool "Overwrite SPL bootmode"
depends on SPL
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7da0ca8..05d98c0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI0=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index ac565ec..403cb7c 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
+CONFIG_ZYNQ_SDHCI0=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h 
b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index e3797a8..7bcefad 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
 #define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H

-#define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_SDHCI1
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}

diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h 
b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
index 6a0e397..5aaf6c0 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -11,7 +11,6 @@
 #ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
 #define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H

-#define CONFIG_ZYNQ_SDHCI0

 #include 

--
2.7.4

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Delete this email message and any attachments immediately.
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[U-Boot] [UBOOT PATCH v2 0/2] arm64: zynqmp: mmc: Moved mmc u-boot headers to the Kconfig

[Vipul Kumar]

This series of patch moved mmc u-boot headers to the
Kconfig and enabled it in respective defconfig.

These are the configs:
-CONFIG_ZYNQ_SDHCI0
-CONFIG_ZYNQ_SDHCI1

-Changes in V2:
- Added depends on MMC_SDHCI_ZYNQ
- Branch: u-boot-microblaze/kconfig

Vipul Kumar (2):
  arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI0
  arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI1

 arch/arm/cpu/armv8/zynqmp/Kconfig| 12 
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig |  2 ++
 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig |  1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig|  1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig  |  1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig  |  1 +
 include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h |  2 --
 include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h |  1 -
 include/configs/xilinx_zynqmp_zcu102.h   |  1 -
 9 files changed, 18 insertions(+), 4 deletions(-)

--
2.7.4

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recipient(s) and contain(s) confidential information that may be proprietary, 
privileged or copyrighted under applicable law. If you are not the intended 
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[U-Boot] [UBOOT PATCH v2 2/2] arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI1

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI1 and
enabled it in defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in v2:
- Added depends on MMC_SDHCI_ZYNQ
- Branch: u-boot-microblaze/kconfig
---
 arch/arm/cpu/armv8/zynqmp/Kconfig| 6 ++
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig  | 1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig  | 1 +
 include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 1 -
 include/configs/xilinx_zynqmp_zcu102.h   | 1 -
 7 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig 
b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 6eddea7..a903344 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -95,6 +95,12 @@ config ZYNQ_SDHCI0
help
  Enable the SDHCI0 controller for Xilinx ZynqMP.

+config ZYNQ_SDHCI1
+   bool "Xilinx SDHCI1 controller"
+   depends on MMC_SDHCI_ZYNQ
+   help
+ Enable the SDHCI1 controller for Xilinx ZynqMP.
+
 config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
bool "Overwrite SPL bootmode"
depends on SPL
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 05d98c0..be0e37f 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
 CONFIG_ZYNQMP_USB=y
 CONFIG_ZYNQ_SDHCI0=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 1df5b0b..67d3fa6 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index c8a8362..76f7993 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 8f85b5f..0624034 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h 
b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index 7bcefad..a415569 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
 #define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H

-#define CONFIG_ZYNQ_SDHCI1
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}

 #include 
diff --git a/include/configs/xilinx_zynqmp_zcu102.h 
b/include/configs/xilinx_zynqmp_zcu102.h
index 27d9d6a..097ac49 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_ZYNQMP_ZCU102_H
 #define __CONFIG_ZYNQMP_ZCU102_H

-#define CONFIG_ZYNQ_SDHCI1
 #define CONFIG_SYS_I2C_MAX_HOPS1
 #define CONFIG_SYS_NUM_I2C_BUSES   18
 #define CONFIG_SYS_I2C_BUSES   { \
--
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[U-Boot] [UBOOT PATCH v2 0/2] microblaze: Moved U-boot headers to Kconfig

[Vipul Kumar]

This seris of patch moved microblaze u-boot headers to the kconfig
and enabled it in respective defconfig.
These are the configs:
-CONFIG_XILINX_GPIO
-CONFIG_XILINX_TB_WATCHDOG

- Changes in v2:
- Removed "Enable" from description
- Added select HW_WATCHDOG
- Branch: u-boot-microblaze/kconfig

Vipul Kumar (2):
  microblaze: Added Kconfig support for CONFIG_XILINX_GPIO
  microblaze: wdt: Added Kconfig support for CONFIG_XILINX_TB_WATCHDOG

 configs/microblaze-generic_defconfig | 2 ++
 drivers/gpio/Kconfig | 5 +
 drivers/watchdog/Kconfig | 7 +++
 include/configs/microblaze-generic.h | 2 --
 4 files changed, 14 insertions(+), 2 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH v2 2/2] microblaze: wdt: Added Kconfig support for CONFIG_XILINX_TB_WATCHDOG

[Vipul Kumar]

This patch added Kconfig support for CONFIG_XILINX_TB_WATCHDOG
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in v2:
- Added select HW_WATCHDOG
- Branch: u-boot-microblaze/kconfig
---
 configs/microblaze-generic_defconfig | 1 +
 drivers/watchdog/Kconfig | 7 +++
 include/configs/microblaze-generic.h | 1 -
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index 699dc44..fba3820 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -63,3 +63,4 @@ CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_SYS_NS16550=y
 CONFIG_XILINX_UARTLITE=y
+CONFIG_XILINX_TB_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index fc46b67..a1e9432 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -78,4 +78,11 @@ config WDT_ORION
   Select this to enable Orion watchdog timer, which can be found on 
some
   Marvell Armada chips.

+config XILINX_TB_WATCHDOG
+   bool "Xilinx watchdog timer support"
+   depends on MICROBLAZE && !SPL_BUILD
+   select HW_WATCHDOG
+   help
+ Available for Xilinx Axi platforms to service timebase watchdog timer.
+
 endmenu
diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index 73c3c2a..391b26a 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -50,7 +50,6 @@
 # define CONFIG_WATCHDOG_IRQ   XILINX_WATCHDOG_IRQ
 # ifndef CONFIG_SPL_BUILD
 #  define CONFIG_HW_WATCHDOG
-#  define CONFIG_XILINX_TB_WATCHDOG
 # endif
 #endif

--
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[U-Boot] [UBOOT PATCH v2 1/2] microblaze: Added Kconfig support for CONFIG_XILINX_GPIO

[Vipul Kumar]

This patch added Kconfig support for CONFIG_XILINX_GPIO
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in v2:
- Removed "Enable" from description
- Branch: u-boot-microblaze/kconfig
---
 configs/microblaze-generic_defconfig | 1 +
 drivers/gpio/Kconfig | 5 +
 include/configs/microblaze-generic.h | 1 -
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index ac49404..699dc44 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -46,6 +46,7 @@ CONFIG_BOOTP_BOOTPATH=y
 CONFIG_BOOTP_GATEWAY=y
 CONFIG_BOOTP_HOSTNAME=y
 CONFIG_SPL_DM=y
+CONFIG_XILINX_GPIO=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 34d4409..cc75aec 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -183,6 +183,11 @@ config SANDBOX_GPIO_COUNT
  of 'anonymous' GPIOs that do not belong to any device or bank.
  Select a suitable value depending on your needs.

+config XILINX_GPIO
+   bool "Xilinx GPIO driver"
+   help
+ This config enable the Xilinx GPIO driver for Microblaze.
+
 config CMD_TCA642X
bool "tca642x - Command to access tca642x state"
help
diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index fe9aaae..73c3c2a 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -41,7 +41,6 @@

 /* gpio */
 #ifdef XILINX_GPIO_BASEADDR
-# define CONFIG_XILINX_GPIO
 # define CONFIG_SYS_GPIO_0_ADDRXILINX_GPIO_BASEADDR
 #endif

--
2.7.4

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[U-Boot] [UBOOT PATCH v2 2/2] spi: Added Kconfig support for SYS_ZYNQ_SPI_WAIT and XILINX_SPI_IDLE_VAL

[Vipul Kumar]

This patch added Kconfig support for CONFIG_SYS_ZYNQ_SPI_WAIT
and CONFIG_XILINX_SPI_IDLE_VAL and set default value.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
- Changes in V2:
- Added depends on XILINX_SPI
- Branch: u-boot-microblaze/kconfig
---
 drivers/spi/Kconfig  | 14 ++
 drivers/spi/xilinx_spi.c |  4 
 drivers/spi/zynq_spi.c   |  3 ---
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 94f6d7d..d8e17cd 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -211,6 +211,20 @@ config SYS_ZYNQ_QSPI_WAIT
help
  Define default Zynq QSPI wait time in milliseconds.

+config SYS_ZYNQ_SPI_WAIT
+   int "Define Zynq SPI wait time in ms"
+   depends on XILINX_SPI
+   default 10
+   help
+ Define default Zynq SPI wait time in milliseconds.
+
+config XILINX_SPI_IDLE_VAL
+   hex "Define the default SPI idle value"
+   depends on XILINX_SPI
+   default 0x
+   help
+ Set the default SPI idle value.
+
 endif # if DM_SPI

 config SOFT_SPI
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index a951a77..9781ea9 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -74,10 +74,6 @@
SPICR_SPE)
 #define XILSPI_SPICR_DFLT_OFF  (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)

-#ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
-#endif
-
 #ifndef CONFIG_SYS_XILINX_SPI_LIST
 #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
 #endif
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index ed2b8cb..be8f525 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_SPI_CR_SS_SHIFT   10  /* Slave select shift */

 #define ZYNQ_SPI_FIFO_DEPTH128
-#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
-#define CONFIG_SYS_ZYNQ_SPI_WAIT   (CONFIG_SYS_HZ/100) /* 10 ms */
-#endif

 /* zynq spi register set */
 struct zynq_spi_regs {
--
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[U-Boot] [UBOOT PATCH v2 1/2] qspi: Added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT

[Vipul Kumar]

This patch added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT
and set it to default value 10 milliseconds.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
-Changes in v2:
- Added depends on ZYNQ_QSPI
- Branch: u-boot-microblaze/kconfig
---
 drivers/spi/Kconfig | 7 +++
 drivers/spi/zynq_qspi.c | 3 ---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 235a8c7..94f6d7d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -204,6 +204,13 @@ config ZYNQ_QSPI
  Zynq QSPI IP core. This IP is used to connect the flash in
  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.

+config SYS_ZYNQ_QSPI_WAIT
+   int "Define Zynq QSPI wait time in ms"
+   depends on ZYNQ_QSPI
+   default 10
+   help
+ Define default Zynq QSPI wait time in milliseconds.
+
 endif # if DM_SPI

 config SOFT_SPI
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 255e02f..c9241aa 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_SS_SHIFT  10  /* Slave select shift */

 #define ZYNQ_QSPI_FIFO_DEPTH   63
-#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
-#define CONFIG_SYS_ZYNQ_QSPI_WAIT  CONFIG_SYS_HZ/100   /* 10 ms */
-#endif

 /* zynq qspi register set */
 struct zynq_qspi_regs {
--
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[U-Boot] [UBOOT PATCH v2 0/2] spi: Moved spi u-bbot headers to Kconfig

[Vipul Kumar]

This seris of patch moved spi headers to Kconfig.
These are the configs:
-CONFIG_SYS_ZYNQ_SPI_WAIT
-CONFIG_XILINX_SPI_IDLE_VAL
-CONFIG_SYS_ZYNQ_QSPI_WAIT

-Changes in V2:
- Added depends on ZYNQ_QSPI
- Added depends on XILINX_SPI
- Branch: u-boot-microblaze/kconfig

Vipul Kumar (2):
  qspi: Added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT
  spi: Added Kconfig support for SYS_ZYNQ_SPI_WAIT and
XILINX_SPI_IDLE_VAL

 drivers/spi/Kconfig  | 21 +
 drivers/spi/xilinx_spi.c |  4 
 drivers/spi/zynq_qspi.c  |  3 ---
 drivers/spi/zynq_spi.c   |  3 ---
 4 files changed, 21 insertions(+), 10 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH 0/2] eeprom: Moved eeprom u-boot headers to the Kconfig

[Vipul Kumar]

This series of patch added Kconfig support for eeprom u-boot
headers and enabled in respective defconfig.

These are the configs:
-CONFIG_ZYNQ_EEPROM
-CONFIG_ZYNQ_EEPROM_BUS
-CONFIG_ZYNQ_GEM_EEPROM_ADDR

Vipul Kumar (2):
  eeprom: Added Kconfig support for ZYNQ_EEPROM
  eeprom: Added Kconfig support for eeprom u-boot headers

 configs/syzygy_hub_defconfig  |  1 +
 configs/xilinx_zynqmp_ep_defconfig|  1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig |  2 ++
 configs/xilinx_zynqmp_zcu102_revA_defconfig   |  2 ++
 configs/xilinx_zynqmp_zcu102_revB_defconfig   |  2 ++
 configs/zynq_zc702_defconfig  |  1 +
 configs/zynq_zc706_defconfig  |  1 +
 configs/zynq_zybo_defconfig   |  1 +
 drivers/misc/Kconfig  | 18 ++
 include/configs/syzygy_hub.h  |  1 -
 include/configs/xilinx_zynqmp_ep.h|  1 -
 include/configs/xilinx_zynqmp_zcu102.h|  2 --
 include/configs/zynq_zc70x.h  |  1 -
 include/configs/zynq_zybo.h   |  1 -
 14 files changed, 29 insertions(+), 6 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH 2/2] eeprom: Added Kconfig support for eeprom u-boot headers

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_EEPROM_BUS
and CONFIG_ZYNQ_GEM_EEPROM_ADDR and enabled it in
respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/syzygy_hub_defconfig  |  1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig |  2 ++
 configs/xilinx_zynqmp_zcu102_revA_defconfig   |  2 ++
 configs/xilinx_zynqmp_zcu102_revB_defconfig   |  2 ++
 configs/zynq_zybo_defconfig   |  1 +
 drivers/misc/Kconfig  | 13 +
 include/configs/syzygy_hub.h  |  1 -
 include/configs/xilinx_zynqmp_zcu102.h|  2 --
 include/configs/zynq_zybo.h   |  1 -
 9 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 996ecdb..d97ee8a 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -34,6 +34,7 @@ CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x57
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index d0a1467..9c34eea 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -54,6 +54,8 @@ CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_EEPROM_BUS=5
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x54
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index ecefb00..de3cff6 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -54,6 +54,8 @@ CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_EEPROM_BUS=5
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x54
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index c2add99..04eb5c7 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -54,6 +54,8 @@ CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_EEPROM_BUS=5
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x54
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 138b249..73b776c 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -39,6 +39,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_ZYNQ_GEM_EEPROM_ADDR=0x50
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index eef7df3..a793ed7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -219,6 +219,19 @@ config ZYNQ_EEPROM
help
  This enables the EEPROM driver for Zynq.

+config ZYNQ_EEPROM_BUS
+   int "Define the EEPROM bus number"
+   depends on ARCH_ZYNQMP
+   default -1
+   help
+ Define the EEPROM bus number.
+
+config ZYNQ_GEM_EEPROM_ADDR
+   hex "Define GEM EEPROM address"
+   default 0x0
+   help
+ Define the EEPROM address for GEM.
+
 if I2C_EEPROM

 config SYS_I2C_EEPROM_ADDR
diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h
index 4147b45..b33de1c 100644
--- a/include/configs/syzygy_hub.h
+++ b/include/configs/syzygy_hub.h
@@ -13,7 +13,6 @@

 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x57
 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA

 #define CONFIG_EXTRA_ENV_SETTINGS   \
diff --git a/include/configs/xilinx_zynqmp_zcu102.h 
b/include/configs/xilinx_zynqmp_zcu102.h
index 85f78ba..b738f3b 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -42,8 +42,6 @@
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}

 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_EEPROM_BUS 5
-#define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x54
 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20

 #include 
diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
index 808967c..d2abd9e 100644
--- a/include/configs/zynq_zybo.h
+++ b/include/configs/zynq_zybo.h
@@ -14,7 +14,6 @@
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x50
 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
 #define CONFIG_DISPLAY
 #define CONFIG_I2C_EDID
--
2.7.4

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[U-Boot] [UBOOT PATCH 1/2] eeprom: Added Kconfig support for ZYNQ_EEPROM

[Vipul Kumar]

This patch added Kconfig support for ZYNQ_EEPROM
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/xilinx_zynqmp_ep_defconfig | 1 +
 configs/zynq_zc702_defconfig   | 1 +
 configs/zynq_zc706_defconfig   | 1 +
 drivers/misc/Kconfig   | 5 +
 include/configs/xilinx_zynqmp_ep.h | 1 -
 include/configs/zynq_zc70x.h   | 1 -
 6 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index 7f8e774..2b8be89 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -58,6 +58,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_EEPROM=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 878bc79..e0a41c0 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -40,6 +40,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_ZYNQ_EEPROM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 7b2e072..c869316 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -40,6 +40,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_ZYNQ_EEPROM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f1c15cb..eef7df3 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -214,6 +214,11 @@ config SPL_I2C_EEPROM
  This option is an SPL-variant of the I2C_EEPROM option.
  See the help of I2C_EEPROM for details.

+config ZYNQ_EEPROM
+   bool "Enable driver for ZYNQ EEPROM"
+   help
+ This enables the EEPROM driver for Zynq.
+
 if I2C_EEPROM

 config SYS_I2C_EEPROM_ADDR
diff --git a/include/configs/xilinx_zynqmp_ep.h 
b/include/configs/xilinx_zynqmp_ep.h
index 3a572b7..6c48e15 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -15,7 +15,6 @@

 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 5200
 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
-#define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
 ZYNQMP_USB1_XHCI_BASEADDR}

diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index fc46fec..88a7abd 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -11,7 +11,6 @@
 #define __CONFIG_ZYNQ_ZC70X_H

 #define CONFIG_ZYNQ_I2C0
-#define CONFIG_ZYNQ_EEPROM

 #include 

--
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[U-Boot] [UBOOT PATCH 2/2] mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/xilinx_zynqmp_ep_defconfig | 1 +
 drivers/mmc/Kconfig| 7 +++
 drivers/mmc/zynq_sdhci.c   | 4 
 include/configs/xilinx_zynqmp_ep.h | 1 -
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index 00db5e3..4de1ac1 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -62,6 +62,7 @@ CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_SDHCI_MIN_FREQ=101562
 CONFIG_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 42b7d21..4f2993c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -478,6 +478,13 @@ config ZYNQ_SDHCI_MAX_FREQ
help
  Set the maximum frequency for the SDHCI controller.

+config ZYNQ_SDHCI_MIN_FREQ
+   int "Set the minimum frequencyof the controller"
+   depends on MMC_SDHCI_ZYNQ
+   default 0
+   help
+ Set the minimum frequencyof the controller.
+
 config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 0fddb42..414778c 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -16,10 +16,6 @@

 DECLARE_GLOBAL_DATA_PTR;

-#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
-# define CONFIG_ZYNQ_SDHCI_MIN_FREQ0
-#endif
-
 struct arasan_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
diff --git a/include/configs/xilinx_zynqmp_ep.h 
b/include/configs/xilinx_zynqmp_ep.h
index a77eeea..a26377a 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_ZYNQMP_EP_H
 #define __CONFIG_ZYNQMP_EP_H

-#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
 ZYNQMP_USB1_XHCI_BASEADDR}
--
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[U-Boot] [UBOOT PATCH 0/2] mmc: Added Kconfig support to set minimum and maximum frequency of the mmc controller

[Vipul Kumar]

This series of patch added Kconfig support for
CONFIG_ZYNQ_SDHCI_MAX_FREQ and CONFIG_ZYNQ_SDHCI_MIN_FREQ and
set the default values.

Vipul Kumar (2):
  mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
  mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ

 arch/arm/cpu/armv8/zynqmp/Kconfig  |  3 +++
 arch/arm/mach-zynq/Kconfig |  3 +++
 configs/xilinx_zynqmp_ep_defconfig |  2 ++
 drivers/mmc/Kconfig| 13 +
 drivers/mmc/zynq_sdhci.c   |  4 
 include/configs/xilinx_zynqmp.h|  3 ---
 include/configs/xilinx_zynqmp_ep.h |  2 --
 include/configs/zynq-common.h  |  5 -
 8 files changed, 21 insertions(+), 14 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH 1/2] mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 arch/arm/cpu/armv8/zynqmp/Kconfig  | 3 +++
 arch/arm/mach-zynq/Kconfig | 3 +++
 configs/xilinx_zynqmp_ep_defconfig | 1 +
 drivers/mmc/Kconfig| 6 ++
 include/configs/xilinx_zynqmp.h| 3 ---
 include/configs/xilinx_zynqmp_ep.h | 1 -
 include/configs/zynq-common.h  | 5 -
 7 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig 
b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 9e521ed..8a311e1 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -96,6 +96,9 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
  Overwrite bootmode selected via boot mode pins to tell SPL what should
  be the next boot device.

+config ZYNQ_SDHCI_MAX_FREQ
+   default 2
+
 config SPL_ZYNQMP_ALT_BOOTMODE
hex
default 0x0 if JTAG_MODE
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index b9cd45b..8772904 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -63,4 +63,7 @@ config BOOT_INIT_FILE
  Add register writes to boot.bin format (max 256 pairs).
  Expect a table of register-value pairs, e.g. "0x12345678 0x4321"

+config ZYNQ_SDHCI_MAX_FREQ
+   default 5200
+
 endif
diff --git a/configs/xilinx_zynqmp_ep_defconfig 
b/configs/xilinx_zynqmp_ep_defconfig
index 7f8e774..00db5e3 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=5200
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
 CONFIG_DEBUG_UART=y
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f2d8256..42b7d21 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -472,6 +472,12 @@ config MMC_SDHCI_ZYNQ
help
  Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs 
platform

+config ZYNQ_SDHCI_MAX_FREQ
+   int "Set the maximum frequency of cotroller"
+   depends on MMC_SDHCI_ZYNQ
+   help
+ Set the maximum frequency for the SDHCI controller.
+
 config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 5533831..1c82050 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -69,9 +69,6 @@

 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define CONFIG_SUPPORT_EMMC_BOOT
-# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
-#  define CONFIG_ZYNQ_SDHCI_MAX_FREQ   2
-# endif
 #endif

 #ifdef CONFIG_NAND_ARASAN
diff --git a/include/configs/xilinx_zynqmp_ep.h 
b/include/configs/xilinx_zynqmp_ep.h
index 3a572b7..a77eeea 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_ZYNQMP_EP_H
 #define __CONFIG_ZYNQMP_EP_H

-#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 5200
 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 2dfac6f..fd3e17d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -76,11 +76,6 @@
 #define CONFIG_MTD_DEVICE
 #endif

-/* MMC */
-#if defined(CONFIG_MMC_SDHCI_ZYNQ)
-# define CONFIG_ZYNQ_SDHCI_MAX_FREQ5200
-#endif
-
 #ifdef CONFIG_USB_EHCI_ZYNQ
 # define CONFIG_EHCI_IS_TDI

--
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[U-Boot] [UBOOT PATCH 0/2] arm64: zynqmp: mmc: Moved mmc u-boot headers to the Kconfig

[Vipul Kumar]

This series of patch moved mmc u-boot headers to the
Kconfig and enabled it in respective defconfig.

These are the configs:
-CONFIG_ZYNQ_SDHCI0
-CONFIG_ZYNQ_SDHCI1

Vipul Kumar (2):
  arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI0
  arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI1

 arch/arm/cpu/armv8/zynqmp/Kconfig| 10 ++
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig |  2 ++
 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig |  1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig|  1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig  |  1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig  |  1 +
 include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h |  2 --
 include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h |  1 -
 include/configs/xilinx_zynqmp_zcu102.h   |  1 -
 9 files changed, 16 insertions(+), 4 deletions(-)

--
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[U-Boot] [UBOOT PATCH 1/2] arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI0

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI0 and
enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 arch/arm/cpu/armv8/zynqmp/Kconfig| 5 +
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 +
 include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 1 -
 include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h | 1 -
 5 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig 
b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 9e521ed..f32ced7 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -89,6 +89,11 @@ config ZYNQMP_PSU_INIT_ENABLED
help
  Include psu_init to full u-boot. SPL include psu_init by default.

+config ZYNQ_SDHCI0
+   bool "Xilinx SDHCI0 controller"
+   help
+ Enable the SDHCI0 controller for Xilinx ZynqMP.
+
 config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
bool "Overwrite SPL bootmode"
depends on SPL
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7da0ca8..05d98c0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI0=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index ac565ec..403cb7c 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
+CONFIG_ZYNQ_SDHCI0=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h 
b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index e3797a8..7bcefad 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
 #define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H

-#define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_SDHCI1
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}

diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h 
b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
index 6a0e397..5aaf6c0 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -11,7 +11,6 @@
 #ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
 #define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H

-#define CONFIG_ZYNQ_SDHCI0

 #include 

--
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[U-Boot] [UBOOT PATCH 2/2] arm64: zynqmp: mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI1

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI1 and
enabled it in defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 arch/arm/cpu/armv8/zynqmp/Kconfig| 5 +
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig  | 1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig  | 1 +
 include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 1 -
 include/configs/xilinx_zynqmp_zcu102.h   | 1 -
 7 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig 
b/arch/arm/cpu/armv8/zynqmp/Kconfig
index f32ced7..0587187 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -94,6 +94,11 @@ config ZYNQ_SDHCI0
help
  Enable the SDHCI0 controller for Xilinx ZynqMP.

+config ZYNQ_SDHCI1
+   bool "Xilinx SDHCI1 controller"
+   help
+ Enable the SDHCI1 controller for Xilinx ZynqMP.
+
 config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
bool "Overwrite SPL bootmode"
depends on SPL
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 05d98c0..be0e37f 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
 CONFIG_ZYNQMP_USB=y
 CONFIG_ZYNQ_SDHCI0=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index d0a1467..9d6f1a0 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index ecefb00..e5f7686 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index c2add99..0cdd621 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
 CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_SDHCI1=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h 
b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index 7bcefad..a415569 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
 #define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H

-#define CONFIG_ZYNQ_SDHCI1
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}

 #include 
diff --git a/include/configs/xilinx_zynqmp_zcu102.h 
b/include/configs/xilinx_zynqmp_zcu102.h
index 85f78ba..c5b7e9a 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_ZYNQMP_ZCU102_H
 #define __CONFIG_ZYNQMP_ZCU102_H

-#define CONFIG_ZYNQ_SDHCI1
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_MAX_HOPS1
--
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[U-Boot] [UBOOT PATCH 5/6] i2c: Added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/syzygy_hub_defconfig  | 1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig   | 1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig   | 1 +
 configs/zynq_zybo_defconfig   | 1 +
 drivers/misc/Kconfig  | 6 ++
 include/configs/syzygy_hub.h  | 1 -
 include/configs/xilinx_zynqmp_zcu102.h| 1 -
 include/configs/zynq_zybo.h   | 1 -
 9 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 334b840..8454a19 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 12a0d64..02cd710 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -55,6 +55,7 @@ CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index b6e8a0e..9176e8e 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -55,6 +55,7 @@ CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index c5bc4cd..3c2a865 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -55,6 +55,7 @@ CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MISC=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 4e3d6c5..dab98d8 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -40,6 +40,7 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f1c15cb..d774569 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -214,6 +214,12 @@ config SPL_I2C_EEPROM
  This option is an SPL-variant of the I2C_EEPROM option.
  See the help of I2C_EEPROM for details.

+config ZYNQ_GEM_I2C_MAC_OFFSET
+   hex "Set the I2C MAC offset"
+   default 0x0
+   help
+ Set the MAC offset for i2C.
+
 if I2C_EEPROM

 config SYS_I2C_EEPROM_ADDR
diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h
index 4147b45..19e201f 100644
--- a/include/configs/syzygy_hub.h
+++ b/include/configs/syzygy_hub.h
@@ -14,7 +14,6 @@
 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x57
-#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA

 #define CONFIG_EXTRA_ENV_SETTINGS   \
"fit_image=fit.itb\0"   \
diff --git a/include/configs/xilinx_zynqmp_zcu102.h 
b/include/configs/xilinx_zynqmp_zcu102.h
index 88819c6..0095f61 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -43,7 +43,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_ZYNQ_EEPROM_BUS 5
 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x54
-#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20

 #include 

diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
index 808967c..a589c92 100644
--- a/include/configs/zynq_zybo.h
+++ b/include/configs/zynq_zybo.h
@@ -15,7 +15,6 @@
 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR0x50
-#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
 #define CONFIG_DISPLAY
 #define CONFIG_I2C_EDID

--
2.7.4

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[U-Boot] [UBOOT PATCH 6/6] i2c: Added kconfig support for CONFIG_ZYNQ_I2C0 and CONFIG_ZYNQ_I2C1

[Vipul Kumar]

This patch added Kconfig support for CONFIG_ZYNQ_I2C0 and
CONFIG_ZYNQ_I2C1 and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/syzygy_hub_defconfig  |  1 +
 configs/topic_miami_defconfig |  2 ++
 configs/topic_miamilite_defconfig |  2 ++
 configs/topic_miamiplus_defconfig |  2 ++
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig |  2 ++
 configs/xilinx_zynqmp_zcu102_revA_defconfig   |  2 ++
 configs/xilinx_zynqmp_zcu102_revB_defconfig   |  2 ++
 configs/zynq_zc702_defconfig  |  1 +
 configs/zynq_zc706_defconfig  |  1 +
 configs/zynq_zybo_defconfig   |  2 ++
 drivers/i2c/Kconfig   | 10 ++
 include/configs/syzygy_hub.h  |  1 -
 include/configs/topic_miami.h |  2 --
 include/configs/xilinx_zynqmp_zcu102.h|  2 --
 include/configs/zynq_zc70x.h  |  1 -
 include/configs/zynq_zybo.h   |  2 --
 16 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 8454a19..78815cc 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index bd8eff7..d18d5ae 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -32,6 +32,8 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/topic_miamilite_defconfig 
b/configs/topic_miamilite_defconfig
index dcf8f47..3a3c47a 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -32,6 +32,8 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/topic_miamiplus_defconfig 
b/configs/topic_miamiplus_defconfig
index 4f771f0..8363838 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -30,6 +30,8 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 02cd710..1df5b0b 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -54,6 +54,8 @@ CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
 CONFIG_MISC=y
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 9176e8e..c8a8362 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -54,6 +54,8 @@ CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
 CONFIG_MISC=y
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 3c2a865..8f85b5f 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -54,6 +54,8 @@ CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
 CONFIG_MISC=y
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_DM_MMC=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index b20744a..7783467 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -41,6 +41,7 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 882150f..4d15ab3 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -41,6 +41,7 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index dab98d8..bdd2c60 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -40,6 +40,8 @@ CONF

[U-Boot] [UBOOT PATCH 2/2] microblaze: wdt: Added Kconfig support for CONFIG_XILINX_TB_WATCHDOG

[Vipul Kumar]

This patch added Kconfig support for CONFIG_XILINX_TB_WATCHDOG
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/microblaze-generic_defconfig | 1 +
 drivers/watchdog/Kconfig | 6 ++
 include/configs/microblaze-generic.h | 1 -
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index e707b9f..47d4204 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -59,3 +59,4 @@ CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_SYS_NS16550=y
 CONFIG_XILINX_UARTLITE=y
+CONFIG_XILINX_TB_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index fc46b67..bd209fa 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -78,4 +78,10 @@ config WDT_ORION
   Select this to enable Orion watchdog timer, which can be found on 
some
   Marvell Armada chips.

+config XILINX_TB_WATCHDOG
+   bool "Xilinx watchdog timer support"
+   depends on MICROBLAZE && !SPL_BUILD
+   help
+ Available for Xilinx Axi platforms to service timebase watchdog timer.
+
 endmenu
diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index de33583..a4d911d 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -50,7 +50,6 @@
 # define CONFIG_WATCHDOG_IRQ   XILINX_WATCHDOG_IRQ
 # ifndef CONFIG_SPL_BUILD
 #  define CONFIG_HW_WATCHDOG
-#  define CONFIG_XILINX_TB_WATCHDOG
 # endif
 #endif

--
2.7.4

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[U-Boot] [UBOOT PATCH 2/2] spi: Added Kconfig support for SYS_ZYNQ_SPI_WAIT and XILINX_SPI_IDLE_VAL

[Vipul Kumar]

This patch added Kconfig support for CONFIG_SYS_ZYNQ_SPI_WAIT
and CONFIG_XILINX_SPI_IDLE_VAL and set default value.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 drivers/spi/Kconfig  | 12 
 drivers/spi/xilinx_spi.c |  4 
 drivers/spi/zynq_spi.c   |  3 ---
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 436e9ad..bcb28cf 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -210,6 +210,18 @@ config SYS_ZYNQ_QSPI_WAIT
help
  Define default Zynq QSPI wait time in milliseconds.

+config SYS_ZYNQ_SPI_WAIT
+   int "Define Zynq SPI wait time in ms"
+   default 10
+   help
+ Define default Zynq SPI wait time in milliseconds.
+
+config XILINX_SPI_IDLE_VAL
+   hex "Define the default SPI idle value"
+   default 0x
+   help
+ Set the default SPI idle value.
+
 endif # if DM_SPI

 config SOFT_SPI
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index a951a77..9781ea9 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -74,10 +74,6 @@
SPICR_SPE)
 #define XILSPI_SPICR_DFLT_OFF  (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)

-#ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
-#endif
-
 #ifndef CONFIG_SYS_XILINX_SPI_LIST
 #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
 #endif
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index ed2b8cb..be8f525 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_SPI_CR_SS_SHIFT   10  /* Slave select shift */

 #define ZYNQ_SPI_FIFO_DEPTH128
-#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
-#define CONFIG_SYS_ZYNQ_SPI_WAIT   (CONFIG_SYS_HZ/100) /* 10 ms */
-#endif

 /* zynq spi register set */
 struct zynq_spi_regs {
--
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[U-Boot] [UBOOT PATCH 1/2] qspi: Added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT

[Vipul Kumar]

This patch added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT
and set it to default value 10 milliseconds.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 drivers/spi/Kconfig | 6 ++
 drivers/spi/zynq_qspi.c | 3 ---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 235a8c7..436e9ad 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -204,6 +204,12 @@ config ZYNQ_QSPI
  Zynq QSPI IP core. This IP is used to connect the flash in
  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.

+config SYS_ZYNQ_QSPI_WAIT
+   int "Define Zynq QSPI wait time in ms"
+   default 10
+   help
+ Define default Zynq QSPI wait time in milliseconds.
+
 endif # if DM_SPI

 config SOFT_SPI
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 255e02f..c9241aa 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_SS_SHIFT  10  /* Slave select shift */

 #define ZYNQ_QSPI_FIFO_DEPTH   63
-#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
-#define CONFIG_SYS_ZYNQ_QSPI_WAIT  CONFIG_SYS_HZ/100   /* 10 ms */
-#endif

 /* zynq qspi register set */
 struct zynq_qspi_regs {
--
2.7.4

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[U-Boot] [UBOOT PATCH 3/6] i2c: Added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SLAVE

[Vipul Kumar]

This patch added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SLAVE
and set it default to 0.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 drivers/i2c/Kconfig | 7 +++
 include/configs/xilinx_zynqmp.h | 1 -
 include/configs/zynq-common.h   | 1 -
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 62d134c..f4871d8 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -274,6 +274,13 @@ config SYS_I2C_ZYNQ
help
  Support for Xilinx I2C controller.

+config SYS_I2C_ZYNQ_SLAVE
+   hex "Set slave addr"
+   depends on SYS_I2C_ZYNQ
+   default 0
+   help
+ Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr.
+
 config SYS_I2C_IHS
 bool "gdsys IHS I2C driver"
 depends on DM_I2C
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 5533831..c81eb28 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -142,7 +142,6 @@
 #if defined(CONFIG_SYS_I2C_ZYNQ)
 # define CONFIG_SYS_I2C
 # define CONFIG_SYS_I2C_ZYNQ_SPEED 10
-# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0
 #endif

 /* EEPROM */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index b47a9ad..c879bfa 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -124,7 +124,6 @@
 #if defined(CONFIG_SYS_I2C_ZYNQ)
 # define CONFIG_SYS_I2C
 # define CONFIG_SYS_I2C_ZYNQ_SPEED 10
-# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0
 #endif

 /* EEPROM */
--
2.7.4

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[U-Boot] [UBOOT PATCH 0/2] microblaze: Moved U-boot headers to Kconfig

[Vipul Kumar]

This seris of patch moved microblaze u-boot headers to the kconfig
and enabled it in respective defconfig.
These are the configs:
-CONFIG_XILINX_GPIO
-CONFIG_XILINX_TB_WATCHDOG

Vipul Kumar (2):
  microblaze: Added Kconfig support for CONFIG_XILINX_GPIO
  microblaze: wdt: Added Kconfig support for CONFIG_XILINX_TB_WATCHDOG

 configs/microblaze-generic_defconfig | 2 ++
 drivers/gpio/Kconfig | 5 +
 drivers/watchdog/Kconfig | 6 ++
 include/configs/microblaze-generic.h | 2 --
 4 files changed, 13 insertions(+), 2 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH 4/6] i2c: Added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SPEED

[Vipul Kumar]

This patch added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SPEED
and set it to default value 10.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 drivers/i2c/Kconfig | 7 +++
 include/configs/xilinx_zynqmp.h | 1 -
 include/configs/zynq-common.h   | 1 -
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index f4871d8..dc2ffd1 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -281,6 +281,13 @@ config SYS_I2C_ZYNQ_SLAVE
help
  Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr.

+config SYS_I2C_ZYNQ_SPEED
+   int "Set I2C speed"
+   depends on SYS_I2C_ZYNQ
+   default 10
+   help
+ Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting.
+
 config SYS_I2C_IHS
 bool "gdsys IHS I2C driver"
 depends on DM_I2C
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index c81eb28..88ecf38 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -141,7 +141,6 @@
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)
 # define CONFIG_SYS_I2C
-# define CONFIG_SYS_I2C_ZYNQ_SPEED 10
 #endif

 /* EEPROM */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index c879bfa..4452919 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -123,7 +123,6 @@
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)
 # define CONFIG_SYS_I2C
-# define CONFIG_SYS_I2C_ZYNQ_SPEED 10
 #endif

 /* EEPROM */
--
2.7.4

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[U-Boot] [UBOOT PATCH 3/4] arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL

[Vipul Kumar]

This patch added Kconfig support for CONFIG_FPGA_ZYNQPL.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 drivers/fpga/Kconfig | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ac08bc1..50e9019 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -50,4 +50,11 @@ config FPGA_SPARTAN3
help
  Enable Spartan3 FPGA driver for loading in BIT format.

+config FPGA_ZYNQPL
+   bool "Enable Xilinx FPGA for Zynq"
+   depends on ARCH_ZYNQ
+   help
+ Enable FPGA driver for loading bitstream in BIT and BIN format
+ on Xilinx Zynq devices.
+
 endmenu
--
2.7.4

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[U-Boot] [UBOOT PATCH 0/6] i2c: Moved i2c u-boot headers to Kconfig

[Vipul Kumar]

This series of patch moved i2c u-boot headers to
the Kconfig and enabled in respective defconfig.

These are the configs:
-CONFIG_SYS_I2C_ZYNQ
-CONFIG_SYS_I2C_ZYNQ_SLAVE
-CONFIG_SYS_I2C_ZYNQ_SPEED
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
-CONFIG_ZYNQ_I2C0
-CONFIG_ZYNQ_I2C1

Vipul Kumar (6):
  i2c: Added Kconfig support for CONFIG_SYS_I2C_ZYNQ
  i2c: Enabled CONFIG_SYS_I2C_ZYNQ in the respective defconfig
  i2c: Added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SLAVE
  i2c: Added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SPEED
  i2c: Added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
  i2c: Added kconfig support for CONFIG_ZYNQ_I2C0 and CONFIG_ZYNQ_I2C1

 configs/syzygy_hub_defconfig  |  3 +++
 configs/topic_miami_defconfig |  3 +++
 configs/topic_miamilite_defconfig |  3 +++
 configs/topic_miamiplus_defconfig |  3 +++
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig |  4 
 configs/xilinx_zynqmp_zcu102_revA_defconfig   |  4 
 configs/xilinx_zynqmp_zcu102_revB_defconfig   |  4 
 configs/zynq_zc702_defconfig  |  2 ++
 configs/zynq_zc706_defconfig  |  2 ++
 configs/zynq_zybo_defconfig   |  4 
 drivers/i2c/Kconfig   | 30 +++
 drivers/misc/Kconfig  |  6 ++
 include/configs/syzygy_hub.h  |  2 --
 include/configs/topic_miami.h |  2 --
 include/configs/xilinx_zynqmp.h   |  2 --
 include/configs/xilinx_zynqmp_zcu102.h|  4 
 include/configs/zynq-common.h |  6 --
 include/configs/zynq_zc70x.h  |  1 -
 include/configs/zynq_zybo.h   |  3 ---
 19 files changed, 68 insertions(+), 20 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH 0/2] spi: Moved spi u-bbot headers to Kconfig

[Vipul Kumar]

This seris of patch moved spi headers to Kconfig.
These are the configs:
-CONFIG_SYS_ZYNQ_SPI_WAIT
-CONFIG_XILINX_SPI_IDLE_VAL
-CONFIG_SYS_ZYNQ_QSPI_WAIT

Vipul Kumar (2):
  qspi: Added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT
  spi: Added Kconfig support for SYS_ZYNQ_SPI_WAIT and
XILINX_SPI_IDLE_VAL

 drivers/spi/Kconfig  | 18 ++
 drivers/spi/xilinx_spi.c |  4 
 drivers/spi/zynq_qspi.c  |  3 ---
 drivers/spi/zynq_spi.c   |  3 ---
 4 files changed, 18 insertions(+), 10 deletions(-)

--
2.7.4

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[U-Boot] [UBOOT PATCH 1/6] i2c: Added Kconfig support for CONFIG_SYS_I2C_ZYNQ

[Vipul Kumar]

This patch added Kconfig support for CONFIG_SYS_I2C_ZYNQ.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 drivers/i2c/Kconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 7dbec77..62d134c 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -268,6 +268,12 @@ config SYS_I2C_BUS_MAX
help
  Define the maximum number of available I2C buses.

+config SYS_I2C_ZYNQ
+   bool "Xilinx I2C driver"
+   depends on ARCH_ZYNQMP || ARCH_ZYNQ || ZYNQ_I2C0 || ZYNQ_I2C1
+   help
+ Support for Xilinx I2C controller.
+
 config SYS_I2C_IHS
 bool "gdsys IHS I2C driver"
 depends on DM_I2C
--
2.7.4

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[U-Boot] [UBOOT PATCH 2/6] i2c: Enabled CONFIG_SYS_I2C_ZYNQ in the respective defconfig

[Vipul Kumar]

This patch enabled CONFIG_SYS_I2C_ZYNQ in the respective
defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/syzygy_hub_defconfig  | 1 +
 configs/topic_miami_defconfig | 1 +
 configs/topic_miamilite_defconfig | 1 +
 configs/topic_miamiplus_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 +
 configs/xilinx_zynqmp_zcu102_revA_defconfig   | 1 +
 configs/xilinx_zynqmp_zcu102_revB_defconfig   | 1 +
 configs/zynq_zc702_defconfig  | 1 +
 configs/zynq_zc706_defconfig  | 1 +
 configs/zynq_zybo_defconfig   | 1 +
 include/configs/xilinx_zynqmp_zcu102.h| 1 -
 include/configs/zynq-common.h | 4 
 12 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 996ecdb..334b840 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -34,6 +34,7 @@ CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index d5929a1..bd8eff7 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/topic_miamilite_defconfig 
b/configs/topic_miamilite_defconfig
index a318e50..dcf8f47 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/topic_miamiplus_defconfig 
b/configs/topic_miamiplus_defconfig
index 7281f7b..4f771f0 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig 
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index d0a1467..12a0d64 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -53,6 +53,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig 
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index ecefb00..b6e8a0e 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -53,6 +53,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index c2add99..c5bc4cd 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -53,6 +53,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 878bc79..b20744a 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -40,6 +40,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 7b2e072..882150f 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -40,6 +40,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 138b249..4e3d6c5 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -39,6 +39,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
diff --git a/include/configs/xilinx_zynqmp_zcu102.h 
b/include/configs/xilinx_zynqmp_zcu102.h
index 85f78ba..88819c6 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -36,7 +36,6 @@
{1, {{I2C_MUX_PCA9

[U-Boot] [UBOOT PATCH 2/4] fpga: Added CONFIG_FPGA_SPARTAN3 in the the respective defconfig

[Vipul Kumar]

This patch added CONFIG_FPGA_SPARTAN3 in the
respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/apf27_defconfig  | 1 +
 configs/astro_mcf5373l_defconfig | 1 +
 configs/mt_ventoux_defconfig | 1 +
 configs/x600_defconfig   | 1 +
 include/configs/apf27.h  | 1 -
 include/configs/astro_mcf5373l.h | 1 -
 include/configs/mt_ventoux.h | 1 -
 include/configs/x600.h   | 1 -
 8 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 00aa7c3..d7437ed 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -34,6 +34,7 @@ 
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),5
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_MXC_GPIO=y
 CONFIG_MMC_MXC=y
 CONFIG_NAND=y
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index 011dc36..71250af 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -19,4 +19,5 @@ CONFIG_CMD_JFFS2=y
 CONFIG_FPGA_ALTERA=y
 CONFIG_FPGA_CYCLON2=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index 49ddcc6..66dcc03 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -31,6 +31,7 @@ 
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),2
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_OMAP24_I2C_SPEED=40
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NAND=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index d1711e0..735c04c 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -39,6 +39,7 @@ CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index d95da27..0bd280c 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -209,7 +209,6 @@
  * FPGA
  */
 #define CONFIG_FPGA_COUNT  1
-#define CONFIG_FPGA_SPARTAN3
 #define CONFIG_SYS_FPGA_WAIT   250 /* 250 ms */
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index f3a8693..70aacda 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -175,7 +175,6 @@
 #define CONFIG_SYS_LONGHELP

 #define CONFIG_FPGA_COUNT  1
-#defineCONFIG_FPGA_SPARTAN3
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT   1000

diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index bee8ddd..6cca902 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -33,7 +33,6 @@
 /*
  * FPGA
  */
-#define CONFIG_FPGA_SPARTAN3
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT   1
 #define CONFIG_MAX_FPGA_DEVICES1
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 3f63761..9ada370 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -85,7 +85,6 @@
 #define CONFIG_SYS_I2C_RTC_ADDR0x68

 /* FPGA config options */
-#define CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_COUNT  1

 /* USB EHCI options */
--
2.7.4

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[U-Boot] [UBOOT PATCH 4/4] arm: zynq: fpga: Added CONFIG_FPGA_ZYNQPL in the respective defconfig

[Vipul Kumar]

This patch added CONFIG_FPGA_ZYNQPL in the respective defconfig.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 configs/syzygy_hub_defconfig   | 1 +
 configs/topic_miami_defconfig  | 1 +
 configs/topic_miamilite_defconfig  | 1 +
 configs/topic_miamiplus_defconfig  | 1 +
 configs/zynq_cc108_defconfig   | 1 +
 configs/zynq_microzed_defconfig| 1 +
 configs/zynq_picozed_defconfig | 1 +
 configs/zynq_z_turn_defconfig  | 1 +
 configs/zynq_zc702_defconfig   | 1 +
 configs/zynq_zc706_defconfig   | 1 +
 configs/zynq_zc770_xm010_defconfig | 1 +
 configs/zynq_zc770_xm011_defconfig | 1 +
 configs/zynq_zc770_xm011_x16_defconfig | 1 +
 configs/zynq_zc770_xm012_defconfig | 1 +
 configs/zynq_zc770_xm013_defconfig | 1 +
 configs/zynq_zed_defconfig | 1 +
 configs/zynq_zybo_defconfig| 1 +
 include/configs/zynq-common.h  | 2 --
 18 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 996ecdb..8f06465 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index d5929a1..e8aaee9 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -30,6 +30,7 @@ CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/topic_miamilite_defconfig 
b/configs/topic_miamilite_defconfig
index a318e50..3f8681f 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -30,6 +30,7 @@ CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/topic_miamiplus_defconfig 
b/configs/topic_miamiplus_defconfig
index 7281f7b..496c43e 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -28,6 +28,7 @@ CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 24e9cfe..3a4de92 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index b34520f..94a1a40 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -34,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 2f90918..f9ee904 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index 68a2208..7a51b85 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 878bc79..c6a7893 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 7b2e072..665b4d3 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/zynq_zc770_xm010_defconfig 
b/configs/zynq_zc770_xm010_defconfig
index 125f97d..f4279c6 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@

[U-Boot] [UBOOT PATCH 1/4] fpga: Added Kconfig support for FPGA_SPARTAN3

[Vipul Kumar]

This patch added Kconfig support for FPGA_SPARTAN3.

Signed-off-by: Vipul Kumar <vip...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
---
 drivers/fpga/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 6b2c866..ac08bc1 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -45,4 +45,9 @@ config FPGA_ZYNQMPPL
  Enable FPGA driver for loading bitstream in BIT and BIN format
  on Xilinx Zynq UltraScale+ (ZynqMP) device.

+config FPGA_SPARTAN3
+   bool "Enable Spartan3 FPGA driver"
+   help
+ Enable Spartan3 FPGA driver for loading in BIT format.
+
 endmenu
--
2.7.4

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[U-Boot] [UBOOT PATCH 0/4] fpga: Moved fpga u-boot headers to the Kconfig

[Vipul Kumar]

This series of patch moved fpga u-boot headers to the
kconfig and enabled in respective defconfig.
These are the configs:
-CONFIG_FPGA_SPARTAN3
-CONFIG_FPGA_ZYNQPL

Vipul Kumar (4):
  fpga: Added Kconfig support for FPGA_SPARTAN3
  fpga: Added CONFIG_FPGA_SPARTAN3 in the the respective defconfig
  arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL
  arm: zynq: fpga: Added CONFIG_FPGA_ZYNQPL in the respective defconfig

 configs/apf27_defconfig|  1 +
 configs/astro_mcf5373l_defconfig   |  1 +
 configs/mt_ventoux_defconfig   |  1 +
 configs/syzygy_hub_defconfig   |  1 +
 configs/topic_miami_defconfig  |  1 +
 configs/topic_miamilite_defconfig  |  1 +
 configs/topic_miamiplus_defconfig  |  1 +
 configs/x600_defconfig |  1 +
 configs/zynq_cc108_defconfig   |  1 +
 configs/zynq_microzed_defconfig|  1 +
 configs/zynq_picozed_defconfig |  1 +
 configs/zynq_z_turn_defconfig  |  1 +
 configs/zynq_zc702_defconfig   |  1 +
 configs/zynq_zc706_defconfig   |  1 +
 configs/zynq_zc770_xm010_defconfig |  1 +
 configs/zynq_zc770_xm011_defconfig |  1 +
 configs/zynq_zc770_xm011_x16_defconfig |  1 +
 configs/zynq_zc770_xm012_defconfig |  1 +
 configs/zynq_zc770_xm013_defconfig |  1 +
 configs/zynq_zed_defconfig |  1 +
 configs/zynq_zybo_defconfig|  1 +
 drivers/fpga/Kconfig   | 12 
 include/configs/apf27.h|  1 -
 include/configs/astro_mcf5373l.h   |  1 -
 include/configs/mt_ventoux.h   |  1 -
 include/configs/x600.h |  1 -
 include/configs/zynq-common.h  |  2 --
 27 files changed, 33 insertions(+), 6 deletions(-)

--
2.7.4

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