This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed
Signed-off-by: Ye Li
---
No changes in v2
arch/arm/mach-imx/imx9/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2
Change to regulator_set_enable_if_allowed to avoid enable failure,
in case same phy supply shared by multiple FEC controllers.
Signed-off-by: Ye Li
---
drivers/net/fec_mxc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index
The spl_spi_get_uboot_offs weak function is defined unsigned int.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/image-container.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index c9455fe..35da0ae
imx_tmu_arch_init does not implement for iMX8MQ, error is returned
Signed-off-by: Ye Li
---
drivers/thermal/imx_tmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 4721cfb..ca775e5 100644
--- a/drivers/thermal/imx_tmu.c
+++ b
The size for flexspi AHB buffer space is wrong, so correct it.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx9/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 15e87b8..2117489 100644
--- a/arch/arm/mach
This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx9/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/mu.h
b/arch
To work with commit 2f3c920(imx8m: workaround ROM serror),
we need to enable the SError exception and install vector in SPL.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8m/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b
Hi Thomas,
It is due to ARMV8_SPL_EXCEPTION_VECTORS not enabled by default in
upstream. I will send a patch
Best regards,
Ye Li
> -Original Message-
> From: Thomas Schaefer
> Sent: Thursday, January 11, 2024 9:40 PM
> To: Ye Li ; Peng Fan (OSS) ;
> 'u-boot@lists
I think there is no particular SW support needed for FIELD_RETURN on 8MN.
From what you described, you have moved the part from closed to FIELD_RETURN.
So are you
able to boot into SPL without signature?
Best regards,
Ye Li
> -Original Message-
> From: Peng Fan (OSS)
> Sent:
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+
PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but
has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver
and add new type for PCA9451A.
Signed-off-by: Ye Li
---
drivers/power/pmic/pca9450.c | 1 +
drivers/power/regulator/pca9450.c | 11 ++-
include
Get and print boot stage through ROM API in SPL
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 7 +++
arch/arm/mach-imx/spl_imx_romapi.c| 22 +-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm
-by: Ye Li
Signed-off-by: Peng Fan
---
board/freescale/imx8ulp_evk/lpddr4_timing.c | 2 +-
board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c
b/board/freescale/imx8ulp_evk
the fdt header check in above case
will not pass.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
board/freescale/imx8ulp_evk/imx8ulp_evk.c | 8
1 file changed, 8 insertions(+)
diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index b58f143
To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li
Acked-by: Peng
not need the setting.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
drivers/misc/sentinel/fuse.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index aa691d3..99342d3 100644
--- a/drivers
From: Jacky Bai
Update the ddr init flow to support LPDDR3 and PLL bypass mode.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
---
drivers/ddr/imx/imx8ulp/ddr_init.c | 55 +-
1 file changed, 43 insertions(+), 12 deletions(-)
diff --git a/drivers/ddr/imx
ned-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index cb6e393..5582ff1 100644
--- a/arch/arm/include/asm/mach-imx/s400_ap
Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
Reviewed-by: Alice Guo
---
drivers/misc/sentinel/fuse.c | 10 ++
1 file
Remove the DDR initialization codes from board and enable the iMX8ULP
DDR driver.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/Kconfig | 1 +
board/freescale/imx8ulp_evk/Makefile | 2 +-
board/freescale/imx8ulp_evk/ddr_init.c | 207 -
3 files
594M
PLL4 PFD2: 792M -> 316.8M
NIC_AP:96M (ND) -> 192M, 48M (LD) -> 96M
NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M
USDHC0:PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD)
USDHC1:PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
USDHC2:PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
Signed-of
From: Jacky Bai
Update the dram timing to support PLL bypass mode
for F1.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
---
board/freescale/imx8ulp_evk/lpddr4_timing.c | 204 ++--
1 file changed, 102 insertions(+), 102 deletions(-)
diff --git a/board/freescale
-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/cgc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index d240aba..104109e 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware
Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
---
drivers/ddr/imx/imx8ulp/Kconfig | 2 +-
1 file
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/rdc.c | 15
Need to add DRAM access permission for S400, as S400 needs to access
it When SPL calls image authentication
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/rdc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 1 +
arch/arm/include
PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/rdc.h | 1 +
arch/arm/mach-imx/imx8ulp/rdc.c | 41 +
board/freescale/imx8ulp_evk/spl.c | 8 ---
3 files changed, 47
From: Peng Fan
To clean the upower codes by aligning codes format, check err_code
and add detail bits list for the memory magic number
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 90 +++
1 file changed, 78 insertions
. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx
, u-boot can't access SEC SIM and FSB.
Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 +
arch/arm/include/asm/global_data.h| 3 +
arch/arm/mach-imx/imx8ulp/soc.c | 104 ++
board/freescale
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/rdc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-imx
Since A1 ROM has fixed the ROM API eMMC issue, we should only use
the workaround for A0.1 part. Add a SOC revision check.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx
As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.
Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
---
arch/arm/mach-imx
Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/soc.c | 6 ++
1 file changed, 2 insertions
):
imx: imx8ulp: upower: replace magic number with macro
imx: imx8ulp: upower: make code cleaner
imx8ulp_evk: disable overflow of port0 for LPAV
Ye Li (18):
imx: imx8ulp: Fix MU device probe failure
imx: imx8ulp: Get chip revision from Sentinel
imx: imx8ulp: Limit the eMMC ROM API
From: Alice Guo
DM watchdog timer driver and non-DM driver exist in ulp_wdog.c at the
same time. Add a compilation restriction that only compile the DM driver
part when CONFIG_WDT=y.
Signed-off-by: Alice Guo
Reviewed-by: Ye Li
---
drivers/watchdog/ulp_wdog.c | 2 ++
1 file changed, 2
Fix the issue in commit 46c9016 (env: mcc: Drop unnecessary #ifdefs)
If CONFIG_SYS_REDUNDAND_ENVIRONMENT is not defined, the offset value
becomes undetermined, so write env to unexpected offset.
Signed-off-by: Ye Li
---
env/mmc.c | 8
1 file changed, 4 insertions(+), 4 deletions
The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9.
So remove it from lifecycle print.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/ele_ahab.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
Before moving the lifecycle to OEM closed, confirm the lifecycle is
OEM open, otherwise cancel to move forward the lifecycle.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/ele_ahab.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-imx/ele_ahab.c
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since
both of them use same sentinel ELE APIs
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 +
arch/arm/include/asm/arch-imx9/imx-regs.h| 2 +
arch/arm/mach-imx/Makefile
Remove legacy command definitions, change to use new ELE_xxx command
request.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 15 ---
arch/arm/mach-imx/imx8ulp/rdc.c | 2 +-
arch/arm/mach-imx/imx9/trdc.c| 2
For ahab_status command, support to get and decode AHAB events
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 99 +++
arch/arm/mach-imx/imx9/ahab.c| 286 ---
2 files changed, 359 insertions(+), 26
Add get_events API to retrieve any singular events that has occurred
since the FW has started from sentinel
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 ++
drivers/misc/sentinel/s400_api.c | 45
2 files
Hi Marcel,
On Tue, 2023-01-17 at 09:16 +, Marcel Ziswiler wrote:
> Caution: EXT Email
>
> Hi Ye Li
>
> On Tue, 2023-01-17 at 13:34 +0800, Ye Li wrote:
> >
> > In commit 48ddafd (imx8mm_evk: Switch to new imx8mm evk board),
> > the iMX8MM EVK support w
The property fsl,mux_mask is deleted by commit ed7bda5 (imx8ulp:
synchronise device tree with linux). This causes the pinctrl
driver not work on 8ULP, so fail to print any log.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch
and defconfig, then cause SPL boot failure.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +-
arch/arm/dts/imx8mm-evk.dtsi| 127 +++-
2 files changed, 68 insertions(+), 63 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
b/arch/arm
ys_pll2_200m", "sys_pll1_40m",
> "sys_pll2_100m",
> "sys_pll1_800m",
> "sys_pll2_500m", "clk_ext4",
> "audio_pll2_out" };
> @@ -324,6 +3
Because mxs_nand_spl driver does not support DM, to use the minimum ECC
layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC.
Signed-off-by: Ye Li
Reviewed-by: Han Xu
---
Changes in v2:
- Use IS_ENABLED to replace #ifdef
drivers/mtd/nand/raw/mxs_nand.c | 3 +++
1 file changed, 3
On Thu, 2022-03-31 at 00:27 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/29/22 11:56, Ye Li wrote:
>
> Hi,
>
> >
> > >
> > > >
> > > > But once you want to upgrade the
> > > > flash.bin, flexspi configurati
On Tue, 2022-03-29 at 11:01 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/29/22 04:49, Ye Li wrote:
>
> Hi,
>
> >
> > >
> > > >
> > > > If you change the ROM API driver, that will break our design.
> > > > You
&g
Because mxs_nand_spl driver does not support DM, to use the minimum ECC
layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC.
Signed-off-by: Ye Li
---
drivers/mtd/nand/raw/mxs_nand.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd
On Mon, 2022-03-28 at 16:54 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/28/22 08:54, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> [...]
>
> >
> > >
> > > >
> > > > 2. Update the u-boot.itb offset in imx8mp-u-bo
the page unaligned offset,
but the spl_simple_fit_read can't do it. spl_simple_fit_read requires
the FIT location at page aligned offset.
Hence, remove the nand_get_mtd overwrite function from mxs_nand_spl
to use page unaligned read by driver.
Signed-off-by: Ye Li
---
drivers/mtd/nand/raw
controller. So once
removed usb_hub, the power domain is power off before removing USB controller.
Signed-off-by: Ye Li
---
common/usb_hub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index ba11a18..990993a 100644
--- a/common/usb_hub.c
Hi Marek,
On Wed, 2022-03-23 at 22:16 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/23/22 03:42, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> >
> > >
> > > >
> > > > >
> > > > > diff --git a/arch/arm
Hi Marek,
On Mon, 2022-03-21 at 15:59 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/21/22 04:35, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> >
> > >
> > > diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-
> > &g
tion or boot
partition.
If you changed to "image_offset +
(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000", the address
for flexspi becomes 0x59000 (= 0x1000 + 0x6 - 0x8000)
Best regards,
Ye Li
>
> static int is_boot_from_stream_device(u32 boot)
> --
> 2.34.1
>
Hi Michael,
On Fri, 2022-03-11 at 15:01 +0100, Dario Binacchi wrote:
> Caution: EXT Email
>
> Hi,
>
> On Fri, Mar 11, 2022 at 1:26 PM Ye Li wrote:
> >
> >
> > Hi Michael,
> >
> > On Fri, 2022-03-11 at 08:57 +0100, Michael Nazzareno Trimarc
he same issue here with IMX6Q/DL GPMI NAND.
> >
> > If I re-flash the ubi within U-Boot (tftpboot $loadaddr rootfs.ubi
> > &&
> > nand erase.part rootfs && nand write $loadaddr rootfs $filesize) I
> > find that U-Boot can attach and mount the ubi fine but Linux will
> > have
> > issues
> Interesting! This sounds like U-Boot and Linux somehow diverge in how
> they handle the ECC data in OOB. I'm pretty confident that Linux does
> things "correctly" and U-Boot should match what Linux does in this
> case.
>
> Does the patch (revert of 616f03dabacb) I mentioned before "solve"
> the
> issue for your case, too?
>
> @Han, Ye, Peng: As you signed-off the mentioned commit, do you have
> any
> ideas for a fix?
The dt nand driver will check "fsl,legacy-bch-geometry" property to use
legacy bch. If this can't work for you in case you don't use DM driver,
I prefer adding a config to select the legacy bch not reverting the
patch.
Best regards,
Ye Li
>
> Thanks
> Frieder
Disable SPL exception vector which causes issue to ROM patch execution
when SPL calling ROM API.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig
b/arch/arm/mach-imx/imx8ulp/Kconfig
index 963fc93
Hi Michael,
On Fri, 2022-03-11 at 08:57 +0100, Michael Nazzareno Trimarchi wrote:
> Caution: EXT Email
>
> Hi
>
> On Tue, Mar 8, 2022 at 7:42 AM Ye Li wrote:
> >
> >
> > The change in commit c1af358 (imx: mx6ull: fix REFTOP_VBGADJ
> > setting)
> >
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111
Signed-off-by: Ye Li
---
arch/arm/mach-imx/mx6/soc.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
inde
sha1_csum_wd(pbuf, buf_len, pout,
> CHUNKSZ_SHA1);
> + else
> + sha256_csum_wd(pbuf, buf_len, pout,
> CHUNKSZ_SHA256);
> + return 0;
How about adding “#ifdef CONFIG_SHA1” and “#ifdef CONFIG_SHA256” here
? Then it can depend on users’ selection to determine the fallback
Best regards,
Ye Li
> }
>
> size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
> --
> 2.25.1
>
locks per sample;
> * 1200 clocks per sample generates better entropy.
> */
> -static void kick_trng(int ent_delay, uint8_t sec_idx)
> +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> {
> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> *)SEC
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> added api and descriptor for blob key encryption key(bkek)
> generation.
> added api for random number generation.
>
> Signed-off-by: Gaurav Jain
> Signed-off-by: Ji Luo
Reviewed-by: Ye Li
Best regards,
Ye Li
>
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8(QM/QXP) - added support for JR driver model.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain
> Signed-off-by: Horia Geantă
Reviewed-by: Ye Li
B
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
>
> disabled use of JR1 in SPL and uboot, as JR1 is reserved
> for SECO FW.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> --
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> added crypto node in device tree.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/Kconfig
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX7D - added support for JR driver model.
>
> removed sec_init() call, sec is initialized based on
> job ring information processed from device tree.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye
; + select ARCH_MISC_INIT
>
Can you also enable the JR driver for MX6SABREAUTO, MX6SABRESD and
MX6UL_9X9_EVK?
Best regards,
Ye Li
> config TARGET_MX6UL_ENGICAM
> bool "Support Engicam GEAM6UL/Is.IoT"
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-
>
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8MM/MN/MP/MQ - added support for JR driver model.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
&
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> disabled use of JR0 in SPL and uboot, as JR0 is reserved
> for secure boot.
>
> Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
Best regards,
Ye Li
> ---
> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 18
Since the mxs_nand_spl has implemented adjust read offset in
nand_spl_load_image, so we don't need to check the bad block in
nand_spl_adjust_offset. Directly return the offset to continue
read by nand_spl_load_image.
Signed-off-by: Ye Li
---
drivers/mtd/nand/raw/mxs_nand_spl.c | 5 +
1 file
HS400_ES is missed when down grade to HS mode during
device_remove the mmc device
Signed-off-by: Ye Li
---
drivers/mmc/mmc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index a1fd533..3cb6fda 100644
--- a/drivers/mmc/mmc.c
When send_status is false or wait_dat0 is not supported, the switch
function should not send CMD13 but directly return.
Signed-off-by: Ye Li
---
drivers/mmc/mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8078a89..a1fd533
According to 8MM/MN/MP reference manual, their pad registers only have
4 valid DSE values. And DSE2 and DSE4 are different with current
definitions in iomux-v3.h. Fix the issue to align with manual.
Signed-off-by: Ye Li
Acked-by: Peng Fan
---
arch/arm/include/asm/mach-imx/iomux-v3.h | 21
become ready (ACMD14 timeout) due to the clock is enabled during
power cycle.
Signed-off-by: Ye Li
Reviewed-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index aabf395
Since SPL has initialized clocks for bus and core. We don't need to
set the default clocks for clock controller node.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB
to facilitate the case that only has FEC enabled.
Signed-off-by: Ye Li
---
configs/imx8mp_evk_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index
DWC EQOS driver has removed to use noncached memory, so delete
the configuration from iMX8MP EVK head file.
Signed-off-by: Ye Li
---
include/configs/imx8mp_evk.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index a6569d5
Since we uses the DTS and PHY reset gpio in EQoS driver to do the
reset, remove the duplicated codes from board file.
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
The setup functions should be independent for two ethernet controllers
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
i.MX8MP EVK has two ethernet ports. Add relevant nodes and properties
for EQoS port to the EVK DTS file.
In -u-boot.dtsi, change the u-boot eqos compatible string, add PHY
reset gpio and remove assigned clocks as not supported in CCF.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi
i.MX8MP has one DWC EQoS controller, so allow to build mac.c when
only this driver is enabled.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0ef2695..74a2a2a 100644
--- a/arch
i.MX8MP has two ENET controllers, have to update the function to
enable loading two MAC addresses.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/mac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
index 3b1496b..9bb63d2 100644
(void *)((CONFIG_SYS_TEXT_BASE -
> CONFIG_FIT_EXTERNAL_OFFSET));
It looks odd to use CONFIG_FIT_EXTERNAL_OFFSET. This config is used
to designate the image offset inside the FIT. It is irrelevant here.
Please follow the patch 719d665a87c6: ("MLK-20467 imx8m: Fix issue for
booting sign
aining, I'll pick up the revert patch then.
> > > >
> > > > For your LMB tree, I like the initial approach but looking at
> > > > 528915c71762 ("imx: Fix potential lmb memory overwritten by
> > > > stack") I
> > > > think that s
kiA%3Dreserved=0
>
> ?
>
The fit buffer was used in SPL is a fit size related offset to u-boot
base. In mkimage, we generate IVT following the same calculation. So we
don't use ivt->self, this address is aligned between SPL and IVT.
Your patch depends on IVT. But actuall
Hi Stefano,
Ok. I will rebase the patches after the 8ULP is merged.
Best regards,
Ye Li
> -Original Message-
> From: Stefano Babic
> Sent: Saturday, July 17, 2021 8:54 PM
> To: Ye Li ; sba...@denx.de; u-boot@lists.denx.de; Peng Fan
> ; ma...@denx.de
> Cc: rfried
Hi Michael,
> -Original Message-
> From: Michael Nazzareno Trimarchi
> Sent: Thursday, July 15, 2021 2:52 PM
> To: Peng Fan (OSS)
> Cc: Peng Fan ; U-Boot-Denx ;
> Stefano Babic ; Ye Li ; Fabio Estevam
> ; Jagan Teki
> Subject: [EXT] Re: Problem on imx: add r
errors like
EHCI timed out on TD - token=0x801f8c80
Signed-off-by: Ye Li
---
Changes in v2:
- Remove unnecessary cast and parenthesis
- Abort the transfer when IAA cycle timeout
- Add steps to reproduce the issue
drivers/usb/host/ehci-hcd.c | 27 +++
drivers/usb/
Hi Marek,
On Tue, 2021-03-09 at 09:08 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/9/21 4:18 AM, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> [...]
>
> >
> > >
> > > >
> > > >
> > >
Hi Marek,
On Mon, 2021-03-08 at 09:50 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/8/21 4:35 AM, Ye Li wrote:
> [...]
> >
> > +static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
> > +{
> > + u32 cmd, status;
> > + int ret;
> >
sts on USB disk. The
USB_ASYNCLISTADDR register is changed to a invalid address when the
issue happens. It is fixed after adding the IAA handshake.
Signed-off-by: Ye Li
---
drivers/usb/host/ehci-hcd.c | 25 +
drivers/usb/host/ehci.h | 1 +
2 files changed, 26 insertion
Hi Marek,
On Fri, 2021-02-26 at 13:44 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 2/26/21 8:15 AM, Ye Li wrote:
> >
> > Hi Marek,
> >
> > On Thu, 2021-02-25 at 21:52 +0100, Marek Vasut wrote:
> > >
> > > Caution: EXT Email
&g
Hi Fabio,
On Thu, 2021-02-25 at 10:49 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Ye Li,
>
> On Thu, Feb 25, 2021 at 10:34 AM Ye Li wrote:
>
> >
> > Sure, I have tested it on 8mq evk. I can reproduce the two issues
> > you
> > met.
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