Re: [U-Boot] no DTB with nand SPL on sama5d3

2019-01-21 Thread Ben Whitten 

Hi,

On 17/01/2019 21:34, Daniel Evans wrote:

Follow up question:

I notice that u-boot-spl-pad.bin is empty even though CONFIG_SPL_PAD_TO = 
CONFIG_SPL_MAX_SIZE = 0x18000.  Is that why it isn’t find the dtb because it 
isn’t padded properly?


As an aside although it buried as a footnote in the datasheet.
When the ROM code in the SAMA5D3 checks to see if SPL is valid code 
based on the size in the 6th vector or by checking the size of boot.bin 
from FAT, it must fit within SRAM0 (64KB, 0x1) [1]


So whilst you have 128KB of SRAM, you can only load and execute SPL 
within 64KB (0x1), perhaps CONFIG_SPL_MAX_SIZE should updated.


[1] Atmel SAMA5D3 datasheet, 11.4.3.1 under Figure 11-7, & 11.4.3.2.

Thanks,
Ben



Dan


On Jan 17, 2019, at 2:09 AM, eugen.hris...@microchip.com wrote:



On 17.01.2019 11:05, Simon Goldschmidt wrote:

On Thu, Jan 17, 2019 at 10:02 AM  wrote:




On 16.01.2019 21:05, Daniel Evans wrote:

Hello,

Yes, I am trying to load the U-boot SPL

What I posted previously was a custom board.  I switched over to the 
sama5d3_xplained and all I get with sama5d3_xplained_nandflash_defconfig is 
ROMBOOT.


This is definitely weird. Are you using vanilla u-boot and no changes on
top with the sama5d3_xplained? Looks like not even your console works in
spl, or, you have a bad binary .


With debug uart enabled it shows the DTB is missing. So when using the
mainline defconfig (where debug uart is disabled) it fails to find a console as
the DTB is missing. That's unfortunate, but expected behaviour with DM_SERIAL,
I guess.

I don't know the hardware, but the real problem seems to me that the binary
being flashed is somehow missing the DTB?


Yes that can happen, I suggested that some parts of the SPL are missing
- either the binary flashed is smaller than the real size (and the DTB,
being at the end is not copied...),

or the value inside the 6th vector is wrong, and the first stage
bootloader is not copying enough data from NAND to RAM when executing
the SPL binary. The first stage BL only copies the number of bytes given
by 6th vector value



Regards,
Simon





AT91bootstrap works fine.

I know there was the issue with the nand_header showing up for the SD card but 
that shouldn’t effect the nand.  Some other patch I am missing to get a 
non-modified boot.bin nand working?


How are you writing your nandflash ? are you using our sam-ba tool to
write it ? do you use writeboot applet ?



The size of the 6th reset vector looks correct, with the assumption that it 
does not include the 208 bytes of nand_header?


Yes it should not include it. And if you write using sam-ba the nand
header will be written by sam-ba, so your binary should not include it
already.

I also suggest you open up a support ticket on support.microchip.com as
our FAE have a lot of experience to assist with such situations.

Hope this helps,
Eugen



Dan




On Jan 16, 2019, at 6:02 AM, eugen.hris...@microchip.com wrote:




On 16.01.2019 03:13, Daniel Evans wrote:

After flashing my boot.bin to nand I get the following output:

RomBOOT
 Missing DTB
### ERROR ### Please RESET the board ###

I found the error message in fdtdec.c, but not sure what I am missing.  I have 
checked that my DTB is included in the boot.bin output.  Any insight on what I 
am missing?


Hello Daniel,

Which defconfig are you using when building u-boot ?

You are trying to load the U-boot SPL right ?

It doesn't look like you even get to the point when you get to load the
u-boot proper, so maybe there are missing parts from your SPL, or the
size inside the 6th reset vector is not correctly calculated

Did you try with our at91bootstrap proprietary second level bootloader
and get the same issue when booting the proper u-boot with it ?

Hope this helps,

Eugen



Dan
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Re: [U-Boot] [PATCH 4/4] ARM: at91: lds: add test SPL binary size and bbs size

2018-11-19 Thread Ben Whitten 
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On
> Behalf Of eugen.hris...@microchip.com
> Sent: 19 November 2018 08:23
> To: u-boot@lists.denx.de
> Cc: nicolas.fe...@microchip.com;
> wenyou.y...@atmel.com
> Subject: [U-Boot] [PATCH 4/4] ARM: at91: lds: add test SPL
> binary size and bbs size
> 
> From: Wenyou Yang 
> 
> Add the test for the SPL binary size and the bbs section size.
> 
> Signed-off-by: Wenyou Yang 
> ---
>  arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 10
> ++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
> b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
> index eca78f8..82098dc 100644
> --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
> +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
> @@ -48,3 +48,13 @@ SECTIONS
>   __bss_end = .;
>   } >.sdram
>  }
> +
> +#if defined(CONFIG_SPL_MAX_SIZE)
> +ASSERT(__image_copy_end - __image_copy_start <

There is no __image_copy_start causing SPL size calculation
to error, replacing with __start resolves it.

> (CONFIG_SPL_MAX_SIZE), \
> + "SPL image too big");
> +#endif
> +
> +#if defined(CONFIG_SPL_BSS_MAX_SIZE)
> +ASSERT(__bss_end - __bss_start <
> (CONFIG_SPL_BSS_MAX_SIZE), \
> + "SPL image BSS too big");
> +#endif
> --
> 2.7.4
> 
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Re: [U-Boot] [PATCH 3/4] configs: wb45n_defconfig: Remove SPL

2018-11-19 Thread Ben Whitten 
Just compiled with the bootlin toolchain
' armv5-eabi--musl--stable-2018.02-2' from within buildroot
and it looks like an image is produced within size.
text   data bss dec hex filename
  1796511804480   236255c49 u-boot-spl

It looks like the assertion calculates the assertion
incorrectly, will comment on that patch.

Ben
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On
> Behalf Of Ben Whitten
> Sent: 19 November 2018 10:30
> To: eugen.hris...@microchip.com; u-boot@lists.denx.de
> Cc: nicolas.fe...@microchip.com
> Subject: Re: [U-Boot] [PATCH 3/4] configs:
> wb45n_defconfig: Remove SPL
> 
> Hi,
> 
> A shame as these boards only really need to start NAND and
> boot uboot proper. Out of interest how much is it over in
> the
> builder?
> 
> If SPL can't be shrunk any further then fair enough and;
> Acked-by: Ben Whitten 
> 
> Thanks,
> Ben
> 
> > -Original Message-
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On
> > Behalf Of eugen.hris...@microchip.com
> > Sent: 19 November 2018 08:23
> > To: u-boot@lists.denx.de
> > Cc: nicolas.fe...@microchip.com
> > Subject: [U-Boot] [PATCH 3/4] configs: wb45n_defconfig:
> > Remove SPL
> >
> > Due the size of SPL being too big, remove the SPL support.
> > ---8<---
> > arm-linux-gnueabi-ld: SPL image too big
> > --->8---
> >
> > Signed-off-by: Eugen Hristev
> > 
> > ---
> >  configs/wb45n_defconfig | 6 --
> >  1 file changed, 6 deletions(-)
> >
> > diff --git a/configs/wb45n_defconfig
> > b/configs/wb45n_defconfig
> > index 9d881e5..aef4e75 100644
> > --- a/configs/wb45n_defconfig
> > +++ b/configs/wb45n_defconfig
> > @@ -3,17 +3,11 @@ CONFIG_SYS_THUMB_BUILD=y
> >  CONFIG_ARCH_AT91=y
> >  CONFIG_SYS_TEXT_BASE=0x23f0
> >  CONFIG_TARGET_WB45N=y
> > -CONFIG_SPL_GPIO_SUPPORT=y
> > -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > -CONFIG_SPL_SERIAL_SUPPORT=y
> > -CONFIG_SPL=y
> >  CONFIG_NR_DRAM_BANKS=1
> >  CONFIG_FIT=y
> >
> >
> CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NA
> > NDFLASH"
> >  CONFIG_BOOTDELAY=3
> >  CONFIG_BOARD_EARLY_INIT_F=y
> > -CONFIG_SPL_NAND_SUPPORT=y
> >  CONFIG_HUSH_PARSER=y
> >  CONFIG_CMD_BOOTZ=y
> >  CONFIG_CMD_MEMTEST=y
> > --
> > 2.7.4
> >
> >
> __
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Re: [U-Boot] [PATCH 3/4] configs: wb45n_defconfig: Remove SPL

2018-11-19 Thread Ben Whitten 
Hi,

A shame as these boards only really need to start NAND and
boot uboot proper. Out of interest how much is it over in the
builder?

If SPL can't be shrunk any further then fair enough and;
Acked-by: Ben Whitten 

Thanks,
Ben

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On
> Behalf Of eugen.hris...@microchip.com
> Sent: 19 November 2018 08:23
> To: u-boot@lists.denx.de
> Cc: nicolas.fe...@microchip.com
> Subject: [U-Boot] [PATCH 3/4] configs: wb45n_defconfig:
> Remove SPL
> 
> Due the size of SPL being too big, remove the SPL support.
> ---8<---
> arm-linux-gnueabi-ld: SPL image too big
> --->8---
> 
> Signed-off-by: Eugen Hristev
> 
> ---
>  configs/wb45n_defconfig | 6 --
>  1 file changed, 6 deletions(-)
> 
> diff --git a/configs/wb45n_defconfig
> b/configs/wb45n_defconfig
> index 9d881e5..aef4e75 100644
> --- a/configs/wb45n_defconfig
> +++ b/configs/wb45n_defconfig
> @@ -3,17 +3,11 @@ CONFIG_SYS_THUMB_BUILD=y
>  CONFIG_ARCH_AT91=y
>  CONFIG_SYS_TEXT_BASE=0x23f0
>  CONFIG_TARGET_WB45N=y
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL=y
>  CONFIG_NR_DRAM_BANKS=1
>  CONFIG_FIT=y
> 
> CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NA
> NDFLASH"
>  CONFIG_BOOTDELAY=3
>  CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_SPL_NAND_SUPPORT=y
>  CONFIG_HUSH_PARSER=y
>  CONFIG_CMD_BOOTZ=y
>  CONFIG_CMD_MEMTEST=y
> --
> 2.7.4
> 
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Re: [U-Boot] [PATCH v2 2/3] fit: allow fit to call hardware accelerated hash

2018-06-28 Thread Ben Whitten 
Hi Tom,

> Subject: Re: [U-Boot] [PATCH v2 2/3] fit: allow fit to call hardware 
> accelerated
> hash
> 
> On Wed, Jun 06, 2018 at 05:03:57PM +0100, Ben Whitten wrote:
> 
> > Move to calling the abstraction which allows for hardware acceleration.
> > We also remove unneeded defines and only include objects if required.
> >
> > Signed-off-by: Ben Whitten 
> [snip]
> > diff --git a/common/image-fit.c b/common/image-fit.c
> > index 8c15ed1..7d8c961 100644
> > --- a/common/image-fit.c
> > +++ b/common/image-fit.c
> > @@ -1082,26 +1082,17 @@ int fit_set_timestamp(void *fit, int noffset,
> time_t timestamp)
> >  int calculate_hash(const void *data, int data_len, const char *algo,
> > uint8_t *value, int *value_len)
> >  {
> > -   if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
> > -   *((uint32_t *)value) = crc32_wd(0, data, data_len,
> > -   CHUNKSZ_CRC32);
> > -   *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
> > -   *value_len = 4;
> > -   } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
> > -   sha1_csum_wd((unsigned char *)data, data_len,
> > -(unsigned char *)value, CHUNKSZ_SHA1);
> > -   *value_len = 20;
> > -   } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
> > -   sha256_csum_wd((unsigned char *)data, data_len,
> > -  (unsigned char *)value, CHUNKSZ_SHA256);
> > -   *value_len = SHA256_SUM_LEN;
> > -   } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
> > -   md5_wd((unsigned char *)data, data_len, value,
> CHUNKSZ_MD5);
> > -   *value_len = 16;
> > -   } else {
> > +   struct hash_algo *hash_algo;
> > +   int ret;
> > +
> > +   ret = hash_lookup_algo(algo, _algo);
> 
> This is unfortunately not code equivalent.  There's a little bit missing
> to switch this over to using SPL_CRC32_SUPPORT as well.  A good test
> would be to make sure that a sunxi platform still builds after this (it
> doesn't currently with the series) and use buildman -Ssdel to compare
> before/after sizes and make sure it's a tiny change in size related to
> the code switch and not a huge change due to droppped (or added!)
> support.  Thanks!

I see that I should be including the crc32.o file regardless in non SPL builds,
now the sunxi board build passes locally.
I tested a fit image with all hashes enabled and they all passed so atleast the
calling of the functions seems to work. Did you spot another inequivalence?
I am un-familiar with the buildman tool, but I shall give it a go as you 
suggest.

Thanks,
Ben
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[U-Boot] [PATCH 1/1] spl: fit: verify images prior to post processing

2018-06-07 Thread Ben Whitten 
Verification of hashes needs to take place before any image post
processing, thus matching full FIT image processing.
This allows mechanisms such as encryption be applied to images
prior to fit generation at the spl level.

Signed-off-by: Ben Whitten 
---
 common/spl/spl_fit.c | 21 +
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 05d6af9..02f7fa2 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -182,9 +182,6 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
uint8_t image_comp = -1, type = -1;
const void *data;
bool external_data = false;
-#ifdef CONFIG_SPL_FIT_SIGNATURE
-   int ret;
-#endif
 
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, _comp))
@@ -245,6 +242,15 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
src = (void *)data;
}
 
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+   printf("## Checking hash(es) for Image %s ... ",
+  fit_get_name(fit, node, NULL));
+   if (!fit_image_verify_with_data(fit, node,
+src, length))
+   return -EPERM;
+   puts("OK\n");
+#endif
+
 #ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
board_fit_image_post_process(, );
 #endif
@@ -270,16 +276,7 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
image_info->entry_point = fdt_getprop_u32(fit, node, "entry");
}
 
-#ifdef CONFIG_SPL_FIT_SIGNATURE
-   printf("## Checking hash(es) for Image %s ...\n",
-  fit_get_name(fit, node, NULL));
-   ret = fit_image_verify_with_data(fit, node,
-(const void *)load_addr, length);
-   printf("\n");
-   return !ret;
-#else
return 0;
-#endif
 }
 
 static int spl_fit_append_fdt(struct spl_image_info *spl_image,
-- 
2.7.4

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[U-Boot] [PATCH v2 3/3] crypto: add Atmel hardware acceleration for SHA1 & 256

2018-06-06 Thread Ben Whitten 
We can use the hardware hash block to reduce space, particularly useful
for verifying FIT signatures from SPL.

Signed-off-by: Ben Whitten 
---
 drivers/crypto/Kconfig |   5 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/atmel_sha.c | 289 +
 drivers/crypto/atmel_sha.h |  52 
 lib/Makefile   |   2 +
 5 files changed, 349 insertions(+)
 create mode 100644 drivers/crypto/atmel_sha.c
 create mode 100644 drivers/crypto/atmel_sha.h

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 1ea116b..7a20edb 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -2,4 +2,9 @@ menu "Hardware crypto devices"
 
 source drivers/crypto/fsl/Kconfig
 
+config ATMEL_SHA
+   bool "Atmel SHA Driver support"
+   help
+ Enables the Atmel SHA accelerator.
+
 endmenu
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index efbd1d3..07af449 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -4,5 +4,6 @@
 #  http://www.samsung.com
 
 obj-$(CONFIG_EXYNOS_ACE_SHA)   += ace_sha.o
+obj-$(CONFIG_ATMEL_SHA)+= atmel_sha.o
 obj-y += rsa_mod_exp/
 obj-y += fsl/
diff --git a/drivers/crypto/atmel_sha.c b/drivers/crypto/atmel_sha.c
new file mode 100644
index 000..ef969eb
--- /dev/null
+++ b/drivers/crypto/atmel_sha.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Atmel SHA engine
+ * Copyright (c) 2018  Laird
+ */
+
+#include 
+#include 
+#include "atmel_sha.h"
+
+#ifdef CONFIG_SHA_HW_ACCEL
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+enum atmel_hash_algos {
+   ATMEL_HASH_SHA1,
+   ATMEL_HASH_SHA256
+};
+
+struct sha_ctx {
+   enum atmel_hash_algos algo;
+   u32 length;
+   u8  buffer[64];
+};
+
+const u8 sha256_der_prefix[SHA256_DER_LEN] = {
+   0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+   0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
+   0x00, 0x04, 0x20
+};
+
+const u8 sha1_der_prefix[SHA1_DER_LEN] = {
+   0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e,
+   0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14
+};
+
+static enum atmel_hash_algos get_hash_type(struct hash_algo *algo)
+{
+   if (!strcmp(algo->name, "sha1"))
+   return ATMEL_HASH_SHA1;
+   else
+   return ATMEL_HASH_SHA256;
+};
+
+static int atmel_sha_process(const u8 *in_addr, u8 buflen)
+{
+   struct atmel_sha *sha = (struct atmel_sha *)ATMEL_BASE_SHA;
+   int i;
+   u32 *addr_buf;
+
+   /* Copy data in */
+   addr_buf = (u32 *)in_addr;
+   for (i = 0; i < (buflen / 4); i++)
+   sha->idatarx[i] = addr_buf[i];
+   debug("Atmel sha, engine is loaded\n");
+
+   /* Wait for hash to complete */
+   while ((readl(>isr) & ATMEL_HASH_ISR_MASK)
+   != ATMEL_HASH_ISR_DATRDY)
+   ;
+   debug("Atmel sha, engine signaled completion\n");
+
+   return 0;
+}
+
+static int atmel_sha_chunk(struct sha_ctx *ctx, const u8 *buf, unsigned int 
size)
+{
+   u8 remaining, fill;
+
+   /* Chunk to 64 byte blocks */
+   remaining = ctx->length & 0x3F;
+   fill = 64 - remaining;
+
+   /* If we have things in the buffer transfer the remaining into it */
+   if (remaining && size >= fill) {
+   memcpy(ctx->buffer + remaining, buf, fill);
+
+   /* Process 64 byte chunk */
+   atmel_sha_process(ctx->buffer, 64);
+
+   size -= fill;
+   buf += fill;
+   ctx->length += fill;
+   remaining = 0;
+   }
+
+   /* We are aligned take from source for any additional */
+   while (size >= 64) {
+   /* Process 64 byte chunk */
+   atmel_sha_process(buf, 64);
+
+   size -= 64;
+   buf += 64;
+   ctx->length += 64;
+   }
+
+   if (size) {
+   memcpy(ctx->buffer + remaining, buf, size);
+   ctx->length += size;
+   }
+
+   return 0;
+}
+
+static int atmel_sha_fill_padding(struct sha_ctx *ctx)
+{
+   unsigned int index, padlen;
+   u64 size, bits;
+   u8 sha256_padding[64] = {
+   0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+   };
+
+   size = ctx->length;
+
+   bits = cpu_to_be64(size << 3);
+
+   /* 64 byte, 512 bit block size */
+   index = ctx->length & 0x3F;
+   padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
+
+   /* set last entry to be 0x80 then 0's*/
+   atmel_sha_chunk(ctx, sha256_padding, padlen);
+   /* Bolt number of bits to the e

[U-Boot] [PATCH v2 2/3] fit: allow fit to call hardware accelerated hash

2018-06-06 Thread Ben Whitten 
Move to calling the abstraction which allows for hardware acceleration.
We also remove unneeded defines and only include objects if required.

Signed-off-by: Ben Whitten 
---
 common/hash.c  |  4 
 common/image-fit.c | 27 +--
 include/image.h| 42 ++
 lib/Makefile   |  5 -
 4 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/common/hash.c b/common/hash.c
index d2f4b3f..ceee124 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -85,6 +85,7 @@ static int hash_finish_sha256(struct hash_algo *algo, void 
*ctx, void
 }
 #endif
 
+#if defined(CONFIG_CRC32)
 static int hash_init_crc32(struct hash_algo *algo, void **ctxp)
 {
uint32_t *ctx = malloc(sizeof(uint32_t));
@@ -110,6 +111,7 @@ static int hash_finish_crc32(struct hash_algo *algo, void 
*ctx, void *dest_buf,
free(ctx);
return 0;
 }
+#endif
 
 /*
  * These are the hash algorithms we support.  If we have hardware acceleration
@@ -159,6 +161,7 @@ static struct hash_algo hash_algo[] = {
 #endif
},
 #endif
+#ifdef CONFIG_CRC32
{
.name   = "crc32",
.digest_size= 4,
@@ -168,6 +171,7 @@ static struct hash_algo hash_algo[] = {
.hash_update= hash_update_crc32,
.hash_finish= hash_finish_crc32,
},
+#endif
 #ifdef CONFIG_MD5
{
.name   = "md5",
diff --git a/common/image-fit.c b/common/image-fit.c
index 8c15ed1..7d8c961 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1082,26 +1082,17 @@ int fit_set_timestamp(void *fit, int noffset, time_t 
timestamp)
 int calculate_hash(const void *data, int data_len, const char *algo,
uint8_t *value, int *value_len)
 {
-   if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
-   *((uint32_t *)value) = crc32_wd(0, data, data_len,
-   CHUNKSZ_CRC32);
-   *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
-   *value_len = 4;
-   } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
-   sha1_csum_wd((unsigned char *)data, data_len,
-(unsigned char *)value, CHUNKSZ_SHA1);
-   *value_len = 20;
-   } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
-   sha256_csum_wd((unsigned char *)data, data_len,
-  (unsigned char *)value, CHUNKSZ_SHA256);
-   *value_len = SHA256_SUM_LEN;
-   } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
-   md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
-   *value_len = 16;
-   } else {
+   struct hash_algo *hash_algo;
+   int ret;
+
+   ret = hash_lookup_algo(algo, _algo);
+   if (ret) {
debug("Unsupported hash alogrithm\n");
-   return -1;
}
+   hash_algo->hash_func_ws((unsigned char *)data, data_len,
+   (unsigned char *)value, hash_algo->chunk_size);
+   *value_len = hash_algo->digest_size;
+
return 0;
 }
 
diff --git a/include/image.h b/include/image.h
index a5a5807..16bc097 100644
--- a/include/image.h
+++ b/include/image.h
@@ -32,6 +32,7 @@ struct fdt_region;
 #define CONFIG_FIT_ENABLE_SHA256_SUPPORT
 #define CONFIG_SHA1
 #define CONFIG_SHA256
+#define CONFIG_CRC32
 #define CONFIG_MD5
 
 #define IMAGE_ENABLE_IGNORE0
@@ -58,38 +59,39 @@ struct fdt_region;
 #include 
 # ifdef CONFIG_SPL_BUILD
 #  ifdef CONFIG_SPL_CRC32_SUPPORT
-#   define IMAGE_ENABLE_CRC32  1
+#   define CONFIG_CRC32
+#  else
+#   undef CONFIG_CRC32
 #  endif
 #  ifdef CONFIG_SPL_MD5_SUPPORT
-#   define IMAGE_ENABLE_MD51
+#   define CONFIG_MD5
+#  else
+#   undef CONFIG_MD5
 #  endif
 #  ifdef CONFIG_SPL_SHA1_SUPPORT
-#   define IMAGE_ENABLE_SHA1   1
+#   define CONFIG_SHA1
+#  else
+#   undef CONFIG_SHA1
 #  endif
 # else
+#  ifndef CONFIG_CRC32
 #  define CONFIG_CRC32 /* FIT images need CRC32 support */
-#  define IMAGE_ENABLE_CRC32   1
-#  define IMAGE_ENABLE_MD5 1
-#  define IMAGE_ENABLE_SHA11
+#  endif
+#  ifndef CONFIG_MD5
+#  define CONFIG_MD5
+#  endif
+#  ifndef CONFIG_SHA1
+#  define CONFIG_SHA1
+#  endif
 # endif
 
-#ifndef IMAGE_ENABLE_CRC32
-#define IMAGE_ENABLE_CRC32 0
-#endif
-
-#ifndef IMAGE_ENABLE_MD5
-#define IMAGE_ENABLE_MD5   0
-#endif
-
-#ifndef IMAGE_ENABLE_SHA1
-#define IMAGE_ENABLE_SHA1  0
-#endif
-
 #if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \
defined(CONFIG_SPL_SHA256_SUPPORT)
-#define IMAGE_ENABLE_SHA2561
+#ifndef CONFIG_SHA256
+#define CONFIG_SHA256
+#endif
 #else
-#define IMAGE_ENABLE_SHA2560
+#undef CONFIG_SHA256
 #endif
 
 #endif /* IMAGE_ENABLE_FIT */
diff --git a/lib/Ma

[U-Boot] [PATCH v2 1/3] crypto: add md5 to common hash functions

2018-06-06 Thread Ben Whitten 
The md5 function was missing from the common hash functions

Signed-off-by: Ben Whitten 
---
 common/hash.c| 8 
 include/image.h  | 1 +
 include/u-boot/md5.h | 7 ---
 lib/Makefile | 1 +
 lib/md5.c| 4 ++--
 5 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/common/hash.c b/common/hash.c
index ef14651..d2f4b3f 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -168,6 +168,14 @@ static struct hash_algo hash_algo[] = {
.hash_update= hash_update_crc32,
.hash_finish= hash_finish_crc32,
},
+#ifdef CONFIG_MD5
+   {
+   .name   = "md5",
+   .digest_size= 16,
+   .chunk_size = CHUNKSZ_MD5,
+   .hash_func_ws   = md5_wd,
+   },
+#endif
 };
 
 /* Try to minimize code size for boards that don't want much hashing */
diff --git a/include/image.h b/include/image.h
index 9522ee4..a5a5807 100644
--- a/include/image.h
+++ b/include/image.h
@@ -32,6 +32,7 @@ struct fdt_region;
 #define CONFIG_FIT_ENABLE_SHA256_SUPPORT
 #define CONFIG_SHA1
 #define CONFIG_SHA256
+#define CONFIG_MD5
 
 #define IMAGE_ENABLE_IGNORE0
 #define IMAGE_INDENT_STRING""
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index e09c16a..365d125 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -21,14 +21,15 @@ struct MD5Context {
  * Calculate and store in 'output' the MD5 digest of 'len' bytes at
  * 'input'. 'output' must have enough space to hold 16 bytes.
  */
-void md5 (unsigned char *input, int len, unsigned char output[16]);
+
+void md5 (const unsigned char *input, unsigned int len, unsigned char *output);
 
 /*
  * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
  * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
  * watchdog every 'chunk_sz' bytes of input processed.
  */
-void md5_wd (unsigned char *input, int len, unsigned char output[16],
-   unsigned int chunk_sz);
+void md5_wd (const unsigned char *input, unsigned int len,
+   unsigned char *output, unsigned int chunk_sz);
 
 #endif /* _MD5_H */
diff --git a/lib/Makefile b/lib/Makefile
index d531ea5..5c4aa73 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -78,6 +78,7 @@ obj-y += div64.o
 obj-y += hang.o
 obj-y += linux_compat.o
 obj-y += linux_string.o
+obj-$(CONFIG_$(SPL_TPL_)MD5_SUPPORT) += md5.o
 obj-y += membuff.o
 obj-$(CONFIG_REGEX) += slre.o
 obj-y += string.o
diff --git a/lib/md5.c b/lib/md5.c
index 2ae4a06..2278001 100644
--- a/lib/md5.c
+++ b/lib/md5.c
@@ -268,7 +268,7 @@ MD5Transform(__u32 buf[4], __u32 const in[16])
  * 'input'. 'output' must have enough space to hold 16 bytes.
  */
 void
-md5 (unsigned char *input, int len, unsigned char output[16])
+md5 (const unsigned char *input, unsigned int len, unsigned char *output)
 {
struct MD5Context context;
 
@@ -284,7 +284,7 @@ md5 (unsigned char *input, int len, unsigned char 
output[16])
  * watchdog every 'chunk_sz' bytes of input processed.
  */
 void
-md5_wd (unsigned char *input, int len, unsigned char output[16],
+md5_wd (const unsigned char *input, unsigned int len, unsigned char *output,
unsigned int chunk_sz)
 {
struct MD5Context context;
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/2] fit: allow fit to call hardware accelerated hash

2018-06-06 Thread Ben Whitten 
On 25 May 2018 at 12:46, Tom Rini  wrote:
> On Thu, May 24, 2018 at 02:43:24PM +0100, Ben Whitten wrote:
>
>> Move to calling the abstraction which allows for hardware acceleration.
>>
>> Signed-off-by: Ben Whitten 
>> ---
>>  common/image-fit.c | 26 --
>>  1 file changed, 16 insertions(+), 10 deletions(-)
>>
>> diff --git a/common/image-fit.c b/common/image-fit.c
>> index 8c15ed1..01ea864 100644
>> --- a/common/image-fit.c
>> +++ b/common/image-fit.c
>> @@ -1082,19 +1082,25 @@ int fit_set_timestamp(void *fit, int noffset, time_t 
>> timestamp)
>>  int calculate_hash(const void *data, int data_len, const char *algo,
>>   uint8_t *value, int *value_len)
>>  {
>> + struct hash_algo *hash_algo;
>> + int ret;
>> +
>> + ret = hash_lookup_algo(algo, _algo);
>> + if (ret)
>> + return ret;
>> +
>>   if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
>> - *((uint32_t *)value) = crc32_wd(0, data, data_len,
>> - CHUNKSZ_CRC32);
>> - *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
>> - *value_len = 4;
>> + hash_algo->hash_func_ws((unsigned char *)data, data_len,
>> + (unsigned char *)value, hash_algo->chunk_size);
>> + *value_len = hash_algo->digest_size;
>>   } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
>> - sha1_csum_wd((unsigned char *)data, data_len,
>> -  (unsigned char *)value, CHUNKSZ_SHA1);
>> - *value_len = 20;
>> + hash_algo->hash_func_ws((unsigned char *)data, data_len,
>> + (unsigned char *)value, hash_algo->chunk_size);
>> + *value_len = hash_algo->digest_size;
>>   } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
>> - sha256_csum_wd((unsigned char *)data, data_len,
>> -(unsigned char *)value, CHUNKSZ_SHA256);
>> - *value_len = SHA256_SUM_LEN;
>> + hash_algo->hash_func_ws((unsigned char *)data, data_len,
>> + (unsigned char *)value, hash_algo->chunk_size);
>> + *value_len = hash_algo->digest_size;
>>   } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
>>   md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
>>   *value_len = 16;
>
> I think we can vastly simplify this function to just, roughly:
> +   struct hash_algo *hash_algo;
> +   int ret;
> +
> +   ret = hash_lookup_algo(algo, _algo);
> +   if (ret)
> +   return ret;
> +
> ret = hash_algo->hash_func_ws((unsigned char *)data, data_len,
> (unsigned char *)value, hash_algo->chunk_size);
> if (!ret)
> *value_len = hash_algo->digest_size;
>
> return ret;
>
> But I didn't confirm that md5 will be covered, but I assume it is.

It's not currently but I can add that and resend.
Do you need a resend of the series or this individually.

Thanks,
Ben
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[U-Boot] [PATCH 2/2] crypto: add Atmel hardware acceleration for SHA1 & 256

2018-05-24 Thread Ben Whitten 
We can use the hardware hash block to reduce space, particularly useful
for verifying FIT signatures from SPL.

Signed-off-by: Ben Whitten <ben.whit...@lairdtech.com>
---
 drivers/crypto/Kconfig |   5 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/atmel_sha.c | 289 +
 drivers/crypto/atmel_sha.h |  52 
 lib/Makefile   |   2 +
 5 files changed, 349 insertions(+)
 create mode 100644 drivers/crypto/atmel_sha.c
 create mode 100644 drivers/crypto/atmel_sha.h

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 1ea116b..7a20edb 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -2,4 +2,9 @@ menu "Hardware crypto devices"
 
 source drivers/crypto/fsl/Kconfig
 
+config ATMEL_SHA
+   bool "Atmel SHA Driver support"
+   help
+ Enables the Atmel SHA accelerator.
+
 endmenu
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index efbd1d3..07af449 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -4,5 +4,6 @@
 #  http://www.samsung.com
 
 obj-$(CONFIG_EXYNOS_ACE_SHA)   += ace_sha.o
+obj-$(CONFIG_ATMEL_SHA)+= atmel_sha.o
 obj-y += rsa_mod_exp/
 obj-y += fsl/
diff --git a/drivers/crypto/atmel_sha.c b/drivers/crypto/atmel_sha.c
new file mode 100644
index 000..ef969eb
--- /dev/null
+++ b/drivers/crypto/atmel_sha.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Atmel SHA engine
+ * Copyright (c) 2018  Laird
+ */
+
+#include 
+#include 
+#include "atmel_sha.h"
+
+#ifdef CONFIG_SHA_HW_ACCEL
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+enum atmel_hash_algos {
+   ATMEL_HASH_SHA1,
+   ATMEL_HASH_SHA256
+};
+
+struct sha_ctx {
+   enum atmel_hash_algos algo;
+   u32 length;
+   u8  buffer[64];
+};
+
+const u8 sha256_der_prefix[SHA256_DER_LEN] = {
+   0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+   0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
+   0x00, 0x04, 0x20
+};
+
+const u8 sha1_der_prefix[SHA1_DER_LEN] = {
+   0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e,
+   0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14
+};
+
+static enum atmel_hash_algos get_hash_type(struct hash_algo *algo)
+{
+   if (!strcmp(algo->name, "sha1"))
+   return ATMEL_HASH_SHA1;
+   else
+   return ATMEL_HASH_SHA256;
+};
+
+static int atmel_sha_process(const u8 *in_addr, u8 buflen)
+{
+   struct atmel_sha *sha = (struct atmel_sha *)ATMEL_BASE_SHA;
+   int i;
+   u32 *addr_buf;
+
+   /* Copy data in */
+   addr_buf = (u32 *)in_addr;
+   for (i = 0; i < (buflen / 4); i++)
+   sha->idatarx[i] = addr_buf[i];
+   debug("Atmel sha, engine is loaded\n");
+
+   /* Wait for hash to complete */
+   while ((readl(>isr) & ATMEL_HASH_ISR_MASK)
+   != ATMEL_HASH_ISR_DATRDY)
+   ;
+   debug("Atmel sha, engine signaled completion\n");
+
+   return 0;
+}
+
+static int atmel_sha_chunk(struct sha_ctx *ctx, const u8 *buf, unsigned int 
size)
+{
+   u8 remaining, fill;
+
+   /* Chunk to 64 byte blocks */
+   remaining = ctx->length & 0x3F;
+   fill = 64 - remaining;
+
+   /* If we have things in the buffer transfer the remaining into it */
+   if (remaining && size >= fill) {
+   memcpy(ctx->buffer + remaining, buf, fill);
+
+   /* Process 64 byte chunk */
+   atmel_sha_process(ctx->buffer, 64);
+
+   size -= fill;
+   buf += fill;
+   ctx->length += fill;
+   remaining = 0;
+   }
+
+   /* We are aligned take from source for any additional */
+   while (size >= 64) {
+   /* Process 64 byte chunk */
+   atmel_sha_process(buf, 64);
+
+   size -= 64;
+   buf += 64;
+   ctx->length += 64;
+   }
+
+   if (size) {
+   memcpy(ctx->buffer + remaining, buf, size);
+   ctx->length += size;
+   }
+
+   return 0;
+}
+
+static int atmel_sha_fill_padding(struct sha_ctx *ctx)
+{
+   unsigned int index, padlen;
+   u64 size, bits;
+   u8 sha256_padding[64] = {
+   0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+   };
+
+   size = ctx->length;
+
+   bits = cpu_to_be64(size << 3);
+
+   /* 64 byte, 512 bit block size */
+   index = ctx->length & 0x3F;
+   padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
+
+   /* set last entry to be 0x80 then 0's*/
+   atmel_sha_chunk(ctx, sha256_padding, padlen);
+

[U-Boot] [PATCH 1/2] fit: allow fit to call hardware accelerated hash

2018-05-24 Thread Ben Whitten 
Move to calling the abstraction which allows for hardware acceleration.

Signed-off-by: Ben Whitten <ben.whit...@lairdtech.com>
---
 common/image-fit.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index 8c15ed1..01ea864 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1082,19 +1082,25 @@ int fit_set_timestamp(void *fit, int noffset, time_t 
timestamp)
 int calculate_hash(const void *data, int data_len, const char *algo,
uint8_t *value, int *value_len)
 {
+   struct hash_algo *hash_algo;
+   int ret;
+
+   ret = hash_lookup_algo(algo, _algo);
+   if (ret)
+   return ret;
+
if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
-   *((uint32_t *)value) = crc32_wd(0, data, data_len,
-   CHUNKSZ_CRC32);
-   *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
-   *value_len = 4;
+   hash_algo->hash_func_ws((unsigned char *)data, data_len,
+   (unsigned char *)value, hash_algo->chunk_size);
+   *value_len = hash_algo->digest_size;
} else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
-   sha1_csum_wd((unsigned char *)data, data_len,
-(unsigned char *)value, CHUNKSZ_SHA1);
-   *value_len = 20;
+   hash_algo->hash_func_ws((unsigned char *)data, data_len,
+   (unsigned char *)value, hash_algo->chunk_size);
+   *value_len = hash_algo->digest_size;
} else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
-   sha256_csum_wd((unsigned char *)data, data_len,
-  (unsigned char *)value, CHUNKSZ_SHA256);
-   *value_len = SHA256_SUM_LEN;
+   hash_algo->hash_func_ws((unsigned char *)data, data_len,
+   (unsigned char *)value, hash_algo->chunk_size);
+   *value_len = hash_algo->digest_size;
} else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
*value_len = 16;
-- 
2.7.4

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[U-Boot] [PATCH v2 2/2] board: laird: add WB50N CPU module

2017-11-23 Thread Ben Whitten 
From: Ben Whitten <ben.whit...@lairdtech.com>

This board is based on the Atmel sama5d3 eval boards.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whit...@lairdtech.com>
Signed-off-by: Dan Kephart <dan.keph...@lairdtech.com>
---
Changes for v2:
   - Updated to current master
   - Moved some configs to kconfig
   - Removed PHY and selected in config

 arch/arm/mach-at91/Kconfig|   8 ++
 board/laird/wb50n/Kconfig |  12 +++
 board/laird/wb50n/MAINTAINERS |   6 ++
 board/laird/wb50n/Makefile|   6 ++
 board/laird/wb50n/wb50n.c | 206 ++
 configs/wb50n_defconfig   |  30 ++
 include/configs/wb50n.h   | 139 
 7 files changed, 407 insertions(+)
 create mode 100644 board/laird/wb50n/Kconfig
 create mode 100644 board/laird/wb50n/MAINTAINERS
 create mode 100644 board/laird/wb50n/Makefile
 create mode 100644 board/laird/wb50n/wb50n.c
 create mode 100644 configs/wb50n_defconfig
 create mode 100644 include/configs/wb50n.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 414b01b..c429648 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -242,6 +242,13 @@ config TARGET_WB45N
select CPU_ARM926EJS
select SUPPORT_SPL
 
+config TARGET_WB50N
+   bool "Support Laird WB50N"
+   select BOARD_LATE_INIT
+   select CPU_V7
+   select SUPPORT_SPL
+   select BOARD_EARLY_INIT_F
+
 endchoice
 
 config SYS_SOC
@@ -277,6 +284,7 @@ source "board/siemens/corvus/Kconfig"
 source "board/siemens/taurus/Kconfig"
 source "board/siemens/smartweb/Kconfig"
 source "board/laird/wb45n/Kconfig"
+source "board/laird/wb50n/Kconfig"
 
 config SPL_LDSCRIPT
default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig
new file mode 100644
index 000..2e7090e
--- /dev/null
+++ b/board/laird/wb50n/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WB50N
+
+config SYS_BOARD
+   default "wb50n"
+
+config SYS_VENDOR
+   default "laird"
+
+config SYS_CONFIG_NAME
+   default "wb50n"
+
+endif
diff --git a/board/laird/wb50n/MAINTAINERS b/board/laird/wb50n/MAINTAINERS
new file mode 100644
index 000..3d38fc4
--- /dev/null
+++ b/board/laird/wb50n/MAINTAINERS
@@ -0,0 +1,6 @@
+WB50N CPU MODULE
+M: Ben Whitten <ben.whit...@lairdtech.com>
+S: Maintained
+F: board/laird/wb50n/
+F: include/configs/wb50n.h
+F: configs/wb50n_defconfig
diff --git a/board/laird/wb50n/Makefile b/board/laird/wb50n/Makefile
new file mode 100644
index 000..d1b6cfa
--- /dev/null
+++ b/board/laird/wb50n/Makefile
@@ -0,0 +1,6 @@
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb50n.o
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
new file mode 100644
index 000..8896e62
--- /dev/null
+++ b/board/laird/wb50n/wb50n.c
@@ -0,0 +1,206 @@
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* - */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void wb50n_nand_hw_init(void)
+{
+   struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+   at91_periph_clk_enable(ATMEL_ID_SMC);
+
+   /* Configure SMC CS3 for NAND/SmartMedia */
+   writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+  AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+  >cs[3].setup);
+   writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+  AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+  >cs[3].pulse);
+   writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+  >cs[3].cycle);
+   writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+  AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
+  AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
+  AT91_SMC_TIMINGS_NFSEL(1), >cs[3].timings);
+   writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+  AT91_SMC_MODE_EXNW_DISABLE |
+  AT91_SMC_MODE_DBW_8 |
+  AT91_SMC_MODE_TDF_CYCLE(3), >cs[3].mode);
+
+   /* Disable Flash Write Protect Line */
+   at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
+}
+
+int board_early_init_f(void)
+{
+   at91_periph_clk_enable(ATMEL_ID_PIOA);
+   at91_periph_clk_enable(ATMEL_ID_PIOB);
+   at91_periph_clk_enable(ATMEL_ID_PIOC);
+   at91_periph_clk_enable(ATMEL_ID_PIOD);
+   at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+   at91_

[U-Boot] [PATCH v2 1/2] board: laird: add WB45N CPU module

2017-11-23 Thread Ben Whitten 
From: Ben Whitten <ben.whit...@lairdtech.com>

This board is based on the Atmel 9x5 eval board.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whit...@lairdtech.com>
Signed-off-by: Dan Kephart <dan.keph...@lairdtech.com>
---
Changes for v2:
   - Updated to current master
   - Moved some configs to kconfig

 arch/arm/mach-at91/Kconfig |   6 +
 arch/arm/mach-at91/include/mach/gpio.h |   2 +
 board/laird/wb45n/Kconfig  |  12 ++
 board/laird/wb45n/MAINTAINERS  |   6 +
 board/laird/wb45n/Makefile |   6 +
 board/laird/wb45n/wb45n.c  | 199 +
 configs/wb45n_defconfig|  27 +
 include/configs/wb45n.h| 161 ++
 8 files changed, 419 insertions(+)
 create mode 100644 board/laird/wb45n/Kconfig
 create mode 100644 board/laird/wb45n/MAINTAINERS
 create mode 100644 board/laird/wb45n/Makefile
 create mode 100644 board/laird/wb45n/wb45n.c
 create mode 100644 configs/wb45n_defconfig
 create mode 100644 include/configs/wb45n.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 7e85b69..414b01b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -237,6 +237,11 @@ config TARGET_VINCO
select SAMA5D4
select SUPPORT_SPL
 
+config TARGET_WB45N
+   bool "Support Laird WB45N"
+   select CPU_ARM926EJS
+   select SUPPORT_SPL
+
 endchoice
 
 config SYS_SOC
@@ -271,6 +276,7 @@ source "board/ronetix/pm9g45/Kconfig"
 source "board/siemens/corvus/Kconfig"
 source "board/siemens/taurus/Kconfig"
 source "board/siemens/smartweb/Kconfig"
+source "board/laird/wb45n/Kconfig"
 
 config SPL_LDSCRIPT
default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
diff --git a/arch/arm/mach-at91/include/mach/gpio.h 
b/arch/arm/mach-at91/include/mach/gpio.h
index df0f719..e206316 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin)
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_B_periph(x, y) \
at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_deglitch(x, y) \
+   at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_gpio_output(x, y) \
at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_gpio_input(x, y) \
diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig
new file mode 100644
index 000..2a67337
--- /dev/null
+++ b/board/laird/wb45n/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WB45N
+
+config SYS_BOARD
+   default "wb45n"
+
+config SYS_VENDOR
+   default "laird"
+
+config SYS_CONFIG_NAME
+   default "wb45n"
+
+endif
diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS
new file mode 100644
index 000..60bb563
--- /dev/null
+++ b/board/laird/wb45n/MAINTAINERS
@@ -0,0 +1,6 @@
+WB45N CPU MODULE
+M: Ben Whitten <ben.whit...@lairdtech.com>
+S: Maintained
+F: board/laird/wb45n/
+F: include/configs/wb45n.h
+F: configs/wb45n_defconfig
diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile
new file mode 100644
index 000..fc645dd
--- /dev/null
+++ b/board/laird/wb45n/Makefile
@@ -0,0 +1,6 @@
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb45n.o
diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c
new file mode 100644
index 000..5914071
--- /dev/null
+++ b/board/laird/wb45n/wb45n.c
@@ -0,0 +1,199 @@
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* - */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+static void wb45n_nand_hw_init(void)
+{
+   struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+   struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+   unsigned long csa;
+
+   csa = readl(>ebicsa);
+   /* Enable CS3 */
+   csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+   /* NAND flash on D0 */
+   csa &= ~AT91_MATRIX_NFD0_ON_D16;
+   writel(csa, >ebicsa);
+
+   /* Configure SMC CS3 for NAND/SmartMedia */
+   writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+  AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+  >cs[3].setup);
+   writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+  AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+  >cs[3].pulse);
+   writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_

[U-Boot] [PATCH v2 0/2] Resubmitting support for Lairds WB boards

2017-11-23 Thread Ben Whitten 
Hi,

Resubmitting the board patches based off current master branch at
16fa2eb with updates to configs.

Ben Whitten (2):
  board: laird: add WB45N CPU module
  board: laird: add WB50N CPU module

 arch/arm/mach-at91/Kconfig |  14 +++
 arch/arm/mach-at91/include/mach/gpio.h |   2 +
 board/laird/wb45n/Kconfig  |  12 ++
 board/laird/wb45n/MAINTAINERS  |   6 +
 board/laird/wb45n/Makefile |   6 +
 board/laird/wb45n/wb45n.c  | 199 +++
 board/laird/wb50n/Kconfig  |  12 ++
 board/laird/wb50n/MAINTAINERS  |   6 +
 board/laird/wb50n/Makefile |   6 +
 board/laird/wb50n/wb50n.c  | 206 +
 configs/wb45n_defconfig|  27 +
 configs/wb50n_defconfig|  30 +
 include/configs/wb45n.h| 161 ++
 include/configs/wb50n.h| 139 ++
 14 files changed, 826 insertions(+)
 create mode 100644 board/laird/wb45n/Kconfig
 create mode 100644 board/laird/wb45n/MAINTAINERS
 create mode 100644 board/laird/wb45n/Makefile
 create mode 100644 board/laird/wb45n/wb45n.c
 create mode 100644 board/laird/wb50n/Kconfig
 create mode 100644 board/laird/wb50n/MAINTAINERS
 create mode 100644 board/laird/wb50n/Makefile
 create mode 100644 board/laird/wb50n/wb50n.c
 create mode 100644 configs/wb45n_defconfig
 create mode 100644 configs/wb50n_defconfig
 create mode 100644 include/configs/wb45n.h
 create mode 100644 include/configs/wb50n.h

-- 
2.7.4

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Re: [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module

2017-11-09 Thread Ben Whitten 
On 02 August 2017 15:49, Tom Rini wrote:
> On Wed, Aug 02, 2017 at 11:58:42AM +0200, Stefano Babic wrote:
> > On 07/07/2017 12:40, Ben Whitten wrote:
> > > This board is based on the Atmel 9x5 eval board.
> > > Supporting the following features:
> > >  - Boot from NAND Flash
> > >  - Ethernet
> > >  - FIT
> > >  - SPL
> > >
> >
> > Patch is assigned to me. However, this is Atmel, now orphaned. I
> > haven't work with AT-91 since a very long time, so I cannot say more
> > about patches, but it is a pity if the patches will be lost. Tom,
> > should I merge them even if they are not i.MX related ? Or do you pick
> > them yourself ?
> 
> Ah, sorry, I saw laird, had the WiFi modules they do for i.MX series platforms
> in mind and went "oh, must be an i.MX system".  Please toss them back to
> me, thanks!

Hi Tom,
Any comments on these boards? Whilst I was at ELCE I bumped into Marek and
had a talk about adding new boards, he had mentioned new boards should be
using DM.
As this is the direction things are moving let me know and I can convert them.

Thanks,
Ben
 


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[U-Boot] [RFC PATCH 2/2] board: laird: add WB50N CPU module

2017-07-07 Thread Ben Whitten 
This board is based on the Atmel sama5d3 eval boards.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whit...@lairdtech.com>
Signed-off-by: Dan Kephart <dan.keph...@lairdtech.com>
---
 arch/arm/mach-at91/Kconfig|   8 ++
 board/laird/wb50n/Kconfig |  12 +++
 board/laird/wb50n/MAINTAINERS |   6 ++
 board/laird/wb50n/Makefile|   6 ++
 board/laird/wb50n/wb50n.c | 206 ++
 configs/wb50n_defconfig   |  26 ++
 include/configs/wb50n.h   | 143 +
 7 files changed, 407 insertions(+)
 create mode 100644 board/laird/wb50n/Kconfig
 create mode 100644 board/laird/wb50n/MAINTAINERS
 create mode 100644 board/laird/wb50n/Makefile
 create mode 100644 board/laird/wb50n/wb50n.c
 create mode 100644 configs/wb50n_defconfig
 create mode 100644 include/configs/wb50n.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index e4d9690..d89c53b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -169,6 +169,13 @@ config TARGET_WB45N
select CPU_ARM926EJS
select SUPPORT_SPL
 
+config TARGET_WB50N
+   bool "Support Laird WB50N"
+   select BOARD_LATE_INIT
+   select CPU_V7
+   select SUPPORT_SPL
+   select BOARD_EARLY_INIT_F
+
 endchoice
 
 config SYS_SOC
@@ -203,5 +210,6 @@ source "board/siemens/corvus/Kconfig"
 source "board/siemens/taurus/Kconfig"
 source "board/siemens/smartweb/Kconfig"
 source "board/laird/wb45n/Kconfig"
+source "board/laird/wb50n/Kconfig"
 
 endif
diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig
new file mode 100644
index 000..2e7090e
--- /dev/null
+++ b/board/laird/wb50n/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WB50N
+
+config SYS_BOARD
+   default "wb50n"
+
+config SYS_VENDOR
+   default "laird"
+
+config SYS_CONFIG_NAME
+   default "wb50n"
+
+endif
diff --git a/board/laird/wb50n/MAINTAINERS b/board/laird/wb50n/MAINTAINERS
new file mode 100644
index 000..3d38fc4
--- /dev/null
+++ b/board/laird/wb50n/MAINTAINERS
@@ -0,0 +1,6 @@
+WB50N CPU MODULE
+M: Ben Whitten <ben.whit...@lairdtech.com>
+S: Maintained
+F: board/laird/wb50n/
+F: include/configs/wb50n.h
+F: configs/wb50n_defconfig
diff --git a/board/laird/wb50n/Makefile b/board/laird/wb50n/Makefile
new file mode 100644
index 000..d1b6cfa
--- /dev/null
+++ b/board/laird/wb50n/Makefile
@@ -0,0 +1,6 @@
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb50n.o
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
new file mode 100644
index 000..354cecf
--- /dev/null
+++ b/board/laird/wb50n/wb50n.c
@@ -0,0 +1,206 @@
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* - */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void wb50n_nand_hw_init(void)
+{
+   struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+   at91_periph_clk_enable(ATMEL_ID_SMC);
+
+   /* Configure SMC CS3 for NAND/SmartMedia */
+   writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+  AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+  >cs[3].setup);
+   writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+  AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+  >cs[3].pulse);
+   writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+  >cs[3].cycle);
+   writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+  AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
+  AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
+  AT91_SMC_TIMINGS_NFSEL(1), >cs[3].timings);
+   writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+  AT91_SMC_MODE_EXNW_DISABLE |
+  AT91_SMC_MODE_DBW_8 |
+  AT91_SMC_MODE_TDF_CYCLE(3), >cs[3].mode);
+
+   /* Disable Flash Write Protect Line */
+   at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
+}
+
+int board_early_init_f(void)
+{
+   at91_periph_clk_enable(ATMEL_ID_PIOA);
+   at91_periph_clk_enable(ATMEL_ID_PIOB);
+   at91_periph_clk_enable(ATMEL_ID_PIOC);
+   at91_periph_clk_enable(ATMEL_ID_PIOD);
+   at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+   at91_seriald_hw_init();
+
+   return 0;
+}
+
+int board_init(void)
+{
+   /* adress of boot parameters */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+   wb50n_nand_hw_init();
+
+   at91_macb_hw_init();
+
+   return 0;
+}
+
+int dram_init(void

[U-Boot] [RFC PATCH 0/2] Add support for two modules from Laird

2017-07-07 Thread Ben Whitten 
Hi
These patches add basic support for two cpu modules from Laird. These boards
are based on the at91sam9x5ek and the sama5d3xek and have been updated from
old versions. I believe I have captured the KConfig moves and adjustents
but if there are better solutions now I should look into please let me know.

Kind regards,
Ben Whitten (2):
  board: laird: add WB45N CPU module
  board: laird: add WB50N CPU module

 arch/arm/mach-at91/Kconfig |  14 +++
 arch/arm/mach-at91/include/mach/gpio.h |   2 +
 board/laird/wb45n/Kconfig  |  12 ++
 board/laird/wb45n/MAINTAINERS  |   6 +
 board/laird/wb45n/Makefile |   6 +
 board/laird/wb45n/wb45n.c  | 199 +++
 board/laird/wb50n/Kconfig  |  12 ++
 board/laird/wb50n/MAINTAINERS  |   6 +
 board/laird/wb50n/Makefile |   6 +
 board/laird/wb50n/wb50n.c  | 206 +
 configs/wb45n_defconfig|  27 +
 configs/wb50n_defconfig|  26 +
 include/configs/wb45n.h| 163 ++
 include/configs/wb50n.h| 143 +++
 14 files changed, 828 insertions(+)
 create mode 100644 board/laird/wb45n/Kconfig
 create mode 100644 board/laird/wb45n/MAINTAINERS
 create mode 100644 board/laird/wb45n/Makefile
 create mode 100644 board/laird/wb45n/wb45n.c
 create mode 100644 board/laird/wb50n/Kconfig
 create mode 100644 board/laird/wb50n/MAINTAINERS
 create mode 100644 board/laird/wb50n/Makefile
 create mode 100644 board/laird/wb50n/wb50n.c
 create mode 100644 configs/wb45n_defconfig
 create mode 100644 configs/wb50n_defconfig
 create mode 100644 include/configs/wb45n.h
 create mode 100644 include/configs/wb50n.h

-- 
2.7.4

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[U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module

2017-07-07 Thread Ben Whitten 
This board is based on the Atmel 9x5 eval board.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whit...@lairdtech.com>
Signed-off-by: Dan Kephart <dan.keph...@lairdtech.com>
---
 arch/arm/mach-at91/Kconfig |   6 +
 arch/arm/mach-at91/include/mach/gpio.h |   2 +
 board/laird/wb45n/Kconfig  |  12 ++
 board/laird/wb45n/MAINTAINERS  |   6 +
 board/laird/wb45n/Makefile |   6 +
 board/laird/wb45n/wb45n.c  | 199 +
 configs/wb45n_defconfig|  27 +
 include/configs/wb45n.h| 163 +++
 8 files changed, 421 insertions(+)
 create mode 100644 board/laird/wb45n/Kconfig
 create mode 100644 board/laird/wb45n/MAINTAINERS
 create mode 100644 board/laird/wb45n/Makefile
 create mode 100644 board/laird/wb45n/wb45n.c
 create mode 100644 configs/wb45n_defconfig
 create mode 100644 include/configs/wb45n.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 99b88d1..e4d9690 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -164,6 +164,11 @@ config TARGET_VINCO
select CPU_V7
select SUPPORT_SPL
 
+config TARGET_WB45N
+   bool "Support Laird WB45N"
+   select CPU_ARM926EJS
+   select SUPPORT_SPL
+
 endchoice
 
 config SYS_SOC
@@ -197,5 +202,6 @@ source "board/ronetix/pm9g45/Kconfig"
 source "board/siemens/corvus/Kconfig"
 source "board/siemens/taurus/Kconfig"
 source "board/siemens/smartweb/Kconfig"
+source "board/laird/wb45n/Kconfig"
 
 endif
diff --git a/arch/arm/mach-at91/include/mach/gpio.h 
b/arch/arm/mach-at91/include/mach/gpio.h
index df0f719..e206316 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin)
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_B_periph(x, y) \
at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_deglitch(x, y) \
+   at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_gpio_output(x, y) \
at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_gpio_input(x, y) \
diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig
new file mode 100644
index 000..2a67337
--- /dev/null
+++ b/board/laird/wb45n/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WB45N
+
+config SYS_BOARD
+   default "wb45n"
+
+config SYS_VENDOR
+   default "laird"
+
+config SYS_CONFIG_NAME
+   default "wb45n"
+
+endif
diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS
new file mode 100644
index 000..60bb563
--- /dev/null
+++ b/board/laird/wb45n/MAINTAINERS
@@ -0,0 +1,6 @@
+WB45N CPU MODULE
+M: Ben Whitten <ben.whit...@lairdtech.com>
+S: Maintained
+F: board/laird/wb45n/
+F: include/configs/wb45n.h
+F: configs/wb45n_defconfig
diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile
new file mode 100644
index 000..fc645dd
--- /dev/null
+++ b/board/laird/wb45n/Makefile
@@ -0,0 +1,6 @@
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb45n.o
diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c
new file mode 100644
index 000..5914071
--- /dev/null
+++ b/board/laird/wb45n/wb45n.c
@@ -0,0 +1,199 @@
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* - */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+static void wb45n_nand_hw_init(void)
+{
+   struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+   struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+   unsigned long csa;
+
+   csa = readl(>ebicsa);
+   /* Enable CS3 */
+   csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+   /* NAND flash on D0 */
+   csa &= ~AT91_MATRIX_NFD0_ON_D16;
+   writel(csa, >ebicsa);
+
+   /* Configure SMC CS3 for NAND/SmartMedia */
+   writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+  AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+  >cs[3].setup);
+   writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+  AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+  >cs[3].pulse);
+   writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+  >cs[3].cycle);
+   writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+  AT91_SMC_MODE_EXNW_DISABLE |
+  AT91_SMC_MODE_DBW_8 |
+  AT91_SMC_MODE_TDF_CYCLE(1), >cs[3].mode);
+
+

[U-Boot] [PATCH v2] Fix GCC format-security errors and convert sprintfs.

2015-12-30 Thread ben . whitten 
From: Ben Whitten <ben.whit...@gmail.com>

With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.

Simple uses of sprintf are also converted to use strcpy.

Signed-off-by: Ben Whitten <ben.whit...@gmail.com>
---
Changes for v2:
- Replaced single string uses of sprintf with strcpy
- Detected more occurrences of potential errors.

 arch/mips/mach-au1x00/au1x00_eth.c  |  2 +-
 arch/powerpc/cpu/mpc8260/ether_scc.c|  2 +-
 arch/powerpc/cpu/mpc8xx/fec.c   |  2 +-
 arch/powerpc/cpu/mpc8xx/scc.c   |  2 +-
 arch/powerpc/cpu/mpc8xx/video.c |  4 ++--
 board/freescale/b4860qds/eth_b4860qds.c |  8 
 board/freescale/corenet_ds/eth_hydra.c  |  2 +-
 board/freescale/corenet_ds/eth_superhydra.c |  2 +-
 board/freescale/ls1021aqds/eth.c|  2 +-
 board/freescale/ls1043aqds/eth.c|  2 +-
 board/freescale/ls2080aqds/eth.c|  2 +-
 board/freescale/t102xqds/eth_t102xqds.c |  2 +-
 board/freescale/t1040qds/eth.c  |  2 +-
 board/freescale/t208xqds/eth_t208xqds.c |  2 +-
 board/freescale/t4qds/eth.c |  2 +-
 board/gdsys/common/ihs_mdio.c   |  2 +-
 board/keymile/common/common.c   |  4 ++--
 board/mpl/common/common_util.c  |  8 
 board/samsung/universal_c210/universal.c|  4 ++--
 board/siemens/rut/board.c   |  2 +-
 board/vscom/baltos/board.c  |  2 +-
 common/cmd_elf.c| 13 -
 common/cmd_mtdparts.c   |  2 +-
 common/cmd_nvedit.c |  2 +-
 disk/part_dos.c |  4 ++--
 disk/part_efi.c |  2 +-
 disk/part_iso.c |  2 +-
 drivers/block/sata_dwc.c|  4 ++--
 drivers/net/altera_tse.c|  2 +-
 drivers/net/at91_emac.c |  2 +-
 drivers/net/ax88180.c   |  2 +-
 drivers/net/cpsw.c  |  2 +-
 drivers/net/davinci_emac.c  |  2 +-
 drivers/net/designware.c|  2 +-
 drivers/net/dm9000x.c   |  2 +-
 drivers/net/fm/memac_phy.c  |  2 +-
 drivers/net/fm/tgec_phy.c   |  2 +-
 drivers/net/fsl_mdio.c  |  2 +-
 drivers/net/ftgmac100.c |  2 +-
 drivers/net/ftmac100.c  |  2 +-
 drivers/net/greth.c |  4 ++--
 drivers/net/keystone_net.c  |  2 +-
 drivers/net/ldpaa_eth/ldpaa_eth.c   |  4 ++--
 drivers/net/lpc32xx_eth.c   |  2 +-
 drivers/net/mpc512x_fec.c   |  2 +-
 drivers/net/mpc5xxx_fec.c   |  2 +-
 drivers/net/mvgbe.c |  2 +-
 drivers/net/ne2000_base.c   |  2 +-
 drivers/net/pch_gbe.c   |  2 +-
 drivers/net/sh_eth.c|  2 +-
 drivers/net/tsec.c  |  2 +-
 drivers/usb/gadget/f_fastboot.c |  6 +++---
 include/configs/tam3517-common.h|  2 +-
 scripts/kconfig/mconf.c |  2 +-
 54 files changed, 76 insertions(+), 73 deletions(-)

diff --git a/arch/mips/mach-au1x00/au1x00_eth.c 
b/arch/mips/mach-au1x00/au1x00_eth.c
index d6ebe07..3f9f91e 100644
--- a/arch/mips/mach-au1x00/au1x00_eth.c
+++ b/arch/mips/mach-au1x00/au1x00_eth.c
@@ -279,7 +279,7 @@ int au1x00_enet_initialize(bd_t *bis){

memset(dev, 0, sizeof *dev);

-   sprintf(dev->name, "Au1X00 ethernet");
+   strcpy(dev->name, "Au1X00 ethernet");
dev->iobase = 0;
dev->priv   = 0;
dev->init   = au1x00_init;
diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c 
b/arch/powerpc/cpu/mpc8260/ether_scc.c
index 5ba8bed..fff8f2b 100644
--- a/arch/powerpc/cpu/mpc8260/ether_scc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_scc.c
@@ -355,7 +355,7 @@ int mpc82xx_scc_enet_initialize(bd_t *bis)
dev = (struct eth_device *) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);

-   sprintf(dev->name, "SCC");
+   strcpy(dev->name, "SCC");
dev->init   = sec_init;
dev->halt   = sec_halt;
dev->send   = sec_send;
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index 2e19603..ea4ab3a 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -148,7 +148,7 @@ int fec_initialize(bd_t *bis)
/* for FEC1 make sure that the name of the interface is the same
   as the old one for compatibility reasons */
if (i == 0) {
-   sprintf (dev->name, "FEC");
+   strcpy(dev->name, "FEC");
}

[U-Boot] [PATCH] Fix GCC format-security errors.

2015-12-29 Thread ben . whitten 
From: Ben Whitten <ben.whit...@gmail.com>

With format-security errors turned on, GCC picks up the use of sprintf without
a format parameter.

Signed-off-by: Ben Whitten <ben.whit...@gmail.com>
---
 common/cmd_elf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 86e694a..3677702 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -289,7 +289,7 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
} else {
tmp = getenv("bootdev");
if (tmp)
-   ptr = sprintf(build_buf, tmp);
+   ptr = sprintf(build_buf, "%s", tmp);
else
printf("## VxWorks boot device not 
specified\n");

@@ -332,7 +332,7 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])

tmp = getenv("othbootargs");
if (tmp)
-   ptr += sprintf(build_buf + ptr, tmp);
+   ptr += sprintf(build_buf + ptr, "%s", tmp);

memcpy((void *)bootaddr, build_buf,
   max(strlen(build_buf), (size_t)255));
--
2.6.4

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