[PATCH v3] i2c: correct I2C deblock logic
From: Haibo Chen
Current code use dm_gpio_get_value() to get SDA and SCL value, and the
value depends on whether DTS file config the GPIO_ACTIVE_LOW. In ususal
case for i2c GPIO, DTS need to set GPIO_ACTIVE_LOW for SCL/SDA pins. So
here the logic is not correct.
And we must not use GPIOD_ACTIVE_LOW in client code include the
dm_gpio_set_dir_flags(), it is DTS's responsibility for this flag. So
remove GPIOD_ACTIVE_LOW here.
Fixes: aa54192d4a87 ("dm: i2c: implement gpio-based I2C deblock")
Signed-off-by: Haibo Chen
---
drivers/i2c/i2c-uclass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 8d9a89ed89..8867a560bd 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -508,13 +508,13 @@ static void i2c_gpio_set_pin(struct gpio_desc *pin, int
bit)
dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
else
dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
- GPIOD_ACTIVE_LOW |
GPIOD_IS_OUT_ACTIVE);
}
static int i2c_gpio_get_pin(struct gpio_desc *pin)
{
- return dm_gpio_get_value(pin);
+ /* DTS need config GPIO_ACTIVE_LOW */
+ return !dm_gpio_get_value(pin);
}
int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,
--
2.34.1
[PATCH] gpio: add GPIOD_ACTIVE_LOW into GPIOD_MASK_DIR
From: Haibo Chen
dm_gpio_set_dir_flags() will clear GPIOD_MASK_DIR and set new flags.
But there are cases like i2c_deblock_gpio_loop() will do like this:
-first conifg GPIO(SDA) output with GPIOD_ACTIVE_LOW
dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
GPIOD_ACTIVE_LOW |
GPIOD_IS_OUT_ACTIVE);
-then config GPIO input
dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
-then get the GPIO input value:
dm_gpio_get_value(pin);
When config the GPIO input, only set GPIOD_IS_IN, but unfortunately
since the previous GPIOD_ACTIVE_LOW is not cleared, still keep in
flags, make the value from dm_gpio_get_value() not logic correct.
So add GPIOD_ACTIVE_LOW into GPIOD_MASK_DIR to avoid this issue.
Signed-off-by: Haibo Chen
---
include/asm-generic/gpio.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index dd0bdf2315..903b237aac 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -131,7 +131,7 @@ struct gpio_desc {
/* Flags for updating the above */
#define GPIOD_MASK_DIR (GPIOD_IS_OUT | GPIOD_IS_IN | \
- GPIOD_IS_OUT_ACTIVE)
+GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW)
#define GPIOD_MASK_DSTYPE (GPIOD_OPEN_DRAIN | GPIOD_OPEN_SOURCE)
#define GPIOD_MASK_PULL(GPIOD_PULL_UP | GPIOD_PULL_DOWN)
--
2.34.1
[PATCH] i2c: correct I2C deblock logic
From: Haibo Chen
Current code use dm_gpio_get_value() to get SDA and SCL value, and the
value depends on the flag GPIOD_ACTIVE_LOW. When toggle SCL to wait
slave release SDA, the SDA are config as GPIOD_IS_IN, and whether contain
the GPIOD_ACTIVE_LOW depends on the DTS setting. Usually, for I2C GPIO,
we use GPIOD_ACTIVE_LOW flag in DTS, so if the SDA is in low level, then
dm_gpio_get_value() will return 1, current code logic will stop the SCL
toggle wrongly, cause the I2C deblock not work as expect.
This patch force set the GPIOD_ACTIVE_LOW for both GPIOD_IS_IN and
GPIOD_IS_OUT, and make the return value of i2c_gpio_get_pin() eaqual to
the physical voltage logic level.
Fixes: aa54192d4a87 ("dm: i2c: implement gpio-based I2C deblock")
Signed-off-by: Haibo Chen
---
drivers/i2c/i2c-uclass.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 8d9a89ed89..4dc707c659 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -505,7 +505,8 @@ uint i2c_get_chip_addr_offset_mask(struct udevice *dev)
static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit)
{
if (bit)
- dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
+ dm_gpio_set_dir_flags(pin, GPIOD_IS_IN |
+ GPIOD_ACTIVE_LOW);
else
dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
GPIOD_ACTIVE_LOW |
@@ -514,7 +515,7 @@ static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit)
static int i2c_gpio_get_pin(struct gpio_desc *pin)
{
- return dm_gpio_get_value(pin);
+ return !dm_gpio_get_value(pin);
}
int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,
--
2.34.1
[PATCH v2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary
From: Haibo Chen
After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use
VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it
involve issue in mmc_switch_voltage(), because of the special
design of usdhc.
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
these are reserved bits(Though RM contain the definition of these bits,
but actually internal IC logic do not implement, already confirm with
IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card
clock output. Here is the definition of this bit in RM:
[8] FRC_SDCLK_ON
Force CLK output active
Do not set this bit to 1 unless it is necessary. Also, make sure that
this bit is cleared when uSDHC’s clock is about to be changed (frequency
change, clock source change, or delay chain tuning).
0b - CLK active or inactive is fully controlled by the hardware.
1b - Force CLK active
In default, the FRC_SDCLK_ON is 0. This means, when there is no command
or data transfer on bus, hardware will gate off the card clock. But in
some case, we need the card clock keep on. Take IO voltage 1.8v switch
as example, after IO voltage change to 1.8v, spec require gate off the
card clock for 5ms, and gate on the clock back, once detect the card
clock on, then the card will draw the dat0 to high immediately. If there
is not clock gate off/on behavior, some card will keep the dat0 to low
level. This is the reason we fail in mmc_switch_voltage().
To fix this issue, and concern that this is only the fsl usdhc hardware
design limitation, set the bit FRC_SDCLK_ON in the beginning of the
wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage
switch process align with SD specification.
For standard tuning process, usdhc specification also require the card
clock keep on, so also add these behavior in fsl_esdhc_execute_tuning().
Reviewed-by: Marek Vasut
Tested-by: Fabio Estevam
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 25 ++---
include/fsl_esdhc_imx.h | 2 ++
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 9299635f50..e0108144e7 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -831,13 +831,16 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
struct mmc *mmc = >mmc;
u32 irqstaten = esdhc_read32(>irqstaten);
u32 irqsigen = esdhc_read32(>irqsigen);
- int i, ret = -ETIMEDOUT;
- u32 val, mixctrl;
+ int i, err, ret = -ETIMEDOUT;
+ u32 val, mixctrl, tmp;
/* clock tuning is not needed for upto 52MHz */
if (mmc->clock <= 5200)
return 0;
+ /* make sure the card clock keep on */
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
val = esdhc_read32(>autoc12err);
@@ -897,6 +900,12 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
esdhc_stop_tuning(mmc);
+ /* change to default setting, let host control the card clock */
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ err = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100);
+ if (err)
+ dev_warn(dev, "card clock not gate off as expect.\n");
+
return ret;
}
#endif
@@ -1555,14 +1564,24 @@ static int __maybe_unused
fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
int timeout_us)
{
- int ret;
+ int ret, err;
u32 tmp;
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
+ /* make sure the card clock keep on */
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp,
!!(tmp & PRSSTAT_DAT0) == !!state,
timeout_us);
+
+ /* change to default setting, let host control the card clock */
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ err = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100);
+ if (err)
+ dev_warn(dev, "card clock not gate off as expect.\n");
+
return ret;
}
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 2153f29bef..b8efd2a166 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -37,6 +37,7 @@
#define VENDORSPEC_HCKEN 0x1000
#define VENDORSPEC_IPGEN 0x0800
#define VENDORSPEC_INIT0x20007809
+#define VENDORSPEC_FRC_SDCLK_ON 0x0100
#define IRQSTAT
[PATCH 2/3] mmc: fsl_esdhc_imx: remove redundant ARCH_MXC
From: Haibo Chen
Now original fsl_esdhc.c are split as fsl_esdhc.c and fsl_esdhc_imx.c.
fsl_esdhc_imx.c only cover i.MX SoC. So ARCH_MXC is redundant.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 362e3e13b6..0be7cae1e5 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -596,16 +596,12 @@ static void set_sysctl(struct fsl_esdhc_priv *priv,
struct mmc *mmc, uint clock)
int sdhc_clk = priv->sdhc_clk;
uint clk;
- if (IS_ENABLED(ARCH_MXC)) {
#if IS_ENABLED(CONFIG_MX53)
- /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
- pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2
: 1;
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
#else
- pre_div = 1;
+ pre_div = 1;
#endif
- } else {
- pre_div = 2;
- }
while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
pre_div *= 2;
@@ -1016,11 +1012,6 @@ static int esdhc_init_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
esdhc_write32(>dllctrl, 0x0);
}
-#ifndef ARCH_MXC
- /* Enable cache snooping */
- esdhc_write32(>scr, 0x0040);
-#endif
-
if (IS_ENABLED(CONFIG_FSL_USDHC))
esdhc_setbits32(>vendorspec,
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
--
2.17.1
[PATCH 3/3] mmc: fsl_esdhc_imx: correct the actual card clock
From: Haibo Chen The original code logic can not show the correct card clock, and also has one risk when the div is 0. Because there is div -=1 before. So move the operation before div -=1, and also involve ddr_pre_div to get the correct value. Signed-off-by: Haibo Chen --- drivers/mmc/fsl_esdhc_imx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 0be7cae1e5..0ea7b0b50c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -609,6 +609,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) div++; + mmc->clock = sdhc_clk / pre_div / div / ddr_pre_div; + pre_div >>= 1; div -= 1; @@ -630,7 +632,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) else esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_CKEN); - mmc->clock = sdhc_clk / pre_div / div; priv->clock = clock; } -- 2.17.1
[PATCH 1/3] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary
From: Haibo Chen
After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use
VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it
involve issue in mmc_switch_voltage(), because of the special
design of usdhc.
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
these are reserved bits(Though RM contain the definition of these bits,
but actually internal IC logic do not implement, already confirm with
IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card
clock output. Here is the definition of this bit in RM:
[8] FRC_SDCLK_ON
Force CLK output active
Do not set this bit to 1 unless it is necessary. Also, make sure that
this bit is cleared when uSDHC’s clock is about to be changed (frequency
change, clock source change, or delay chain tuning).
0b - CLK active or inactive is fully controlled by the hardware.
1b - Force CLK active
In default, the FRC_SDCLK_ON is 0. This means, when there is no command
or data transfer on bus, hardware will gate off the card clock. But in
some case, we need the card clock keep on. Take IO voltage 1.8v switch
as example, after IO voltage change to 1.8v, spec require gate off the
card clock for 5ms, and gate on the clock back, once detect the card
clock on, then the card will draw the dat0 to high immediately. If there
is not clock gate off/on behavior, some card will keep the dat0 to low
level. This is the reason we fail in mmc_switch_voltage().
To fix this issue, and concern that this is only the fsl usdhc hardware
design limitation, set the bit FRC_SDCLK_ON in the beginning of the
wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage
switch process align with SD specification.
For standard tuning process, usdhc specification also require the card
clock keep on, so also add these behavior in fsl_esdhc_execute_tuning().
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 19 ++-
include/fsl_esdhc_imx.h | 2 ++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 9299635f50..362e3e13b6 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -832,12 +832,15 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
u32 irqstaten = esdhc_read32(>irqstaten);
u32 irqsigen = esdhc_read32(>irqsigen);
int i, ret = -ETIMEDOUT;
- u32 val, mixctrl;
+ u32 val, mixctrl, tmp;
/* clock tuning is not needed for upto 52MHz */
if (mmc->clock <= 5200)
return 0;
+ /* make sure the card clock keep on */
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
val = esdhc_read32(>autoc12err);
@@ -897,6 +900,11 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
esdhc_stop_tuning(mmc);
+ /* change to default setting, let host control the card clock */
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ if (readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100))
+ pr_warn("fsl_esdhc_imx: card clock not gate off as expect.\n");
+
return ret;
}
#endif
@@ -1560,9 +1568,18 @@ static int fsl_esdhc_wait_dat0(struct udevice *dev, int
state,
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
+ /* make sure the card clock keep on */
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp,
!!(tmp & PRSSTAT_DAT0) == !!state,
timeout_us);
+
+ /* change to default setting, let host control the card clock */
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ if (readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100))
+ pr_warn("fsl_esdhc_imx: card clock not gate off as expect.\n");
+
return ret;
}
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 2153f29bef..b8efd2a166 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -37,6 +37,7 @@
#define VENDORSPEC_HCKEN 0x1000
#define VENDORSPEC_IPGEN 0x0800
#define VENDORSPEC_INIT0x20007809
+#define VENDORSPEC_FRC_SDCLK_ON 0x0100
#define IRQSTAT0x0002e030
#define IRQSTAT_DMAE (0x1000)
@@ -94,6 +95,7 @@
#define PRSSTAT_CINS (0x0001)
#define PRSSTAT_BREN (0x0800)
#define PRSSTAT_BWEN (0x0400)
+#define PRSSTAT_SDOFF (0x0080)
#define PRSSTAT_SDSTB (0X0008)
#define PRSSTAT_DLA(0x0004)
#define PRSSTAT_CICHB (0x0002)
--
2.17.1
[PATCH 2/2] mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if necessary
From: Haibo Chen
Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need
around 18ms, common code only delay 10ms, so need to delay extra 8ms.
Otherwise voltage switch will timeout when wait for data0 line.
This IO voltage switch time depends on board design, depend on the
PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF
capacitance.
Signed-off-by: Haibo Chen
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 1 +
drivers/mmc/fsl_esdhc_imx.c | 12
2 files changed, 13 insertions(+)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index e843a5648e..bccf4fe947 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -102,6 +102,7 @@
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
{
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 722f33c68c..ef2b71e6b7 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -146,6 +146,7 @@ struct esdhc_soc_data {
* @start_tuning_tap: the start point for tuning in tuning_ctrl register
* @strobe_dll_delay_target: settings in strobe_dllctrl
* @signal_voltage: indicating the current voltage
+ * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
@@ -170,6 +171,7 @@ struct fsl_esdhc_priv {
u32 tuning_start_tap;
u32 strobe_dll_delay_target;
u32 signal_voltage;
+ u32 signal_voltage_switch_extra_delay_ms;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
struct udevice *vmmc_dev;
@@ -836,6 +838,14 @@ static int esdhc_set_voltage(struct mmc *mmc)
}
#endif
esdhc_setbits32(>vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ /*
+* some board like imx8mm-evk need about 18ms to switch
+* the IO voltage from 3.3v to 1.8v, common code only
+* delay 10ms, so need to delay extra time to make sure
+* the IO voltage change to 1.8v.
+*/
+ if (priv->signal_voltage_switch_extra_delay_ms)
+ mdelay(priv->signal_voltage_switch_extra_delay_ms);
if (esdhc_read32(>vendorspec) & ESDHC_VENDORSPEC_VSELECT)
return 0;
@@ -1450,6 +1460,8 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
priv->strobe_dll_delay_target = val;
+ val = fdtdec_get_int(fdt, node,
"fsl,signal-voltage-switch-extra-delay-ms", 0);
+ priv->signal_voltage_switch_extra_delay_ms = val;
if (dev_read_bool(dev, "broken-cd"))
priv->broken_cd = 1;
--
2.17.1
[PATCH 1/2] mmc: fsl_esdhc_imx: remove redundant cmd11 related code.
From: Haibo Chen
Common code already handle the voltage switch sequence based on spec,
so remove the redundant voltage switch code.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 637537d262..722f33c68c 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -521,15 +521,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
goto out;
}
- /* Switch voltage to 1.8V if CMD11 succeeded */
- if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
- esdhc_setbits32(>vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
- printf("Run CMD11 1.8V switch\n");
- /* Sleep for 5 ms - max time for card to switch to 1.8V */
- udelay(5000);
- }
-
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
int timeout = 5;
--
2.17.1
[PATCH 2/2] mmc: fsl_esdhc_imx: remove redundant cmd11 related code.
From: Haibo Chen
Common code already handle the voltage switch sequence based on spec,
so remove the redundant voltage switch code.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index af36558b3c..a199cf3df6 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -515,15 +515,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
goto out;
}
- /* Switch voltage to 1.8V if CMD11 succeeded */
- if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
- esdhc_setbits32(>vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
- printf("Run CMD11 1.8V switch\n");
- /* Sleep for 5 ms - max time for card to switch to 1.8V */
- udelay(5000);
- }
-
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
int timeout = 5;
@@ -839,6 +830,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
}
#endif
esdhc_setbits32(>vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ mdelay(5);
if (esdhc_read32(>vendorspec) & ESDHC_VENDORSPEC_VSELECT)
return 0;
--
2.17.1
[PATCH 1/2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
From: Haibo Chen
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON,
after CMD11, hardware will gate off the card clock automatically, so card do
not detect the clock off/on behavior, so will draw the data0 line low until
next command.
Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
Tested-by: Tim Harvey
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 29 +
include/fsl_esdhc_imx.h | 2 ++
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index e0e132698e..af36558b3c 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -654,7 +654,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(>vendorspec, VENDORSPEC_CKEN);
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
#else
esdhc_clrbits32(>sysctl, SYSCTL_CKEN);
#endif
@@ -666,7 +669,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#else
esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
@@ -721,8 +724,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val;
+ u32 tmp;
+ int ret;
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp
& PRSSTAT_SDOFF, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never gate
off.\n");
esdhc_write32(>strobe_dllctrl,
ESDHC_STROBE_DLL_CTRL_RESET);
/*
@@ -740,6 +749,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
pr_warn("HS400 strobe DLL status REF not lock!\n");
if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
pr_warn("HS400 strobe DLL status SLV not lock!\n");
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
}
}
@@ -963,14 +973,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
#ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(>vendorspec, VENDORSPEC_CKEN);
+ u32 tmp;
+
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp
& PRSSTAT_SDOFF, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never gate
off.\n");
#else
esdhc_clrbits32(>sysctl, SYSCTL_CKEN);
#endif
} else {
#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_CKEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#else
esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
@@ -1046,7 +1060,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv,
struct mmc *mmc)
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(>sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
#else
- esdhc_setbits32(>vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#endif
/* Set the initial clock speed */
@@ -1184,8 +1198,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_write32(>autoc12err, 0);
esdhc_write32(>clktunectrlstatus, 0);
#else
- esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
[PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
From: Haibo Chen
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON,
after CMD11, hardware will gate off the card clock automatically, so card do
not detect the clock off/on behavior, so will draw the data0 line low until
next command.
Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 29 +
include/fsl_esdhc_imx.h | 2 ++
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 8ac859797f..da33ee8253 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -653,7 +653,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(>vendorspec, VENDORSPEC_CKEN);
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
#else
esdhc_clrbits32(>sysctl, SYSCTL_CKEN);
#endif
@@ -665,7 +668,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#else
esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
@@ -720,8 +723,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val;
+ u32 tmp;
+ int ret;
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp
& PRSSTAT_SDOFF, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never gate
off.\n");
esdhc_write32(>strobe_dllctrl,
ESDHC_STROBE_DLL_CTRL_RESET);
/*
@@ -739,6 +748,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
pr_warn("HS400 strobe DLL status REF not lock!\n");
if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
pr_warn("HS400 strobe DLL status SLV not lock!\n");
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
}
}
@@ -962,14 +972,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
#ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(>vendorspec, VENDORSPEC_CKEN);
+ u32 tmp;
+
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp
& PRSSTAT_SDOFF, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never gate
off.\n");
#else
esdhc_clrbits32(>sysctl, SYSCTL_CKEN);
#endif
} else {
#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_CKEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#else
esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
@@ -1045,7 +1059,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv,
struct mmc *mmc)
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(>sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
#else
- esdhc_setbits32(>vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#endif
/* Set the initial clock speed */
@@ -1183,8 +1197,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_write32(>autoc12err, 0);
esdhc_write32(>clktunectrlstatus, 0);
#else
- esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#endif
[PATCH v2] mmc: fsl_esdhc_imx: add wait_dat0() support
From: Haibo Chen
Add wait_dat0() support, upper layer will use this callback.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c67a8..29592d1f2c 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1646,6 +1646,20 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice
*dev)
}
#endif
+static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ int ret;
+ u32 tmp;
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp,
+ !!(tmp & PRSSTAT_DAT0) == !!state,
+ timeout_us);
+ return ret;
+}
+
static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
@@ -1656,6 +1670,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
#endif
+ .wait_dat0 = fsl_esdhc_wait_dat0,
};
#endif
--
2.17.1
[PATCH] mmc: fsl_esdhc_imx: optimize the timing setting
From: Haibo Chen
For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the
card clock will be divied by 2 automatically by the host. So need
to first config the DDR_EN correctly, then update the card clock.
This will make sure the actual card clock is as our expected.
IC also suggest config the DDR_EN firstly, then config the clock
divider.
For HS400/HS400ES mode, need to config the strobe dll, this need
to based on the correct target clock rate, so need to do this after
clock rate is update.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 3843d61d71..98bc81f2de 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -760,7 +760,6 @@ static int esdhc_set_timing(struct mmc *mmc)
case MMC_HS_400_ES:
mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
esdhc_write32(>mixctrl, mixctrl);
- esdhc_set_strobe_dll(mmc);
break;
case MMC_HS:
case MMC_HS_52:
@@ -933,6 +932,23 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
int ret __maybe_unused;
u32 clock;
+#ifdef MMC_SUPPORTS_TUNING
+ /*
+* call esdhc_set_timing() before update the clock rate,
+* This is because current we support DDR and SDR mode,
+* Once the DDR_EN bit is set, the card clock will be
+* divide by 2 automatically. So need to do this before
+* setting clock rate.
+*/
+ if (priv->mode != mmc->selected_mode) {
+ ret = esdhc_set_timing(mmc);
+ if (ret) {
+ printf("esdhc_set_timing error %d\n", ret);
+ return ret;
+ }
+ }
+#endif
+
/* Set the clock speed */
clock = mmc->clock;
if (clock < mmc->cfg->f_min)
@@ -957,13 +973,13 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
#endif
}
- if (priv->mode != mmc->selected_mode) {
- ret = esdhc_set_timing(mmc);
- if (ret) {
- printf("esdhc_set_timing error %d\n", ret);
- return ret;
- }
- }
+ /*
+* For HS400/HS400ES mode, make sure set the strobe dll in the
+* target clock rate. So call esdhc_set_strobe_dll() after the
+* clock updated.
+*/
+ if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode ==
MMC_HS_400_ES)
+ esdhc_set_strobe_dll(mmc);
if (priv->signal_voltage != mmc->signal_voltage) {
ret = esdhc_set_voltage(mmc);
--
2.17.1
[PATCH v2] mmc: fsl_esdhc_imx: add wait_dat0() support
From: Haibo Chen
Add wait_dat0() support, upper layer will use this callback.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c67a8..3843d61d71 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1646,6 +1646,28 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice
*dev)
}
#endif
+static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ int ret = -ETIMEDOUT;
+ bool dat0_high;
+ bool target_dat0_high = !!state;
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
+ while (timeout_us--) {
+ dat0_high = !!(esdhc_read32(>prsstat) & PRSSTAT_DAT0);
+ if (dat0_high == target_dat0_high) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ return ret;
+}
+
static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
@@ -1656,6 +1678,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
#endif
+ .wait_dat0 = fsl_esdhc_wait_dat0,
};
#endif
--
2.17.1
[PATCH] mmc: fsl_esdhc_imx: add wait_dat0() support
From: Haibo Chen
Add wait_dat0() support, upper layer will use this callback.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c67a8..dc6a6006fa 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1646,6 +1646,28 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice
*dev)
}
#endif
+static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ int ret = -ETIMEDOUT;
+ bool dat0_high;
+ bool target_dat0_high = !!state;
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
+ while (timeout_us--) {
+ dat0_high = !!(esdhc_read32(>prsstat) & PRSSTAT_DAT0);
+ if (dat0_high == target_dat0_high) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ return ret;
+}
+
static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
@@ -1656,6 +1678,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
#endif
+ .wait_dat0 = fsl_esdhc_wait_dat0,
};
#endif
--
2.17.1
[PATCH v2] mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32
From: Haibo Chen
Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align
the usage, change to only use esdhc_read32/esdhc_write32.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 64 ++---
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 0c866b168f..7e69000e00 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -729,7 +729,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
u32 val;
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
- writel(ESDHC_STROBE_DLL_CTRL_RESET, >strobe_dllctrl);
+ esdhc_write32(>strobe_dllctrl,
ESDHC_STROBE_DLL_CTRL_RESET);
/*
* enable strobe dll ctrl and adjust the delay target
@@ -738,10 +738,10 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
val = ESDHC_STROBE_DLL_CTRL_ENABLE |
(priv->strobe_dll_delay_target <<
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
- writel(val, >strobe_dllctrl);
+ esdhc_write32(>strobe_dllctrl, val);
/* wait 1us to make sure strobe dll status register stable */
mdelay(1);
- val = readl(>strobe_dllstat);
+ val = esdhc_read32(>strobe_dllstat);
if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
pr_warn("HS400 strobe DLL status REF not lock!\n");
if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
@@ -755,18 +755,18 @@ static int esdhc_set_timing(struct mmc *mmc)
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 mixctrl;
- mixctrl = readl(>mixctrl);
+ mixctrl = esdhc_read32(>mixctrl);
mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
switch (mmc->selected_mode) {
case MMC_LEGACY:
esdhc_reset_tuning(mmc);
- writel(mixctrl, >mixctrl);
+ esdhc_write32(>mixctrl, mixctrl);
break;
case MMC_HS_400:
case MMC_HS_400_ES:
mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
- writel(mixctrl, >mixctrl);
+ esdhc_write32(>mixctrl, mixctrl);
esdhc_set_strobe_dll(mmc);
break;
case MMC_HS:
@@ -777,12 +777,12 @@ static int esdhc_set_timing(struct mmc *mmc)
case UHS_SDR25:
case UHS_SDR50:
case UHS_SDR104:
- writel(mixctrl, >mixctrl);
+ esdhc_write32(>mixctrl, mixctrl);
break;
case UHS_DDR50:
case MMC_DDR_52:
mixctrl |= MIX_CTRL_DDREN;
- writel(mixctrl, >mixctrl);
+ esdhc_write32(>mixctrl, mixctrl);
break;
default:
printf("Not supported %d\n", mmc->selected_mode);
@@ -862,8 +862,8 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
struct mmc *mmc = >mmc;
- u32 irqstaten = readl(>irqstaten);
- u32 irqsigen = readl(>irqsigen);
+ u32 irqstaten = esdhc_read32(>irqstaten);
+ u32 irqsigen = esdhc_read32(>irqsigen);
int i, ret = -ETIMEDOUT;
u32 val, mixctrl;
@@ -873,25 +873,25 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- val = readl(>autoc12err);
- mixctrl = readl(>mixctrl);
+ val = esdhc_read32(>autoc12err);
+ mixctrl = esdhc_read32(>mixctrl);
val &= ~MIX_CTRL_SMPCLK_SEL;
mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
val |= MIX_CTRL_EXE_TUNE;
mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
- writel(val, >autoc12err);
- writel(mixctrl, >mixctrl);
+ esdhc_write32(>autoc12err, val);
+ esdhc_write32(>mixctrl, mixctrl);
}
/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
- mixctrl = readl(>mixctrl);
+ mixctrl = esdhc_read32(>mixctrl);
mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
- writel(mixctrl, >mixctrl);
+ esdhc_write32(>mixctrl, mixctrl);
- writel(IRQSTATEN_BRR, >irqstaten);
- writel(IRQSTATEN_BRR, >irqsigen);
+ esdhc_write32(>irqstaten, IRQSTATEN_BRR);
+ esdhc_write32(>irqsigen, IRQSTATEN_BRR);
/*
* Issue
[PATCH 2/2] mmc: fsl_esdhc_imx: remove the 1ms delay before sending command
From: Haibo Chen
This 1ms delay before sending command already exist from the beginning
of the fsl_esdhc driver added in year 2008. Now this driver has been
split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c
only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay
before sending any command. So remove this 1ms, this will save a lot
time if handling a large mmc data.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index a0a0903ae4..ac65ed1ee1 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -462,13 +462,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
while (esdhc_read32(>prsstat) & PRSSTAT_DLA)
;
- /* Wait at least 8 SD clock cycles before the next command */
- /*
-* Note: This is way more than 8 cycles, but 1ms seems to
-* resolve timing issues with some cards
-*/
- udelay(1000);
-
/* Set up for a data transfer if we have one */
if (data) {
err = esdhc_setup_data(priv, mmc, data);
--
2.17.1
[PATCH 1/2] mmc: do not send cmd13 if the parameter 'send_status' is 0 for __mmc_switch
From: Haibo Chen
According to the code logic in __mmc_switch, if the parameter 'send_status'
is zero, no need to send cmd13, just wait the stated timeout time, then
can return directly.
Signed-off-by: Haibo Chen
---
drivers/mmc/mmc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d79cdef62e..6cb2af4232 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -805,8 +805,10 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index,
u8 value,
* capable of polling by using mmc_wait_dat0, then rely on waiting the
* stated timeout to be sufficient.
*/
- if (ret == -ENOSYS && !send_status)
+ if (ret == -ENOSYS && !send_status) {
mdelay(timeout_ms);
+ return 0;
+ }
/* Finally wait until the card is ready or indicates a failure
* to switch. It doesn't hurt to use CMD13 here even if send_status
--
2.17.1
[PATCH v3] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
From: Haibo Chen
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 788677984b..0c866b168f 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
@@ -631,6 +632,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
+ u32 tmp;
+ int ret;
#ifdef ARCH_MXC
#ifdef CONFIG_MX53
/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
@@ -664,7 +667,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
esdhc_clrsetbits32(>sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(1);
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDSTB, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
#ifdef CONFIG_FSL_USDHC
esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
--
2.17.1
[PATCH] mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32
From: Haibo Chen
Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align
the usage, change to only use esdhc_read32/esdhc_write32.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 64 ++---
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 0c866b168f..a0a0903ae4 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -729,7 +729,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
u32 val;
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
- writel(ESDHC_STROBE_DLL_CTRL_RESET, >strobe_dllctrl);
+ esdhc_write32(ESDHC_STROBE_DLL_CTRL_RESET,
>strobe_dllctrl);
/*
* enable strobe dll ctrl and adjust the delay target
@@ -738,10 +738,10 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
val = ESDHC_STROBE_DLL_CTRL_ENABLE |
(priv->strobe_dll_delay_target <<
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
- writel(val, >strobe_dllctrl);
+ esdhc_write32(val, >strobe_dllctrl);
/* wait 1us to make sure strobe dll status register stable */
mdelay(1);
- val = readl(>strobe_dllstat);
+ val = esdhc_read32(>strobe_dllstat);
if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
pr_warn("HS400 strobe DLL status REF not lock!\n");
if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
@@ -755,18 +755,18 @@ static int esdhc_set_timing(struct mmc *mmc)
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 mixctrl;
- mixctrl = readl(>mixctrl);
+ mixctrl = esdhc_read32(>mixctrl);
mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
switch (mmc->selected_mode) {
case MMC_LEGACY:
esdhc_reset_tuning(mmc);
- writel(mixctrl, >mixctrl);
+ esdhc_write32(mixctrl, >mixctrl);
break;
case MMC_HS_400:
case MMC_HS_400_ES:
mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
- writel(mixctrl, >mixctrl);
+ esdhc_write32(mixctrl, >mixctrl);
esdhc_set_strobe_dll(mmc);
break;
case MMC_HS:
@@ -777,12 +777,12 @@ static int esdhc_set_timing(struct mmc *mmc)
case UHS_SDR25:
case UHS_SDR50:
case UHS_SDR104:
- writel(mixctrl, >mixctrl);
+ esdhc_write32(mixctrl, >mixctrl);
break;
case UHS_DDR50:
case MMC_DDR_52:
mixctrl |= MIX_CTRL_DDREN;
- writel(mixctrl, >mixctrl);
+ esdhc_write32(mixctrl, >mixctrl);
break;
default:
printf("Not supported %d\n", mmc->selected_mode);
@@ -862,8 +862,8 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
struct mmc *mmc = >mmc;
- u32 irqstaten = readl(>irqstaten);
- u32 irqsigen = readl(>irqsigen);
+ u32 irqstaten = esdhc_read32(>irqstaten);
+ u32 irqsigen = esdhc_read32(>irqsigen);
int i, ret = -ETIMEDOUT;
u32 val, mixctrl;
@@ -873,25 +873,25 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- val = readl(>autoc12err);
- mixctrl = readl(>mixctrl);
+ val = esdhc_read32(>autoc12err);
+ mixctrl = esdhc_read32(>mixctrl);
val &= ~MIX_CTRL_SMPCLK_SEL;
mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
val |= MIX_CTRL_EXE_TUNE;
mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
- writel(val, >autoc12err);
- writel(mixctrl, >mixctrl);
+ esdhc_write32(val, >autoc12err);
+ esdhc_write32(mixctrl, >mixctrl);
}
/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
- mixctrl = readl(>mixctrl);
+ mixctrl = esdhc_read32(>mixctrl);
mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
- writel(mixctrl, >mixctrl);
+ esdhc_write32(mixctrl, >mixctrl);
- writel(IRQSTATEN_BRR, >irqstaten);
- writel(IRQSTATEN_BRR, >irqsigen);
+ esdhc_write32(IRQSTATEN_BRR, >irqstaten);
+ esdhc_write32(IRQSTATEN_BRR, >irqsigen);
/*
* Issue
[PATCH v2] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
From: Haibo Chen
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 788677984b..8f7ac5b7a3 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
@@ -631,6 +632,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
+ u32 tmp;
+ int ret;
#ifdef ARCH_MXC
#ifdef CONFIG_MX53
/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
@@ -664,7 +667,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
esdhc_clrsetbits32(>sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(1);
+ ret = readl_poll_timeout(>prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
#ifdef CONFIG_FSL_USDHC
esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
--
2.17.1
[PATCH] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
From: Haibo Chen
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 788677984b..b60623e0ce 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -631,6 +631,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
+ u32 time_out = 50;
#ifdef ARCH_MXC
#ifdef CONFIG_MX53
/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
@@ -664,7 +665,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
mmc *mmc, uint clock)
esdhc_clrsetbits32(>sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(1);
+ while (!(esdhc_read32(>prsstat) & PRSSTAT_SDSTB)) {
+ if (time_out == 0) {
+ printf("fsl_esdhc_imx: Internal clock never
stabilised.\n");
+ break;
+ }
+ time_out--;
+ udelay(2);
+ }
#ifdef CONFIG_FSL_USDHC
esdhc_setbits32(>vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
--
2.17.1
[PATCH 1/2] mmc: fsl_esdhc_imx: fix the mask for tuning start point
From: Haibo Chen
According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is
TUNING_START_TAP, bit[7] of this register is to disable the command
CRC check for standard tuning. So fix it here.
Fixes: fa33d207494c ("mmc: split fsl_esdhc driver for i.MX")
Signed-off-by: Haibo Chen
---
include/fsl_esdhc_imx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 33c6d52bfe..220a76b9ee 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -203,7 +203,7 @@
#define ESDHC_STD_TUNING_EN BIT(24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
-#define ESDHC_TUNING_START_TAP_MASK0xff
+#define ESDHC_TUNING_START_TAP_MASK0x7f
#define ESDHC_TUNING_STEP_MASK 0x0007
#define ESDHC_TUNING_STEP_SHIFT16
--
2.17.1
[PATCH 2/2] mmc: fsl_esdhc_imx: disable the CMD CRC check for standard tuning
From: Haibo Chen
In current code, we add 1ms dealy after each tuning command for standard
tuning method. Adding this 1ms dealy is because USDHC default check the
CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning
IC logic do not wait for the tuning data sending out by the card, trigger
the buffer read ready interrupt immediately, and step to next cycle. So
when next time the new tuning command send out by USDHC, card may still
not send out the tuning data of the upper command，then some eMMC cards
may stuck, can't response to any command, block the whole tuning procedure.
If do not check the CMD CRC for tuning, then do not has this issue. USDHC
will wait for the tuning data of each tuning command and check them. If the
tuning data pass the check, it also means the CMD line also okay for tuning.
So this patch disable the CMD CRC check for tuning, save some time for the
whole tuning procedure.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 22 --
include/fsl_esdhc_imx.h | 1 +
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index f42e018434..5b61eeb214 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -907,19 +907,9 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev,
uint32_t opcode)
ctrl = readl(>autoc12err);
if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
(ctrl & MIX_CTRL_SMPCLK_SEL)) {
- /*
-* need to wait some time, make sure sd/mmc fininsh
-* send out tuning data, otherwise, the sd/mmc can't
-* response to any command when the card still out
-* put the tuning data.
-*/
- mdelay(1);
ret = 0;
break;
}
-
- /* Add 1ms delay for SD and eMMC */
- mdelay(1);
}
writel(irqstaten, >irqstaten);
@@ -1267,6 +1257,18 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
val |= priv->tuning_start_tap;
val &= ~ESDHC_TUNING_STEP_MASK;
val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+
+ /* Disable the CMD CRC check for tuning, if not, need to
+* add some delay after every tuning command, because
+* hardware standard tuning logic will directly go to
next
+* step once it detect the CMD CRC error, will not wait
for
+* the card side to finally send out the tuning data,
trigger
+* the buffer read ready interrupt immediately. If
usdhc send
+* the next tuning command some eMMC card will stuck,
can't
+* response, block the tuning procedure or the first
command
+* after the whole tuning procedure always can't get
any response.
+*/
+ val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
writel(val, >tuning_ctrl);
}
}
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 220a76b9ee..279a66d9bf 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -204,6 +204,7 @@
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
#define ESDHC_TUNING_START_TAP_MASK0x7f
+#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE BIT(7)
#define ESDHC_TUNING_STEP_MASK 0x0007
#define ESDHC_TUNING_STEP_SHIFT16
--
2.17.1
[PATCH v2] mmc: retry CMD1 in mmc_send_op_cond() until the eMMC is ready
From: Haibo Chen
According to eMMC specification v5.1 section 6.4.3, we should issue
CMD1 repeatedly in the idle state until the eMMC is ready even if
mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC
devices seems to enter the inactive mode after mmc_complete_op_cond()
issued CMD0 when the eMMC device is busy.
Signed-off-by: Haibo Chen
---
drivers/mmc/mmc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 85762b82e0..475f75fc64 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -662,12 +662,15 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, int
use_arg)
static int mmc_send_op_cond(struct mmc *mmc)
{
int err, i;
+ int timeout = 1000;
+ uint start;
/* Some cards seem to need this */
mmc_go_idle(mmc);
+ start = get_timer(0);
/* Asking to the card its capabilities */
- for (i = 0; i < 2; i++) {
+ for (i = 0; ; i++) {
err = mmc_send_op_cond_iter(mmc, i != 0);
if (err)
return err;
@@ -675,6 +678,10 @@ static int mmc_send_op_cond(struct mmc *mmc)
/* exit if not busy (flag seems to be inverted) */
if (mmc->ocr & OCR_BUSY)
break;
+
+ if (get_timer(start) > timeout)
+ return -ETIMEDOUT;
+ udelay(100);
}
mmc->op_cond_pending = 1;
return 0;
--
2.17.1
[PATCH] mmc: retry CMD1 in mmc_send_op_cond() until the eMMC is ready
From: Haibo Chen
According to eMMC specification v5.1 section 6.4.3, we should issue
CMD1 repeatedly in the idle state until the eMMC is ready even if
mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC
devices seems to enter the inactive mode after mmc_complete_op_cond()
issued CMD0 when the eMMC device is busy. This patch also align with
Linux 5.7.
Signed-off-by: Haibo Chen
---
drivers/mmc/mmc.c | 41 +
1 file changed, 33 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 523c055967..509549756b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -664,21 +664,46 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, int
use_arg)
static int mmc_send_op_cond(struct mmc *mmc)
{
+ struct mmc_cmd cmd;
int err, i;
+ int timeout = 1000;
+ ulong start;
/* Some cards seem to need this */
mmc_go_idle(mmc);
- /* Asking to the card its capabilities */
- for (i = 0; i < 2; i++) {
- err = mmc_send_op_cond_iter(mmc, i != 0);
+ cmd.cmdidx = MMC_CMD_SEND_OP_COND;
+ cmd.resp_type = MMC_RSP_R3;
+ cmd.cmdarg = 0;
+
+ start = get_timer(0);
+ /*
+* According to eMMC specification v5.1 section 6.4.3, we
+* should issue CMD1 repeatedly in the idle state until
+* the eMMC is ready. Otherwise some eMMC devices seem to enter
+* the inactive mode after mmc_complete_op_cond() issued CMD0 when
+* the eMMC device is busy.
+*/
+ while (1) {
+ err = mmc_send_cmd(mmc, , NULL);
if (err)
return err;
-
- /* exit if not busy (flag seems to be inverted) */
- if (mmc->ocr & OCR_BUSY)
- break;
+ if (mmc_host_is_spi(mmc)) {
+ if (!(cmd.response[0] & (1 << 0)))
+ break;
+ } else {
+ mmc->ocr = cmd.response[0];
+ /* exit if not busy (flag seems to be inverted) */
+ if (mmc->ocr & OCR_BUSY)
+ break;
+ }
+ if (get_timer(start) > timeout)
+ return -EOPNOTSUPP;
+ udelay(100);
+ if (!mmc_host_is_spi(mmc))
+ cmd.cmdarg = cmd.response[0] | (1 << 30);
}
+
mmc->op_cond_pending = 1;
return 0;
}
@@ -691,7 +716,7 @@ static int mmc_complete_op_cond(struct mmc *mmc)
int err;
mmc->op_cond_pending = 0;
- if (!(mmc->ocr & OCR_BUSY)) {
+ if (mmc->ocr & OCR_BUSY) {
/* Some cards seem to need this */
mmc_go_idle(mmc);
--
2.17.1
[U-Boot] [PATCH] mmc: cat u8 to u64 to avoid unexpected error
Suspicious implicit sign extension exist. ext_csd[] is defined as "u8", capacity is defined as u64, so u8 is promoted to signed int first int the "|" expersion, then the sign extended to u64. if the tmp sign value is largeer than 0x7fff, after the sign extension, the upper bits of the result will all be 1. Thanks to coverity <http://www.coverity.com> e.g. u8 data_8; u64 data_64; data_8 = 0x80; data_64 = data_8 << 24; //0x8000 data_64 = ((u64)data_8) << 24; //0x8000 Signed-off-by: Haibo Chen <haibo.c...@nxp.com> --- drivers/mmc/mmc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 43ea0bb..c1d1dc6 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1176,10 +1176,10 @@ static int mmc_startup(struct mmc *mmc) * ext_csd's capacity is valid if the value is more * than 2GB */ - capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 - | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 - | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 - | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; + capacity = ((u64)ext_csd[EXT_CSD_SEC_CNT]) << 0 + | ((u64)ext_csd[EXT_CSD_SEC_CNT + 1]) << 8 + | ((u64)ext_csd[EXT_CSD_SEC_CNT + 2]) << 16 + | ((u64)ext_csd[EXT_CSD_SEC_CNT + 3]) << 24; capacity *= MMC_MAX_BLOCK_LEN; if ((capacity >> 20) > 2 * 1024) mmc->capacity_user = capacity; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
