From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 845369. The ARM errata 751472, 794072, 761320,
845369 only applied to the following configuration:
This erratum affects configurations with either:
- One processor if the ACP is
From: Nitin Garg nitin.g...@freescale.com
The ARM errata 845369 only applies to one processor
if the ACP is present OR two or more processors.
i.MX6 family does not have the ACP and thus only the MPCore
system will be impacted, which are the i.MX6DQ, i.MX6DL.
Signed-off-by: Nitin Garg
From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable ARM errata
751472, 794072, 761320 only applied to the
following configuration:
This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors
i.MX6 family does not
From: Nitin Garg nitin.g...@freescale.com
Under very rare timing circumstances, transition into
streaming mode might create a data corruption. Exists on
all Cortex-A9 revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
Changes in v3: None
Changes in v2: None
README
From: Nitin Garg nitin.g...@freescale.com
Under very rare timing circumstances, transition into
streaming mode might create a data corruption. Exists on
all Cortex-A9 revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
Changes in v3: None
Changes in v2: None
README
From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable ARM errata
751472, 794072, 761320 only applied to the
following configuration:
This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors
i.MX6 family does not
From: Nitin Garg nitin.g...@freescale.com
The ARM errata 845369 only applies to one processor
if the ACP is present OR two or more processors.
i.MX6 family does not have the ACP and thus only the MPCore
system will be impacted, which are the i.MX6DQ, i.MX6DL.
Signed-off-by: Nitin Garg
From: Nitin Garg nitin.g...@freescale.com
Under very rare timing circumstances, transition into
streaming mode might create a data corruption. Exists on
all Cortex-A9 revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
README |1 +
From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 845369.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
include/configs/mx6_common.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/mx6_common.h
From: Nitin Garg nitin.g...@freescale.com
i.MX6 SoC has onchip temperature sensor. Add driver
for this sensor.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
drivers/Makefile |1 +
drivers/thermal/Makefile |8 +++
drivers/thermal/imx_thermal.c | 144
From: Nitin Garg nitin.g...@freescale.com
This patch set adds i.MX6 thermal sensor driver
and enables it for mx6sabre boards. Also adds
various anadig bit definitions as required for
upcoming drivers.
Changes in v6:
-Aligned imx thermal driver macro defines with kernel
Changes in v5:
-Don't
From: Nitin Garg nitin.g...@freescale.com
read cpu temperature using the onchip thermal
sensor.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/imx-common/cpu.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
From: Nitin Garg nitin.g...@freescale.com
Add CONFIG_IMX6_THERMAL to mx6sabre_common.h file. Since
thermal driver depends on ocotp, make sure to enable
CONFIG_MXC_OCOTP when CONFIG_IMX6_THERMAL is slected.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
include/configs/mx6sabre_common.h
From: Nitin Garg nitin.g...@freescale.com
Add api to check and enable pll3 as required
for thermal sensor driver.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/cpu/armv7/mx6/clock.c| 25 +
arch/arm/include/asm/arch-mx6/clock.h |1 +
2
From: Nitin Garg nitin.g...@freescale.com
Provide cgtqmx6eval board its own variant of ddr
setup config file. Move board/freescale/imx/ddr/
mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/
as this is was designed for the mx6sabresd board.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
From: Nitin Garg nitin.g...@freescale.com
Add support for mx6 onchip temperature sensor and enable it
for all mx6sabre boards.
Nitin Garg (2):
Changes since v2:
- Split the patch into 2: Feature impl and board enablement
Changes since v1:
- Make temperature sensor feature configurable
-
From: Nitin Garg nitin.g...@freescale.com
Add CONFIG_IMX6_TEMP_SENSOR to mx6sabre_common.h file
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
include/configs/mx6sabre_common.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/mx6sabre_common.h
From: Nitin Garg nitin.g...@freescale.com
i.MX6 SoC has onChip temperature sensor. Add support
for this sensor.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/cpu/armv7/mx6/soc.c | 138 +++-
arch/arm/imx-common/cpu.c|7 +-
From: Nitin Garg nitin.g...@freescale.com
Support CPU temperature sensors on i.MX6 SoC.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/cpu/armv7/mx6/soc.c | 137 +++-
arch/arm/imx-common/cpu.c|7 +-
arch/arm/include/asm/arch-mx6/crm_regs.h |
From: Nitin Garg nitin.g...@freescale.com
This patch adds support for i.MX6 on chip temperature sensor support.
Nitin Garg (1):
Add i.MX6 CPU temperature sensor support
arch/arm/cpu/armv7/mx6/soc.c | 137 +++-
arch/arm/imx-common/cpu.c|7 +-
From: Nitin Garg nitin.g...@freescale.com
Support CPU temperature sensors on i.MX6 SoC.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/cpu/armv7/mx6/soc.c | 137 +++-
arch/arm/imx-common/cpu.c|7 +-
arch/arm/include/asm/arch-mx6/crm_regs.h |
From: Nitin Garg nitin.g...@freescale.com
This patch adds support for i.MX6 on chip temperature sensor support.
Nitin Garg (1):
Add i.MX6 CPU temperature sensor support
arch/arm/cpu/armv7/mx6/soc.c | 137 +++-
arch/arm/imx-common/cpu.c|7 +-
From: Nitin Garg nitin.g...@freescale.com
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg| 169 ---
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg | 169 +++
configs/cgtqmx6qeval_defconfig
From: Nitin Garg nitin.g...@freescale.com
Since board/freescale/imx/ddr/ contains single file and that file
actually belongs to mx6sabresd, move it so that its move evident.
Nitin Garg (1):
Move board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg to
From: Nitin Garg nitin.g...@freescale.com
Add hab_auth_img u-boot command which can be used for HAB authentication
of images.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/cpu/armv7/mx6/clock.c| 40 ++-
arch/arm/cpu/armv7/mx6/hab.c | 180
From: Nitin Garg nitin.g...@freescale.com
Add hab_auth_img u-boot command which can be used for HAB authentication
of images.
Nitin Garg (1):
Support i.MX6 High Assurance Boot (HAB) authentication of images
arch/arm/cpu/armv7/mx6/clock.c| 40 ++-
From: Nitin Garg nitin.g...@freescale.com
i.MX6sl evk has a keyboard on the board, so add mxc_keyb driver to
support keypad.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
drivers/input/Makefile |1 +
drivers/input/mxc_keyb.c | 588 ++
From: Nitin Garg nitin.g...@freescale.com
i.MX6sl evk has a keyboard on the board, so add mxc_keyb driver to support
keypad.
Nitin Garg (1):
Add support for i.MX6SL EVK board keypad
drivers/input/Makefile |1 +
drivers/input/mxc_keyb.c | 588
From: Nitin Garg nitin.g...@freescale.com
These patches implement workaround for 2 Cortex-A9 erratas.
Enable these errata workaround for MX6.
Nitin Garg (3):
ARM: Add workaround for Cortex-A9 errata 794072
ARM: Add workaround for Cortex-A9 errata 761320
MX6: Enable ARM errata workaround
From: Nitin Garg nitin.g...@freescale.com
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
README |1 +
From: Nitin Garg nitin.g...@freescale.com
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
README
From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 794072 and 761320.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
include/configs/mx6_common.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 794072 and 761320.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
include/configs/mx6_common.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
From: Nitin Garg nitin.g...@freescale.com
These patches implement workaround for 2 Cortex-A9 erratas.
Enable these errata workaround for MX6.
Changes since v2:
- Added Acked-by Dirk Behme for PATCH 1/3
- Added Stefano for review
Changes since v1:
- Enabled these erratas for MX6 as suggested
From: Nitin Garg nitin.g...@freescale.com
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
README |1 +
From: Nitin Garg nitin.g...@freescale.com
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
Acked-by: Dirk Behme
From: Nitin Garg nitin.g...@freescale.com
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
README |1 +
From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 794072 and 761320.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
include/configs/mx6_common.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
From: Nitin Garg nitin.g...@freescale.com
These patches implement workaround for 2 Cortex-A9 erratas.
Enable these errata workaround for MX6.
Changes since v2:
- Added Acked-by Dirk Behme for PATCH 1/3
- Added Stefano for review
Changes since v1:
- Enabled these erratas for MX6 as suggested
From: Nitin Garg nitin.g...@freescale.com
Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 794072 and 761320.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
include/configs/mx6_common.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
From: Nitin Garg nitin.g...@freescale.com
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
Acked-by: Dirk Behme
From: Nitin Garg nitin.g...@freescale.com
These patches implement workaround for 2 Cortex-A9 erratas.
Nitin Garg (2):
ARM: Add workaround for Cortex-A9 errata 794072
ARM: Add workaround for Cortex-A9 errata 761320
README |2 ++
arch/arm/cpu/armv7/start.S | 10
From: Nitin Garg nitin.g...@freescale.com
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
README
From: Nitin Garg nitin.g...@freescale.com
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
README |1 +
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