Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Drop accidental creation of link.dts due to bad rebase
Changes in v2:
- Make changes to chromebook_link.dts since link.dts is gone
- Use intel,ich-spi as the compatible string
arch/x86/dts/chromebook_link.dts | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 9490b16..45ada61 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -7,6 +7,10 @@
model = Google Link;
compatible = google,link, intel,celeron-ivybridge;
+ aliases {
+ spi0 = /spi;
+ };
+
config {
silent_console = 0;
};
@@ -150,11 +154,20 @@
spi {
#address-cells = 1;
#size-cells = 0;
- compatible = intel,ich9;
+ compatible = intel,ich-spi;
spi-flash@0 {
+ #size-cells = 1;
+ #address-cells = 1;
reg = 0;
compatible = winbond,w25q64, spi-flash;
memory-map = 0xff80 0x0080;
+ rw-mrc-cache {
+ label = rw-mrc-cache;
+ /* Alignment: 4k (for updating) */
+ reg = 0x003e 0x0001;
+ type = wiped;
+ wipe-value = [ff];
+ };
};
};
--
2.2.0.rc0.207.ga3a616c
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