Re: [GIT PULL] u-boot-riscv/master
On Thu, May 02, 2024 at 12:38:11AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ff0de1f0557ed7d2dab47ba976a37347a1fdc432: > > Merge patch series "Update PHYTEC SOM Detection" (2024-04-29 10:56:05 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 19b762cf83f68b9d9a1f14e75d75781cedf4049f: > > board: starfive: Rename spl_soc_init() to spl_dram_init() (2024-05-02 > 00:01:18 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20596 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit ff0de1f0557ed7d2dab47ba976a37347a1fdc432: Merge patch series "Update PHYTEC SOM Detection" (2024-04-29 10:56:05 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 19b762cf83f68b9d9a1f14e75d75781cedf4049f: board: starfive: Rename spl_soc_init() to spl_dram_init() (2024-05-02 00:01:18 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20596 - RISC-V: cmd: Add SBI implementation ID and extension ID - Board: Rename spl_soc_init to spl_dram_init - Board: milkv_duo: Add SPI NOR flash, Ethernet, Sysreset support Heinrich Schuchardt (2): cmd: sbi: add Supervisor Software Events extension cmd: sbi: add coreboot and oreboot implementation IDs Kongyang Liu (10): mmc: cv1800b: Add transmit tap delay config to fix write error sysreset: cv1800b: Add sysreset driver for cv1800b SoC board: sophgo: milkv_duo: Bind sysreset driver configs: milkv_duo: Add sysreset configs board: milkv_duo: Add init code for Milk-V Duo ethernet riscv: dts: sophgo: Add ethernet node configs: milkv_duo: Add ethernet configs spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC riscv: dts: sophgo: Add spi nor flash controller node configs: milkv_duo: Add spi nor configs Lukas Funke (2): board: sifive: Rename spl_soc_init() to spl_dram_init() board: starfive: Rename spl_soc_init() to spl_dram_init() Yu Chien Peter Lin (1): riscv: andesv5: Set default cache line size to 64-bytes arch/riscv/cpu/andesv5/Kconfig | 1 + arch/riscv/cpu/fu540/spl.c | 2 +- arch/riscv/cpu/fu740/spl.c | 2 +- arch/riscv/cpu/jh7110/spl.c | 2 +- arch/riscv/dts/cv1800b-milkv-duo.dts | 18 ++ arch/riscv/dts/cv18xx.dtsi | 40 arch/riscv/include/asm/arch-fu540/spl.h | 2 +- arch/riscv/include/asm/arch-fu740/spl.h | 2 +- arch/riscv/include/asm/arch-jh7110/spl.h | 2 +- arch/riscv/include/asm/sbi.h | 1 + board/sifive/unleashed/spl.c | 4 +- board/sifive/unmatched/spl.c | 4 +- board/sophgo/milkv_duo/Makefile | 3 +- board/sophgo/milkv_duo/board.c | 10 + board/sophgo/milkv_duo/ethernet.c| 79 board/sophgo/milkv_duo/ethernet.h| 11 ++ board/starfive/visionfive2/spl.c | 4 +- cmd/riscv/sbi.c | 3 + configs/milkv_duo_defconfig | 10 + drivers/mmc/cv1800b_sdhci.c | 4 +- drivers/net/designware.c | 1 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cv1800b_spif.c | 321 +++ drivers/sysreset/Kconfig | 5 + drivers/sysreset/Makefile| 1 + drivers/sysreset/sysreset_cv1800b.c | 64 ++ 27 files changed, 591 insertions(+), 14 deletions(-) create mode 100644 board/sophgo/milkv_duo/ethernet.c create mode 100644 board/sophgo/milkv_duo/ethernet.h create mode 100644 drivers/spi/cv1800b_spif.c create mode 100644 drivers/sysreset/sysreset_cv1800b.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, Apr 09, 2024 at 04:25:36PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 069d07396e30aa9be396c1dd3fc158ac199e6843: > > Merge tag 'efi-2024-07-rc1' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-08 14:33:59 > -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c1f78a4f632276bb4d77f8c79fe203709a9fa397: > > doc: describe Milk-V Mars board (2024-04-09 11:30:37 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20256 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 069d07396e30aa9be396c1dd3fc158ac199e6843: Merge tag 'efi-2024-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-08 14:33:59 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c1f78a4f632276bb4d77f8c79fe203709a9fa397: doc: describe Milk-V Mars board (2024-04-09 11:30:37 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20256 - RISC-V: Support backtrace and improve isa extension parsing - cpu: Add cv1800b SoC support - board: Add Milk-V Mars board support - board: Add Milk-V Duo SD card support Ben Dooks (1): riscv: add backtrace support Conor Dooley (2): riscv: don't read riscv, isa in the riscv cpu's get_desc() riscv: support extension probing using riscv, isa-extensions Heinrich Schuchardt (7): riscv: starfive: MMC card detect riscv: do not set default fdt for VisionFive 2 eeprom: starfive: function get_product_id_from_eeprom() riscv: set fdtfile on Milk-V Mars board: starfive: support Milk-V Mars board riscv: starfive: avoid including common.h doc: describe Milk-V Mars board Kongyang Liu (5): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b mmc: cv1800b: Add sdhci driver support for cv1800b SoC riscv: dts: sophgo: Add clk node and sdhci node configs: milkv_duo: Add SD card configs Łukasz Stelmach (1): riscv: Move virtio scan to board_late_init() arch/riscv/Kconfig | 22 arch/riscv/Makefile| 4 + arch/riscv/cpu/cpu.c | 60 +++ arch/riscv/cpu/cv1800b/Kconfig | 12 +++ arch/riscv/cpu/cv1800b/Makefile| 7 ++ arch/riscv/cpu/cv1800b/cache.c | 45 arch/riscv/cpu/cv1800b/cpu.c | 9 ++ arch/riscv/cpu/cv1800b/dram.c | 21 arch/riscv/cpu/start.S | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 8 ++ arch/riscv/dts/cv1800b.dtsi| 4 + arch/riscv/dts/cv18xx.dtsi | 22 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- arch/riscv/include/asm/arch-jh7110/eeprom.h| 9 ++ arch/riscv/lib/interrupts.c| 35 +++ board/emulation/qemu-riscv/qemu-riscv.c| 12 +-- board/sophgo/milkv_duo/Kconfig | 4 +- board/starfive/visionfive2/spl.c | 100 +++--- board/starfive/visionfive2/starfive_visionfive2.c | 48 ++--- .../starfive/visionfive2/visionfive2-i2c-eeprom.c | 9 +- configs/milkv_duo_defconfig| 10 ++ configs/starfive_visionfive2_defconfig | 1 - doc/board/starfive/index.rst | 1 + doc/board/starfive/milk-v_mars.rst | 111 doc/board/starfive/visionfive2.rst | 18 drivers/cpu/riscv_cpu.c| 8 +- drivers/mmc/Kconfig| 13 +++ drivers/mmc/Makefile | 1 + drivers/mmc/cv1800b_sdhci.c| 116 + 29 files changed, 649 insertions(+), 64 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c create mode 100644 doc/board/starfive/milk-v_mars.rst create mode 100644 drivers/mmc/cv1800b_sdhci.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, Mar 26, 2024 at 09:22:27PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc: > > Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 0cfe1bc6ed9b322d2b03ded3175ac5de3ed2b784: > > spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR (2024-03-26 17:31:24 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20075 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc: Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 0cfe1bc6ed9b322d2b03ded3175ac5de3ed2b784: spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR (2024-03-26 17:31:24 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20075 - Fix RISC-V falcon mode booting issue Randolph (1): spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR common/spl/spl_opensbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, Mar 12, 2024 at 04:51:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: > > Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 544af8207c69829b1697f3aa5dd682a299a6dea4: > > board: starfive: maintainer: Add visionfive2 PCIe driver (2024-03-12 > 14:36:13 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19910 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 544af8207c69829b1697f3aa5dd682a299a6dea4: board: starfive: maintainer: Add visionfive2 PCIe driver (2024-03-12 14:36:13 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19910 * riscv: lib: improve extension detection * riscv: sbi: fix display format and global variable storage * sifive: fu740: reduce DDR speed * board: starfive vf2: switch to standard boot and fix DTS Bo Gan (1): riscv: dts: jh7110: Enable PLL node in SPL Conor Dooley (1): riscv: cpu: improve multi-letter extension detection in supports_extension() Heinrich Schuchardt (3): serial: move sbi_dbcn_available to .data section cmd: sbi: Correctly display unknown implementation IDs cmd: sbi: formatting PolarFire Hart Software Services version Leon M. Busch-George (1): riscv: dts: jh7110: fix indentation Minda Chen (2): board: starfive: Update maintainer of VisionFive v2 board board: starfive: maintainer: Add visionfive2 PCIe driver Nam Cao (1): starfive: visionfive2: switch to standard boot Thomas Perrot (1): riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s arch/riscv/cpu/cpu.c | 22 -- arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110-u-boot.dtsi | 4 board/starfive/visionfive2/MAINTAINERS | 3 ++- cmd/riscv/sbi.c| 3 ++- configs/starfive_visionfive2_defconfig | 2 +- drivers/serial/serial_sbi.c| 2 +- include/configs/starfive-visionfive2.h | 14 +- 9 files changed, 29 insertions(+), 25 deletions(-) Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Wed, Jan 31, 2024 at 06:21:34PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 28760ce8640ff6266bd1c1c568a4a231576f3919: > > Merge tag 'clk-2024.04-rc2' of > https://source.denx.de/u-boot/custodians/u-boot-clk (2024-01-30 07:54:28 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 6882255ac3107c58e1153311df8a8270087f8cb3: > > riscv: dts: starfive: add regulator device (2024-01-31 16:52:53 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19505 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 28760ce8640ff6266bd1c1c568a4a231576f3919: Merge tag 'clk-2024.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-clk (2024-01-30 07:54:28 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 6882255ac3107c58e1153311df8a8270087f8cb3: riscv: dts: starfive: add regulator device (2024-01-31 16:52:53 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19505 * Add RISC-V falcon mode documentation * Add Clang build support * Add cmd to detect Debug Trigger Extension support * Add PWM setting for Unmatched board * Add Milk-V Duo board support * Add new device node and enable new config option for VisionFive2 board * Add second virtio device for RISC-V QEMU Aurelien Jarno (3): board: starfive: handle compatible property in dynamic DT configuration riscv: qemu: enable booting on a second virtio device configs: visionfive2: Disable ENV_IS_NOWHERE Heinrich Schuchardt (1): cmd: sbi: add support for Debug Trigger Extension Kongyang Liu (3): riscv: dts: sophgo: add basic device tree for Milk-V Duo board riscv: sophgo: milkv_duo: initial support added doc: sophgo: milkv_duo: document Milk-V Duo board Lukasz Tekieli (2): net: phy: motorcomm: configure pad drive strength register board: visionfive2: configure PHY pad drive strength Nam Cao (2): riscv: dts: jh7110: add power management unit controller node riscv: dts: starfive: add regulator device Randolph (3): doc: falcon: riscv: Falcon Mode boot on RISC-V spl: riscv: falcon: move fdt blob to specified address configs: andes: add the fdt blob copy address for SPL Vincent Chen (1): board: sifive: spl: Initialized the PWM setting in the SPL stage kleines Filmröllchen (1): riscv: Support building with Clang arch/riscv/Kconfig | 4 + arch/riscv/config.mk | 2 +- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 38 + arch/riscv/dts/cv1800b.dtsi | 18 +++ arch/riscv/dts/cv18xx.dtsi | 192 +++ arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 + arch/riscv/dts/jh7110.dtsi | 6 + arch/riscv/include/asm/arch-fu740/eeprom.h | 15 ++ arch/riscv/include/asm/sbi.h | 1 + board/AndesTech/ae350/ae350.c| 25 --- board/sifive/unmatched/spl.c | 52 ++ board/sophgo/milkv_duo/Kconfig | 28 board/sophgo/milkv_duo/MAINTAINERS | 6 + board/sophgo/milkv_duo/Makefile | 5 + board/sophgo/milkv_duo/board.c | 9 ++ board/starfive/visionfive2/spl.c | 12 ++ cmd/riscv/sbi.c | 1 + common/spl/Kconfig | 2 +- common/spl/spl_opensbi.c | 15 ++ configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + configs/milkv_duo_defconfig | 23 +++ configs/starfive_visionfive2_defconfig | 1 - doc/board/index.rst | 1 + doc/board/sophgo/index.rst | 8 + doc/board/sophgo/milkv_duo.rst | 64 doc/develop/falcon.rst | 158 +++ drivers/net/phy/motorcomm.c | 130 +++ include/configs/milkv_duo.h | 12 ++ include/configs/qemu-riscv.h | 1 + 33 files changed, 811 insertions(+), 28 deletions(-) create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/dts/cv1800b.dtsi create mode 100644 arch/riscv/dts/cv18xx.dtsi create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h create mode 100644 board/sophgo/milkv_duo/Kconfig create mode 100644 board/sophgo/milkv_duo/MAINTAINERS create mode 100644 board/sophgo/milkv_duo/Makefile create mode 100644 board/sophgo/milkv_duo/board.c create mode 100644 configs/milkv_duo_defconfig create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst create mode 100644 include/configs/milkv_duo.h Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, Dec 14, 2023 at 08:46:14PM +0800, Leo Liang wrote: > Hi Tom, > > On Thu, Dec 14, 2023 at 07:19:02AM -0500, Tom Rini wrote: > > On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote: > > > > > Hi Tom, > > > > > > The following changes since commit > > > 20d0464300c25db673cfb5e4539aa3767606d151: > > > > > > Merge tag 'u-boot-imx-20231212' of > > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 > > > -0500) > > > > > > are available in the Git repository at: > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: > > > > > > riscv: sifive: unmatched: migrate to text environment (2023-12-13 > > > 16:19:43 +0800) > > > > > > CI result shows no issue: > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 > > > > > > - VisionFive2: Enable CONFIG_SYSRESET > > > - StarFive: Modify starfive timer driver > > > - AMD/Xilinx: Add MicroBlaze V support > > > - Unmatched: Migrate to text environment > > > > > > > Are all of these really appropriate for a release less than a month away > > or should I take this to -next? Thanks. > > Ah! You're right! > I think merging to -next seems to be more appropriate! > Thanks for the reminder! > OK. It'll be easiest then if you wait until I've merged the next -rc in to next and rebase this PR on top of that. -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] u-boot-riscv/master
Hi Tom, On Thu, Dec 14, 2023 at 07:19:02AM -0500, Tom Rini wrote: > On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote: > > > Hi Tom, > > > > The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: > > > > Merge tag 'u-boot-imx-20231212' of > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 > > -0500) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: > > > > riscv: sifive: unmatched: migrate to text environment (2023-12-13 > > 16:19:43 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 > > > > - VisionFive2: Enable CONFIG_SYSRESET > > - StarFive: Modify starfive timer driver > > - AMD/Xilinx: Add MicroBlaze V support > > - Unmatched: Migrate to text environment > > > > Are all of these really appropriate for a release less than a month away > or should I take this to -next? Thanks. Ah! You're right! I think merging to -next seems to be more appropriate! Thanks for the reminder! Best regards, Leo > -- > Tom
Re: [GIT PULL] u-boot-riscv/master
On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote: > Hi Tom, > > The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: > > Merge tag 'u-boot-imx-20231212' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: > > riscv: sifive: unmatched: migrate to text environment (2023-12-13 16:19:43 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 > > - VisionFive2: Enable CONFIG_SYSRESET > - StarFive: Modify starfive timer driver > - AMD/Xilinx: Add MicroBlaze V support > - Unmatched: Migrate to text environment > Are all of these really appropriate for a release less than a month away or should I take this to -next? Thanks. -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: Merge tag 'u-boot-imx-20231212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: riscv: sifive: unmatched: migrate to text environment (2023-12-13 16:19:43 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment Jaehoon Chung (2): riscv: dts: jh7110: Add a gpio-restart node configs: visionfive2: Enable CONFIG_SYSRESET config Kuan Lim Lee (1): timer: starfive: Add Starfive timer support Michal Simek (1): riscv: Add support for AMD/Xilinx MicroBlaze V Yong-Xuan Wang (1): riscv: sifive: unmatched: migrate to text environment arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 2 + arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/dts/xilinx-mbv32.dts | 106 +++ board/sifive/unmatched/unmatched.env | 19 board/xilinx/Kconfig | 3 +- board/xilinx/common/board.c | 5 ++ board/xilinx/mbv/Kconfig | 28 ++ board/xilinx/mbv/MAINTAINERS | 7 ++ board/xilinx/mbv/Makefile| 5 ++ board/xilinx/mbv/board.c | 11 +++ configs/sifive_unmatched_defconfig | 2 +- configs/starfive_visionfive2_defconfig | 1 + configs/xilinx_mbv32_defconfig | 30 +++ configs/xilinx_mbv32_smode_defconfig | 32 +++ drivers/timer/starfive-timer.c | 16 ++-- include/configs/sifive-unmatched.h | 37 include/configs/xilinx_mbv.h | 6 ++ 18 files changed, 273 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/dts/xilinx-mbv32.dts create mode 100644 board/sifive/unmatched/unmatched.env create mode 100644 board/xilinx/mbv/Kconfig create mode 100644 board/xilinx/mbv/MAINTAINERS create mode 100644 board/xilinx/mbv/Makefile create mode 100644 board/xilinx/mbv/board.c create mode 100644 configs/xilinx_mbv32_defconfig create mode 100644 configs/xilinx_mbv32_smode_defconfig create mode 100644 include/configs/xilinx_mbv.h Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, Dec 07, 2023 at 09:46:23PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63: > > Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 94533cd9c15a60b74420e53a725fab54d38dd555: > > starfive: visionfive2: add device tree overlay support (2023-12-06 16:05:39 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18812 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63: Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 94533cd9c15a60b74420e53a725fab54d38dd555: starfive: visionfive2: add device tree overlay support (2023-12-06 16:05:39 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18812 - StarFive: Add StarFive watchdog driver - VisionFive2: Support device tree overlay for VisionFive2 board - Andes: Fix PLIC-SW setting - RISC-V: Fix NVMe support by implying NVME_PCI for QEMU - RISC-V: Fix binman for 64 bit format load address Chanho Park (4): clk: starfive: jh7110: Add watchdog clocks watchdog: Add StarFive Watchdog driver riscv: dts: jh7110: Add watchdog device tree node configs: visionfive2: Enable watchdog driver Heinrich Schuchardt (1): risc-v: qemu: imply NVME_PCI John Clark (1): starfive: visionfive2: add device tree overlay support Randolph (1): riscv: binman: fix the load field format Yu Chien Peter Lin (1): riscv: andes: Fix enable register settings of PLICSW arch/riscv/dts/binman.dtsi | 14 +- arch/riscv/dts/jh7110.dtsi | 10 + arch/riscv/lib/andes_plicsw.c | 33 ++-- board/emulation/qemu-riscv/Kconfig | 2 +- configs/starfive_visionfive2_defconfig | 5 + drivers/clk/starfive/clk-jh7110.c | 9 + drivers/watchdog/Kconfig | 7 + drivers/watchdog/Makefile | 1 + drivers/watchdog/starfive_wdt.c| 329 + include/configs/starfive-visionfive2.h | 1 + 10 files changed, 382 insertions(+), 29 deletions(-) create mode 100644 drivers/watchdog/starfive_wdt.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, Nov 02, 2023 at 06:49:56PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4: > > Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01 > 09:44:33 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0: > > configs: visionfive2: Enable JH7110 RNG driver (2023-11-02 17:45:53 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18407 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4: Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01 09:44:33 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0: configs: visionfive2: Enable JH7110 RNG driver (2023-11-02 17:45:53 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18407 + CI: Use OpenSBI 1.3.1 release for testing + riscv: Support resume after exception + rng: Support RNG provided by RISC-V Zkr ISA extension + board: starfive VF2: Support jtag + board: starfive VF2: Support TRNG driver + board: sifive unmatched: Move kernel load address Chanho Park (7): riscv: cpu: jh7110: Add gpio helper macros board: starfive: spl: Support jtag for VisionFive2 board riscv: import read/write_relaxed functions clk: starfive: jh7110: Add security clocks rng: Add StarFive JH7110 RNG driver riscv: dts: jh7110: Add rng device tree node configs: visionfive2: Enable JH7110 RNG driver Heinrich Schuchardt (3): CI: use OpenSBI 1.3.1 for testing riscv: allow resume after exception rng: Provide a RNG based on the RISC-V Zkr ISA extension Samuel Holland (3): riscv: Sort target configs alphabetically riscv: Align the trap handler to 64 bytes riscv: Weakly define invalidate_icache_range() Yong-Xuan Wang (1): board: sifive: unmatched: move kernel load address to 0x8020 .azure-pipelines.yml | 8 +- .gitlab-ci.yml| 8 +- arch/riscv/Kconfig| 18 +- arch/riscv/cpu/mtrap.S| 2 +- arch/riscv/dts/jh7110.dtsi| 10 ++ arch/riscv/include/asm/arch-jh7110/gpio.h | 85 + arch/riscv/include/asm/io.h | 45 + arch/riscv/lib/cache.c| 2 +- arch/riscv/lib/interrupts.c | 13 ++ board/starfive/visionfive2/spl.c | 23 +++ configs/starfive_visionfive2_defconfig| 2 + doc/api/index.rst | 1 + doc/api/interrupt.rst | 6 + drivers/clk/starfive/clk-jh7110.c | 10 ++ drivers/rng/Kconfig | 14 ++ drivers/rng/Makefile | 2 + drivers/rng/jh7110_rng.c | 274 ++ drivers/rng/riscv_zkr_rng.c | 116 + include/configs/sifive-unmatched.h| 2 +- include/interrupt.h | 45 + 20 files changed, 666 insertions(+), 20 deletions(-) create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h create mode 100644 doc/api/interrupt.rst create mode 100644 drivers/rng/jh7110_rng.c create mode 100644 drivers/rng/riscv_zkr_rng.c create mode 100644 include/interrupt.h Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Fri, Feb 26, 2021 at 09:53:24AM +0800, Leo Liang wrote: > Hi Tom, > > Please pull some RISC-V updates. > CI result: > https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/6505 > > The following changes since commit cbe607b920bc0827d8fe379ed4f5ae4e2058513e: > > Merge tag 'xilinx-for-v2021.04-rc3' of > https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze (2021-02-23 > 10:45:55 -0500) > > are available in the Git repository at: > > g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 5540294fa48598bf1aa8aa4d9084506a19bbd64c: > > riscv: k210: Enable QSPI for spi3 (2021-02-25 18:06:08 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, Please pull some RISC-V updates. CI result: https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/6505 The following changes since commit cbe607b920bc0827d8fe379ed4f5ae4e2058513e: Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze (2021-02-23 10:45:55 -0500) are available in the Git repository at: g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 5540294fa48598bf1aa8aa4d9084506a19bbd64c: riscv: k210: Enable QSPI for spi3 (2021-02-25 18:06:08 +0800) Heinrich Schuchardt (1): cmd/riscv/sbi: support System Reset Extension Sean Anderson (1): riscv: k210: Enable QSPI for spi3 arch/riscv/dts/k210-maix-bit.dts | 2 ++ cmd/riscv/sbi.c | 1 + 2 files changed, 3 insertions(+) Best regards, Leo
