On Thu, Mar 19, 2015 at 04:45:35PM +, York Sun wrote:
The timer clock is system clock divided by 4, not fixed 12MHz. This is
common to the SoC, not board specific.
Signed-off-by: York Sun york...@freescale.com
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README |8
On Thu, Mar 19, 2015 at 06:16:25PM +, York Sun wrote:
On 03/19/2015 11:08 AM, Mark Rutland wrote:
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+
On 03/19/2015 11:08 AM, Mark Rutland wrote:
+
+int timer_init(void)
+{
+u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+/*
On 03/19/2015 11:17 AM, Mark Rutland wrote:
On Thu, Mar 19, 2015 at 06:16:25PM +, York Sun wrote:
On 03/19/2015 11:08 AM, Mark Rutland wrote:
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
On Thu, Mar 19, 2015 at 06:24:10PM +, York Sun wrote:
On 03/19/2015 11:17 AM, Mark Rutland wrote:
On Thu, Mar 19, 2015 at 06:16:25PM +, York Sun wrote:
On 03/19/2015 11:08 AM, Mark Rutland wrote:
+
+int timer_init(void)
+{
+u32 __iomem *cntcr = (u32
On 03/19/2015 11:46 AM, Mark Rutland wrote:
On Thu, Mar 19, 2015 at 06:24:10PM +, York Sun wrote:
On 03/19/2015 11:17 AM, Mark Rutland wrote:
On Thu, Mar 19, 2015 at 06:16:25PM +, York Sun wrote:
On 03/19/2015 11:08 AM, Mark Rutland wrote:
+
+int timer_init(void)
+{
+u32
The timer clock is system clock divided by 4, not fixed 12MHz. This is
common to the SoC, not board specific.
Signed-off-by: York Sun york...@freescale.com
---
README |8
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24
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