Hi Tom,
On Mon, Jan 30, 2012 at 6:03 PM, Tom Rini wrote:
> On Sun, Jan 29, 2012 at 6:36 AM, Christian Riesch
> wrote:
>
>> 3) As Sughosh pointed out, the current code changes the V bit
>> (location of exceptions). Sughosh's patch removes this code that does
>> this change. I'm not sure if this
On Mon Jan 30, 2012 at 10:03:40AM -0700, Tom Rini wrote:
> Q1) Currently, the low level initialization code for ARM926EJS CPUs in
> the u-boot bootloader clears the V-bit of the cp15 control register
> c1. By default, this bit is set on AM1808 and OMAP-L138 before u-boot
> ist started. Sughosh Gan
On Sun, Jan 29, 2012 at 6:36 AM, Christian Riesch
wrote:
> 3) As Sughosh pointed out, the current code changes the V bit
> (location of exceptions). Sughosh's patch removes this code that does
> this change. I'm not sure if this is correct or not, so maybe you,
> Tom, could put your TI hat on ag
Hello Heiko,
On Mon, Jan 30, 2012 at 7:39 AM, Heiko Schocher wrote:
> Christian Riesch wrote:
>> 2) The current version of Sughosh's patch does not change the logic
>> behind the LOWLEVEL_INIT defines but just fixes the code to agree with
>> ARM's manual. Instead of invalidating the cache it now
hi Christian,
On Mon Jan 30, 2012 at 09:10:46AM +0100, Christian Riesch wrote:
> >> Perhaps we should revert that change and instead remove
> >> CONFIG_SKIP_LOWLEVEL_INIT from the da850 board config files. But since
> >> we don't need the lowlevel_init function for DA850 SoCs we must either
> >
Hi,
On Monday, January 30, 2012, Heiko Schocher wrote:
> Hello Christian,
>
> Christian Riesch wrote:
>> Hi all,
>>
>> On Fri, Jan 27, 2012 at 7:33 PM, Tom Rini wrote:
>>> So, what do we want to do here? We really want to get this fix in so
>>> we can get the hawkboard SPL changes in, and the o
hi Christian,
On Sun Jan 29, 2012 at 02:36:39PM +0100, Christian Riesch wrote:
> Hi all,
>
> On Fri, Jan 27, 2012 at 7:33 PM, Tom Rini wrote:
> > So, what do we want to do here? We really want to get this fix in so
> > we can get the hawkboard SPL changes in, and the other platforms /
> > fixup
Hello Christian,
Christian Riesch wrote:
> Hi all,
>
> On Fri, Jan 27, 2012 at 7:33 PM, Tom Rini wrote:
>> So, what do we want to do here? We really want to get this fix in so
>> we can get the hawkboard SPL changes in, and the other platforms /
>> fixups that are gated by that.
>>
>> If I can
Hi all,
On Fri, Jan 27, 2012 at 7:33 PM, Tom Rini wrote:
> So, what do we want to do here? We really want to get this fix in so
> we can get the hawkboard SPL changes in, and the other platforms /
> fixups that are gated by that.
>
> If I can sum it up, in the relevant section of code we have in
On Fri, Jan 20, 2012 at 6:06 AM, Aneesh V wrote:
> Hi Christian,
>
>
> On Friday 20 January 2012 06:18 PM, Christian Riesch wrote:
>>
>> Hi Aneesh,
>>
>> On Fri, Jan 20, 2012 at 1:13 PM, Aneesh V wrote:
>>>
>>> On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
On Fri, Jan 20,
Hi Christian,
On Friday 20 January 2012 06:18 PM, Christian Riesch wrote:
Hi Aneesh,
On Fri, Jan 20, 2012 at 1:13 PM, Aneesh V wrote:
On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
On Fri, Jan 20, 2012 at 9:52 AM, Aneesh Vwrote:
Sughosh,
[...]
Can you send the value of
Hi Aneesh,
On Fri, Jan 20, 2012 at 1:13 PM, Aneesh V wrote:
> On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
>> On Fri, Jan 20, 2012 at 9:52 AM, Aneesh V wrote:
>>> Sughosh,
>>
>> [...]
>>>
>>> Can you send the value of SCR you found at SPL entry? This will clarify
>>> what's enable
On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
Hi Aneesh,
On Fri, Jan 20, 2012 at 9:52 AM, Aneesh V wrote:
Sughosh,
[...]
Can you send the value of SCR you found at SPL entry? This will clarify
what's enabled and what's not.
I would like to try that on my board as well for com
On Fri, Jan 20, 2012 at 12:28 AM, Christian Riesch
wrote:
> On Thu, Jan 19, 2012 at 12:54 PM, Aneesh V wrote:
>> On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote:
>>> On Thu, Jan 19, 2012 at 11:17 AM, Aneesh V wrote:
On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
so sorry to you,
i think it's difference between DISABLE and Flush.
be careful.
On Wed, Jan 11, 2012 at 2:12 AM, Sughosh Ganu wrote:
> The current implementation invalidates the cache instead of flushing
> it. This causes problems on platforms where the spl/u-boot is already
> loaded to the RAM
Hi Aneesh,
On Fri, Jan 20, 2012 at 9:52 AM, Aneesh V wrote:
> Sughosh,
[...]
> Can you send the value of SCR you found at SPL entry? This will clarify
> what's enabled and what's not.
I would like to try that on my board as well for comparison. Could you
please tell me how this register can be r
Sughosh,
On Friday 20 January 2012 12:58 PM, Christian Riesch wrote:
On Thu, Jan 19, 2012 at 12:54 PM, Aneesh V wrote:
On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote:
On Thu, Jan 19, 2012 at 11:17 AM, Aneesh Vwrote:
On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
On Thu, Jan 19, 2012 at 12:54 PM, Aneesh V wrote:
> On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote:
>> On Thu, Jan 19, 2012 at 11:17 AM, Aneesh V wrote:
>>> On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
Tried a few things on my end.
* Read the D-cache value
On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote:
Hi Aneesh,
On Thu, Jan 19, 2012 at 11:17 AM, Aneesh V wrote:
On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
Tried a few things on my end.
* Read the D-cache value in the spl, and confirmed that the data
cache
Hi Aneesh,
On Thu, Jan 19, 2012 at 11:17 AM, Aneesh V wrote:
> On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
>> Tried a few things on my end.
>> * Read the D-cache value in the spl, and confirmed that the data
>> cache is indeed not enabled.
> What is the value of the B bit in
Hi Sughosh,
On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
On Tue Jan 17, 2012 at 08:27:58AM -0700, Tom Rini wrote:
On Mon, Jan 16, 2012 at 11:46 PM, Sughosh Ganu wrote:
Hmm.. how did u-boot work on such boards? How can u-boot work with D-Cache
enabled, if u-boot is not initializ
On Tue Jan 17, 2012 at 08:27:58AM -0700, Tom Rini wrote:
> On Mon, Jan 16, 2012 at 11:46 PM, Sughosh Ganu
> wrote:
> >> >> Hmm.. how did u-boot work on such boards? How can u-boot work with
> >> >> D-Cache
> >> >> enabled, if u-boot is not initializing it? (And I think, on davinci SoC
> >> >> w
On Mon, Jan 16, 2012 at 11:46 PM, Sughosh Ganu wrote:
> On Mon Jan 16, 2012 at 10:57:05AM -0700, Tom Rini wrote:
>> On Fri, Jan 13, 2012 at 10:38 AM, Sughosh Ganu
>> wrote:
>> > hi Heiko,
>> >
>> > On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
>> >> Hello Sugosh,
>> >>
>> >> Sug
On Mon Jan 16, 2012 at 10:57:05AM -0700, Tom Rini wrote:
> On Fri, Jan 13, 2012 at 10:38 AM, Sughosh Ganu
> wrote:
> > hi Heiko,
> >
> > On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
> >> Hello Sugosh,
> >>
> >> Sughosh Ganu wrote:
> >> > hi Christian,
> >> >
> >> > On Fri Jan 13
Hello Tom,
Tom Rini wrote:
> On Fri, Jan 13, 2012 at 10:38 AM, Sughosh Ganu
> wrote:
>> hi Heiko,
>>
>> On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
>>> Hello Sugosh,
>>>
>>> Sughosh Ganu wrote:
hi Christian,
On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Rie
On Fri, Jan 13, 2012 at 10:38 AM, Sughosh Ganu wrote:
> hi Heiko,
>
> On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
>> Hello Sugosh,
>>
>> Sughosh Ganu wrote:
>> > hi Christian,
>> >
>> > On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
>> >> Hi Sughosh,
>> >> I ha
Hello Sughosh,
Sughosh Ganu wrote:
> hi Heiko,
>
> On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
>> Hello Sugosh,
>>
>> Sughosh Ganu wrote:
>>> hi Christian,
>>>
>>> On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
Hi Sughosh,
I had a look at the patch a
hi Christian,
On Sat Jan 14, 2012 at 06:20:06PM +0100, Christian Riesch wrote:
> Hi Sughosh,
> On Thursday, January 12, 2012, Sughosh Ganu wrote:
> >> 1) The first test was done with the SPL and yes, here the RBL loads
> >> the SPL into SRAM, initializes DDR memory and then copies u-boot.bin
>
Hi Sughosh,
On Thursday, January 12, 2012, Sughosh Ganu wrote:
> hi Christian,
>
> On Thu Jan 12, 2012 at 03:04:37PM +0100, Christian Riesch wrote:
>> On Thu, Jan 12, 2012 at 2:53 PM, Sughosh Ganu
wrote:
>> > On Thu Jan 12, 2012 at 01:03:05PM +0100, Christian Riesch wrote:
>
>
>
>> >>
>> >> Sin
Hi Albert,
On Saturday, January 14, 2012, Albert ARIBAUD
wrote:
> Le 12/01/2012 07:29, Sughosh Ganu a écrit :
>>
>> On Thu Jan 12, 2012 at 06:56:01AM +0100, Christian Riesch wrote:
>>>
>>> On Wednesday, January 11, 2012, Marek Vasut
wrote:
>>
>>
>>
> RBL executes an AIS script. Sughosh, cou
Le 12/01/2012 07:29, Sughosh Ganu a écrit :
On Thu Jan 12, 2012 at 06:56:01AM +0100, Christian Riesch wrote:
On Wednesday, January 11, 2012, Marek Vasut wrote:
RBL executes an AIS script. Sughosh, could you please explain what your
AIS
does or how you create it?
So basically, this SPL
On Fri Jan 13, 2012 at 11:49:57PM +0530, Aneesh V wrote:
> On Friday 13 January 2012 11:08 PM, Sughosh Ganu wrote:
> >>
> >>Are you sure, the RBL enables the D-Cache on your board? Nevertheless,
> >>I think, we must disable the D-Cache here with "cleaning" it (as your
> >>patch did) instead only
On Friday 13 January 2012 11:08 PM, Sughosh Ganu wrote:
hi Heiko,
On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
Hello Sugosh,
Sughosh Ganu wrote:
hi Christian,
On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
Hi Sughosh,
I had a look at the patch and I tried
hi Heiko,
On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
> Hello Sugosh,
>
> Sughosh Ganu wrote:
> > hi Christian,
> >
> > On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
> >> Hi Sughosh,
> >> I had a look at the patch and I tried to understand what's going on
>
On Fri Jan 13, 2012 at 07:41:37AM -0700, Tom Rini wrote:
> On Fri, Jan 13, 2012 at 1:26 AM, Sughosh Ganu wrote:
> >> > bic r0, r0, #0x0087 /* clear bits 7, 2:0 (B--- -CAM)
> >> > */
> >> > orr r0, r0, #0x0002 /* set bit 2 (A) Align */
> >> > orr
hi Heiko,
On Fri Jan 13, 2012 at 04:06:22PM +0100, Heiko Schocher wrote:
>
> >>mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
> >>
> >>/*
> >> * disable MMU stuff and caches
> >> */
> >>mrc p15, 0, r0, c1, c0, 0
> >> - bic r0, r0, #0x00
Hello Sugosh,
Sughosh Ganu wrote:
> hi Christian,
>
> On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
>> Hi Sughosh,
>> I had a look at the patch and I tried to understand what's going on
>> here (I must confess that I didn't know anything about this cache
>> stuff).
>
> Ok, t
Hello Christian,
Christian Riesch wrote:
> Hi Sughosh,
> I had a look at the patch and I tried to understand what's going on
> here (I must confess that I didn't know anything about this cache
> stuff).
>
> On Tue, Jan 10, 2012 at 7:12 PM, Sughosh Ganu wrote:
>> The current implementation invali
On Fri, Jan 13, 2012 at 1:26 AM, Sughosh Ganu wrote:
> hi Christian,
>
> On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
>> Hi Sughosh,
>> I had a look at the patch and I tried to understand what's going on
>> here (I must confess that I didn't know anything about this cache
>> st
hi Christian,
On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
> Hi Sughosh,
> I had a look at the patch and I tried to understand what's going on
> here (I must confess that I didn't know anything about this cache
> stuff).
Ok, thanks for taking time off to understand this issu
Hi Sughosh,
I had a look at the patch and I tried to understand what's going on
here (I must confess that I didn't know anything about this cache
stuff).
On Tue, Jan 10, 2012 at 7:12 PM, Sughosh Ganu wrote:
> The current implementation invalidates the cache instead of flushing
> it. This causes p
hi Christian,
On Thu Jan 12, 2012 at 03:04:37PM +0100, Christian Riesch wrote:
> On Thu, Jan 12, 2012 at 2:53 PM, Sughosh Ganu wrote:
> > On Thu Jan 12, 2012 at 01:03:05PM +0100, Christian Riesch wrote:
> >>
> >> Since all my tests were successful I wonder what issues did you have
> >> with th
On Thu, Jan 12, 2012 at 2:53 PM, Sughosh Ganu wrote:
> On Thu Jan 12, 2012 at 01:03:05PM +0100, Christian Riesch wrote:
>> On Tue, Jan 10, 2012 at 7:12 PM, Sughosh Ganu
>> wrote:
>> > The current implementation invalidates the cache instead of flushing
>> > it. This causes problems on platforms
hi Christian,
On Thu Jan 12, 2012 at 01:03:05PM +0100, Christian Riesch wrote:
> Hi Sughosh,
>
> On Tue, Jan 10, 2012 at 7:12 PM, Sughosh Ganu wrote:
> > The current implementation invalidates the cache instead of flushing
> > it. This causes problems on platforms where the spl/u-boot is already
Hi Sughosh,
On Tue, Jan 10, 2012 at 7:12 PM, Sughosh Ganu wrote:
> The current implementation invalidates the cache instead of flushing
> it. This causes problems on platforms where the spl/u-boot is already
> loaded to the RAM, with caches enabled by a first stage bootloader.
>
> The V bit of th
On Wed Jan 11, 2012 at 07:50:50PM +0100, Marek Vasut wrote:
> > On Wed Jan 11, 2012 at 04:01:31PM +0100, Marek Vasut wrote:
> > > > More so, given the fact that we don't have any control over
> > > > rbl -- so if rbl changes it's layout for any subsequent board, we'd
> > > > have to add that
On Thu Jan 12, 2012 at 06:56:01AM +0100, Christian Riesch wrote:
> On Wednesday, January 11, 2012, Marek Vasut wrote:
> >> RBL executes an AIS script. Sughosh, could you please explain what your
> AIS
> >> does or how you create it?
> >
> > So basically, this SPL business can be avoided and thi
On Wednesday, January 11, 2012, Marek Vasut wrote:
>> Hi,
>>
>> On Wednesday, January 11, 2012, Marek Vasut
wrote:
>> >> On Wed Jan 11, 2012 at 04:01:31PM +0100, Marek Vasut wrote:
>> >> > > More so, given the fact that we don't have any control over
>> >> > > rbl -- so if rbl changes it's la
> Hi,
>
> On Wednesday, January 11, 2012, Marek Vasut wrote:
> >> On Wed Jan 11, 2012 at 04:01:31PM +0100, Marek Vasut wrote:
> >> > > More so, given the fact that we don't have any control over
> >> > > rbl -- so if rbl changes it's layout for any subsequent board,
> >> > > we'd have to ad
Hi,
On Wednesday, January 11, 2012, Marek Vasut wrote:
>> On Wed Jan 11, 2012 at 04:01:31PM +0100, Marek Vasut wrote:
>> > > More so, given the fact that we don't have any control over
>> > > rbl -- so if rbl changes it's layout for any subsequent board, we'd
>> > > have to add that as well
> On Wed Jan 11, 2012 at 04:01:31PM +0100, Marek Vasut wrote:
> > > More so, given the fact that we don't have any control over
> > > rbl -- so if rbl changes it's layout for any subsequent board, we'd
> > > have to add that as well to the nand driver, and both in u-boot as
> > > well as th
On Wed Jan 11, 2012 at 04:01:31PM +0100, Marek Vasut wrote:
> > More so, given the fact that we don't have any control over
> > rbl -- so if rbl changes it's layout for any subsequent board, we'd
> > have to add that as well to the nand driver, and both in u-boot as
> > well as the kernel.
> On Wed Jan 11, 2012 at 02:52:44PM +0100, Marek Vasut wrote:
> > > > Changing the ecc layout for a single board, hmm not sure. Using a
> > > > spl instead does me no harm whatsoever -- I don't need to update
> > > > the spl frequently in any case, and then can use the nand driver
> > > > a
On Wed Jan 11, 2012 at 02:52:44PM +0100, Marek Vasut wrote:
> > > Changing the ecc layout for a single board, hmm not sure. Using a
> > > spl instead does me no harm whatsoever -- I don't need to update the
> > > spl frequently in any case, and then can use the nand driver as is.
> >
> > An
> > On Wed Jan 11, 2012 at 01:42:38PM +0100, Marek Vasut wrote:
> > > > On Wed Jan 11, 2012 at 11:47:27AM +0100, Marek Vasut wrote:
> > > > > > On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > > > > > > > The current implementation invalidates the cache instead of
> > > > > > > > flu
> On Wed Jan 11, 2012 at 01:42:38PM +0100, Marek Vasut wrote:
> > > On Wed Jan 11, 2012 at 11:47:27AM +0100, Marek Vasut wrote:
> > > > > On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > > > > > > The current implementation invalidates the cache instead of
> > > > > > > flushing it.
On Wed Jan 11, 2012 at 01:42:38PM +0100, Marek Vasut wrote:
> > On Wed Jan 11, 2012 at 11:47:27AM +0100, Marek Vasut wrote:
> > > > On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > > > > > The current implementation invalidates the cache instead of
> > > > > > flushing it. This cause
> On Wed Jan 11, 2012 at 11:47:27AM +0100, Marek Vasut wrote:
> > > On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > > > > The current implementation invalidates the cache instead of
> > > > > flushing it. This causes problems on platforms where the
> > > > > spl/u-boot is already lo
On Wed Jan 11, 2012 at 11:47:27AM +0100, Marek Vasut wrote:
> > On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > > > The current implementation invalidates the cache instead of flushing
> > > > it. This causes problems on platforms where the spl/u-boot is already
> > > > loaded to th
> On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > > The current implementation invalidates the cache instead of flushing
> > > it. This causes problems on platforms where the spl/u-boot is already
> > > loaded to the RAM, with caches enabled by a first stage bootloader.
> >
> > Wha
On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote:
> > The current implementation invalidates the cache instead of flushing
> > it. This causes problems on platforms where the spl/u-boot is already
> > loaded to the RAM, with caches enabled by a first stage bootloader.
>
> What platforms
> The current implementation invalidates the cache instead of flushing
> it. This causes problems on platforms where the spl/u-boot is already
> loaded to the RAM, with caches enabled by a first stage bootloader.
What platforms are affected?
M
>
> The V bit of the cp15's control register c1 is s
The current implementation invalidates the cache instead of flushing
it. This causes problems on platforms where the spl/u-boot is already
loaded to the RAM, with caches enabled by a first stage bootloader.
The V bit of the cp15's control register c1 is set to the value of
VINITHI on reset. Do not
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