Re: [U-Boot] [PATCH 1/3] armv8: ls1088a: Add NXP LS1088A SoC support

2017-03-25 Thread york sun 
On 02/15/2017 07:07 AM, Ashish Kumar wrote:
> The QorIQ LS1088A processor is built on the Layerscape
> architecture combining eight ARM A53 processor cores
> with advanced, high-performance datapath acceleration
> and networks, peripheral interfaces required for
> networking, wireless infrastructure, and general-purpose
> embedded applications.
>
> LS1088A is compliant to the Layerscape Chassis Generation 3.
>
> Features summary:
>  - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
>  - Cores are in 2 cluster of 4-cores each
>  - Cache coherent interconnect (CCI-400)
>  - One 64-bit DDR4 SDRAM memory controller with ECC
>  - Data path acceleration architecture 2.0 (DPAA2)
>  - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
>  - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
>

Please remove the indentation in commit message.

> Signed-off-by: Alison Wang 
> Signed-off-by: Prabhakar Kushwaha 
> Signed-off-by: Ashish Kumar 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
>  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|  10 ++
>  arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 124 
> +
>  arch/arm/include/asm/arch-fsl-layerscape/config.h  |  46 
>  arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   4 +
>  .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   1 +
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h |   4 +
>  drivers/net/ldpaa_eth/Makefile |   1 +
>  drivers/net/ldpaa_eth/ls1088a.c|  87 +++
>  10 files changed, 292 insertions(+)
>  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
>  create mode 100644 drivers/net/ldpaa_eth/ls1088a.c
>



> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index 83f5501..3aed123 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -219,6 +219,52 @@
>
>  #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC1
>
> +#elif defined(CONFIG_ARCH_LS1088A)
> +#define CONFIG_MAX_CPUS  8
> +#define CONFIG_SYS_FSL_NUM_CC_PLLS   3
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT8
> +#define CONFIG_NUM_DDR_CONTROLLERS   1
> +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS{ 1, 1 }
> +#define CONFIG_SYS_FSL_PLATFORM_CLK_RATIO1
> +#define CONFIG_GICV3
> +#define CONFIG_FSL_TZPC_BP147
> +#define CONFIG_FSL_TZASC_400
> +#define CONFIG_FSL_TZASC_1
> +
> +#define  SRDS_MAX_LANES  4
> +#define CONFIG_SYS_FSL_SRDS_1
> +#define CONFIG_SYS_FSL_SRDS_2
> +
> +/* DDR */
> +#define CONFIG_SYS_FSL_DDR_LE
> +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE   ((phys_size_t)2 << 30)
> +#define CONFIG_MAX_MEM_MAPPEDCONFIG_SYS_LS2_DDR_BLOCK1_SIZE
> +
> +#define CONFIG_SYS_FSL_CCSR_GUR_LE
> +#define CONFIG_SYS_FSL_CCSR_SCFG_LE
> +#define CONFIG_SYS_FSL_ESDHC_LE
> +#define CONFIG_SYS_FSL_IFC_LE
> +#define CONFIG_SYS_FSL_PEX_LUT_LE
> +
> +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
> +
> +/* SFP */
> +#define CONFIG_SYS_FSL_SFP_VER_3_4
> +#define CONFIG_SYS_FSL_SFP_LE
> +#define CONFIG_SYS_FSL_SRK_LE
> +
> +/* SEC */
> +#define CONFIG_SYS_FSL_SEC_LE
> +#define CONFIG_SYS_FSL_SEC_COMPAT5
> +
> +/* Security Monitor */
> +#define CONFIG_SYS_FSL_SEC_MON_LE
> +
> +/* Secure Boot */
> +#define CONFIG_ESBC_HDR_LS
> +
> +/* DCFG - GUR */
> +#define CONFIG_SYS_FSL_CCSR_GUR_LE
>  #else
>  #error SoC not defined
>  #endif

Many of your config macros were moved into Kconfig. You made the update 
in your #2 and #3 patches. How did you miss this one? Please update your 
patch.

York
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[U-Boot] [PATCH 1/3] armv8: ls1088a: Add NXP LS1088A SoC support

2017-02-15 Thread Ashish Kumar 
The QorIQ LS1088A processor is built on the Layerscape
architecture combining eight ARM A53 processor cores
with advanced, high-performance datapath acceleration
and networks, peripheral interfaces required for
networking, wireless infrastructure, and general-purpose
embedded applications.

LS1088A is compliant to the Layerscape Chassis Generation 3.

Features summary:
 - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
 - Cores are in 2 cluster of 4-cores each
 - Cache coherent interconnect (CCI-400)
 - One 64-bit DDR4 SDRAM memory controller with ECC
 - Data path acceleration architecture 2.0 (DPAA2)
 - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
 - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc

Signed-off-by: Alison Wang 
Signed-off-by: Prabhakar Kushwaha 
Signed-off-by: Ashish Kumar 
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|  10 ++
 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 124 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  46 
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   4 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   4 +
 drivers/net/ldpaa_eth/Makefile |   1 +
 drivers/net/ldpaa_eth/ls1088a.c|  87 +++
 10 files changed, 292 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
 create mode 100644 drivers/net/ldpaa_eth/ls1088a.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index c9ab93e..cfad154 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -38,3 +38,7 @@ endif
 ifneq ($(CONFIG_ARCH_LS1046A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
 endif
+
+ifneq ($(CONFIG_ARCH_LS1088A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 955e0b7..d7e2d3c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
return;
 }
 
+__weak int serdes_get_number(int serdes, int cfg)
+{
+   return cfg;
+}
+
 int is_serdes_configured(enum srds_prtcl device)
 {
int ret = 0;
@@ -73,6 +78,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
printf("invalid SerDes%d\n", sd);
break;
}
+
+   cfg = serdes_get_number(sd, cfg);
+
/* Is serdes enabled at all? */
if (cfg == 0)
return -ENODEV;
@@ -99,6 +107,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 
sd_prctl_mask,
 
cfg = gur_in32(>rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
+
+   cfg = serdes_get_number(sd, cfg);
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
if (!is_serdes_prtcl_valid(sd, cfg))
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
new file mode 100644
index 000..9f89bd0
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+struct serdes_config {
+   u8 ip_protocol;
+   u8 lanes[SRDS_MAX_LANES];
+   u8 rcw_lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+   /* SerDes 1 */
+   {0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 }  },
+   {0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
+   {0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
+   {0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
+   {0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
+   {0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
+   {0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
+   {0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
+   {0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
+   {0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
+   {0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2  }, {4, 4, 3, 1 } },
+   {0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2  }, {4, 4, 3, 2 } },
+   {0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
+   {0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
+   {0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
+   {}
+};
+static struct serdes_config serdes2_cfg_tbl[] =