Re: [U-Boot] [PATCH 2/2] dm: clk: fix PWR_CR3 register's bit 2 name

[Vikas MANOCHA]

Hi,

> -Original Message-
> From: Patrice CHOTARD
> Sent: Monday, October 09, 2017 2:41 AM
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; s...@chromium.org; Vikas 
> MANOCHA 
> Cc: Patrice CHOTARD ; Patrick DELAUNAY 
> ; Christophe KERELLO
> 
> Subject: [PATCH 2/2] dm: clk: fix PWR_CR3 register's bit 2 name
> 
> From: Patrice Chotard 
> 
> Fix bit 2 name of PWR_CR3 register to match with the last STM32H7 reference 
> manual available here :
> 
> http://www.st.com/content/st_com/en/support/resources/
> resource-selector.html?querycriteria=productId=SS1951$$
> resourceCategory=technical_literature$$resourceType=reference_manual
> 
> Update also comment about voltage scaling 1 values
> 
> Signed-off-by: Patrice Chotard 

Reviewed-by: Vikas Manocha 

Cheers,
Vikas

> ---
>  drivers/clk/clk_stm32h7.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index 
> 9ca497a..ffa902d 100644
> --- a/drivers/clk/clk_stm32h7.c
> +++ b/drivers/clk/clk_stm32h7.c
> @@ -109,7 +109,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define  QSPISRC_PER_CK  3
> 
>  #define PWR_CR3  0x0c
> -#define PWR_CR3_SDEN BIT(2)
> +#define PWR_CR3_SCUENBIT(2)
>  #define PWR_D3CR 0x18
>  #define PWR_D3CR_VOS_MASKGENMASK(15, 14)
>  #define PWR_D3CR_VOS_SHIFT   14
> @@ -361,11 +361,11 @@ int configure_clocks(struct udevice *dev)
>   writel(0x0, >d2ccip1r);
>   writel(0x0, >d2ccip2r);
> 
> - /* Set voltage scaling at scale 1 */
> + /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
>   clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
>   VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
> - /* disable step down converter */
> - clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN);
> + /* Lock supply configuration update */
> + clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
>   while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
>   ;
> 
> --
> 1.9.1

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[U-Boot] [PATCH 2/2] dm: clk: fix PWR_CR3 register's bit 2 name

[patrice.chotard]

From: Patrice Chotard 

Fix bit 2 name of PWR_CR3 register to match with the
last STM32H7 reference manual available here :

http://www.st.com/content/st_com/en/support/resources/
resource-selector.html?querycriteria=productId=SS1951$$
resourceCategory=technical_literature$$resourceType=reference_manual

Update also comment about voltage scaling 1 values

Signed-off-by: Patrice Chotard 
---
 drivers/clk/clk_stm32h7.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index 9ca497a..ffa902d 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -109,7 +109,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #defineQSPISRC_PER_CK  3
 
 #define PWR_CR30x0c
-#define PWR_CR3_SDEN   BIT(2)
+#define PWR_CR3_SCUEN  BIT(2)
 #define PWR_D3CR   0x18
 #define PWR_D3CR_VOS_MASK  GENMASK(15, 14)
 #define PWR_D3CR_VOS_SHIFT 14
@@ -361,11 +361,11 @@ int configure_clocks(struct udevice *dev)
writel(0x0, >d2ccip1r);
writel(0x0, >d2ccip2r);
 
-   /* Set voltage scaling at scale 1 */
+   /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
-   /* disable step down converter */
-   clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN);
+   /* Lock supply configuration update */
+   clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
;
 
-- 
1.9.1

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