Re: [U-Boot] [PATCH v2 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation

[Stephen Warren]

On 08/09/2017 02:18 PM, Marcel Ziswiler wrote:

On Wed, 2017-08-09 at 12:51 -0600, Stephen Warren wrote:

On 08/09/2017 09:44 AM, Marcel Ziswiler wrote:

From: Marcel Ziswiler 

Allow optionally bringing up the Apalis type specific 4 lane PCIe
port
as well as the PCIe switch as found on the Apalis Evaluation board.
In
order to avoid violating the PCIe reset timing do this by
overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis
PCIe
port are also left disabled in the device tree by default.
diff --git a/board/toradex/apalis_t30/apalis_t30.c
b/board/toradex/apalis_t30/apalis_t30.c
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+   /*
+* Reset PLX PEX 8605 PCIe Switch plus
PCIe devices on
+* Apalis Evaluation Board
+*/
+   gpio_direction_output(PEX_PERST_N, 0);
+   gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+   /*
+* Must be asserted for 100 ms after power
and clocks
+* are stable
+*/
+   mdelay(100);
+
+   gpio_set_value(PEX_PERST_N, 1);
+   /*
+* Err_5: PEX_REFCLK_OUTpx/nx Clock
Outputs is not
+* Guaranteed Until 900 us After
PEX_PERST# De-assertion
+*/
+   mdelay(1);
+   gpio_set_value(RESET_MOCI_CTRL, 1);


Don't we need to also call the core tegra_pcie_port_reset() function
here, so that the driver gets to do any reset of the PCIe controller
HW
that's required? I think that part should happen irrespective of
whether
CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT is enabled?


I really don't think so. All it really would do is just resetting by the means 
of the regular PEX_CTL signals which our design is not using like that anyway.


OK, I guess whatever the outcome, we could always fix it later since 
it's purely board-specific code. So, this patch,


Acked-by: Stephen Warren 
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Re: [U-Boot] [PATCH v2 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation

[Marcel Ziswiler]

On Wed, 2017-08-09 at 12:51 -0600, Stephen Warren wrote:
> On 08/09/2017 09:44 AM, Marcel Ziswiler wrote:
> > From: Marcel Ziswiler 
> > 
> > Allow optionally bringing up the Apalis type specific 4 lane PCIe
> > port
> > as well as the PCIe switch as found on the Apalis Evaluation board.
> > In
> > order to avoid violating the PCIe reset timing do this by
> > overriding the
> > tegra_pcie_board_port_reset() function. Note however that both the
> > Apalis type specific 4 lane PCIe port as well as the regular Apalis
> > PCIe
> > port are also left disabled in the device tree by default.
> > diff --git a/board/toradex/apalis_t30/apalis_t30.c
> > b/board/toradex/apalis_t30/apalis_t30.c
> > +void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
> > +   /*
> > +    * Reset PLX PEX 8605 PCIe Switch plus
> > PCIe devices on
> > +    * Apalis Evaluation Board
> > +    */
> > +   gpio_direction_output(PEX_PERST_N, 0);
> > +   gpio_direction_output(RESET_MOCI_CTRL, 0);
> > +
> > +   /*
> > +    * Must be asserted for 100 ms after power
> > and clocks
> > +    * are stable
> > +    */
> > +   mdelay(100);
> > +
> > +   gpio_set_value(PEX_PERST_N, 1);
> > +   /*
> > +    * Err_5: PEX_REFCLK_OUTpx/nx Clock
> > Outputs is not
> > +    * Guaranteed Until 900 us After
> > PEX_PERST# De-assertion
> > +    */
> > +   mdelay(1);
> > +   gpio_set_value(RESET_MOCI_CTRL, 1);
> 
> Don't we need to also call the core tegra_pcie_port_reset() function 
> here, so that the driver gets to do any reset of the PCIe controller
> HW 
> that's required? I think that part should happen irrespective of
> whether 
> CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT is enabled?

I really don't think so. All it really would do is just resetting by the means 
of the regular PEX_CTL signals which our design is not using like that anyway.
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Re: [U-Boot] [PATCH v2 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation

[Stephen Warren]

On 08/09/2017 09:44 AM, Marcel Ziswiler wrote:

From: Marcel Ziswiler 

Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe
port are also left disabled in the device tree by default.



diff --git a/board/toradex/apalis_t30/apalis_t30.c 
b/board/toradex/apalis_t30/apalis_t30.c



+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)



+   /*
+* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
+* Apalis Evaluation Board
+*/
+   gpio_direction_output(PEX_PERST_N, 0);
+   gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+   /*
+* Must be asserted for 100 ms after power and clocks
+* are stable
+*/
+   mdelay(100);
+
+   gpio_set_value(PEX_PERST_N, 1);
+   /*
+* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
+* Guaranteed Until 900 us After PEX_PERST# De-assertion
+*/
+   mdelay(1);
+   gpio_set_value(RESET_MOCI_CTRL, 1);


Don't we need to also call the core tegra_pcie_port_reset() function 
here, so that the driver gets to do any reset of the PCIe controller HW 
that's required? I think that part should happen irrespective of whether 
CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT is enabled?

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[U-Boot] [PATCH v2 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation

[Marcel Ziswiler]

From: Marcel Ziswiler 

Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe
port are also left disabled in the device tree by default.

Signed-off-by: Marcel Ziswiler 
---

Changes in v2:
- Stick to struct tegra_pcie_port as suggested by Stephen.
- Introduce proper CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT Kconfig option
  as suggested by Stephen.
- Improved the ifdef vs. if curly braces sequencing as suggested by
  Stephen.
- Keep PCIe port reset status in order to safeguard for future changes
  to the port reset order or even allow for re-initialisation should
  that ever be implemented in the higher levels of the driver model.

 board/toradex/apalis_t30/Kconfig  |  9 ++
 board/toradex/apalis_t30/apalis_t30.c | 54 +++
 2 files changed, 63 insertions(+)

diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index 16224da..9cd4970 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -25,6 +25,15 @@ config TDX_CFG_BLOCK_PART
 config TDX_CFG_BLOCK_OFFSET
default "-512"
 
+config APALIS_T30_PCIE_EVALBOARD_INIT
+   bool "Apalis Evaluation Board PCIe Initialisation"
+   help
+ Bring up the Apalis type specific 4 lane PCIe port as well as the
+ Apalis PCIe port with the PCIe switch as found on the Apalis
+ Evaluation board. Note that by default both those ports are also left
+ disabled in the device tree which needs changing as well for this to
+ actually work.
+
 source "board/toradex/common/Kconfig"
 
 endif
diff --git a/board/toradex/apalis_t30/apalis_t30.c 
b/board/toradex/apalis_t30/apalis_t30.c
index 827eefd..60d1865 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "../common/tdx-common.h"
 
 #include "pinmux-config-apalis_t30.h"
@@ -23,6 +24,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PMU_I2C_ADDRESS0x2D
 #define MAX_I2C_RETRY  3
 
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+#define PEX_PERST_NTEGRA_GPIO(S, 7) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRLTEGRA_GPIO(I, 4)
+
+static int pci_reset_status;
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+
 int arch_misc_init(void)
 {
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
@@ -107,6 +115,52 @@ int tegra_pcie_board_init(void)
return err;
}
 
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+   gpio_request(PEX_PERST_N, "PEX_PERST_N");
+   gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+
return 0;
 }
+
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+{
+   int index = tegra_pcie_port_index_of_port(port);
+   if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
+   tegra_pcie_port_reset(port);
+   }
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+   /*
+* Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port
+* 0 share the same RESET_MOCI therefore only assert it once for both
+* ports to avoid loosing the previously brought up port again.
+*/
+   else if ((index == 1) || (index == 0)) {
+   /* only do it once per init cycle */
+   if (pci_reset_status % 2 == 0) {
+   /*
+* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
+* Apalis Evaluation Board
+*/
+   gpio_direction_output(PEX_PERST_N, 0);
+   gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+   /*
+* Must be asserted for 100 ms after power and clocks
+* are stable
+*/
+   mdelay(100);
+
+   gpio_set_value(PEX_PERST_N, 1);
+   /*
+* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
+* Guaranteed Until 900 us After PEX_PERST# De-assertion
+*/
+   mdelay(1);
+   gpio_set_value(RESET_MOCI_CTRL, 1);
+   }
+   pci_reset_status++;
+   }
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+}
 #endif /* CONFIG_PCI_TEGRA */
-- 
2.9.4

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