On 08/09/2017 02:18 PM, Marcel Ziswiler wrote:
On Wed, 2017-08-09 at 12:51 -0600, Stephen Warren wrote:
On 08/09/2017 09:44 AM, Marcel Ziswiler wrote:
From: Marcel Ziswiler <marcel.ziswi...@toradex.com>

Allow optionally bringing up the Apalis type specific 4 lane PCIe
as well as the PCIe switch as found on the Apalis Evaluation board.
order to avoid violating the PCIe reset timing do this by
overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis
port are also left disabled in the device tree by default.
diff --git a/board/toradex/apalis_t30/apalis_t30.c
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+                       /*
+                        * Reset PLX PEX 8605 PCIe Switch plus
PCIe devices on
+                        * Apalis Evaluation Board
+                        */
+                       gpio_direction_output(PEX_PERST_N, 0);
+                       gpio_direction_output(RESET_MOCI_CTRL, 0);
+                       /*
+                        * Must be asserted for 100 ms after power
and clocks
+                        * are stable
+                        */
+                       mdelay(100);
+                       gpio_set_value(PEX_PERST_N, 1);
+                       /*
+                        * Err_5: PEX_REFCLK_OUTpx/nx Clock
Outputs is not
+                        * Guaranteed Until 900 us After
PEX_PERST# De-assertion
+                        */
+                       mdelay(1);
+                       gpio_set_value(RESET_MOCI_CTRL, 1);

Don't we need to also call the core tegra_pcie_port_reset() function
here, so that the driver gets to do any reset of the PCIe controller
that's required? I think that part should happen irrespective of

I really don't think so. All it really would do is just resetting by the means 
of the regular PEX_CTL signals which our design is not using like that anyway.

OK, I guess whatever the outcome, we could always fix it later since it's purely board-specific code. So, this patch,

Acked-by: Stephen Warren <swar...@nvidia.com>
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